From bd18eea4614fb180ba438905caf361c3a208c011 Mon Sep 17 00:00:00 2001
From: Fischertechnik-OpenSource <fischertechnik-opensource@online.de>
Date: Wed, 12 Feb 2025 11:47:29 +0100
Subject: [PATCH] Update to 3.1.8
---
build.sh | 376 +
txt2-M4-rt-core/CMakeLists.txt | 22 +
txt2-M4-rt-core/TxtControlLib/TxtControlLib.c | 91 +-
txt2-M4-rt-core/TxtControlLib/ftactions.c | 80 +-
txt2-M4-rt-core/TxtControlLib/ftslave.c | 58 +
txt2-M4-rt-core/cubemx/txt | 1 -
txt2-M4-rt-core/cubemx/txt/.cproject | 480 +
txt2-M4-rt-core/cubemx/txt/.mxproject | 14 +
txt2-M4-rt-core/cubemx/txt/.project | 2431 ++
.../txt2/kernel/stm32mp157c-txt2-mx.dts | 825 +
.../DeviceTree/txt2/tf-a/stm32mp15-mx.dtsi | 119 +
.../txt2/tf-a/stm32mp157c-txt2-mx.dts | 299 +
.../DeviceTree/txt2/u-boot/stm32mp15-mx.dtsi | 119 +
.../u-boot/stm32mp157c-txt2-mx-u-boot.dtsi | 178 +
.../txt2/u-boot/stm32mp157c-txt2-mx.dts | 825 +
.../txt2/u-boot/stm32mp157c-txt2-mx.dts.bak | 825 +
.../cubemx/txt/CM4/Inc/FreeRTOSConfig.h | 175 +
txt2-M4-rt-core/cubemx/txt/CM4/Inc/main.h | 174 +
.../cubemx/txt/CM4/Inc/mbox_ipcc.h | 39 +
txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp.h | 58 +
.../cubemx/txt/CM4/Inc/openamp_conf.h | 242 +
.../cubemx/txt/CM4/Inc/openamp_log.h | 134 +
.../cubemx/txt/CM4/Inc/rsc_table.h | 43 +
.../cubemx/txt/CM4/Inc/stm32mp1xx_hal_conf.h | 396 +
.../cubemx/txt/CM4/Inc/stm32mp1xx_it.h | 69 +
.../cubemx/txt/CM4/Src/app_freertos.c | 95 +
txt2-M4-rt-core/cubemx/txt/CM4/Src/main.c | 1144 +
.../cubemx/txt/CM4/Src/mbox_ipcc.c | 182 +
txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp.c | 176 +
.../cubemx/txt/CM4/Src/openamp_log.c | 102 +
.../cubemx/txt/CM4/Src/rsc_table.c | 174 +
.../cubemx/txt/CM4/Src/stm32mp1xx_hal_msp.c | 857 +
.../cubemx/txt/CM4/Src/stm32mp1xx_it.c | 228 +
txt2-M4-rt-core/cubemx/txt/CM4/Src/syscalls.c | 207 +
.../txt/Common/System/system_stm32mp1xx.c | 290 +
.../ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h | 32050 ++++++++++++++++
.../Device/ST/STM32MP1xx/Include/stm32mp1xx.h | 228 +
.../ST/STM32MP1xx/Include/system_stm32mp1xx.h | 106 +
.../txt/Drivers/CMSIS/Include/cmsis_armcc.h | 865 +
.../Drivers/CMSIS/Include/cmsis_armclang.h | 1869 +
.../Drivers/CMSIS/Include/cmsis_compiler.h | 266 +
.../txt/Drivers/CMSIS/Include/cmsis_gcc.h | 2085 +
.../txt/Drivers/CMSIS/Include/cmsis_iccarm.h | 935 +
.../txt/Drivers/CMSIS/Include/cmsis_version.h | 39 +
.../txt/Drivers/CMSIS/Include/core_armv8mbl.h | 1918 +
.../txt/Drivers/CMSIS/Include/core_armv8mml.h | 2927 ++
.../txt/Drivers/CMSIS/Include/core_cm0.h | 949 +
.../txt/Drivers/CMSIS/Include/core_cm0plus.h | 1083 +
.../txt/Drivers/CMSIS/Include/core_cm1.h | 976 +
.../txt/Drivers/CMSIS/Include/core_cm23.h | 1993 +
.../txt/Drivers/CMSIS/Include/core_cm3.h | 1941 +
.../txt/Drivers/CMSIS/Include/core_cm33.h | 3002 ++
.../txt/Drivers/CMSIS/Include/core_cm4.h | 2129 +
.../txt/Drivers/CMSIS/Include/core_cm7.h | 2671 ++
.../txt/Drivers/CMSIS/Include/core_sc000.h | 1022 +
.../txt/Drivers/CMSIS/Include/core_sc300.h | 1915 +
.../txt/Drivers/CMSIS/Include/mpu_armv7.h | 270 +
.../txt/Drivers/CMSIS/Include/mpu_armv8.h | 333 +
.../txt/Drivers/CMSIS/Include/tz_context.h | 70 +
.../Inc/Legacy/stm32_hal_legacy.h | 3780 ++
.../Inc/stm32mp1xx_hal.h | 802 +
.../Inc/stm32mp1xx_hal_adc.h | 1814 +
.../Inc/stm32mp1xx_hal_adc_ex.h | 1113 +
.../Inc/stm32mp1xx_hal_cortex.h | 441 +
.../Inc/stm32mp1xx_hal_def.h | 199 +
.../Inc/stm32mp1xx_hal_dma.h | 952 +
.../Inc/stm32mp1xx_hal_dma_ex.h | 256 +
.../Inc/stm32mp1xx_hal_exti.h | 371 +
.../Inc/stm32mp1xx_hal_fdcan.h | 2319 ++
.../Inc/stm32mp1xx_hal_gpio.h | 362 +
.../Inc/stm32mp1xx_hal_gpio_ex.h | 317 +
.../Inc/stm32mp1xx_hal_hsem.h | 210 +
.../Inc/stm32mp1xx_hal_ipcc.h | 291 +
.../Inc/stm32mp1xx_hal_mdma.h | 858 +
.../Inc/stm32mp1xx_hal_pwr.h | 496 +
.../Inc/stm32mp1xx_hal_pwr_ex.h | 440 +
.../Inc/stm32mp1xx_hal_rcc.h | 4493 +++
.../Inc/stm32mp1xx_hal_rcc_ex.h | 2028 +
.../Inc/stm32mp1xx_hal_spi.h | 1092 +
.../Inc/stm32mp1xx_hal_spi_ex.h | 77 +
.../Inc/stm32mp1xx_hal_tim.h | 2222 ++
.../Inc/stm32mp1xx_hal_tim_ex.h | 449 +
.../Inc/stm32mp1xx_hal_uart.h | 1631 +
.../Inc/stm32mp1xx_hal_uart_ex.h | 509 +
.../Inc/stm32mp1xx_ll_adc.h | 7207 ++++
.../Src/stm32mp1xx_hal.c | 941 +
.../Src/stm32mp1xx_hal_adc.c | 3740 ++
.../Src/stm32mp1xx_hal_adc_ex.c | 2466 ++
.../Src/stm32mp1xx_hal_cortex.c | 439 +
.../Src/stm32mp1xx_hal_dma.c | 1591 +
.../Src/stm32mp1xx_hal_dma_ex.c | 603 +
.../Src/stm32mp1xx_hal_exti.c | 767 +
.../Src/stm32mp1xx_hal_fdcan.c | 5097 +++
.../Src/stm32mp1xx_hal_gpio.c | 565 +
.../Src/stm32mp1xx_hal_hsem.c | 437 +
.../Src/stm32mp1xx_hal_ipcc.c | 780 +
.../Src/stm32mp1xx_hal_mdma.c | 1854 +
.../Src/stm32mp1xx_hal_pwr.c | 781 +
.../Src/stm32mp1xx_hal_pwr_ex.c | 798 +
.../Src/stm32mp1xx_hal_rcc.c | 2701 ++
.../Src/stm32mp1xx_hal_rcc_ex.c | 3408 ++
.../Src/stm32mp1xx_hal_spi.c | 3796 ++
.../Src/stm32mp1xx_hal_spi_ex.c | 229 +
.../Src/stm32mp1xx_hal_tim.c | 6917 ++++
.../Src/stm32mp1xx_hal_tim_ex.c | 2381 ++
.../Src/stm32mp1xx_hal_uart.c | 4579 +++
.../Src/stm32mp1xx_hal_uart_ex.c | 729 +
.../Src/stm32mp1xx_ll_adc.c | 1071 +
.../FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h | 846 +
.../FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c | 1924 +
.../FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h | 734 +
.../Third_Party/FreeRTOS/Source/croutine.c | 353 +
.../FreeRTOS/Source/event_groups.c | 753 +
.../FreeRTOS/Source/include/FreeRTOS.h | 1278 +
.../FreeRTOS/Source/include/StackMacros.h | 133 +
.../FreeRTOS/Source/include/croutine.h | 720 +
.../Source/include/deprecated_definitions.h | 279 +
.../FreeRTOS/Source/include/event_groups.h | 757 +
.../FreeRTOS/Source/include/list.h | 412 +
.../FreeRTOS/Source/include/message_buffer.h | 799 +
.../FreeRTOS/Source/include/mpu_prototypes.h | 157 +
.../FreeRTOS/Source/include/mpu_wrappers.h | 186 +
.../FreeRTOS/Source/include/portable.h | 181 +
.../FreeRTOS/Source/include/projdefs.h | 124 +
.../FreeRTOS/Source/include/queue.h | 1655 +
.../FreeRTOS/Source/include/semphr.h | 1140 +
.../FreeRTOS/Source/include/stack_macros.h | 129 +
.../FreeRTOS/Source/include/stream_buffer.h | 855 +
.../FreeRTOS/Source/include/task.h | 2421 ++
.../FreeRTOS/Source/include/timers.h | 1295 +
.../Third_Party/FreeRTOS/Source/list.c | 198 +
.../Source/portable/GCC/ARM_CM4F/port.c | 775 +
.../Source/portable/GCC/ARM_CM4F/portmacro.h | 243 +
.../FreeRTOS/Source/portable/MemMang/heap_4.c | 436 +
.../Third_Party/FreeRTOS/Source/queue.c | 2941 ++
.../FreeRTOS/Source/stream_buffer.c | 1263 +
.../Third_Party/FreeRTOS/Source/tasks.c | 5214 +++
.../Third_Party/FreeRTOS/Source/timers.c | 1102 +
.../Third_Party/OpenAMP/libmetal/lib/device.c | 167 +
.../libmetal/lib/include/metal/alloc.h | 46 +
.../libmetal/lib/include/metal/assert.h | 24 +
.../libmetal/lib/include/metal/atomic.h | 32 +
.../libmetal/lib/include/metal/cache.h | 57 +
.../libmetal/lib/include/metal/compiler.h | 25 +
.../lib/include/metal/compiler/gcc/atomic.h | 123 +
.../lib/include/metal/compiler/gcc/compiler.h | 27 +
.../lib/include/metal/compiler/iar/compiler.h | 27 +
.../lib/include/metal/compiler/iar/errno.h | 118 +
.../include/metal/compiler/mdk-arm/errno.h | 137 +
.../libmetal/lib/include/metal/condition.h | 73 +
.../libmetal/lib/include/metal/config.h | 50 +
.../OpenAMP/libmetal/lib/include/metal/cpu.h | 17 +
.../libmetal/lib/include/metal/device.h | 176 +
.../OpenAMP/libmetal/lib/include/metal/dma.h | 79 +
.../libmetal/lib/include/metal/errno.h | 24 +
.../OpenAMP/libmetal/lib/include/metal/io.h | 354 +
.../OpenAMP/libmetal/lib/include/metal/irq.h | 116 +
.../OpenAMP/libmetal/lib/include/metal/list.h | 102 +
.../OpenAMP/libmetal/lib/include/metal/log.h | 93 +
.../libmetal/lib/include/metal/mutex.h | 87 +
.../lib/include/metal/processor/arm/atomic.h | 15 +
.../lib/include/metal/processor/arm/cpu.h | 17 +
.../libmetal/lib/include/metal/shmem.h | 83 +
.../libmetal/lib/include/metal/sleep.h | 44 +
.../libmetal/lib/include/metal/spinlock.h | 71 +
.../OpenAMP/libmetal/lib/include/metal/sys.h | 148 +
.../lib/include/metal/system/generic/alloc.h | 39 +
.../lib/include/metal/system/generic/assert.h | 28 +
.../lib/include/metal/system/generic/cache.h | 40 +
.../include/metal/system/generic/condition.h | 73 +
.../metal/system/generic/cortexm/sys.h | 65 +
.../lib/include/metal/system/generic/io.h | 44 +
.../lib/include/metal/system/generic/irq.h | 34 +
.../lib/include/metal/system/generic/log.h | 52 +
.../lib/include/metal/system/generic/mutex.h | 79 +
.../lib/include/metal/system/generic/sleep.h | 38 +
.../lib/include/metal/system/generic/sys.h | 61 +
.../OpenAMP/libmetal/lib/include/metal/time.h | 41 +
.../libmetal/lib/include/metal/utilities.h | 152 +
.../libmetal/lib/include/metal/version.h | 76 +
.../Third_Party/OpenAMP/libmetal/lib/init.c | 34 +
.../Third_Party/OpenAMP/libmetal/lib/io.c | 139 +
.../Third_Party/OpenAMP/libmetal/lib/log.c | 62 +
.../Third_Party/OpenAMP/libmetal/lib/shmem.c | 48 +
.../libmetal/lib/system/generic/condition.c | 49 +
.../libmetal/lib/system/generic/cortexm/sys.c | 77 +
.../lib/system/generic/generic_device.c | 32 +
.../lib/system/generic/generic_init.c | 28 +
.../libmetal/lib/system/generic/generic_io.c | 31 +
.../lib/system/generic/generic_shmem.c | 18 +
.../libmetal/lib/system/generic/time.c | 19 +
.../open-amp/lib/include/openamp/compiler.h | 71 +
.../open-amp/lib/include/openamp/elf_loader.h | 428 +
.../open-amp/lib/include/openamp/open_amp.h | 17 +
.../open-amp/lib/include/openamp/remoteproc.h | 871 +
.../lib/include/openamp/remoteproc_loader.h | 108 +
.../lib/include/openamp/remoteproc_virtio.h | 150 +
.../open-amp/lib/include/openamp/rpmsg.h | 358 +
.../lib/include/openamp/rpmsg_retarget.h | 119 +
.../lib/include/openamp/rpmsg_virtio.h | 190 +
.../lib/include/openamp/rsc_table_parser.h | 64 +
.../open-amp/lib/include/openamp/virtio.h | 176 +
.../lib/include/openamp/virtio_ring.h | 152 +
.../open-amp/lib/include/openamp/virtqueue.h | 236 +
.../lib/remoteproc/remoteproc_virtio.c | 330 +
.../OpenAMP/open-amp/lib/rpmsg/CMakeLists.txt | 2 +
.../OpenAMP/open-amp/lib/rpmsg/rpmsg.c | 270 +
.../open-amp/lib/rpmsg/rpmsg_internal.h | 105 +
.../OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c | 692 +
.../OpenAMP/open-amp/lib/virtio/virtio.c | 121 +
.../OpenAMP/open-amp/lib/virtio/virtqueue.c | 618 +
.../OpenAMP/virtual_driver/virt_uart.c | 128 +
.../OpenAMP/virtual_driver/virt_uart.h | 76 +
.../cubemx/txt/startup/startup_stm32mp15xx.s | 792 +
txt2-M4-rt-core/cubemx/txt/stm32mp15xx_m4.ld | 202 +
txt2-M4-rt-core/cubemx/txt/txt2.ioc | 1399 +
txt2-M4-rt-core/cubemx/txt/txt2.xml | 9 +
.../txt2-rev0/CM4/Inc/stm32mp1xx_hal_conf.h | 4 +-
.../Inc/Legacy/stm32_hal_legacy.h | 4 +
.../Inc/stm32mp1xx_hal_adc.h | 4 +
.../Inc/stm32mp1xx_hal_spi.h | 4 +-
.../Inc/stm32mp1xx_hal_tim.h | 6 +-
.../Inc/stm32mp1xx_hal_tim_ex.h | 15 +
.../Inc/stm32mp1xx_hal_uart.h | 7 +-
.../Src/stm32mp1xx_hal_adc.c | 4 +
.../Src/stm32mp1xx_hal_adc_ex.c | 7 +
.../Src/stm32mp1xx_hal_spi.c | 22 +-
.../Src/stm32mp1xx_hal_tim.c | 19 +-
.../Src/stm32mp1xx_hal_tim_ex.c | 18 +-
.../Src/stm32mp1xx_hal_uart.c | 62 +-
.../cubemx/txt2/CM4/Inc/stm32mp1xx_hal_conf.h | 4 +-
.../Inc/Legacy/stm32_hal_legacy.h | 4 +
.../Inc/stm32mp1xx_hal_adc.h | 4 +
.../Inc/stm32mp1xx_hal_spi.h | 4 +-
.../Inc/stm32mp1xx_hal_tim.h | 5 +-
.../Inc/stm32mp1xx_hal_tim_ex.h | 4 +
.../Inc/stm32mp1xx_hal_uart.h | 2 +
.../Src/stm32mp1xx_hal_adc.c | 5 +-
.../Src/stm32mp1xx_hal_adc_ex.c | 10 +-
.../Src/stm32mp1xx_hal_spi.c | 36 +-
.../Src/stm32mp1xx_hal_tim.c | 20 +-
.../Src/stm32mp1xx_hal_tim_ex.c | 11 +-
.../Src/stm32mp1xx_hal_uart.c | 57 +-
txt2-M4-rt-core/ft/ft.hpp | 6 +
txt2-M4-rt-core/ft/ftop.h | 14 +
txt2-M4-rt-core/ft/ftslave.h | 14 +
txt2-M4-rt-core/ftinc/ftcmdline.h | 72 +
txt2-M4-rt-core/ftinc/ftext.h | 10 +-
txt2-M4-rt-core/ftinc/ftimpltypes.h | 23 +
txt2-M4-rt-core/ftinc/ftinc.i | 15 +
txt2-M4-rt-core/ftinc/ftlibtypes.h | 2 +-
txt2-M4-rt-core/ftinc/ftshmem.h | 11 +-
txt2-M4-rt-core/ftsrc/ftext.c | 1 +
txt2-M4-rt-core/ftsrc/ftserver.c | 29 +-
txt2-M4-rt-core/ftutil/ftcmdline.c | 203 +
txt2-M4-rt-core/ftutil/ftctrl.cpp | 177 +
txt2-M4-rt-core/ftutil/txt_servo_setpos.cpp | 76 +
txt2-M4-rt-core/inc/HWServo.h | 8 +
txt2-M4-rt-core/inc/mcommon.h | 4 +-
txt2-M4-rt-core/pyexamples/tdiscovery.py | 14 +-
txt2-M4-rt-core/src/HWServo.c | 60 +-
txt2-M4-rt-core/utils/install.sh | 36 +
262 files changed, 196243 insertions(+), 121 deletions(-)
create mode 100644 build.sh
delete mode 120000 txt2-M4-rt-core/cubemx/txt
create mode 100644 txt2-M4-rt-core/cubemx/txt/.cproject
create mode 100644 txt2-M4-rt-core/cubemx/txt/.mxproject
create mode 100644 txt2-M4-rt-core/cubemx/txt/.project
create mode 100644 txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/kernel/stm32mp157c-txt2-mx.dts
create mode 100644 txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp15-mx.dtsi
create mode 100644 txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp157c-txt2-mx.dts
create mode 100644 txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp15-mx.dtsi
create mode 100644 txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx-u-boot.dtsi
create mode 100644 txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts
create mode 100644 txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts.bak
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/FreeRTOSConfig.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/main.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/mbox_ipcc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_conf.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_log.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/rsc_table.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_hal_conf.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_it.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/app_freertos.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/main.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/mbox_ipcc.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp_log.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/rsc_table.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_hal_msp.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_it.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/CM4/Src/syscalls.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Common/System/system_stm32mp1xx.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armcc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armclang.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_compiler.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_gcc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_iccarm.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_version.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mbl.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mml.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0plus.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm1.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm23.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm3.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm33.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm4.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm7.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc000.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc300.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv7.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv8.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/tz_context.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cortex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_fdcan.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_hsem.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/list.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/queue.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/timers.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/device.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/alloc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/assert.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/atomic.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cache.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/atomic.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/compiler.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/compiler.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/errno.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/mdk-arm/errno.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/condition.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/config.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cpu.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/device.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/dma.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/errno.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/io.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/irq.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/list.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/log.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/mutex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/atomic.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/cpu.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/shmem.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sleep.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/spinlock.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sys.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/assert.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cache.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/condition.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cortexm/sys.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/io.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/irq.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/log.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/mutex.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sleep.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sys.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/time.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/utilities.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/version.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/init.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/io.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/log.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/shmem.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/condition.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_device.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_init.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_io.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_shmem.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/time.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/compiler.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/elf_loader.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/open_amp.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_loader.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_virtio.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_retarget.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_virtio.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rsc_table_parser.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio_ring.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtqueue.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/remoteproc/remoteproc_virtio.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/CMakeLists.txt
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_internal.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtio.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtqueue.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.c
create mode 100644 txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.h
create mode 100644 txt2-M4-rt-core/cubemx/txt/startup/startup_stm32mp15xx.s
create mode 100644 txt2-M4-rt-core/cubemx/txt/stm32mp15xx_m4.ld
create mode 100644 txt2-M4-rt-core/cubemx/txt/txt2.ioc
create mode 100644 txt2-M4-rt-core/cubemx/txt/txt2.xml
create mode 100644 txt2-M4-rt-core/ftinc/ftcmdline.h
create mode 100644 txt2-M4-rt-core/ftutil/ftcmdline.c
create mode 100644 txt2-M4-rt-core/ftutil/ftctrl.cpp
create mode 100644 txt2-M4-rt-core/ftutil/txt_servo_setpos.cpp
create mode 100644 txt2-M4-rt-core/utils/install.sh
diff --git a/build.sh b/build.sh
new file mode 100644
index 0000000..4bb1345
--- /dev/null
+++ b/build.sh
@@ -0,0 +1,376 @@
+#!/bin/bash
+this_script=$(realpath -s "$0")
+scripts_path=$(dirname "$this_script")
+real_project_dir="$scripts_path"
+PROJECT_DIR="$scripts_path"
+startup_params="$*"
+startup_params="${startup_params/\$real_project_dir/\%project_dir\%}"
+
+cd $scripts_path
+
+if [ ! -f /.dockerenv ]; then
+ git submodule update --init --recursive
+ git pull --recurse-submodules
+
+ echo "Starting Docker Container..."
+ cd "$(cd "$(dirname "$0")"; pwd)"
+ docker compose down
+ docker compose pull
+ docker compose up -d
+ docker exec -it "builder" bash -c "cd /workspace;chmod +x build.sh;./build.sh $startup_params"
+ exit $?
+fi
+
+#
+# Print command (GREEN)
+#
+# $1 string to print
+#
+print_command() {
+ GREEN='\033[1;32m'
+ NC='\033[0m' # No Color
+ printf "${GREEN}$1${NC}\n"
+}
+
+#
+# Print command (GREEN)
+#
+# $1 string to print
+#
+print_green() {
+ GREEN='\033[1;32m'
+ NC='\033[0m' # No Color
+ printf "${GREEN}$1${NC}\n"
+}
+
+#
+# Print blue
+#
+# $1 string to print
+#
+print_blue() {
+ BLUE='\033[1;34m'
+ NC='\033[0m' # No Color
+ printf "${BLUE}$1${NC}\n"
+}
+
+#
+# Print error (RED)
+#
+# $1 string to print
+#
+print_red() {
+ RED='\033[1;31m'
+ NC='\033[0m' # No Color
+ printf "${RED}$1${NC}\n"
+}
+
+#
+# Print error (RED)
+#
+# $1 string to print
+#
+print_error() {
+ RED='\033[1;31m'
+ NC='\033[0m' # No Color
+ printf "${RED}$1${NC}\n"
+}
+
+#
+# Display new section
+#
+# $1 Section name
+#
+display_section() {
+ print_blue " "
+ print_blue "##########################################"
+ print_blue "## $*"
+ print_blue "##########################################"
+ print_blue " "
+}
+
+#
+# Display error
+#
+# $1 Error
+#
+exit_with_error() {
+ print_error " "
+ print_error "##########################################"
+ print_error "## Error: $1"
+ print_error "##########################################"
+ print_error " "
+ if [ ! "$2" ]
+ then
+ exit 1
+ fi
+ exit $2
+}
+
+export -f print_command
+export -f print_red
+export -f print_green
+export -f print_blue
+export -f print_error
+export -f display_section
+export -f exit_with_error
+
+if [ ! "${CPU_ARCH}" ]
+then
+ echo CPU_ARCH is not defined, using armhf as default
+ CPU_ARCH="armhf"
+fi
+
+if [ ! "${CPU_COMPILER_PREFIX}" ]
+then
+ echo CPU_COMPILER_PREFIX is not defined, using arm-linux-gnueabihf as default
+ CPU_COMPILER_PREFIX="arm-linux-gnueabihf"
+fi
+
+if [ ! "${MCU_COMPILER_PREFIX}" ]
+then
+ echo MCU_COMPILER_PREFIX is not defined, using arm-none-eabi as default
+ MCU_COMPILER_PREFIX="arm-none-eabi"
+fi
+
+if [ ! "${SRC_DIR}" ]
+then
+ echo SRC_DIR is not defined, using $PROJECT_DIR/txt2-M4-rt-core as default
+ SRC_DIR="$PROJECT_DIR/txt2-M4-rt-core"
+fi
+
+if [ ! "${BUILD_DIR}" ]
+then
+ echo BUILD_DIR is not defined, using $PROJECT_DIR/build as default
+ BUILD_DIR="$SRC_DIR/build"
+fi
+
+if [ ! "${ARTIFACTS_DIR}" ]
+then
+ echo ARTIFACTS_DIR is not defined, using $PROJECT_DIR/release as default
+ ARTIFACTS_DIR="$PROJECT_DIR/release"
+fi
+
+if [ ! "${CROSS_COMPILE}" ]
+then
+ echo CROSS_COMPILE is not defined, using /usr/bin/${CPU_COMPILER_PREFIX}- as default
+ CROSS_COMPILE="/usr/bin/${CPU_COMPILER_PREFIX}-"
+fi
+
+export LANGUAGE=en_US.UTF-8
+export LANG=en_US.UTF-8
+export LC_ALL=en_US.UTF-8#
+export DEBIAN_FRONTEND=noninteractive
+export DEBIAN_PRIORITY=critical
+export CPU_ARCH=${CPU_ARCH}
+export CPU_COMPILER_PREFIX=${CPU_COMPILER_PREFIX}
+export MCU_COMPILER_PREFIX=${MCU_COMPILER_PREFIX}
+export BUILD_DIR=${BUILD_DIR}
+
+GLIBC_VERSION="2.28"
+
+prepare_locale()
+{
+ apt-get update || true
+ apt-get upgrade -yq
+
+ apt-get install -yq locales locales-all
+ sed -i -e 's/# en_US.UTF-8 UTF-8/en_US.UTF-8 UTF-8/' /etc/locale.gen && \
+ dpkg-reconfigure --frontend=noninteractive locales && \
+ update-locale LANG=en_US.UTF-8
+ ln -fs /usr/share/zoneinfo/Europe/Berlin /etc/localtime || true
+}
+
+prepare_repo()
+{
+ display_section Preparing APT-Repository...
+ . /etc/os-release
+ dpkg --add-architecture ${CPU_ARCH}
+ echo "deb [arch=amd64,i386] http://us.archive.ubuntu.com/ubuntu/ $UBUNTU_CODENAME main restricted universe multiverse" > /etc/apt/sources.list
+ echo "deb [arch=amd64,i386] http://us.archive.ubuntu.com/ubuntu/ $UBUNTU_CODENAME-updates main restricted universe multiverse" >> /etc/apt/sources.list
+ echo "deb [arch=amd64,i386] http://us.archive.ubuntu.com/ubuntu/ $UBUNTU_CODENAME-backports main restricted universe multiverse" >> /etc/apt/sources.list
+ echo "deb [arch=amd64,i386] http://security.ubuntu.com/ubuntu $UBUNTU_CODENAME-security main restricted universe multiverse" >> /etc/apt/sources.list
+ echo "deb [arch=${CPU_ARCH}] http://ports.ubuntu.com/ubuntu-ports/ $UBUNTU_CODENAME main restricted universe multiverse" >> /etc/apt/sources.list
+ echo "deb [arch=${CPU_ARCH}] http://ports.ubuntu.com/ubuntu-ports/ $UBUNTU_CODENAME-updates main restricted universe multiverse" >> /etc/apt/sources.list
+ echo "deb [arch=${CPU_ARCH}] http://ports.ubuntu.com/ubuntu-ports/ $UBUNTU_CODENAME-backports main restricted universe multiverse" >> /etc/apt/sources.list
+ echo "deb [arch=${CPU_ARCH}] http://ports.ubuntu.com/ubuntu-ports/ $UBUNTU_CODENAME-security main restricted universe multiverse" >> /etc/apt/sources.list
+ apt update
+}
+
+prepare_host_dependencies()
+{
+ display_section "Preparing host dependencies..."
+ apt update
+ apt install git swig bison flex cmake automake python3-sip libpython3-dev python3-dev libc6 libc6-dev build-essential libmawk-dev gawk -yq || exit_with_error "Could not install host dependencies"
+}
+
+prepare_cross_compiler()
+{
+ display_section "Preparing cross compiler..."
+ apt update
+ apt install binutils-${MCU_COMPILER_PREFIX} gcc-${MCU_COMPILER_PREFIX} -yq || exit_with_error "Could not install cross compiler dependencies"
+ apt install libc6-dev-armhf-cross libc6-armhf-cross binutils-${CPU_COMPILER_PREFIX} gcc-${CPU_COMPILER_PREFIX} g++-${CPU_COMPILER_PREFIX} pkg-config-${CPU_COMPILER_PREFIX} -yq || exit_with_error "Could not install cross compiler dependencies"
+}
+
+prepare_target_dependencies()
+{
+ display_section "Preparing target dependencies..."
+ apt update
+ apt install gawk:${CPU_ARCH} libmosquitto-dev:${CPU_ARCH} libmosquittopp-dev:${CPU_ARCH} libssl-dev:${CPU_ARCH} openssl:${CPU_ARCH} libudev-dev:${CPU_ARCH} python3-dev:${CPU_ARCH} libpython3-dev:${CPU_ARCH} -yq || exit_with_error "Could not install target dependencies"
+
+ export CROSS_COMPILE="/usr/bin/${MCU_COMPILER_PREFIX}-"
+ if [ -d "/usr/lib/${MCU_COMPILER_PREFIX}" ]
+ then
+ export LIBDIR="/usr/lib/${MCU_COMPILER_PREFIX}"
+ else
+ export LIBDIR="/usr/lib"
+ fi
+ if [ -d "/usr/include/${MCU_COMPILER_PREFIX}" ]
+ then
+ export INCDIR="/usr/include/${MCU_COMPILER_PREFIX}"
+ else
+ export LIBDIR="/usr/include"
+ fi
+
+ export glibc_install="$(pwd)/glibc/build/install"
+
+ git clone git://sourceware.org/git/glibc.git
+ cd glibc
+ git checkout glibc-${GLIBC_VERSION}
+ mkdir build
+ cd build
+
+ #../configure --disable-sanity-checks
+ ../configure --prefix "$glibc_install" --disable-werror --enable-cet --host=${CPU_COMPILER_PREFIX}
+ make -j $(nproc) >> /dev/null
+ make install -j $(nproc)
+
+ ls ${glibc_install}/lib/
+ export CFLAGS="${CFLAGS} -L ${glibc_install}/lib -I ${glibc_install}/include -Wl,--rpath=${glibc_install}/lib -Wl,--dynamic-linker=${glibc_install}/lib/ld-linux-armhf.so.3"
+ export CXXFLAGS="${CXXFLAGS} -L ${glibc_install}/lib -I ${glibc_install}/include -Wl,--rpath=${glibc_install}/lib -Wl,--dynamic-linker=${glibc_install}/lib/ld-linux-armhf.so.3"
+
+}
+
+cd $PROJECT_DIR
+
+case "${1}" in
+ "prepare")
+ display_section "Start preparing build..."
+ mkdir -p $BUILD_DIR
+ mkdir -p $ARTIFACTS_DIR
+ rm $BUILD_DIR/* || true
+ rm $ARTIFACTS_DIR/* || true
+ prepare_locale
+ prepare_repo
+ prepare_host_dependencies
+ prepare_cross_compiler
+ prepare_target_dependencies
+ ;;
+ "build")
+ bash $this_script "build_libs"
+ errorcode=$?
+ if [ "$errorcode" != "0" ]
+ then
+ exit_with_error "Building libraries failed..." $errorcode
+ fi
+ bash $this_script "build_firmware"
+ errorcode=$?
+ if [ "$errorcode" != "0" ]
+ then
+ exit_with_error "Building RT core firmware failed..." $errorcode
+ fi
+ ;;
+ "build_libs")
+ display_section "Building libraries..."
+ export CROSS_COMPILE="/usr/bin/${CPU_COMPILER_PREFIX}-"
+ if [ -d "/usr/lib/${CPU_COMPILER_PREFIX}" ]
+ then
+ export LIBDIR="/usr/lib/${CPU_COMPILER_PREFIX}"
+ else
+ export LIBDIR="/usr/lib"
+ fi
+ if [ -d "/usr/include/${CPU_COMPILER_PREFIX}" ]
+ then
+ export INCDIR="/usr/include/${CPU_COMPILER_PREFIX}"
+ else
+ export LIBDIR="/usr/include"
+ fi
+ cd $BUILD_DIR
+ PROCESSOR_ARCHITECTURE=arm cmake ../ -DCMAKE_CROSSCOMPILING=1 -DCMAKE_C_COMPILER=${CPU_COMPILER_PREFIX}-gcc -DCMAKE_CXX_COMPILER=${CPU_COMPILER_PREFIX}-g++ -DUSE_PYTHON=YES -DCMAKE_SYSTEM_PROCESSOR=arm -DCMAKE_SYSTEM_NAME=linux
+ make
+ ;;
+ "build_firmware")
+ display_section "Building firmware..."
+ cd $BUILD_DIR
+ export CROSS_COMPILE="/usr/bin/${MCU_COMPILER_PREFIX}-"
+ if [ -d "/usr/lib/${MCU_COMPILER_PREFIX}" ]
+ then
+ export LIBDIR="/usr/lib/${MCU_COMPILER_PREFIX}"
+ else
+ export LIBDIR="/usr/lib"
+ fi
+ if [ -d "/usr/include/${MCU_COMPILER_PREFIX}" ]
+ then
+ export INCDIR="/usr/include/${MCU_COMPILER_PREFIX}"
+ else
+ export LIBDIR="/usr/include"
+ fi
+
+ make -f ../Makefile.stm32 clean
+ make -f ../Makefile.stm32 all
+ ;;
+ "after_build")
+ ls -l $BUILD_DIR
+ rm -R $BUILD_DIR/CMakeFiles || true
+ rm $BUILD_DIR/CMakeCache.txt || true
+ rm $BUILD_DIR/Makefile || true
+ rm $BUILD_DIR/cmake_install.cmake || true
+ rm -R $BUILD_DIR/rev0 || true
+ rm -R $BUILD_DIR/rev1 || true
+ rm $BUILD_DIR/*.map || true
+ rm $BUILD_DIR/*.sym || true
+ rm $BUILD_DIR/*.bin || true
+ cp $SRC_DIR/utils/install.sh $BUILD_DIR/install.sh || true
+ chmod +x $BUILD_DIR/install.sh || true
+ mkdir -p $BUILD_DIR/includes || true
+ cp -drv $SRC_DIR/ft $BUILD_DIR/includes/ || true
+ cp -R $BUILD_DIR/* $ARTIFACTS_DIR/
+ mkdir -p $ARTIFACTS_DIR/firmware
+ mv $ARTIFACTS_DIR/*.elf $ARTIFACTS_DIR/firmware/
+ ;;
+ "")
+ bash $this_script "prepare"
+ errorcode=$?
+ if [ "$errorcode" != "0" ]
+ then
+ exit_with_error "Prepare stage failed..." $errorcode
+ fi
+ bash $this_script "build"
+ errorcode=$?
+ if [ "$errorcode" != "0" ]
+ then
+ exit_with_error "Build stage failed..." $errorcode
+ fi
+ bash $this_script "after_build"
+ errorcode=$?
+ if [ "$errorcode" != "0" ]
+ then
+ exit_with_error "After build stage failed..." $errorcode
+ fi
+ bash $this_script "cleanup"
+ errorcode=$?
+ if [ "$errorcode" != "0" ]
+ then
+ exit_with_error "Cleanup stage failed..." $errorcode
+ fi
+ exit 0;
+ ;;
+ "cleanup")
+ display_section "Cleanup..."
+
+ exit 0
+ ;;
+ *)
+ echo "ERROR: not supported..."
+ ;;
+esac
diff --git a/txt2-M4-rt-core/CMakeLists.txt b/txt2-M4-rt-core/CMakeLists.txt
index 1fd007a..e1940f4 100644
--- a/txt2-M4-rt-core/CMakeLists.txt
+++ b/txt2-M4-rt-core/CMakeLists.txt
@@ -6,6 +6,8 @@ set(LIB_VERSION_MINOR 2)
set(LIB_VERSION_PATCH 0)
set(LIB_VERSION_STRING ${LIB_VERSION_MAJOR}.${LIB_VERSION_MINOR}.${LIB_VERSION_PATCH})
set(CMAKE_SKIP_BUILD_RPATH TRUE)
+message("CMAKE_SYSTEM_PROCESSOR ${CMAKE_SYSTEM_PROCESSOR}")
+message("CMAKE_SYSTEM_NAME ${CMAKE_SYSTEM_NAME}")
if (NOT USE_PYTHON)
set(USE_PYTHON NO)
@@ -80,6 +82,26 @@ target_compile_options(ftcalib
-Wextra
-Wfatal-errors)
+
+
+add_executable(txt_servo_setpos ftutil/txt_servo_setpos.cpp)
+ target_include_directories(txt_servo_setpos PRIVATE ftinc ft)
+ target_link_libraries(txt_servo_setpos PRIVATE pthread TxtControlLib cftlock m)
+ target_compile_options(txt_servo_setpos
+ PRIVATE -Wall
+ -Wpedantic
+ -Wextra
+ -Wfatal-errors)
+
+add_executable(fttxtctrl ftutil/ftctrl.cpp ftutil/ftcmdline.c)
+ target_include_directories(fttxtctrl PRIVATE ftinc ft)
+ target_link_libraries(fttxtctrl PRIVATE pthread TxtControlLib cftlock m)
+ target_compile_options(fttxtctrl
+ PRIVATE -Wall
+ -Wpedantic
+ -Wextra
+ -Wfatal-errors)
+
add_executable(ftdaemon ftutil/ftdaemon.c)
target_include_directories(ftdaemon PRIVATE ftinc ft)
target_link_libraries(ftdaemon PRIVATE pthread TxtControlLib)
diff --git a/txt2-M4-rt-core/TxtControlLib/TxtControlLib.c b/txt2-M4-rt-core/TxtControlLib/TxtControlLib.c
index cece08f..89ce238 100644
--- a/txt2-M4-rt-core/TxtControlLib/TxtControlLib.c
+++ b/txt2-M4-rt-core/TxtControlLib/TxtControlLib.c
@@ -359,53 +359,30 @@ static void *ftopThread(void *info)
return NULL;
}
-/**
- * @brief Get the Servo Min Max calibration values
- *
- * @param num Servo number 1-3
- * @param [out] pu16Min Servo minimum calibration value
- * @param [out] pu16Max Servo maximum calibration value
- */
-static void getServoMinMax(int num, uint16_t* pu16Min, uint16_t* pu16Max)
+static int readServoConfigCommand(int num,char* outData,int maxData)
{
FILE *fp;
- char buffer[128];
- char valName[20];
- char* pstr;
- int i;
-
- memset(buffer,0,sizeof(buffer));
- memset(valName,0,sizeof(valName));
-
- if ((pu16Min == NULL) || (pu16Max == NULL))
- {
- return;
- }
-
- *pu16Min = 600;
- *pu16Max = 2400;
- switch (num)
- {
- case 1:
- fp = popen("/usr/bin/sudo -n /usr/sbin/txt_servo getvalues 1", "r");
- break;
- case 2:
- fp = popen("/usr/bin/sudo -n /usr/sbin/txt_servo getvalues 2", "r");
- break;
- case 3:
- fp = popen("/usr/bin/sudo -n /usr/sbin/txt_servo getvalues 3", "r");
- break;
- default:
- return;
- }
+ char cmdString[64] = {0};
+ sprintf(cmdString,"/usr/bin/sudo -n /usr/sbin/txt_servo getvalues %d",num);
+ fp = popen(cmdString, "r");
if (fp == NULL) {
- return;
+ return -1;
}
- while (fgets(buffer, sizeof(buffer), fp) != NULL) {
+ while (fgets(outData, maxData, fp) != NULL) {
//printf("%s", buffer);
}
pclose(fp);
+ return 0;
+}
+
+static int parseServoConfigCommand(char* buffer, uint16_t* pu16Min, uint16_t* pu16Max)
+{
+ char valName[20];
+ char* pstr;
+ int i;
+
+ memset(valName,0,sizeof(valName));
pstr=buffer;
valName[0] = 0;
@@ -441,15 +418,51 @@ static void getServoMinMax(int num, uint16_t* pu16Min, uint16_t* pu16Max)
}
}
}
+ return 0;
+}
+
+/**
+ * @brief Get the Servo Min Max calibration values
+ *
+ * @param num Servo number 1-3
+ * @param [out] pu16Min Servo minimum calibration value
+ * @param [out] pu16Max Servo maximum calibration value
+ */
+static void getServoMinMax(int num, uint16_t* pu16Min, uint16_t* pu16Max)
+{
+ char buffer[128];
+
+ memset(buffer,0,sizeof(buffer));
+
+ if ((pu16Min == NULL) || (pu16Max == NULL))
+ {
+ return;
+ }
+
+ *pu16Min = 600;
+ *pu16Max = 2400;
+ if (readServoConfigCommand(num,buffer,sizeof(buffer)) < 0)
+ {
+ return;
+ }
+ parseServoConfigCommand(buffer,pu16Min,pu16Max);
}
static void syncServoCalibration(ftobject_txt2 *txt)
{
uint16_t u16Min, u16Max;
+ void *ftDev = NULL;
for(int i = 0; i < FT_MAX_SERVO;i++)
{
getServoMinMax(i+1,&u16Min,&u16Max);
+ if ((txt->dynamic_settings.servo[i].min != u16Min) ||
+ (txt->dynamic_settings.servo[i].min != u16Max))
+ {
+ ftDev = ftop_alloc_servo(txt, ftdev_s1 + i);
+ ftop_set_servo_limits(ftDev, u16Min, u16Max);
+ ftop_free_device(ftDev);
+ }
txt->dynamic_settings.servo[i].min = u16Min;
txt->dynamic_settings.servo[i].max = u16Max;
}
diff --git a/txt2-M4-rt-core/TxtControlLib/ftactions.c b/txt2-M4-rt-core/TxtControlLib/ftactions.c
index 687a087..36996f0 100644
--- a/txt2-M4-rt-core/TxtControlLib/ftactions.c
+++ b/txt2-M4-rt-core/TxtControlLib/ftactions.c
@@ -348,6 +348,8 @@ void ftop_set_pwm(void *device, int value)
if (pwm > 512)
pwm = 512;
+ /*
+ //old implementation, moved to RT core
if (cobj->conn >= ftdev_s1 && cobj->conn <= ftdev_s3)
{
u16Min = txt2->dynamic_settings.servo[cobj->conn - ftdev_s1].min;
@@ -360,7 +362,7 @@ void ftop_set_pwm(void *device, int value)
ftop_set_pwm_us(device,u16Duty);
return;
}
- }
+ }*/
if (cobj->conn < ftdev_o1 || cobj->conn > ftdev_s3)
return;
@@ -421,6 +423,62 @@ unsigned int ftop_get_pwm(void *device)
return cobj->speed;
}
+/**
+ @brief Set servo limits
+ @param [in] device device
+ @param [in] u16Min (300-3000) min value
+ @param [in] u16Max (300-3000) max value
+ */
+void ftop_set_servo_limits(void *device, uint16_t u16Min, uint16_t u16Max)
+{
+ ftobject_motor *cobj = device;
+ ftobject_txt2 *txt2 = ftop_get_txt(device);
+
+ if (cobj->conn < ftdev_o1 || cobj->conn > ftdev_s3)
+ return 0;
+
+ if (cobj->conn >= ftdev_c1 && cobj->conn <= ftdev_c4)
+ return 0;
+
+
+ struct ftop_set_servo_limits command = {
+ {sizeof(command), ftop_op_set_servo_limits, txt2->canid, 0},
+ {
+ {cobj->conn - ftdev_s1 + 1,u16Min,u16Max},
+ {0,0,0},
+ {0,0,0},
+ }
+ };
+
+ ftop_socket_send(txt2->transport, &command, sizeof(command));
+}
+
+/**
+ @brief Set servo limits
+ @param [in] device TXT2 device
+ */
+void ftop_init_servo_limits(void *device)
+{
+ ftobject_txt2 *txt2 = device;
+
+ struct ftop_set_servo_limits command = {
+ {sizeof(command), ftop_op_set_pwm, txt2->canid, 0},
+ {
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ }
+ };
+ for (int i = 0;i < FT_MAX_SERVO;i++)
+ {
+ command.servocalibration[i].min = txt2->dynamic_settings.servo[i].min;
+ command.servocalibration[i].max = txt2->dynamic_settings.servo[i].max;
+ command.servocalibration[i].servonum = i + 1;
+ }
+
+ ftop_socket_send(txt2->transport, &command, sizeof(command));
+}
+
/**
@brief Set motor step counter
@param [in] device motor device
@@ -642,12 +700,14 @@ int ftop_wait_event(void *device, uint32_t emask)
return result;
}
+
/**
@brief Update config
@param [in] device TXT2 controller
*/
void ftop_update_config(void *device)
{
+ char line[256];
ftobject_txt2 *txt2 = device;
struct ftop_setup_config command = {
{sizeof(command), ftop_op_send_config, txt2->canid, 0},
@@ -655,6 +715,24 @@ void ftop_update_config(void *device)
ftop_socket_send(txt2->transport, &command, sizeof(command));
+ if (!txt2->mode != ft_txt_slave)
+ {
+ //TODO: Read TXT2 Version
+ FILE* file = fopen("/slot.raucs", "r");
+ if (file!=NULL)
+ {
+ txt2->txtMasterLinuxFirmware[0] = 0;
+ while (fgets(line, sizeof(line), file)) {
+ if (strncmp(line,"bundle.version=",15) == 0)
+ {
+ strncat(txt2->txtMasterLinuxFirmware,&line[15],sizeof(txt2->txtMasterLinuxFirmware));
+ break;
+ }
+ }
+ close(file);
+ }
+ }
+
if (ftdebug & FT_DEBUG_A7_OP) {
fprintf(stderr, "update_config 0x%x\n", txt2->connusage);
ftOutputInputsConfig(&txt2->new_config.inputs);
diff --git a/txt2-M4-rt-core/TxtControlLib/ftslave.c b/txt2-M4-rt-core/TxtControlLib/ftslave.c
index 3bc7618..fa9e2a3 100644
--- a/txt2-M4-rt-core/TxtControlLib/ftslave.c
+++ b/txt2-M4-rt-core/TxtControlLib/ftslave.c
@@ -67,6 +67,35 @@ int ftop_get_firmware(void *device)
return txt2->firmware;
}
+/**
+ @brief Get TXT2 master Linux firmware version
+ @param [in] device TXT2 controller
+ @return Device master Linux firmware version
+ */
+const char* ftop_get_masterlinuxfirmware(void *device)
+{
+ ftobject_txt2 *txt2 = device;
+ char line[256];
+ if (!txt2->mode != ft_txt_slave)
+ {
+ //TODO: Read TXT2 Version
+ FILE* file = fopen("/slot.raucs", "r");
+ if (file!=NULL)
+ {
+ txt2->txtMasterLinuxFirmware[0] = 0;
+ while (fgets(line, sizeof(line), file)) {
+ if (strncmp(line,"bundle.version=",15) == 0)
+ {
+ strncat(txt2->txtMasterLinuxFirmware,&line[15],sizeof(txt2->txtMasterLinuxFirmware));
+ break;
+ }
+ }
+ close(file);
+ }
+ }
+ return txt2->txtMasterLinuxFirmware;
+}
+
/**
@brief Get TXT2 uid
@param [in] device TXT2 controller
@@ -218,6 +247,35 @@ uint32_t ftop_get_txt_uid(void *device, unsigned int number)
return uids[number];
}
+/**
+ @brief Get TXT2 master linux firmware
+ @param [in] device master TXT2 controller
+ @return slave name
+ */
+const char *ftop_get_txt_masterlinuxfirmware(void *device)
+{
+ ftobject_txt2 *txt2 = device;
+ char line[256];
+ if (!txt2->mode != ft_txt_slave)
+ {
+ //TODO: Read TXT2 Version
+ FILE* file = fopen("/slot.raucs", "r");
+ if (file!=NULL)
+ {
+ txt2->txtMasterLinuxFirmware[0] = 0;
+ while (fgets(line, sizeof(line), file)) {
+ if (strncmp(line,"bundle.version=",15) == 0)
+ {
+ strncat(txt2->txtMasterLinuxFirmware,&line[15],sizeof(txt2->txtMasterLinuxFirmware));
+ break;
+ }
+ }
+ close(file);
+ }
+ }
+ return txt2->txtMasterLinuxFirmware;
+}
+
/**
@brief Get TXT2 slave name
@param [in] device master TXT2 controller
diff --git a/txt2-M4-rt-core/cubemx/txt b/txt2-M4-rt-core/cubemx/txt
deleted file mode 120000
index d21f727..0000000
--- a/txt2-M4-rt-core/cubemx/txt
+++ /dev/null
@@ -1 +0,0 @@
-txt2
\ No newline at end of file
diff --git a/txt2-M4-rt-core/cubemx/txt/.cproject b/txt2-M4-rt-core/cubemx/txt/.cproject
new file mode 100644
index 0000000..2ee60e5
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/.cproject
@@ -0,0 +1,480 @@
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diff --git a/txt2-M4-rt-core/cubemx/txt/.mxproject b/txt2-M4-rt-core/cubemx/txt/.mxproject
new file mode 100644
index 0000000..3a8c4da
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/.mxproject
@@ -0,0 +1,14 @@
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+HeaderFiles=FreeRTOSConfig.h;openamp_conf.h;mbox_ipcc.h;openamp.h;rsc_table.h;openamp_log.h;stm32mp1xx_it.h;stm32mp1xx_hal_conf.h;main.h;resmgr_utility.h;res_mgr_conf.h;
+SourcePath=/home/ioblakov/txt2-rt-core/txt2-M4-rt-core/cubemx/txt2/CM4/Src
+SourceFiles=app_freertos.c;mbox_ipcc.c;openamp.c;rsc_table.c;openamp_log.c;stm32mp1xx_it.c;stm32mp1xx_hal_msp.c;main.c;resmgr_utility.c;
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+SourceFiles=../CM4/Src/main.c;../CM4/Src/app_freertos.c;../CM4/Src/mbox_ipcc.c;../CM4/Src/openamp.c;../CM4/Src/rsc_table.c;../CM4/Src/openamp_log.c;../CM4/Src/stm32mp1xx_it.c;../CM4/Src/stm32mp1xx_hal_msp.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c;../Middlewares/Third_Party/FreeRTOS/Source/croutine.c;../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;../Middlewares/Third_Party/FreeRTOS/Source/list.c;../Middlewares/Third_Party/FreeRTOS/Source/queue.c;../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;../Middlewares/Third_Party/FreeRTOS/Source/tasks.c;../Middlewares/Third_Party/FreeRTOS/Source/timers.c;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/device.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/init.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/io.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/log.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/shmem.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/condition.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_device.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_init.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_io.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_shmem.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/time.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/remoteproc/remoteproc_virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtqueue.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c;../Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.c;../Common/System/system_stm32mp1xx.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c;../Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c;../Middlewares/Third_Party/FreeRTOS/Source/croutine.c;../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;../Middlewares/Third_Party/FreeRTOS/Source/list.c;../Middlewares/Third_Party/FreeRTOS/Source/queue.c;../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;../Middlewares/Third_Party/FreeRTOS/Source/tasks.c;../Middlewares/Third_Party/FreeRTOS/Source/timers.c;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/device.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/init.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/io.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/log.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/shmem.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/condition.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_device.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_init.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_io.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_shmem.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/time.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/remoteproc/remoteproc_virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtqueue.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c;../Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.c;../Common/System/system_stm32mp1xx.c;../Drivers/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c;;../Middlewares/Third_Party/FreeRTOS/Source/croutine.c;../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c;../Middlewares/Third_Party/FreeRTOS/Source/list.c;../Middlewares/Third_Party/FreeRTOS/Source/queue.c;../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c;../Middlewares/Third_Party/FreeRTOS/Source/tasks.c;../Middlewares/Third_Party/FreeRTOS/Source/timers.c;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c;../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/device.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/init.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/io.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/log.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/shmem.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/condition.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_device.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_init.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_io.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_shmem.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/time.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/remoteproc/remoteproc_virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtio.c;../Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtqueue.c;../Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c;../Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.c;
+HeaderPath=../Middlewares/Third_Party/OpenAMP/open-amp/lib/include;../Middlewares/Third_Party/OpenAMP/libmetal/lib/include;../Middlewares/Third_Party/OpenAMP/open-amp/lib/include;../Middlewares/Third_Party/OpenAMP/libmetal/lib/include;../Drivers/STM32MP1xx_HAL_Driver/Inc;../Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy;../Middlewares/Third_Party/FreeRTOS/Source/include;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2;../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F;../Drivers/CMSIS/Device/ST/STM32MP1xx/Include;../Middlewares/Third_Party/OpenAMP/virtual_driver;../Drivers/CMSIS/Include;../CM4/Inc;
+CDefines=CORE_CM4;NO_ATOMIC_64_SUPPORT;METAL_INTERNAL;METAL_MAX_DEVICE_REGIONS:2;VIRTIO_SLAVE_ONLY;CORE_CM4;CORE_CM4;CORE_CM4;USE_HAL_DRIVER;STM32MP157Cxx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
diff --git a/txt2-M4-rt-core/cubemx/txt/.project b/txt2-M4-rt-core/cubemx/txt/.project
new file mode 100644
index 0000000..79de025
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/.project
@@ -0,0 +1,2431 @@
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+ <nature>com.st.stm32ide.mpu.ide.core.MPUEmbeddedMCUProjectNature</nature>
+
+ <nature>com.st.stm32ide.mpu.ide.core.MPUEmbeddedMCUProjectNature</nature>
+ </natures>
+
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+
+
+ <linkedResources>
+
+ </linkedResources>
+
+
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+
+
+</projectDescription>
diff --git a/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/kernel/stm32mp157c-txt2-mx.dts b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/kernel/stm32mp157c-txt2-mx.dts
new file mode 100644
index 0000000..138e070
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/kernel/stm32mp157c-txt2-mx.dts
@@ -0,0 +1,825 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+/dts-v1/;
+#include "stm32mp157c.dtsi"
+#include "stm32mp157cad-pinctrl.dtsi"
+#include "stm32mp157c-m4-srm.dtsi"
+
+/* USER CODE BEGIN includes */
+/* USER CODE END includes */
+
+/ {
+ model = "STMicroelectronics custom STM32CubeMX board";
+ compatible = "st,stm32mp157c-txt2-mx", "st,stm32mp157";
+
+ memory@c0000000 {
+ reg = <0xc0000000 0x20000000>;
+
+ /* USER CODE BEGIN memory */
+ /* USER CODE END memory */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* USER CODE BEGIN reserved-memory */
+ /* USER CODE END reserved-memory */
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
+ /* USER CODE BEGIN root */
+ /* USER CODE END root */
+
+ clocks {
+ /* USER CODE BEGIN clocks */
+ /* USER CODE END clocks */
+
+ clk_lsi: clk-lsi {
+ clock-frequency = <32000>;
+ };
+
+ clk_hsi: clk-hsi {
+ clock-frequency = <64000000>;
+ };
+
+ clk_csi: clk-csi {
+ clock-frequency = <4000000>;
+ };
+
+ clk_lse: clk-lse {
+ clock-frequency = <32768>;
+ };
+
+ clk_hse: clk-hse {
+ clock-frequency = <24000000>;
+ };
+ };
+
+}; /*root*/
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+
+ i2c1_pins_mx: i2c1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
+ <STM32_PINMUX('D', 12, AF5)>; /* I2C1_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_mx: i2c1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* I2C1_SDA */
+ <STM32_PINMUX('D', 12, ANALOG)>; /* I2C1_SCL */
+ };
+ };
+
+ i2c2_pins_mx: i2c2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('B', 11, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_mx: i2c2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('B', 11, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c4_pins_mx: i2c4_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF4)>, /* I2C4_SDA */
+ <STM32_PINMUX('E', 2, AF4)>; /* I2C4_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c4_sleep_pins_mx: i2c4_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* I2C4_SDA */
+ <STM32_PINMUX('E', 2, ANALOG)>; /* I2C4_SCL */
+ };
+ };
+
+ i2s2_pins_mx: i2s2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, AF5)>, /* I2S2_WS */
+ <STM32_PINMUX('B', 15, AF5)>, /* I2S2_SDO */
+ <STM32_PINMUX('C', 2, AF5)>, /* I2S2_SDI */
+ <STM32_PINMUX('C', 6, AF5)>, /* I2S2_MCK */
+ <STM32_PINMUX('D', 3, AF5)>; /* I2S2_CK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ i2s2_sleep_pins_mx: i2s2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* I2S2_WS */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* I2S2_SDO */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* I2S2_SDI */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* I2S2_MCK */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* I2S2_CK */
+ };
+ };
+
+ m4_adc_pins_mx: m4_adc_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 4, ANALOG)>; /* ADC1_INP4 */
+ };
+ };
+
+ m4_fdcan1_pins_mx: m4_fdcan1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* FDCAN1_RX */
+ <STM32_PINMUX('A', 12, RSVD)>; /* FDCAN1_TX */
+ };
+ };
+
+ m4_spi3_pins_mx: m4_spi3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>, /* SPI3_NSS */
+ <STM32_PINMUX('D', 6, RSVD)>, /* SPI3_MOSI */
+ <STM32_PINMUX('D', 10, RSVD)>, /* SPI3_MISO */
+ <STM32_PINMUX('E', 0, RSVD)>; /* SPI3_SCK */
+ };
+ };
+
+ m4_tim12_pins_mx: m4_tim12_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>; /* TIM12_CH1 */
+ };
+ };
+
+ m4_tim15_pins_mx: m4_tim15_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, RSVD)>; /* TIM15_CH1 */
+ };
+ };
+
+ m4_tim2_pwm_pins_mx: m4_tim2_pwm_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 1, RSVD)>, /* TIM2_CH2 */
+ <STM32_PINMUX('A', 2, RSVD)>, /* TIM2_CH3 */
+ <STM32_PINMUX('G', 8, RSVD)>; /* TIM2_CH1 */
+ };
+ };
+
+ m4_tim3_pins_mx: m4_tim3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, RSVD)>; /* TIM3_CH4 */
+ };
+ };
+
+ m4_tim4_pins_mx: m4_tim4_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 8, RSVD)>; /* TIM4_CH3 */
+ };
+ };
+
+ m4_usart6_pins_mx: m4_usart6_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 14, RSVD)>; /* USART6_TX */
+ };
+ };
+
+ quadspi_pins_mx: quadspi_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QUADSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* QUADSPI_BK1_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, ANALOG)>; /* QUADSPI_CLK */
+ };
+ };
+
+ sdmmc1_pins_mx: sdmmc1_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc2_pins_mx: sdmmc2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, AF7)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, AF7)>; /* SDMMC2_D0 */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc3_pins_mx: sdmmc3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc3_opendrain_pins_mx: sdmmc3_opendrain_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc3_sleep_pins_mx: sdmmc3_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>; /* SDMMC3_CK */
+ };
+ };
+
+ spi1_pins_mx: spi1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ spi1_sleep_pins_mx: spi1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, ANALOG)>; /* SPI1_MOSI */
+ };
+ };
+
+ tim8_pwm_pins_mx: tim8_pwm_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, AF3)>; /* TIM8_CH2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ tim8_pwm_sleep_pins_mx: tim8_pwm_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM8_CH2 */
+ };
+ };
+
+ uart4_pins_mx: uart4_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ uart4_sleep_pins_mx: uart4_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* UART4_RX */
+ <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ };
+
+ /* USER CODE BEGIN pinctrl */
+ /* USER CODE END pinctrl */
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN pinctrl_z */
+ /* USER CODE END pinctrl_z */
+};
+
+&m4_rproc{
+ /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ recovery;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_rproc */
+ /* USER CODE END m4_rproc */
+
+ m4_system_resources{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_system_resources */
+ /* USER CODE END m4_system_resources */
+ };
+};
+
+&bsec{
+ status = "okay";
+
+ /* USER CODE BEGIN bsec */
+ /* USER CODE END bsec */
+};
+
+&crc1{
+ status = "okay";
+
+ /* USER CODE BEGIN crc1 */
+ /* USER CODE END crc1 */
+};
+
+&cryp1{
+ status = "okay";
+
+ /* USER CODE BEGIN cryp1 */
+ /* USER CODE END cryp1 */
+};
+
+&dts{
+ status = "okay";
+
+ /* USER CODE BEGIN dts */
+ /* USER CODE END dts */
+};
+
+&gpu{
+ status = "okay";
+
+ /* USER CODE BEGIN gpu */
+ /* USER CODE END gpu */
+};
+
+&hash1{
+ status = "okay";
+
+ /* USER CODE BEGIN hash1 */
+ /* USER CODE END hash1 */
+};
+
+&hsem{
+ status = "okay";
+
+ /* USER CODE BEGIN hsem */
+ /* USER CODE END hsem */
+};
+
+&i2c1{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_mx>;
+ pinctrl-1 = <&i2c1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c1 */
+ /* USER CODE END i2c1 */
+};
+
+&i2c2{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_mx>;
+ pinctrl-1 = <&i2c2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c2 */
+ /* USER CODE END i2c2 */
+};
+
+&i2c4{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_mx>;
+ pinctrl-1 = <&i2c4_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c4 */
+ /* USER CODE END i2c4 */
+};
+
+&i2s2{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s2_pins_mx>;
+ pinctrl-1 = <&i2s2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2s2 */
+ /* USER CODE END i2s2 */
+};
+
+&ipcc{
+ status = "okay";
+
+ /* USER CODE BEGIN ipcc */
+ /* USER CODE END ipcc */
+};
+
+&m4_adc{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_adc_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_adc */
+ /* USER CODE END m4_adc */
+};
+
+&m4_m_can1{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_fdcan1_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_m_can1 */
+ /* USER CODE END m4_m_can1 */
+};
+
+&m4_spi3{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi3_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_spi3 */
+ /* USER CODE END m4_spi3 */
+};
+
+&m4_timers12{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim12_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers12 */
+ /* USER CODE END m4_timers12 */
+};
+
+&m4_timers15{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim15_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers15 */
+ /* USER CODE END m4_timers15 */
+};
+
+&m4_timers2{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim2_pwm_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers2 */
+ /* USER CODE END m4_timers2 */
+};
+
+&m4_timers3{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim3_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers3 */
+ /* USER CODE END m4_timers3 */
+};
+
+&m4_timers4{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim4_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers4 */
+ /* USER CODE END m4_timers4 */
+};
+
+&m4_timers5{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers5 */
+ /* USER CODE END m4_timers5 */
+};
+
+&m4_timers6{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers6 */
+ /* USER CODE END m4_timers6 */
+};
+
+&m4_timers7{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers7 */
+ /* USER CODE END m4_timers7 */
+};
+
+&m4_usart6{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_usart6_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_usart6 */
+ /* USER CODE END m4_usart6 */
+};
+
+&qspi{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&quadspi_pins_mx>;
+ pinctrl-1 = <&quadspi_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN qspi */
+ /* USER CODE END qspi */
+};
+
+&rcc{
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ /* USER CODE BEGIN rcc */
+ /* USER CODE END rcc */
+};
+
+&rng1{
+ status = "okay";
+
+ /* USER CODE BEGIN rng1 */
+ /* USER CODE END rng1 */
+};
+
+&rtc{
+ status = "okay";
+
+ /* USER CODE BEGIN rtc */
+ /* USER CODE END rtc */
+};
+
+&sdmmc1{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_pins_mx>;
+ pinctrl-1 = <&sdmmc1_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc1 */
+ /* USER CODE END sdmmc1 */
+};
+
+&sdmmc2{
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_pins_mx>;
+ pinctrl-1 = <&sdmmc2_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc2 */
+ /* USER CODE END sdmmc2 */
+};
+
+&sdmmc3{
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_pins_mx>;
+ pinctrl-1 = <&sdmmc3_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc3_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc3 */
+ /* USER CODE END sdmmc3 */
+};
+
+&spi1{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_mx>;
+ pinctrl-1 = <&spi1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN spi1 */
+ /* USER CODE END spi1 */
+};
+
+&tamp{
+ status = "okay";
+
+ /* USER CODE BEGIN tamp */
+ /* USER CODE END tamp */
+};
+
+&timers8{
+ status = "okay";
+
+ /* USER CODE BEGIN timers8 */
+ /* USER CODE END timers8 */
+
+ pwm{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tim8_pwm_pins_mx>;
+ pinctrl-1 = <&tim8_pwm_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN timers8_pwm */
+ /* USER CODE END timers8_pwm */
+ };
+};
+
+&uart4{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&uart4_pins_mx>;
+ pinctrl-1 = <&uart4_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN uart4 */
+ /* USER CODE END uart4 */
+};
+
+&usbh_ehci{
+ status = "okay";
+
+ /* USER CODE BEGIN usbh_ehci */
+ /* USER CODE END usbh_ehci */
+};
+
+&usbh_ohci{
+ status = "okay";
+
+ /* USER CODE BEGIN usbh_ohci */
+ /* USER CODE END usbh_ohci */
+};
+
+&usbphyc{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc */
+ /* USER CODE END usbphyc */
+};
+
+&usbphyc_port0{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc_port0 */
+ /* USER CODE END usbphyc_port0 */
+};
+
+&usbphyc_port1{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc_port1 */
+ /* USER CODE END usbphyc_port1 */
+};
+
+&vrefbuf{
+ status = "okay";
+
+ /* USER CODE BEGIN vrefbuf */
+ /* USER CODE END vrefbuf */
+};
+
+/* USER CODE BEGIN addons */
+/* USER CODE END addons */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp15-mx.dtsi b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp15-mx.dtsi
new file mode 100644
index 0000000..816fcbb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp15-mx.dtsi
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ *
+ */
+
+/*
+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
+ * DDR type: DDR3 / DDR3L
+ * DDR width: 16bits
+ * DDR density: 4Gb
+ * System frequency: 528000Khz
+ * Relaxed Timing Mode: false
+ * Address mapping type: RBC
+ *
+ * Save Date: 2020.11.03, save Time: 15:39:59
+ */
+
+#define DDR_MEM_NAME "DDR3-DDR3L 16bits 528000Khz"
+#define DDR_MEM_SPEED 528000
+#define DDR_MEM_SIZE 0x20000000
+
+#define DDR_MSTR 0x00041401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0040008A
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B1214
+#define DDR_DRAMTMG1 0x000A041B
+#define DDR_DRAMTMG2 0x0607080F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x07040607
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02050105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000C01
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00070707
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x1F000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x06060606
+#define DDR_ADDRMAP6 0x0F060606
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022A41B
+#define DDR_PTR1 0x047C0740
+#define DDR_PTR2 0x042D9C80
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200011F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x36D477D0
+#define DDR_DTPR1 0x098A00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000830
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000248
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x00000038
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE80
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE80
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
diff --git a/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp157c-txt2-mx.dts b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp157c-txt2-mx.dts
new file mode 100644
index 0000000..cd62cb3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/tf-a/stm32mp157c-txt2-mx.dts
@@ -0,0 +1,299 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-mx.dtsi"
+
+#include "stm32mp157c.dtsi"
+#include "stm32mp157cad-pinctrl.dtsi"
+#include "stm32mp15-ddr.dtsi"
+#include "stm32mp157c-security.dtsi"
+
+/* USER CODE BEGIN includes */
+/* USER CODE END includes */
+
+/ {
+ model = "STMicroelectronics custom STM32CubeMX board";
+ compatible = "st,stm32mp157c-txt2-mx", "st,stm32mp157";
+
+ /* USER CODE BEGIN root */
+ /* USER CODE END root */
+
+ clocks {
+ /* USER CODE BEGIN clocks */
+ /* USER CODE END clocks */
+
+ clk_lse: clk-lse {
+ st,drive = < LSEDRV_MEDIUM_HIGH >;
+
+ /* USER CODE BEGIN clk_lse */
+ /* USER CODE END clk_lse */
+ };
+
+ clk_hse: clk-hse {
+
+ /* USER CODE BEGIN clk_hse */
+ /* USER CODE END clk_hse */
+ };
+ };
+
+}; /*root*/
+
+&pinctrl {
+ quadspi_pins_mx: quadspi_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QUADSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ sdmmc1_pins_mx: sdmmc1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ uart4_pins_mx: uart4_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /* USER CODE BEGIN pinctrl */
+ /* USER CODE END pinctrl */
+};
+
+&pinctrl_z {
+ /* USER CODE BEGIN pinctrl_z */
+ /* USER CODE END pinctrl_z */
+};
+
+&rcc {
+ st,csi-cal;
+ st,hsi-cal;
+ st,cal-sec = <60>;
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 0 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_QSPI_ACLK
+ CLK_ETH_DISABLED
+ CLK_SDMMC12_PLL4P
+ CLK_STGEN_HSE
+ CLK_USBPHY_DISABLED
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL4P
+ CLK_SPI45_DISABLED
+ CLK_SPI6_DISABLED
+ CLK_I2C46_HSI
+ CLK_SDMMC3_HCLK2
+ CLK_ADC_CKPER
+ CLK_CEC_DISABLED
+ CLK_I2C12_HSI
+ CLK_I2C35_DISABLED
+ CLK_UART1_DISABLED
+ CLK_UART24_PCLK1
+ CLK_UART35_DISABLED
+ CLK_UART6_PCLK2
+ CLK_UART78_DISABLED
+ CLK_SPDIF_DISABLED
+ CLK_FDCAN_HSE
+ CLK_SAI1_DISABLED
+ CLK_SAI2_DISABLED
+ CLK_SAI3_DISABLED
+ CLK_SAI4_DISABLED
+ CLK_RNG1_CSI
+ CLK_LPTIM1_DISABLED
+ CLK_LPTIM23_DISABLED
+ CLK_LPTIM45_DISABLED
+ >;
+ pll1:st,pll@0 {
+ cfg = < 2 80 0 1 1 PQR(1,0,0) >;
+ };
+ pll2:st,pll@1 {
+ cfg = < 2 65 1 1 0 PQR(1,1,1) >;
+ };
+ pll3:st,pll@2 {
+ cfg = < 1 49 2 4 11 PQR(1,1,0) >;
+ };
+ pll4:st,pll@3 {
+ cfg = < 5 124 9 9 9 PQR(1,0,0) >;
+ };
+};
+
+&bsec{
+ status = "okay";
+ secure-status = "okay";
+
+ /* USER CODE BEGIN bsec */
+ /* USER CODE END bsec */
+};
+
+&etzpc{
+ st,decprot = <
+ /*"Non Secured" peripherals*/
+ DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_DLYBQ_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_SDMMC3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_DLYBSD3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_SPI1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM8_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
+ /*"Mcu Isolation" peripherals*/
+ DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TT_FDCAN_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_SPI3_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM3_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM4_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM5_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM6_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_TIM7_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+ DECPROT(STM32MP1_ETZPC_USART6_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
+
+ /*Restriction: following IDs are not managed - please to use User-Section if needed:
+ STM32MP1_ETZPC_DMA1_ID, STM32MP1_ETZPC_DMA2_ID, STM32MP1_ETZPC_DMAMUX_ID,
+ STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/
+
+ /* USER CODE BEGIN etzpc_decprot */
+ /*STM32CubeMX generates a basic and standard configuration for ETZPC.
+ Additional device configurations can be added here if needed.
+ "etzpc" node could be also overloaded in "addons" User-Section.*/
+ /* USER CODE END etzpc_decprot */
+ >;
+
+ secure-status = "okay";
+
+ /* USER CODE BEGIN etzpc */
+ /* USER CODE END etzpc */
+};
+
+&qspi{
+ pinctrl-names = "default";
+ pinctrl-0 = <&quadspi_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN qspi */
+ /* USER CODE END qspi */
+};
+
+&rcc{
+ status = "okay";
+ secure-status = "okay";
+
+ /* USER CODE BEGIN rcc */
+ /* USER CODE END rcc */
+};
+
+&rng1{
+ status = "okay";
+ secure-status = "okay";
+
+ /* USER CODE BEGIN rng1 */
+ /* USER CODE END rng1 */
+};
+
+&rtc{
+ status = "okay";
+ secure-status = "okay";
+
+ /* USER CODE BEGIN rtc */
+ /* USER CODE END rtc */
+};
+
+&sdmmc1{
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc1 */
+ /* USER CODE END sdmmc1 */
+};
+
+&tamp{
+ status = "okay";
+ secure-status = "okay";
+
+ /* USER CODE BEGIN tamp */
+ /* USER CODE END tamp */
+};
+
+&uart4{
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN uart4 */
+ /* USER CODE END uart4 */
+};
+
+/* USER CODE BEGIN addons */
+/* USER CODE END addons */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp15-mx.dtsi b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp15-mx.dtsi
new file mode 100644
index 0000000..816fcbb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp15-mx.dtsi
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ *
+ */
+
+/*
+ * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
+ * DDR type: DDR3 / DDR3L
+ * DDR width: 16bits
+ * DDR density: 4Gb
+ * System frequency: 528000Khz
+ * Relaxed Timing Mode: false
+ * Address mapping type: RBC
+ *
+ * Save Date: 2020.11.03, save Time: 15:39:59
+ */
+
+#define DDR_MEM_NAME "DDR3-DDR3L 16bits 528000Khz"
+#define DDR_MEM_SPEED 528000
+#define DDR_MEM_SIZE 0x20000000
+
+#define DDR_MSTR 0x00041401
+#define DDR_MRCTRL0 0x00000010
+#define DDR_MRCTRL1 0x00000000
+#define DDR_DERATEEN 0x00000000
+#define DDR_DERATEINT 0x00800000
+#define DDR_PWRCTL 0x00000000
+#define DDR_PWRTMG 0x00400010
+#define DDR_HWLPCTL 0x00000000
+#define DDR_RFSHCTL0 0x00210000
+#define DDR_RFSHCTL3 0x00000000
+#define DDR_RFSHTMG 0x0040008A
+#define DDR_CRCPARCTL0 0x00000000
+#define DDR_DRAMTMG0 0x121B1214
+#define DDR_DRAMTMG1 0x000A041B
+#define DDR_DRAMTMG2 0x0607080F
+#define DDR_DRAMTMG3 0x0050400C
+#define DDR_DRAMTMG4 0x07040607
+#define DDR_DRAMTMG5 0x06060403
+#define DDR_DRAMTMG6 0x02020002
+#define DDR_DRAMTMG7 0x00000202
+#define DDR_DRAMTMG8 0x00001005
+#define DDR_DRAMTMG14 0x000000A0
+#define DDR_ZQCTL0 0xC2000040
+#define DDR_DFITMG0 0x02050105
+#define DDR_DFITMG1 0x00000202
+#define DDR_DFILPCFG0 0x07000000
+#define DDR_DFIUPD0 0xC0400003
+#define DDR_DFIUPD1 0x00000000
+#define DDR_DFIUPD2 0x00000000
+#define DDR_DFIPHYMSTR 0x00000000
+#define DDR_ODTCFG 0x06000600
+#define DDR_ODTMAP 0x00000001
+#define DDR_SCHED 0x00000C01
+#define DDR_SCHED1 0x00000000
+#define DDR_PERFHPR1 0x01000001
+#define DDR_PERFLPR1 0x08000200
+#define DDR_PERFWR1 0x08000400
+#define DDR_DBG0 0x00000000
+#define DDR_DBG1 0x00000000
+#define DDR_DBGCMD 0x00000000
+#define DDR_POISONCFG 0x00000000
+#define DDR_PCCFG 0x00000010
+#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGW_0 0x00000000
+#define DDR_PCFGQOS0_0 0x02100C03
+#define DDR_PCFGQOS1_0 0x00800100
+#define DDR_PCFGWQOS0_0 0x01100C03
+#define DDR_PCFGWQOS1_0 0x01000200
+#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGW_1 0x00000000
+#define DDR_PCFGQOS0_1 0x02100C03
+#define DDR_PCFGQOS1_1 0x00800040
+#define DDR_PCFGWQOS0_1 0x01100C03
+#define DDR_PCFGWQOS1_1 0x01000200
+#define DDR_ADDRMAP1 0x00070707
+#define DDR_ADDRMAP2 0x00000000
+#define DDR_ADDRMAP3 0x1F000000
+#define DDR_ADDRMAP4 0x00001F1F
+#define DDR_ADDRMAP5 0x06060606
+#define DDR_ADDRMAP6 0x0F060606
+#define DDR_ADDRMAP9 0x00000000
+#define DDR_ADDRMAP10 0x00000000
+#define DDR_ADDRMAP11 0x00000000
+#define DDR_PGCR 0x01442E02
+#define DDR_PTR0 0x0022A41B
+#define DDR_PTR1 0x047C0740
+#define DDR_PTR2 0x042D9C80
+#define DDR_ACIOCR 0x10400812
+#define DDR_DXCCR 0x00000C40
+#define DDR_DSGCR 0xF200011F
+#define DDR_DCR 0x0000000B
+#define DDR_DTPR0 0x36D477D0
+#define DDR_DTPR1 0x098A00D8
+#define DDR_DTPR2 0x10023600
+#define DDR_MR0 0x00000830
+#define DDR_MR1 0x00000000
+#define DDR_MR2 0x00000248
+#define DDR_MR3 0x00000000
+#define DDR_ODTCR 0x00010000
+#define DDR_ZQ0CR1 0x00000038
+#define DDR_DX0GCR 0x0000CE81
+#define DDR_DX0DLLCR 0x40000000
+#define DDR_DX0DQTR 0xFFFFFFFF
+#define DDR_DX0DQSTR 0x3DB02000
+#define DDR_DX1GCR 0x0000CE81
+#define DDR_DX1DLLCR 0x40000000
+#define DDR_DX1DQTR 0xFFFFFFFF
+#define DDR_DX1DQSTR 0x3DB02000
+#define DDR_DX2GCR 0x0000CE80
+#define DDR_DX2DLLCR 0x40000000
+#define DDR_DX2DQTR 0xFFFFFFFF
+#define DDR_DX2DQSTR 0x3DB02000
+#define DDR_DX3GCR 0x0000CE80
+#define DDR_DX3DLLCR 0x40000000
+#define DDR_DX3DQTR 0xFFFFFFFF
+#define DDR_DX3DQSTR 0x3DB02000
diff --git a/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx-u-boot.dtsi b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx-u-boot.dtsi
new file mode 100644
index 0000000..b7f1809
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx-u-boot.dtsi
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/
+/*
+ * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-mx.dtsi"
+
+#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr.dtsi"
+
+/* USER CODE BEGIN includes */
+/* USER CODE END includes */
+
+/ {
+
+ /* USER CODE BEGIN root */
+ /* USER CODE END root */
+
+ clocks {
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN clocks */
+ /* USER CODE END clocks */
+
+ clk_lsi: clk-lsi {
+ u-boot,dm-pre-reloc;
+ status = "disabled";
+
+ /* USER CODE BEGIN clk_lsi */
+ /* USER CODE END clk_lsi */
+ };
+
+ clk_hsi: clk-hsi {
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN clk_hsi */
+ /* USER CODE END clk_hsi */
+ };
+
+ clk_csi: clk-csi {
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN clk_csi */
+ /* USER CODE END clk_csi */
+ };
+
+ clk_lse: clk-lse {
+ u-boot,dm-pre-reloc;
+ st,drive = < LSEDRV_MEDIUM_HIGH >;
+
+ /* USER CODE BEGIN clk_lse */
+ /* USER CODE END clk_lse */
+ };
+
+ clk_hse: clk-hse {
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN clk_hse */
+ /* USER CODE END clk_hse */
+ };
+ };
+
+}; /*root*/
+
+&rcc {
+ u-boot,dm-pre-reloc;
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 0 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_QSPI_ACLK
+ CLK_ETH_DISABLED
+ CLK_SDMMC12_PLL4P
+ CLK_STGEN_HSE
+ CLK_USBPHY_DISABLED
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL4P
+ CLK_SPI45_DISABLED
+ CLK_SPI6_DISABLED
+ CLK_I2C46_HSI
+ CLK_SDMMC3_HCLK2
+ CLK_ADC_CKPER
+ CLK_CEC_DISABLED
+ CLK_I2C12_HSI
+ CLK_I2C35_DISABLED
+ CLK_UART1_DISABLED
+ CLK_UART24_PCLK1
+ CLK_UART35_DISABLED
+ CLK_UART6_PCLK2
+ CLK_UART78_DISABLED
+ CLK_SPDIF_DISABLED
+ CLK_FDCAN_HSE
+ CLK_SAI1_DISABLED
+ CLK_SAI2_DISABLED
+ CLK_SAI3_DISABLED
+ CLK_SAI4_DISABLED
+ CLK_RNG1_CSI
+ CLK_LPTIM1_DISABLED
+ CLK_LPTIM23_DISABLED
+ CLK_LPTIM45_DISABLED
+ >;
+ pll1:st,pll@0 {
+ cfg = < 2 80 0 1 1 PQR(1,0,0) >;
+ u-boot,dm-pre-reloc;
+ };
+ pll2:st,pll@1 {
+ cfg = < 2 65 1 1 0 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+ pll3:st,pll@2 {
+ cfg = < 1 49 2 4 11 PQR(1,1,0) >;
+ u-boot,dm-pre-reloc;
+ };
+ pll4:st,pll@3 {
+ cfg = < 5 124 9 9 9 PQR(1,0,0) >;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&qspi{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN qspi */
+ /* USER CODE END qspi */
+};
+
+&rcc{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN rcc */
+ /* USER CODE END rcc */
+};
+
+&sdmmc1{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN sdmmc1 */
+ /* USER CODE END sdmmc1 */
+};
+
+&uart4{
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN uart4 */
+ /* USER CODE END uart4 */
+};
+
+/* USER CODE BEGIN addons */
+/* USER CODE END addons */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts
new file mode 100644
index 0000000..3e5bf3c
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts
@@ -0,0 +1,825 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+/dts-v1/;
+#include "stm32mp157c.dtsi"
+#include "stm32mp157cad-pinctrl.dtsi"
+#include "stm32mp157c-m4-srm.dtsi"
+
+/* USER CODE BEGIN includes */
+/* USER CODE END includes */
+
+/ {
+ model = "STMicroelectronics custom STM32CubeMX board";
+ compatible = "st,stm32mp157c-txt2-mx", "st,stm32mp157";
+
+ memory@c0000000 {
+ reg = <0xc0000000 0x20000000>;
+
+ /* USER CODE BEGIN memory */
+ /* USER CODE END memory */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* USER CODE BEGIN reserved-memory */
+ /* USER CODE END reserved-memory */
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
+ /* USER CODE BEGIN root */
+ /* USER CODE END root */
+
+ clocks {
+ /* USER CODE BEGIN clocks */
+ /* USER CODE END clocks */
+
+ clk_lsi: clk-lsi {
+ clock-frequency = <32000>;
+ };
+
+ clk_hsi: clk-hsi {
+ clock-frequency = <64000000>;
+ };
+
+ clk_csi: clk-csi {
+ clock-frequency = <4000000>;
+ };
+
+ clk_lse: clk-lse {
+ clock-frequency = <32768>;
+ };
+
+ clk_hse: clk-hse {
+ clock-frequency = <24000000>;
+ };
+ };
+
+}; /*root*/
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+
+ i2c1_pins_mx: i2c1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
+ <STM32_PINMUX('D', 12, AF5)>; /* I2C1_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_mx: i2c1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* I2C1_SDA */
+ <STM32_PINMUX('D', 12, ANALOG)>; /* I2C1_SCL */
+ };
+ };
+
+ i2c2_pins_mx: i2c2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('B', 11, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_mx: i2c2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('B', 11, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c4_pins_mx: i2c4_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF4)>, /* I2C4_SDA */
+ <STM32_PINMUX('E', 2, AF4)>; /* I2C4_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c4_sleep_pins_mx: i2c4_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* I2C4_SDA */
+ <STM32_PINMUX('E', 2, ANALOG)>; /* I2C4_SCL */
+ };
+ };
+
+ i2s2_pins_mx: i2s2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, AF5)>, /* I2S2_WS */
+ <STM32_PINMUX('B', 15, AF5)>, /* I2S2_SDO */
+ <STM32_PINMUX('C', 2, AF5)>, /* I2S2_SDI */
+ <STM32_PINMUX('C', 6, AF5)>, /* I2S2_MCK */
+ <STM32_PINMUX('D', 3, AF5)>; /* I2S2_CK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ i2s2_sleep_pins_mx: i2s2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* I2S2_WS */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* I2S2_SDO */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* I2S2_SDI */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* I2S2_MCK */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* I2S2_CK */
+ };
+ };
+
+ m4_adc_pins_mx: m4_adc_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 4, ANALOG)>; /* ADC1_INP4 */
+ };
+ };
+
+ m4_fdcan1_pins_mx: m4_fdcan1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* FDCAN1_RX */
+ <STM32_PINMUX('A', 12, RSVD)>; /* FDCAN1_TX */
+ };
+ };
+
+ m4_spi3_pins_mx: m4_spi3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>, /* SPI3_NSS */
+ <STM32_PINMUX('D', 6, RSVD)>, /* SPI3_MOSI */
+ <STM32_PINMUX('D', 10, RSVD)>, /* SPI3_MISO */
+ <STM32_PINMUX('E', 0, RSVD)>; /* SPI3_SCK */
+ };
+ };
+
+ m4_tim12_pins_mx: m4_tim12_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>; /* TIM12_CH1 */
+ };
+ };
+
+ m4_tim15_pins_mx: m4_tim15_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, RSVD)>; /* TIM15_CH1 */
+ };
+ };
+
+ m4_tim2_pwm_pins_mx: m4_tim2_pwm_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 1, RSVD)>, /* TIM2_CH2 */
+ <STM32_PINMUX('A', 2, RSVD)>, /* TIM2_CH3 */
+ <STM32_PINMUX('G', 8, RSVD)>; /* TIM2_CH1 */
+ };
+ };
+
+ m4_tim3_pins_mx: m4_tim3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, RSVD)>; /* TIM3_CH4 */
+ };
+ };
+
+ m4_tim4_pins_mx: m4_tim4_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 8, RSVD)>; /* TIM4_CH3 */
+ };
+ };
+
+ m4_usart6_pins_mx: m4_usart6_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 14, RSVD)>; /* USART6_TX */
+ };
+ };
+
+ quadspi_pins_mx: quadspi_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QUADSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* QUADSPI_BK1_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, ANALOG)>; /* QUADSPI_CLK */
+ };
+ };
+
+ sdmmc1_pins_mx: sdmmc1_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc2_pins_mx: sdmmc2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, AF7)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, AF7)>; /* SDMMC2_D0 */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc3_pins_mx: sdmmc3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc3_opendrain_pins_mx: sdmmc3_opendrain_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc3_sleep_pins_mx: sdmmc3_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>; /* SDMMC3_CK */
+ };
+ };
+
+ spi1_pins_mx: spi1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ spi1_sleep_pins_mx: spi1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, ANALOG)>; /* SPI1_MOSI */
+ };
+ };
+
+ tim8_pwm_pins_mx: tim8_pwm_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, AF3)>; /* TIM8_CH2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ tim8_pwm_sleep_pins_mx: tim8_pwm_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM8_CH2 */
+ };
+ };
+
+ uart4_pins_mx: uart4_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ uart4_sleep_pins_mx: uart4_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* UART4_RX */
+ <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ };
+
+ /* USER CODE BEGIN pinctrl */
+ /* USER CODE END pinctrl */
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN pinctrl_z */
+ /* USER CODE END pinctrl_z */
+};
+
+&m4_rproc{
+ /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ recovery;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_rproc */
+ /* USER CODE END m4_rproc */
+
+ m4_system_resources{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_system_resources */
+ /* USER CODE END m4_system_resources */
+ };
+};
+
+&bsec{
+ status = "okay";
+
+ /* USER CODE BEGIN bsec */
+ /* USER CODE END bsec */
+};
+
+&crc1{
+ status = "okay";
+
+ /* USER CODE BEGIN crc1 */
+ /* USER CODE END crc1 */
+};
+
+&cryp1{
+ status = "okay";
+
+ /* USER CODE BEGIN cryp1 */
+ /* USER CODE END cryp1 */
+};
+
+&dts{
+ status = "okay";
+
+ /* USER CODE BEGIN dts */
+ /* USER CODE END dts */
+};
+
+&gpu{
+ status = "okay";
+
+ /* USER CODE BEGIN gpu */
+ /* USER CODE END gpu */
+};
+
+&hash1{
+ status = "okay";
+
+ /* USER CODE BEGIN hash1 */
+ /* USER CODE END hash1 */
+};
+
+&hsem{
+ status = "okay";
+
+ /* USER CODE BEGIN hsem */
+ /* USER CODE END hsem */
+};
+
+&i2c1{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_mx>;
+ pinctrl-1 = <&i2c1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c1 */
+ /* USER CODE END i2c1 */
+};
+
+&i2c2{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_mx>;
+ pinctrl-1 = <&i2c2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c2 */
+ /* USER CODE END i2c2 */
+};
+
+&i2c4{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_mx>;
+ pinctrl-1 = <&i2c4_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c4 */
+ /* USER CODE END i2c4 */
+};
+
+&i2s2{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s2_pins_mx>;
+ pinctrl-1 = <&i2s2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2s2 */
+ /* USER CODE END i2s2 */
+};
+
+&ipcc{
+ status = "okay";
+
+ /* USER CODE BEGIN ipcc */
+ /* USER CODE END ipcc */
+};
+
+&m4_adc{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_adc_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_adc */
+ /* USER CODE END m4_adc */
+};
+
+&m4_m_can1{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_fdcan1_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_m_can1 */
+ /* USER CODE END m4_m_can1 */
+};
+
+&m4_spi3{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi3_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_spi3 */
+ /* USER CODE END m4_spi3 */
+};
+
+&m4_timers12{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim12_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers12 */
+ /* USER CODE END m4_timers12 */
+};
+
+&m4_timers15{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim15_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers15 */
+ /* USER CODE END m4_timers15 */
+};
+
+&m4_timers2{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim2_pwm_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers2 */
+ /* USER CODE END m4_timers2 */
+};
+
+&m4_timers3{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim3_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers3 */
+ /* USER CODE END m4_timers3 */
+};
+
+&m4_timers4{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim4_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers4 */
+ /* USER CODE END m4_timers4 */
+};
+
+&m4_timers5{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers5 */
+ /* USER CODE END m4_timers5 */
+};
+
+&m4_timers6{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers6 */
+ /* USER CODE END m4_timers6 */
+};
+
+&m4_timers7{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers7 */
+ /* USER CODE END m4_timers7 */
+};
+
+&m4_usart6{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_usart6_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_usart6 */
+ /* USER CODE END m4_usart6 */
+};
+
+&qspi{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&quadspi_pins_mx>;
+ pinctrl-1 = <&quadspi_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN qspi */
+ /* USER CODE END qspi */
+};
+
+&rcc{
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ /* USER CODE BEGIN rcc */
+ /* USER CODE END rcc */
+};
+
+&rng1{
+ status = "okay";
+
+ /* USER CODE BEGIN rng1 */
+ /* USER CODE END rng1 */
+};
+
+&rtc{
+ status = "okay";
+
+ /* USER CODE BEGIN rtc */
+ /* USER CODE END rtc */
+};
+
+&sdmmc1{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_pins_mx>;
+ pinctrl-1 = <&sdmmc1_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc1 */
+ /* USER CODE END sdmmc1 */
+};
+
+&sdmmc2{
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_pins_mx>;
+ pinctrl-1 = <&sdmmc2_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc2 */
+ /* USER CODE END sdmmc2 */
+};
+
+&sdmmc3{
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_pins_mx>;
+ pinctrl-1 = <&sdmmc3_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc3_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc3 */
+ /* USER CODE END sdmmc3 */
+};
+
+&spi1{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_mx>;
+ pinctrl-1 = <&spi1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN spi1 */
+ /* USER CODE END spi1 */
+};
+
+&tamp{
+ status = "okay";
+
+ /* USER CODE BEGIN tamp */
+ /* USER CODE END tamp */
+};
+
+&timers8{
+ status = "okay";
+
+ /* USER CODE BEGIN timers8 */
+ /* USER CODE END timers8 */
+
+ pwm{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tim8_pwm_pins_mx>;
+ pinctrl-1 = <&tim8_pwm_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN timers8_pwm */
+ /* USER CODE END timers8_pwm */
+ };
+};
+
+&uart4{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&uart4_pins_mx>;
+ pinctrl-1 = <&uart4_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN uart4 */
+ /* USER CODE END uart4 */
+};
+
+&usbh_ehci{
+ status = "okay";
+
+ /* USER CODE BEGIN usbh_ehci */
+ /* USER CODE END usbh_ehci */
+};
+
+&usbh_ohci{
+ status = "okay";
+
+ /* USER CODE BEGIN usbh_ohci */
+ /* USER CODE END usbh_ohci */
+};
+
+&usbphyc{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc */
+ /* USER CODE END usbphyc */
+};
+
+&usbphyc_port0{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc_port0 */
+ /* USER CODE END usbphyc_port0 */
+};
+
+&usbphyc_port1{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc_port1 */
+ /* USER CODE END usbphyc_port1 */
+};
+
+&vrefbuf{
+ status = "okay";
+
+ /* USER CODE BEGIN vrefbuf */
+ /* USER CODE END vrefbuf */
+};
+
+/* USER CODE BEGIN addons */
+/* USER CODE END addons */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts.bak b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts.bak
new file mode 100644
index 0000000..3e5bf3c
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CA7/DeviceTree/txt2/u-boot/stm32mp157c-txt2-mx.dts.bak
@@ -0,0 +1,825 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
+ * Author: STM32CubeMX code generation for STMicroelectronics.
+ */
+
+/* For more information on Device Tree configuration, please refer to
+ * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
+ */
+
+/dts-v1/;
+#include "stm32mp157c.dtsi"
+#include "stm32mp157cad-pinctrl.dtsi"
+#include "stm32mp157c-m4-srm.dtsi"
+
+/* USER CODE BEGIN includes */
+/* USER CODE END includes */
+
+/ {
+ model = "STMicroelectronics custom STM32CubeMX board";
+ compatible = "st,stm32mp157c-txt2-mx", "st,stm32mp157";
+
+ memory@c0000000 {
+ reg = <0xc0000000 0x20000000>;
+
+ /* USER CODE BEGIN memory */
+ /* USER CODE END memory */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* USER CODE BEGIN reserved-memory */
+ /* USER CODE END reserved-memory */
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
+ /* USER CODE BEGIN root */
+ /* USER CODE END root */
+
+ clocks {
+ /* USER CODE BEGIN clocks */
+ /* USER CODE END clocks */
+
+ clk_lsi: clk-lsi {
+ clock-frequency = <32000>;
+ };
+
+ clk_hsi: clk-hsi {
+ clock-frequency = <64000000>;
+ };
+
+ clk_csi: clk-csi {
+ clock-frequency = <4000000>;
+ };
+
+ clk_lse: clk-lse {
+ clock-frequency = <32768>;
+ };
+
+ clk_hse: clk-hse {
+ clock-frequency = <24000000>;
+ };
+ };
+
+}; /*root*/
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+
+ i2c1_pins_mx: i2c1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
+ <STM32_PINMUX('D', 12, AF5)>; /* I2C1_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_mx: i2c1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* I2C1_SDA */
+ <STM32_PINMUX('D', 12, ANALOG)>; /* I2C1_SCL */
+ };
+ };
+
+ i2c2_pins_mx: i2c2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('B', 11, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_mx: i2c2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('B', 11, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c4_pins_mx: i2c4_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF4)>, /* I2C4_SDA */
+ <STM32_PINMUX('E', 2, AF4)>; /* I2C4_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c4_sleep_pins_mx: i2c4_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* I2C4_SDA */
+ <STM32_PINMUX('E', 2, ANALOG)>; /* I2C4_SCL */
+ };
+ };
+
+ i2s2_pins_mx: i2s2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, AF5)>, /* I2S2_WS */
+ <STM32_PINMUX('B', 15, AF5)>, /* I2S2_SDO */
+ <STM32_PINMUX('C', 2, AF5)>, /* I2S2_SDI */
+ <STM32_PINMUX('C', 6, AF5)>, /* I2S2_MCK */
+ <STM32_PINMUX('D', 3, AF5)>; /* I2S2_CK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ i2s2_sleep_pins_mx: i2s2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* I2S2_WS */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* I2S2_SDO */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* I2S2_SDI */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* I2S2_MCK */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* I2S2_CK */
+ };
+ };
+
+ m4_adc_pins_mx: m4_adc_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 4, ANALOG)>; /* ADC1_INP4 */
+ };
+ };
+
+ m4_fdcan1_pins_mx: m4_fdcan1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* FDCAN1_RX */
+ <STM32_PINMUX('A', 12, RSVD)>; /* FDCAN1_TX */
+ };
+ };
+
+ m4_spi3_pins_mx: m4_spi3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, RSVD)>, /* SPI3_NSS */
+ <STM32_PINMUX('D', 6, RSVD)>, /* SPI3_MOSI */
+ <STM32_PINMUX('D', 10, RSVD)>, /* SPI3_MISO */
+ <STM32_PINMUX('E', 0, RSVD)>; /* SPI3_SCK */
+ };
+ };
+
+ m4_tim12_pins_mx: m4_tim12_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, RSVD)>; /* TIM12_CH1 */
+ };
+ };
+
+ m4_tim15_pins_mx: m4_tim15_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 5, RSVD)>; /* TIM15_CH1 */
+ };
+ };
+
+ m4_tim2_pwm_pins_mx: m4_tim2_pwm_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 1, RSVD)>, /* TIM2_CH2 */
+ <STM32_PINMUX('A', 2, RSVD)>, /* TIM2_CH3 */
+ <STM32_PINMUX('G', 8, RSVD)>; /* TIM2_CH1 */
+ };
+ };
+
+ m4_tim3_pins_mx: m4_tim3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 1, RSVD)>; /* TIM3_CH4 */
+ };
+ };
+
+ m4_tim4_pins_mx: m4_tim4_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 8, RSVD)>; /* TIM4_CH3 */
+ };
+ };
+
+ m4_usart6_pins_mx: m4_usart6_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 14, RSVD)>; /* USART6_TX */
+ };
+ };
+
+ quadspi_pins_mx: quadspi_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QUADSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* QUADSPI_BK1_NCS */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QUADSPI_BK1_IO3 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QUADSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* QUADSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QUADSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 10, ANALOG)>; /* QUADSPI_CLK */
+ };
+ };
+
+ sdmmc1_pins_mx: sdmmc1_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc2_pins_mx: sdmmc2_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, AF7)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, AF7)>; /* SDMMC2_D0 */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc3_pins_mx: sdmmc3_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc3_opendrain_pins_mx: sdmmc3_opendrain_mx-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
+ bias-pull-up;
+ drive-open-drain;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ sdmmc3_sleep_pins_mx: sdmmc3_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* SDMMC3_CMD */
+ <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>; /* SDMMC3_CK */
+ };
+ };
+
+ spi1_pins_mx: spi1_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ spi1_sleep_pins_mx: spi1_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, ANALOG)>; /* SPI1_MOSI */
+ };
+ };
+
+ tim8_pwm_pins_mx: tim8_pwm_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, AF3)>; /* TIM8_CH2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ tim8_pwm_sleep_pins_mx: tim8_pwm_sleep_mx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM8_CH2 */
+ };
+ };
+
+ uart4_pins_mx: uart4_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-pull-up;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ uart4_sleep_pins_mx: uart4_sleep_mx-0 {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* UART4_RX */
+ <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ };
+
+ /* USER CODE BEGIN pinctrl */
+ /* USER CODE END pinctrl */
+};
+
+&pinctrl_z {
+ u-boot,dm-pre-reloc;
+
+ /* USER CODE BEGIN pinctrl_z */
+ /* USER CODE END pinctrl_z */
+};
+
+&m4_rproc{
+ /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ recovery;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_rproc */
+ /* USER CODE END m4_rproc */
+
+ m4_system_resources{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_system_resources */
+ /* USER CODE END m4_system_resources */
+ };
+};
+
+&bsec{
+ status = "okay";
+
+ /* USER CODE BEGIN bsec */
+ /* USER CODE END bsec */
+};
+
+&crc1{
+ status = "okay";
+
+ /* USER CODE BEGIN crc1 */
+ /* USER CODE END crc1 */
+};
+
+&cryp1{
+ status = "okay";
+
+ /* USER CODE BEGIN cryp1 */
+ /* USER CODE END cryp1 */
+};
+
+&dts{
+ status = "okay";
+
+ /* USER CODE BEGIN dts */
+ /* USER CODE END dts */
+};
+
+&gpu{
+ status = "okay";
+
+ /* USER CODE BEGIN gpu */
+ /* USER CODE END gpu */
+};
+
+&hash1{
+ status = "okay";
+
+ /* USER CODE BEGIN hash1 */
+ /* USER CODE END hash1 */
+};
+
+&hsem{
+ status = "okay";
+
+ /* USER CODE BEGIN hsem */
+ /* USER CODE END hsem */
+};
+
+&i2c1{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_mx>;
+ pinctrl-1 = <&i2c1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c1 */
+ /* USER CODE END i2c1 */
+};
+
+&i2c2{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_mx>;
+ pinctrl-1 = <&i2c2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c2 */
+ /* USER CODE END i2c2 */
+};
+
+&i2c4{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_mx>;
+ pinctrl-1 = <&i2c4_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2c4 */
+ /* USER CODE END i2c4 */
+};
+
+&i2s2{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s2_pins_mx>;
+ pinctrl-1 = <&i2s2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN i2s2 */
+ /* USER CODE END i2s2 */
+};
+
+&ipcc{
+ status = "okay";
+
+ /* USER CODE BEGIN ipcc */
+ /* USER CODE END ipcc */
+};
+
+&m4_adc{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_adc_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_adc */
+ /* USER CODE END m4_adc */
+};
+
+&m4_m_can1{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_fdcan1_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_m_can1 */
+ /* USER CODE END m4_m_can1 */
+};
+
+&m4_spi3{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_spi3_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_spi3 */
+ /* USER CODE END m4_spi3 */
+};
+
+&m4_timers12{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim12_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers12 */
+ /* USER CODE END m4_timers12 */
+};
+
+&m4_timers15{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim15_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers15 */
+ /* USER CODE END m4_timers15 */
+};
+
+&m4_timers2{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim2_pwm_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers2 */
+ /* USER CODE END m4_timers2 */
+};
+
+&m4_timers3{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim3_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers3 */
+ /* USER CODE END m4_timers3 */
+};
+
+&m4_timers4{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_tim4_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers4 */
+ /* USER CODE END m4_timers4 */
+};
+
+&m4_timers5{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers5 */
+ /* USER CODE END m4_timers5 */
+};
+
+&m4_timers6{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers6 */
+ /* USER CODE END m4_timers6 */
+};
+
+&m4_timers7{
+ status = "okay";
+
+ /* USER CODE BEGIN m4_timers7 */
+ /* USER CODE END m4_timers7 */
+};
+
+&m4_usart6{
+ pinctrl-names = "default";
+ pinctrl-0 = <&m4_usart6_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN m4_usart6 */
+ /* USER CODE END m4_usart6 */
+};
+
+&qspi{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&quadspi_pins_mx>;
+ pinctrl-1 = <&quadspi_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN qspi */
+ /* USER CODE END qspi */
+};
+
+&rcc{
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ /* USER CODE BEGIN rcc */
+ /* USER CODE END rcc */
+};
+
+&rng1{
+ status = "okay";
+
+ /* USER CODE BEGIN rng1 */
+ /* USER CODE END rng1 */
+};
+
+&rtc{
+ status = "okay";
+
+ /* USER CODE BEGIN rtc */
+ /* USER CODE END rtc */
+};
+
+&sdmmc1{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_pins_mx>;
+ pinctrl-1 = <&sdmmc1_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc1 */
+ /* USER CODE END sdmmc1 */
+};
+
+&sdmmc2{
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_pins_mx>;
+ pinctrl-1 = <&sdmmc2_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc2_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc2 */
+ /* USER CODE END sdmmc2 */
+};
+
+&sdmmc3{
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_pins_mx>;
+ pinctrl-1 = <&sdmmc3_opendrain_pins_mx>;
+ pinctrl-2 = <&sdmmc3_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN sdmmc3 */
+ /* USER CODE END sdmmc3 */
+};
+
+&spi1{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_mx>;
+ pinctrl-1 = <&spi1_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN spi1 */
+ /* USER CODE END spi1 */
+};
+
+&tamp{
+ status = "okay";
+
+ /* USER CODE BEGIN tamp */
+ /* USER CODE END tamp */
+};
+
+&timers8{
+ status = "okay";
+
+ /* USER CODE BEGIN timers8 */
+ /* USER CODE END timers8 */
+
+ pwm{
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tim8_pwm_pins_mx>;
+ pinctrl-1 = <&tim8_pwm_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN timers8_pwm */
+ /* USER CODE END timers8_pwm */
+ };
+};
+
+&uart4{
+ u-boot,dm-pre-reloc;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&uart4_pins_mx>;
+ pinctrl-1 = <&uart4_sleep_pins_mx>;
+ status = "okay";
+
+ /* USER CODE BEGIN uart4 */
+ /* USER CODE END uart4 */
+};
+
+&usbh_ehci{
+ status = "okay";
+
+ /* USER CODE BEGIN usbh_ehci */
+ /* USER CODE END usbh_ehci */
+};
+
+&usbh_ohci{
+ status = "okay";
+
+ /* USER CODE BEGIN usbh_ohci */
+ /* USER CODE END usbh_ohci */
+};
+
+&usbphyc{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc */
+ /* USER CODE END usbphyc */
+};
+
+&usbphyc_port0{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc_port0 */
+ /* USER CODE END usbphyc_port0 */
+};
+
+&usbphyc_port1{
+ status = "okay";
+
+ /* USER CODE BEGIN usbphyc_port1 */
+ /* USER CODE END usbphyc_port1 */
+};
+
+&vrefbuf{
+ status = "okay";
+
+ /* USER CODE BEGIN vrefbuf */
+ /* USER CODE END vrefbuf */
+};
+
+/* USER CODE BEGIN addons */
+/* USER CODE END addons */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/FreeRTOSConfig.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/FreeRTOSConfig.h
new file mode 100644
index 0000000..c1a94f9
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/FreeRTOSConfig.h
@@ -0,0 +1,175 @@
+/* USER CODE BEGIN Header */
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* USER CODE END Header */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+/* Section where include file can be added */
+/* USER CODE END Includes */
+
+/* Ensure definitions are only used by the compiler, and not by the assembler. */
+#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)
+ #include <stdint.h>
+ extern uint32_t SystemCoreClock;
+ void xPortSysTickHandler(void);
+/* USER CODE BEGIN 0 */
+ extern void configureTimerForRunTimeStats(void);
+ extern unsigned long getRunTimeCounterValue(void);
+/* USER CODE END 0 */
+#endif
+#define configENABLE_FPU 0
+#define configENABLE_MPU 0
+
+#define configUSE_PREEMPTION 1
+#define configSUPPORT_STATIC_ALLOCATION 1
+#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( SystemCoreClock )
+#define configTICK_RATE_HZ ((TickType_t)1000)
+#define configMAX_PRIORITIES ( 56 )
+#define configMINIMAL_STACK_SIZE ((uint16_t)512)
+#define configTOTAL_HEAP_SIZE ((size_t)10240)
+#define configMAX_TASK_NAME_LEN ( 16 )
+#define configGENERATE_RUN_TIME_STATS 1
+#define configUSE_TRACE_FACILITY 1
+#define configUSE_16_BIT_TICKS 0
+#define configUSE_MUTEXES 1
+#define configQUEUE_REGISTRY_SIZE 8
+#define configUSE_RECURSIVE_MUTEXES 1
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
+/* Defaults to size_t for backward compatibility, but can be changed
+ if lengths will always be less than the number of bytes in a size_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( 2 )
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH 512
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_xTimerPendFunctionCall 1
+#define INCLUDE_xQueueGetMutexHolder 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+#define INCLUDE_eTaskGetState 1
+
+/*
+ * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used
+ * by the application thus the correct define need to be enabled below
+ */
+#define USE_FreeRTOS_HEAP_4
+
+/* Cortex-M specific definitions. */
+#ifdef __NVIC_PRIO_BITS
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+ #define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS 4
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
+
+/* Interrupt priorities used by the kernel port layer itself. These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+/* USER CODE BEGIN 1 */
+#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}
+/* USER CODE END 1 */
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+
+/* IMPORTANT: This define is commented when used with STM32Cube firmware, when the timebase source is SysTick,
+ to prevent overwriting SysTick_Handler defined within STM32Cube HAL */
+
+/* #define xPortSysTickHandler SysTick_Handler */
+
+/* USER CODE BEGIN 2 */
+/* Definitions needed when configGENERATE_RUN_TIME_STATS is on */
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS configureTimerForRunTimeStats
+#define portGET_RUN_TIME_COUNTER_VALUE getRunTimeCounterValue
+#define portALT_GET_RUN_TIME_COUNTER_VALUE(val) { \
+ extern uint32_t *task_times; \
+ task_times[(uint8_t)pxCurrentTCB->pcTaskName[0]] = pxCurrentTCB->ulRunTimeCounter; \
+ val = getRunTimeCounterValue(); \
+}
+/* USER CODE END 2 */
+
+/* USER CODE BEGIN Defines */
+/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */
+/* USER CODE END Defines */
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/main.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/main.h
new file mode 100644
index 0000000..f2e57c2
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/main.h
@@ -0,0 +1,174 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file main.h
+ * @brief Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#define TXT2_BOARD_REVISION 1
+#include "mcommon.h"
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+/* USER CODE END EM */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+void systickHandler(void);
+void HWPowerDown();
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define MOTOR_NSS_Pin GPIO_PIN_15
+#define MOTOR_NSS_GPIO_Port GPIOA
+#define COUNTER_1_Pin GPIO_PIN_5
+#define COUNTER_1_GPIO_Port GPIOE
+#define MOTOR_SCK_Pin GPIO_PIN_0
+#define MOTOR_SCK_GPIO_Port GPIOE
+#define IOMUX_DI_Pin GPIO_PIN_14
+#define IOMUX_DI_GPIO_Port GPIOG
+#define SERVO_PWM2_Pin GPIO_PIN_1
+#define SERVO_PWM2_GPIO_Port GPIOA
+#define SERVO_PWM3_Pin GPIO_PIN_2
+#define SERVO_PWM3_GPIO_Port GPIOA
+#define COUNTER_2_Pin GPIO_PIN_1
+#define COUNTER_2_GPIO_Port GPIOB
+#define CAN_Pin GPIO_PIN_11
+#define CAN_GPIO_Port GPIOA
+#define AIO_IN_Pin GPIO_PIN_4
+#define AIO_IN_GPIO_Port GPIOC
+#define COUNTER_3_Pin GPIO_PIN_8
+#define COUNTER_3_GPIO_Port GPIOB
+#define SERVO_PWM1_Pin GPIO_PIN_8
+#define SERVO_PWM1_GPIO_Port GPIOG
+#define CANA12_Pin GPIO_PIN_12
+#define CANA12_GPIO_Port GPIOA
+#define MOTOR_MISO_Pin GPIO_PIN_10
+#define MOTOR_MISO_GPIO_Port GPIOD
+#define COUNTER_4_Pin GPIO_PIN_14
+#define COUNTER_4_GPIO_Port GPIOB
+#define MOTOR_MOSI_Pin GPIO_PIN_6
+#define MOTOR_MOSI_GPIO_Port GPIOD
+/* USER CODE BEGIN Private defines */
+#define AUDIO_NRESET_Pin GPIO_PIN_12
+#define AUDIO_NRESET_GPIO_Port GPIOE
+#define CAN_STANDBY_Pin GPIO_PIN_4
+#define CAN_STANDBY_GPIO_Port GPIOE
+#define DISP_NRST_Pin GPIO_PIN_5
+#define DISP_NRST_GPIO_Port GPIOE
+#define ENC2_B_Pin GPIO_PIN_10
+#define ENC2_B_GPIO_Port GPIOA
+#define TOUCH_WAKE_Pin GPIO_PIN_8
+#define TOUCH_WAKE_GPIO_Port GPIOA
+#define ENC2_A_Pin GPIO_PIN_9
+#define ENC2_A_GPIO_Port GPIOA
+#define IOMUX_EN_Pin GPIO_PIN_12
+#define IOMUX_EN_GPIO_Port GPIOG
+#define AUDIO_GPIN_Pin GPIO_PIN_11
+#define AUDIO_GPIN_GPIO_Port GPIOE
+#define MOTOR_NFAULT_Pin GPIO_PIN_15
+#define MOTOR_NFAULT_GPIO_Port GPIOE
+#define PWR_BUCK_ALERT_Pin GPIO_PIN_13
+#define PWR_BUCK_ALERT_GPIO_Port GPIOE
+#define TEST_TP1_Pin GPIO_PIN_13
+#define TEST_TP1_GPIO_Port GPIOC
+#define LED_GREEN_Pin GPIO_PIN_14
+#define LED_GREEN_GPIO_Port GPIOA
+#define LED_RED_Pin GPIO_PIN_13
+#define LED_RED_GPIO_Port GPIOA
+#define PWR_BUCK_EN_Pin GPIO_PIN_3
+#define PWR_BUCK_EN_GPIO_Port GPIOA
+#define PWR_HOLD_Pin GPIO_PIN_3
+#define PWR_HOLD_GPIO_Port GPIOC
+#define AIO_PRESCALE_Pin GPIO_PIN_13
+#define AIO_PRESCALE_GPIO_Port GPIOG
+#define ENC1_B_Pin GPIO_PIN_1
+#define ENC1_B_GPIO_Port GPIOB
+#define ENC1_A_Pin GPIO_PIN_0
+#define ENC1_A_GPIO_Port GPIOB
+#define IOMUX_C_Pin GPIO_PIN_10
+#define IOMUX_C_GPIO_Port GPIOG
+#define DISP_CS_Pin GPIO_PIN_8
+#define DISP_CS_GPIO_Port GPIOE
+#define DISP_LPTE_Pin GPIO_PIN_5
+#define DISP_LPTE_GPIO_Port GPIOC
+#define DISP_MESH_Pin GPIO_PIN_7
+#define DISP_MESH_GPIO_Port GPIOE
+#define IOMUX_DO_Pin GPIO_PIN_7
+#define IOMUX_DO_GPIO_Port GPIOG
+#define CAN_TERM_Pin GPIO_PIN_10
+#define CAN_TERM_GPIO_Port GPIOE
+#define LED_BLUE_Pin GPIO_PIN_7
+#define LED_BLUE_GPIO_Port GPIOA
+#define DISP_A0_Pin GPIO_PIN_6
+#define DISP_A0_GPIO_Port GPIOA
+#define IOMUX_B_Pin GPIO_PIN_9
+#define IOMUX_B_GPIO_Port GPIOG
+#define PWR_DC_Pin GPIO_PIN_1
+#define PWR_DC_GPIO_Port GPIOE
+#define MOTOR_NSLEEP_Pin GPIO_PIN_14
+#define MOTOR_NSLEEP_GPIO_Port GPIOE
+#define RESET_OUT_Pin GPIO_PIN_15
+#define RESET_OUT_GPIO_Port GPIOD
+#define IOMUX_A_Pin GPIO_PIN_14
+#define IOMUX_A_GPIO_Port GPIOD
+#define USB_OC_Pin GPIO_PIN_4
+#define USB_OC_GPIO_Port GPIOA
+#define BUTTON_IN_Pin GPIO_PIN_13
+#define BUTTON_IN_GPIO_Port GPIOB
+#define TOUCH_INT_Pin GPIO_PIN_9
+#define TOUCH_INT_GPIO_Port GPIOE
+#define SERVO_EN_Pin GPIO_PIN_0
+#define SERVO_EN_GPIO_Port GPIOC
+#define SERVO_OC_Pin GPIO_PIN_0
+#define SERVO_OC_GPIO_Port GPIOA
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/mbox_ipcc.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/mbox_ipcc.h
new file mode 100644
index 0000000..6fad7ac
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/mbox_ipcc.h
@@ -0,0 +1,39 @@
+/**
+ ******************************************************************************
+ * @file mbox_ipcc.h
+ * @author MCD Application Team
+ * @brief Header for mbox_ipcc.c module
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#ifndef MBOX_IPCC_H_
+#define MBOX_IPCC_H_
+
+/* USER CODE BEGIN firstSection */
+/* can be used to modify / undefine following code or add new definitions */
+/* USER CODE END firstSection */
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+int MAILBOX_Notify(void *priv, uint32_t id);
+int MAILBOX_Init(void);
+int MAILBOX_Poll(struct virtio_device *vdev);
+
+/* USER CODE BEGIN lastSection */
+/* can be used to modify / undefine previous code or add new definitions */
+/* USER CODE END lastSection */
+
+#endif /* MBOX_IPCC_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp.h
new file mode 100644
index 0000000..e13dd19
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp.h
@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file openamp.h
+ * @brief Header for openamp applications
+ * @author MCD Application Team
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __openamp_H
+#define __openamp_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "openamp/open_amp.h"
+#include "openamp_conf.h"
+
+#define OPENAMP_send rpmsg_send
+#define OPENAMP_destroy_ept rpmsg_destroy_ept
+
+/* Initialize the openamp framework*/
+int MX_OPENAMP_Init(int RPMsgRole, rpmsg_ns_bind_cb ns_bind_cb);
+
+/* Deinitialize the openamp framework*/
+void OPENAMP_DeInit(void);
+
+/* Initialize the endpoint struct*/
+void OPENAMP_init_ept(struct rpmsg_endpoint *ept);
+
+/* Create and register the endpoint */
+int OPENAMP_create_endpoint(struct rpmsg_endpoint *ept, const char *name,
+ uint32_t dest, rpmsg_ept_cb cb,
+ rpmsg_ns_unbind_cb unbind_cb);
+
+/* Check for new rpmsg reception */
+void OPENAMP_check_for_message(void);
+
+/* Wait loop on endpoint ready ( message dest address is know)*/
+void OPENAMP_Wait_EndPointready(struct rpmsg_endpoint *rp_ept);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__openamp_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_conf.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_conf.h
new file mode 100644
index 0000000..1815927
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_conf.h
@@ -0,0 +1,242 @@
+/**
+ ******************************************************************************
+ * @file openamp_conf.h
+ * @author MCD Application Team
+ * @brief Configuration file for OpenAMP MW
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __OPENAMP_CONF__H__
+#define __OPENAMP_CONF__H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#if defined (__LOG_TRACE_IO_) || defined(__LOG_UART_IO_)
+#include "openamp_log.h"
+#endif
+
+ /* ########################## Mailbox Interface Selection ############################## */
+ /**
+ * @brief This is the list of Mailbox interface to be used in the OpenAMP MW
+ * Please note that not all interfaces are supported by a STM32 device
+ */
+#define MAILBOX_IPCC_IF_ENABLED
+//#define MAILBOX_HSEM_IF_ENABLED
+
+ /* Includes ------------------------------------------------------------------*/
+ /**
+ * @brief Include Maibox interface header file
+ */
+
+#ifdef MAILBOX_IPCC_IF_ENABLED
+#include "mbox_ipcc.h"
+#endif /* MAILBOX_IPCC_IF_ENABLED */
+
+#ifdef MAILBOX_HSEM_IF_ENABLED
+#include "mbox_hsem.h"
+#endif /* MAILBOX_HSEM_IF_ENABLED */
+
+ /* ########################## Virtual Diver Module Selection ############################## */
+ /**
+ * @brief This is the list of modules to be used in the OpenAMP Virtual driver module
+ * Please note that virtual driver are not supported on all stm32 families
+ */
+//#define VIRTUAL_UART_MODULE_ENABLED
+//#define VIRTUAL_I2C_MODULE_ENABLED
+
+ /* Includes ------------------------------------------------------------------*/
+ /**
+ * @brief Include Virtual Driver module's header file
+ */
+
+#ifdef VIRTUAL_UART_MODULE_ENABLED
+#include "virt_uart.h"
+#endif /* VIRTUAL_UART_MODULE_ENABLED */
+
+#ifdef VIRTUAL_I2C_MODULE_ENABLED
+#include "virt_i2c.h"
+#endif /* VIRTUAL_I2C_MODULE_ENABLED */
+
+ /* ########################## Linux Master Selection ############################## */
+ /**
+ * @brief Due to Linux compatibility, it's important to distinguish if the MASTER is Linux or not.
+ * In that case, the LINUX_RPROC_MASTER define is required
+ */
+#define LINUX_RPROC_MASTER
+
+/* USER CODE BEGIN INCLUDE */
+
+/* USER CODE END INCLUDE */
+
+/** @addtogroup OPENAMP_MW
+ * @{
+ */
+
+/** @defgroup OPENAMP_CONF OPENAMP_CONF
+ * @brief Configuration file for Openamp mw
+ * @{
+ */
+
+/** @defgroup OPENAMP_CONF_Exported_Variables OPENAMP_CONF_Exported_Variables
+ * @brief Public variables.
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPENAMP_CONF_Exported_Defines OPENAMP_CONF_Exported_Defines
+ * @brief Defines for configuration of the Openamp mw
+ * @{
+ */
+
+#if defined (__ICCARM__)
+/*
+ * For IAR, the .icf file should contain the following lines:
+ * define symbol __OPENAMP_region_start__ = BASE_ADDRESS; (0x38000400 for example)
+ * define symbol __OPENAMP_region_size__ = MEM_SIZE; (0xB000 as example)
+ *
+ * export symbol __OPENAMP_region_start__;
+ * export symbol __OPENAMP_region_size__;
+ */
+extern const uint32_t __OPENAMP_region_start__;
+extern const uint8_t __OPENAMP_region_size__;
+#define SHM_START_ADDRESS ((metal_phys_addr_t)&__OPENAMP_region_start__)
+#define SHM_SIZE ((size_t)&__OPENAMP_region_size__)
+
+#elif defined(__CC_ARM)
+/*
+ * For MDK-ARM, the scatter file .sct should contain the following line:
+ * LR_IROM1 .... {
+ * ...
+ * __OpenAMP_SHMEM__ 0x38000400 EMPTY 0x0000B000 {} ; Shared Memory area used by OpenAMP
+ * }
+ *
+ */
+extern unsigned int Image$$__OpenAMP_SHMEM__$$Base;
+extern unsigned int Image$$__OpenAMP_SHMEM__$$ZI$$Length;
+#define SHM_START_ADDRESS (unsigned int)&Image$$__OpenAMP_SHMEM__$$Base
+#define SHM_SIZE ((size_t)&Image$$__OpenAMP_SHMEM__$$ZI$$Length)
+
+#else
+/*
+ * for GCC add the following content to the .ld file:
+ * MEMORY
+ * {
+ * ...
+ * OPEN_AMP_SHMEM (xrw) : ORIGIN = 0x38000400, LENGTH = 63K
+ * }
+ * __OPENAMP_region_start__ = ORIGIN(OPEN_AMP_SHMEM);
+ * __OPENAMP_region_end__ = ORIGIN(OPEN_AMP_SHMEM) + LENGTH(OPEN_AMP_SHMEM);
+ *
+ * using the LENGTH(OPEN_AMP_SHMEM) to set the SHM_SIZE lead to a crash thus we
+ * use the start and end address.
+ */
+
+extern int __OPENAMP_region_start__[]; /* defined by linker script */
+extern int __OPENAMP_region_end__[]; /* defined by linker script */
+
+#define SHM_START_ADDRESS ((metal_phys_addr_t)__OPENAMP_region_start__)
+#define SHM_SIZE (size_t)((void *)__OPENAMP_region_end__ - (void *) __OPENAMP_region_start__)
+
+#endif
+
+#if defined LINUX_RPROC_MASTER
+#define VRING_RX_ADDRESS -1 /* allocated by Master processor: CA7 */
+#define VRING_TX_ADDRESS -1 /* allocated by Master processor: CA7 */
+#define VRING_BUFF_ADDRESS -1 /* allocated by Master processor: CA7 */
+#define VRING_ALIGNMENT 16 /* fixed to match with linux constraint */
+#define VRING_NUM_BUFFS 16 /* number of rpmsg buffer */
+#else
+
+#define VRING_RX_ADDRESS 0x10040000 /* allocated by Master processor: CA7 */
+#define VRING_TX_ADDRESS 0x10040400 /* allocated by Master processor: CA7 */
+#define VRING_BUFF_ADDRESS 0x10040800 /* allocated by Master processor: CA7 */
+#define VRING_ALIGNMENT 16 /* fixed to match with 4k page alignement requested by linux */
+#define VRING_NUM_BUFFS 16 /* number of rpmsg buffer */
+#endif
+/* Fixed parameter */
+#define NUM_RESOURCE_ENTRIES 2
+#define VRING_COUNT 2
+#define VDEV_ID 0xFF
+#define VRING0_ID 0 /* VRING0 ID (master to remote) fixed to 0 for linux compatibility*/
+#define VRING1_ID 1 /* VRING1 ID (remote to master) fixed to 1 for linux compatibility */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPENAMP_CONF_Exported_Macros OPENAMP_CONF_Exported_Macros
+ * @brief Aliases.
+ * @{
+ */
+
+/* DEBUG macros */
+
+#if defined (__LOG_TRACE_IO_) || defined(__LOG_UART_IO_)
+ #define OPENAMP_log_dbg log_dbg
+ #define OPENAMP_log_info log_info
+ #define OPENAMP_log_warn log_warn
+ #define OPENAMP_log_err log_err
+#else
+ #define OPENAMP_log_dbg(...)
+ #define OPENAMP_log_info(...)
+ #define OPENAMP_log_warn(...)
+ #define OPENAMP_log_err(...)
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup OPENAMP_CONF_Exported_Types OPENAMP_CONF_Exported_Types
+ * @brief Types.
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPENAMP_CONF_Exported_FunctionsPrototype OPENAMP_CONF_Exported_FunctionsPrototype
+ * @brief Declaration of public functions for OpenAMP mw.
+ * @{
+ */
+
+/* Exported functions -------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __OPENAMP_CONF__H__ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_log.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_log.h
new file mode 100644
index 0000000..8d33fe1
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/openamp_log.h
@@ -0,0 +1,134 @@
+/**
+ ******************************************************************************
+ * @file log.h
+ * @author MCD Application Team
+ * @brief logging services
+ ******************************************************************************
+ *
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup LOG
+ * @{
+ */
+
+/** @addtogroup stm32mp1xx_Log
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __LOG_STM32MP1XX_H
+#define __LOG_STM32MP1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32MP1xx_Log_Includes
+ * @{
+ */
+#include "stm32mp1xx_hal.h"
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_Log_Exported_Constants
+ * @{
+ */
+#if defined (__LOG_TRACE_IO_)
+#define SYSTEM_TRACE_BUF_SZ 2048
+#endif
+
+#define LOGQUIET 0
+#define LOGERR 1
+#define LOGWARN 2
+#define LOGINFO 3
+#define LOGDBG 4
+
+#ifndef LOGLEVEL
+#define LOGLEVEL LOGINFO
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_Log_Exported_types
+ * @{
+ */
+#if defined (__LOG_TRACE_IO_)
+extern char system_log_buf[SYSTEM_TRACE_BUF_SZ]; /*!< buffer for debug traces */
+#endif /* __LOG_TRACE_IO_ */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_Log_Exported_Macros
+ * @{
+ */
+#if defined (__LOG_TRACE_IO_) || defined(__LOG_UART_IO_)
+#if LOGLEVEL >= LOGDBG
+#define log_dbg(fmt, ...) printf("[%05ld.%03ld][DBG ]" fmt, HAL_GetTick()/1000, HAL_GetTick() % 1000, ##__VA_ARGS__)
+#else
+#define log_dbg(fmt, ...)
+#endif
+#if LOGLEVEL >= LOGINFO
+#define log_info(fmt, ...) printf("[%05ld.%03ld][INFO ]" fmt, HAL_GetTick()/1000, HAL_GetTick() % 1000, ##__VA_ARGS__)
+#else
+#define log_info(fmt, ...)
+#endif
+#if LOGLEVEL >= LOGWARN
+#define log_warn(fmt, ...) printf("[%05ld.%03ld][WARN ]" fmt, HAL_GetTick()/1000, HAL_GetTick() % 1000, ##__VA_ARGS__)
+#else
+#define log_warn(fmt, ...)
+#endif
+#if LOGLEVEL >= LOGERR
+#define log_err(fmt, ...) printf("[%05ld.%03ld][ERR ]" fmt, HAL_GetTick()/1000, HAL_GetTick() % 1000, ##__VA_ARGS__)
+#else
+#define log_err(fmt, ...)
+#endif
+#else
+#define log_dbg(fmt, ...)
+#define log_info(fmt, ...)
+#define log_warn(fmt, ...)
+#define log_err(fmt, ...)
+#endif /* __LOG_TRACE_IO_ */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_Log_Exported_Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__LOG_STM32MP1XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/rsc_table.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/rsc_table.h
new file mode 100644
index 0000000..1b1ca47
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/rsc_table.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ */
+
+/* This file populates resource table for BM remote
+ * for use by the Linux Master */
+
+#ifndef RSC_TABLE_H_
+#define RSC_TABLE_H_
+
+#include "openamp/open_amp.h"
+#include "openamp_conf.h"
+
+/* Place resource table in special ELF section */
+//#define __section_t(S) __attribute__((__section__(#S)))
+//#define __resource __section_t(.resource_table)
+
+/* Resource table for the given remote */
+struct shared_resource_table {
+ unsigned int version;
+ unsigned int num;
+ unsigned int reserved[2];
+ unsigned int offset[NUM_RESOURCE_ENTRIES];
+ /* text carveout entry */
+
+ /* rpmsg vdev entry */
+ struct fw_rsc_vdev vdev;
+ struct fw_rsc_vdev_vring vring0;
+ struct fw_rsc_vdev_vring vring1;
+ struct fw_rsc_trace cm_trace;
+};
+
+void resource_table_init(int RPMsgRole, void **table_ptr, int *length);
+
+#endif /* RSC_TABLE_H_ */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_hal_conf.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_hal_conf.h
new file mode 100644
index 0000000..7ea36c6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_hal_conf.h
@@ -0,0 +1,396 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_conf.h
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_CONF_H
+#define STM32MP1xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+/*#define HAL_CEC_MODULE_ENABLED */
+/*#define HAL_CRC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_DAC_MODULE_ENABLED */
+/*#define HAL_DCMI_MODULE_ENABLED */
+/*#define HAL_DSI_MODULE_ENABLED */
+/*#define HAL_DFSDM_MODULE_ENABLED */
+/*#define HAL_DTS_MODULE_ENABLED */
+/*#define HAL_ETH_MODULE_ENABLED */
+#define HAL_FDCAN_MODULE_ENABLED
+/*#define HAL_HASH_MODULE_ENABLED */
+/*#define HAL_HCD_MODULE_ENABLED */
+#define HAL_HSEM_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED */
+/*#define HAL_I2S_MODULE_ENABLED */
+#define HAL_IPCC_MODULE_ENABLED
+/*#define HAL_IWDG_MODULE_ENABLED */
+/*#define HAL_LPTIM_MODULE_ENABLED */
+/*#define HAL_LTDC_MODULE_ENABLED */
+/*#define HAL_NAND_MODULE_ENABLED */
+/*#define HAL_NOR_MODULE_ENABLED */
+/*#define HAL_PCD_MODULE_ENABLED */
+/*#define HAL_QSPI_MODULE_ENABLED */
+/*#define HAL_RNG_MODULE_ENABLED */
+/*#define HAL_SAI_MODULE_ENABLED */
+/*#define HAL_SD_MODULE_ENABLED */
+/*#define HAL_MMC_MODULE_ENABLED */
+/*#define HAL_RTC_MODULE_ENABLED */
+/*#define HAL_SMBUS_MODULE_ENABLED */
+/*#define HAL_SPDIFRX_MODULE_ENABLED */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_SRAM_MODULE_ENABLED */
+/*#define HAL_TAMP_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED */
+/*#define HAL_SMARTCARD_MODULE_ENABLED */
+/*#define HAL_WWDG_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+/* #define HAL_DMA_MODULE_ENABLED */
+/* #define HAL_MDMA_MODULE_ENABLED */
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+ * @brief This is the list of modules where register callback can be used
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0u
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
+#define USE_HAL_UART_REGISTER_CALLBACKS 0u
+#define USE_HAL_USART_REGISTER_CALLBACKS 0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE (24000000U) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE (64000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 32000U
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal oscillator (CSI) default value.
+ * This value is the default CSI value after Reset.
+ */
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */
+ /* Warning: Must be set to higher priority for HAL_Delay() */
+ /* and HAL_GetTick() usage under interrupt context */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 0U
+#define INSTRUCTION_CACHE_ENABLE 0U
+#define DATA_CACHE_ENABLE 0U
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32mp1xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32mp1xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+ #include "stm32mp1xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32mp1xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32mp1xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32mp1xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32mp1xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32mp1xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32mp1xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32mp1xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32mp1xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+ #include "stm32mp1xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32mp1xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32mp1xx_hal_hcd.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32mp1xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32mp1xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32mp1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32mp1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32mp1xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32mp1xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32mp1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32mp1xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32mp1xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32mp1xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32mp1xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32mp1xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32mp1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32mp1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32mp1xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32mp1xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32mp1xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32mp1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32mp1xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_TAMP_MODULE_ENABLED
+ #include "stm32mp1xx_hal_tamp.h"
+#endif /* HAL_TAMP_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32mp1xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32mp1xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32mp1xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32mp1xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_it.h b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_it.h
new file mode 100644
index 0000000..d9ca873
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Inc/stm32mp1xx_it.h
@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_IT_H
+#define __STM32MP1xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+void SysTick_Handler(void);
+void IPCC_RX1_IRQHandler(void);
+void IPCC_TX1_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/app_freertos.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/app_freertos.c
new file mode 100644
index 0000000..fe928b5
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/app_freertos.c
@@ -0,0 +1,95 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name : app_freertos.c
+ * Description : Code for freertos applications
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "FreeRTOS.h"
+#include "task.h"
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN Variables */
+
+/* USER CODE END Variables */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN FunctionPrototypes */
+
+/* USER CODE END FunctionPrototypes */
+
+/* Hook prototypes */
+void configureTimerForRunTimeStats(void);
+unsigned long getRunTimeCounterValue(void);
+void vApplicationIdleHook(void);
+
+/* USER CODE BEGIN 1 */
+/* Functions needed when configGENERATE_RUN_TIME_STATS is on */
+__weak void configureTimerForRunTimeStats(void)
+{
+
+}
+
+__weak unsigned long getRunTimeCounterValue(void)
+{
+return 0;
+}
+/* USER CODE END 1 */
+
+/* USER CODE BEGIN 2 */
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+ HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+}
+/* USER CODE END 2 */
+
+/* Private application code --------------------------------------------------*/
+/* USER CODE BEGIN Application */
+
+/* USER CODE END Application */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/main.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/main.c
new file mode 100644
index 0000000..cbe4570
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/main.c
@@ -0,0 +1,1144 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file main.c
+ * @brief Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "cmsis_os.h"
+#include "openamp.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "ftext.h"
+#include "HWFDCAN.h"
+#include "ftcalib.h"
+#include "HWInit.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+typedef StaticTask_t osStaticThreadDef_t;
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+
+FDCAN_HandleTypeDef hfdcan1;
+
+IPCC_HandleTypeDef hipcc;
+
+SPI_HandleTypeDef hspi3;
+
+TIM_HandleTypeDef htim2;
+TIM_HandleTypeDef htim3;
+TIM_HandleTypeDef htim4;
+TIM_HandleTypeDef htim5;
+TIM_HandleTypeDef htim6;
+TIM_HandleTypeDef htim7;
+TIM_HandleTypeDef htim12;
+TIM_HandleTypeDef htim15;
+
+UART_HandleTypeDef huart6;
+
+/* Definitions for ftserver */
+osThreadId_t ftserverHandle;
+uint32_t ftserverBuffer[ 2048 ];
+osStaticThreadDef_t ftserverControlBlock;
+const osThreadAttr_t ftserver_attributes = {
+ .name = "ftserver",
+ .stack_mem = &ftserverBuffer[0],
+ .stack_size = sizeof(ftserverBuffer),
+ .cb_mem = &ftserverControlBlock,
+ .cb_size = sizeof(ftserverControlBlock),
+ .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for hwloop */
+osThreadId_t hwloopHandle;
+uint32_t hwloopBuffer[ 1024 ];
+osStaticThreadDef_t hwloopControlBlock;
+const osThreadAttr_t hwloop_attributes = {
+ .name = "hwloop",
+ .stack_mem = &hwloopBuffer[0],
+ .stack_size = sizeof(hwloopBuffer),
+ .cb_mem = &hwloopControlBlock,
+ .cb_size = sizeof(hwloopControlBlock),
+ .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for NotificationThr */
+osThreadId_t NotificationThrHandle;
+uint32_t NotificationThrBuffer[ 1024 ];
+osStaticThreadDef_t NotificationThrControlBlock;
+const osThreadAttr_t NotificationThr_attributes = {
+ .name = "NotificationThr",
+ .stack_mem = &NotificationThrBuffer[0],
+ .stack_size = sizeof(NotificationThrBuffer),
+ .cb_mem = &NotificationThrControlBlock,
+ .cb_size = sizeof(NotificationThrControlBlock),
+ .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for RTExtEngine */
+osThreadId_t RTExtEngineHandle;
+uint32_t RTExtEngineBuffer[ 512 ];
+osStaticThreadDef_t RTExtEngineControlBlock;
+const osThreadAttr_t RTExtEngine_attributes = {
+ .name = "RTExtEngine",
+ .stack_mem = &RTExtEngineBuffer[0],
+ .stack_size = sizeof(RTExtEngineBuffer),
+ .cb_mem = &RTExtEngineControlBlock,
+ .cb_size = sizeof(RTExtEngineControlBlock),
+ .priority = (osPriority_t) osPriorityLow,
+};
+/* Definitions for MotorTask */
+osThreadId_t MotorTaskHandle;
+uint32_t MotorTaskBuffer[ 512 ];
+osStaticThreadDef_t MotorTaskControlBlock;
+const osThreadAttr_t MotorTask_attributes = {
+ .name = "MotorTask",
+ .stack_mem = &MotorTaskBuffer[0],
+ .stack_size = sizeof(MotorTaskBuffer),
+ .cb_mem = &MotorTaskControlBlock,
+ .cb_size = sizeof(MotorTaskControlBlock),
+ .priority = (osPriority_t) osPriorityBelowNormal,
+};
+/* USER CODE BEGIN PV */
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void PeriphCommonClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_FDCAN1_Init(void);
+static void MX_IPCC_Init(void);
+static void MX_SPI3_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_TIM6_Init(void);
+static void MX_TIM7_Init(void);
+static void MX_USART6_UART_Init(void);
+static void MX_TIM15_Init(void);
+static void MX_TIM12_Init(void);
+static void MX_TIM3_Init(void);
+static void MX_TIM4_Init(void);
+static void MX_TIM5_Init(void);
+int MX_OPENAMP_Init(int RPMsgRole, rpmsg_ns_bind_cb ns_bind_cb);
+void appmain(void *argument);
+extern void ftopThread(void *argument);
+extern void sendThread(void *argument);
+extern void HWFDCAN_thread(void *argument);
+extern void MotorTaskStart(void *argument);
+
+/* USER CODE BEGIN PFP */
+uint32_t *task_times;
+
+unsigned long getRunTimeCounterValue(void)
+{
+ return TIM5->CNT;
+}
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+static GPIO_InitTypeDef GPIO_InitStruct = {0};
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* USER CODE BEGIN 1 */
+ /* USER CODE END 1 */
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* IPCC initialisation */
+ MX_IPCC_Init();
+ /* OpenAmp initialisation ---------------------------------*/
+ MX_OPENAMP_Init(RPMSG_REMOTE, NULL);
+
+ /* USER CODE BEGIN SysInit */
+ HWInit();
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_ADC1_Init();
+ MX_FDCAN1_Init();
+ MX_SPI3_Init();
+ MX_TIM2_Init();
+ MX_TIM6_Init();
+ MX_TIM7_Init();
+ MX_USART6_UART_Init();
+ MX_TIM15_Init();
+ MX_TIM12_Init();
+ MX_TIM3_Init();
+ MX_TIM4_Init();
+ MX_TIM5_Init();
+ /* USER CODE BEGIN 2 */
+ SWInit();
+ /* USER CODE END 2 */
+
+ /* Init scheduler */
+ osKernelInitialize();
+
+ /* USER CODE BEGIN RTOS_MUTEX */
+ /* add mutexes, ... */
+ /* USER CODE END RTOS_MUTEX */
+
+ /* USER CODE BEGIN RTOS_SEMAPHORES */
+ /* add semaphores, ... */
+ /* USER CODE END RTOS_SEMAPHORES */
+
+ /* USER CODE BEGIN RTOS_TIMERS */
+ /* start timers, add new ones, ... */
+ /* USER CODE END RTOS_TIMERS */
+
+ /* USER CODE BEGIN RTOS_QUEUES */
+ /* add queues, ... */
+ /* USER CODE END RTOS_QUEUES */
+
+ /* Create the thread(s) */
+ /* creation of ftserver */
+ ftserverHandle = osThreadNew(appmain, NULL, &ftserver_attributes);
+
+ /* creation of hwloop */
+ hwloopHandle = osThreadNew(ftopThread, NULL, &hwloop_attributes);
+
+ /* creation of NotificationThr */
+ NotificationThrHandle = osThreadNew(sendThread, NULL, &NotificationThr_attributes);
+
+ /* creation of RTExtEngine */
+ RTExtEngineHandle = osThreadNew(HWFDCAN_thread, NULL, &RTExtEngine_attributes);
+
+ /* creation of MotorTask */
+ MotorTaskHandle = osThreadNew(MotorTaskStart, NULL, &MotorTask_attributes);
+
+ /* USER CODE BEGIN RTOS_THREADS */
+ /* add threads, ... */
+ ThreadsInit();
+ /* USER CODE END RTOS_THREADS */
+
+ /* Start scheduler */
+ osKernelStart();
+
+ /* We should never get here as control is now taken by the scheduler */
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Configure LSE Drive Capability
+ */
+ HAL_PWR_EnableBkUpAccess();
+ __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
+ /** Initializes the CPU, AHB and APB busses clocks
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI|RCC_OSCILLATORTYPE_HSI
+ |RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSIDivValue = RCC_HSI_DIV1;
+ RCC_OscInitStruct.CSIState = RCC_CSI_ON;
+ RCC_OscInitStruct.CSICalibrationValue = 16;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLL12SOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 3;
+ RCC_OscInitStruct.PLL.PLLN = 81;
+ RCC_OscInitStruct.PLL.PLLP = 1;
+ RCC_OscInitStruct.PLL.PLLQ = 2;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLFRACV = 0;
+ RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_INTEGER;
+ RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL2.PLLSource = RCC_PLL12SOURCE_HSE;
+ RCC_OscInitStruct.PLL2.PLLM = 3;
+ RCC_OscInitStruct.PLL2.PLLN = 66;
+ RCC_OscInitStruct.PLL2.PLLP = 2;
+ RCC_OscInitStruct.PLL2.PLLQ = 2;
+ RCC_OscInitStruct.PLL2.PLLR = 1;
+ RCC_OscInitStruct.PLL2.PLLFRACV = 0;
+ RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_INTEGER;
+ RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL3.PLLSource = RCC_PLL3SOURCE_HSE;
+ RCC_OscInitStruct.PLL3.PLLM = 2;
+ RCC_OscInitStruct.PLL3.PLLN = 50;
+ RCC_OscInitStruct.PLL3.PLLP = 3;
+ RCC_OscInitStruct.PLL3.PLLQ = 5;
+ RCC_OscInitStruct.PLL3.PLLR = 12;
+ RCC_OscInitStruct.PLL3.PLLRGE = RCC_PLL3IFRANGE_1;
+ RCC_OscInitStruct.PLL3.PLLFRACV = 0;
+ RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_INTEGER;
+ RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL4.PLLSource = RCC_PLL4SOURCE_HSE;
+ RCC_OscInitStruct.PLL4.PLLM = 6;
+ RCC_OscInitStruct.PLL4.PLLN = 125;
+ RCC_OscInitStruct.PLL4.PLLP = 10;
+ RCC_OscInitStruct.PLL4.PLLQ = 10;
+ RCC_OscInitStruct.PLL4.PLLR = 10;
+ RCC_OscInitStruct.PLL4.PLLRGE = RCC_PLL4IFRANGE_0;
+ RCC_OscInitStruct.PLL4.PLLFRACV = 0;
+ RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** RCC Clock Config
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_ACLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+ |RCC_CLOCKTYPE_PCLK3|RCC_CLOCKTYPE_PCLK4
+ |RCC_CLOCKTYPE_PCLK5|RCC_CLOCKTYPE_MPU;
+ RCC_ClkInitStruct.MPUInit.MPU_Clock = RCC_MPUSOURCE_PLL1;
+ RCC_ClkInitStruct.MPUInit.MPU_Div = RCC_MPU_DIV2;
+ RCC_ClkInitStruct.AXISSInit.AXI_Clock = RCC_AXISSOURCE_PLL2;
+ RCC_ClkInitStruct.AXISSInit.AXI_Div = RCC_AXI_DIV1;
+ RCC_ClkInitStruct.MCUInit.MCU_Clock = RCC_MCUSSOURCE_PLL3;
+ RCC_ClkInitStruct.MCUInit.MCU_Div = RCC_MCU_DIV1;
+ RCC_ClkInitStruct.APB4_Div = RCC_APB4_DIV2;
+ RCC_ClkInitStruct.APB5_Div = RCC_APB5_DIV4;
+ RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
+ RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
+ RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Set the HSE division factor for RTC clock
+ */
+ __HAL_RCC_RTC_HSEDIV(1);
+}
+
+/**
+ * @brief Peripherals Common Clock Configuration
+ * @retval None
+ */
+void PeriphCommonClock_Config(void)
+{
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+ /** Initializes the common periph clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER;
+ PeriphClkInit.CkperClockSelection = RCC_CKPERCLKSOURCE_HSE;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/**
+ * @brief ADC1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_ADC1_Init(void)
+{
+
+ /* USER CODE BEGIN ADC1_Init 0 */
+
+ /* USER CODE END ADC1_Init 0 */
+
+ ADC_MultiModeTypeDef multimode = {0};
+ ADC_ChannelConfTypeDef sConfig = {0};
+
+ /* USER CODE BEGIN ADC1_Init 1 */
+ hadc1.Instance = ADC1;
+ /* Sometime ADC1 state is unpredictable */
+ __HAL_ADC_DISABLE_IT(&hadc1, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ __HAL_ADC_CLEAR_FLAG(&hadc1, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ LL_ADC_REG_StopConversion(ADC1);
+ /* Workaround */
+#undef ADC_SAMPLETIME_32CYCLES_5
+#define ADC_SAMPLETIME_32CYCLES_5 adcsampling
+ /* USER CODE END ADC1_Init 1 */
+ /** Common config
+ */
+ hadc1.Instance = ADC1;
+ hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
+ hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ hadc1.Init.LowPowerAutoWait = DISABLE;
+ hadc1.Init.ContinuousConvMode = DISABLE;
+ hadc1.Init.NbrOfConversion = 1;
+ hadc1.Init.DiscontinuousConvMode = DISABLE;
+ hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T6_TRGO;
+ hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
+ hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+ hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
+ hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+ hadc1.Init.OversamplingMode = DISABLE;
+ if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Configure the ADC multi-mode
+ */
+ multimode.Mode = ADC_MODE_INDEPENDENT;
+ if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /** Configure Regular Channel
+ */
+ sConfig.Channel = ADC_CHANNEL_4;
+ sConfig.Rank = ADC_REGULAR_RANK_1;
+ sConfig.SamplingTime = ADC_SAMPLETIME_32CYCLES_5;
+ sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ sConfig.Offset = 0;
+ if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN ADC1_Init 2 */
+
+ /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+ * @brief FDCAN1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_FDCAN1_Init(void)
+{
+
+ /* USER CODE BEGIN FDCAN1_Init 0 */
+
+ /* USER CODE END FDCAN1_Init 0 */
+
+ /* USER CODE BEGIN FDCAN1_Init 1 */
+
+ /* USER CODE END FDCAN1_Init 1 */
+ hfdcan1.Instance = FDCAN1;
+ hfdcan1.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+ hfdcan1.Init.Mode = FDCAN_MODE_BUS_MONITORING;
+ hfdcan1.Init.AutoRetransmission = DISABLE;
+ hfdcan1.Init.TransmitPause = DISABLE;
+ hfdcan1.Init.ProtocolException = ENABLE;
+ hfdcan1.Init.NominalPrescaler = 1;
+ hfdcan1.Init.NominalSyncJumpWidth = 1;
+ hfdcan1.Init.NominalTimeSeg1 = 2;
+ hfdcan1.Init.NominalTimeSeg2 = 2;
+ hfdcan1.Init.DataPrescaler = 1;
+ hfdcan1.Init.DataSyncJumpWidth = 1;
+ hfdcan1.Init.DataTimeSeg1 = 1;
+ hfdcan1.Init.DataTimeSeg2 = 1;
+ hfdcan1.Init.MessageRAMOffset = 0;
+ hfdcan1.Init.StdFiltersNbr = 3;
+ hfdcan1.Init.ExtFiltersNbr = 2;
+ hfdcan1.Init.RxFifo0ElmtsNbr = 16;
+ hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+ hfdcan1.Init.RxFifo1ElmtsNbr = 16;
+ hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+ hfdcan1.Init.RxBuffersNbr = 2;
+ hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+ hfdcan1.Init.TxEventsNbr = 32;
+ hfdcan1.Init.TxBuffersNbr = 20;
+ hfdcan1.Init.TxFifoQueueElmtsNbr = 0;
+ hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+ hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+ if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN FDCAN1_Init 2 */
+ /* No interrupts */
+ FDCAN1->ILE &= ~3;
+ FDCAN1->IE &= 0x3fefffff;
+
+ /* USER CODE END FDCAN1_Init 2 */
+
+}
+
+/**
+ * @brief IPCC Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_IPCC_Init(void)
+{
+
+ /* USER CODE BEGIN IPCC_Init 0 */
+
+ /* USER CODE END IPCC_Init 0 */
+
+ /* USER CODE BEGIN IPCC_Init 1 */
+
+ /* USER CODE END IPCC_Init 1 */
+ hipcc.Instance = IPCC;
+ if (HAL_IPCC_Init(&hipcc) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN IPCC_Init 2 */
+
+ /* USER CODE END IPCC_Init 2 */
+
+}
+
+/**
+ * @brief SPI3 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_SPI3_Init(void)
+{
+
+ /* USER CODE BEGIN SPI3_Init 0 */
+ /* Fix problem with CubeMX constants */
+ /* Workaround for dynamic parameters */
+#undef SPI_MASTER_INTERDATA_IDLENESS_13CYCLE
+#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE spi3idleness
+#undef SPI_BAUDRATEPRESCALER_2
+#undef SPI_BAUDRATEPRESCALER_16
+#define SPI_BAUDRATEPRESCALER_2 spi3divider
+#define SPI_BAUDRATEPRESCALER_16 spi3divider
+
+ /* Stop SPI3 */
+ SPI3->IER = 0;
+ CLEAR_BIT(SPI3->CR1, SPI_CR1_SPE | SPI_CR1_CSTART);
+ SPI3->IFCR = 0xff8; /* TODO */
+
+ /* USER CODE END SPI3_Init 0 */
+
+ /* USER CODE BEGIN SPI3_Init 1 */
+
+ /* USER CODE END SPI3_Init 1 */
+ /* SPI3 parameter configuration*/
+ hspi3.Instance = SPI3;
+ hspi3.Init.Mode = SPI_MODE_MASTER;
+ hspi3.Init.Direction = SPI_DIRECTION_2LINES;
+ hspi3.Init.DataSize = SPI_DATASIZE_16BIT;
+ hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
+ hspi3.Init.CLKPhase = SPI_PHASE_2EDGE;
+ hspi3.Init.NSS = SPI_NSS_HARD_OUTPUT;
+ hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
+ hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
+ hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
+ hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+ hspi3.Init.CRCPolynomial = 0x0;
+ hspi3.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+ hspi3.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
+ hspi3.Init.FifoThreshold = SPI_FIFO_THRESHOLD_04DATA;
+ hspi3.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+ hspi3.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+ hspi3.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
+ hspi3.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_13CYCLE;
+ hspi3.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_ENABLE;
+ hspi3.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
+ hspi3.Init.IOSwap = SPI_IO_SWAP_DISABLE;
+ if (HAL_SPI_Init(&hspi3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN SPI3_Init 2 */
+ /* USER CODE END SPI3_Init 2 */
+
+}
+
+/**
+ * @brief TIM2 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM2_Init(void)
+{
+
+ /* USER CODE BEGIN TIM2_Init 0 */
+ /* Stop output */
+ GPIO_InitStruct.Pin = SERVO_PWM1_Pin | SERVO_PWM2_Pin | SERVO_PWM3_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(SERVO_PWM2_GPIO_Port, &GPIO_InitStruct);
+ /* USER CODE END TIM2_Init 0 */
+
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ TIM_OC_InitTypeDef sConfigOC = {0};
+
+ /* USER CODE BEGIN TIM2_Init 1 */
+
+ /* USER CODE END TIM2_Init 1 */
+ htim2.Instance = TIM2;
+ htim2.Init.Prescaler = Prescaler;
+ htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim2.Init.Period = SERVO_PERIOD;
+ htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
+ if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sConfigOC.OCMode = TIM_OCMODE_PWM1;
+ sConfigOC.Pulse = SERVO_MID_PULSE;
+ sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM2_Init 2 */
+ if (HAL_TIM_OnePulse_Init(&htim2, TIM_OPMODE_REPETITIVE) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE END TIM2_Init 2 */
+ HAL_TIM_MspPostInit(&htim2);
+
+}
+
+/**
+ * @brief TIM3 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM3_Init(void)
+{
+
+ /* USER CODE BEGIN TIM3_Init 0 */
+
+ /* USER CODE END TIM3_Init 0 */
+
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ TIM_IC_InitTypeDef sConfigIC = {0};
+
+ /* USER CODE BEGIN TIM3_Init 1 */
+
+ /* USER CODE END TIM3_Init 1 */
+ htim3.Instance = TIM3;
+ htim3.Init.Prescaler = 0;
+ htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim3.Init.Period = 0;
+ htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_IC_Init(&htim3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+ sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
+ sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
+ sConfigIC.ICFilter = 0;
+ if (HAL_TIM_IC_ConfigChannel(&htim3, &sConfigIC, TIM_CHANNEL_4) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM3_Init 2 */
+
+ /* USER CODE END TIM3_Init 2 */
+
+}
+
+/**
+ * @brief TIM4 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM4_Init(void)
+{
+
+ /* USER CODE BEGIN TIM4_Init 0 */
+
+ /* USER CODE END TIM4_Init 0 */
+
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ TIM_IC_InitTypeDef sConfigIC = {0};
+
+ /* USER CODE BEGIN TIM4_Init 1 */
+
+ /* USER CODE END TIM4_Init 1 */
+ htim4.Instance = TIM4;
+ htim4.Init.Prescaler = 0;
+ htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim4.Init.Period = 0;
+ htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_IC_Init(&htim4) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+ sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
+ sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
+ sConfigIC.ICFilter = 0;
+ if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_3) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM4_Init 2 */
+
+ /* USER CODE END TIM4_Init 2 */
+
+}
+
+/**
+ * @brief TIM5 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM5_Init(void)
+{
+
+ /* USER CODE BEGIN TIM5_Init 0 */
+#if !COLLECT_TASK_INFO
+ return;
+#endif
+ /* USER CODE END TIM5_Init 0 */
+
+ TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+ /* USER CODE BEGIN TIM5_Init 1 */
+
+ /* USER CODE END TIM5_Init 1 */
+ htim5.Instance = TIM5;
+ htim5.Init.Prescaler = 2000;
+ htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim5.Init.Period = 0xffffffff;
+ htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
+ if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM5_Init 2 */
+
+ /* USER CODE END TIM5_Init 2 */
+
+}
+
+/**
+ * @brief TIM6 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM6_Init(void)
+{
+
+ /* USER CODE BEGIN TIM6_Init 0 */
+
+ /* USER CODE END TIM6_Init 0 */
+
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+ /* USER CODE BEGIN TIM6_Init 1 */
+
+ /* USER CODE END TIM6_Init 1 */
+ htim6.Instance = TIM6;
+ htim6.Init.Prescaler = PrescalerI18;
+ htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim6.Init.Period = MuxerDelay;
+ htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_TIM_OnePulse_Init(&htim6, TIM_OPMODE_SINGLE) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM6_Init 2 */
+
+ /* USER CODE END TIM6_Init 2 */
+
+}
+
+/**
+ * @brief TIM7 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM7_Init(void)
+{
+
+ /* USER CODE BEGIN TIM7_Init 0 */
+
+ /* USER CODE END TIM7_Init 0 */
+
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+ /* USER CODE BEGIN TIM7_Init 1 */
+ htim7.Instance = TIM7;
+ __HAL_TIM_DISABLE_IT(&htim7, TIM_IT_UPDATE); /* TIM state can be unpredictable */
+ __HAL_TIM_CLEAR_IT(&htim7, TIM_IT_UPDATE);
+ HAL_TIM_OnePulse_DeInit(&htim7);
+ /* USER CODE END TIM7_Init 1 */
+ htim7.Instance = TIM7;
+ htim7.Init.Prescaler = PrescalerI18;
+ htim7.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim7.Init.Period = MuxerDelay;
+ htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_Base_Init(&htim7) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_TIM_OnePulse_Init(&htim7, TIM_OPMODE_SINGLE) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM7_Init 2 */
+
+ /* USER CODE END TIM7_Init 2 */
+
+}
+
+/**
+ * @brief TIM12 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM12_Init(void)
+{
+
+ /* USER CODE BEGIN TIM12_Init 0 */
+
+ /* USER CODE END TIM12_Init 0 */
+
+ TIM_IC_InitTypeDef sConfigIC = {0};
+
+ /* USER CODE BEGIN TIM12_Init 1 */
+
+ /* USER CODE END TIM12_Init 1 */
+ htim12.Instance = TIM12;
+ htim12.Init.Prescaler = 0;
+ htim12.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim12.Init.Period = 0;
+ htim12.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ htim12.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_IC_Init(&htim12) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+ sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
+ sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
+ sConfigIC.ICFilter = 0;
+ if (HAL_TIM_IC_ConfigChannel(&htim12, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM12_Init 2 */
+
+ /* USER CODE END TIM12_Init 2 */
+
+}
+
+/**
+ * @brief TIM15 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_TIM15_Init(void)
+{
+
+ /* USER CODE BEGIN TIM15_Init 0 */
+
+ /* USER CODE END TIM15_Init 0 */
+
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ TIM_IC_InitTypeDef sConfigIC = {0};
+
+ /* USER CODE BEGIN TIM15_Init 1 */
+
+ /* USER CODE END TIM15_Init 1 */
+ htim15.Instance = TIM15;
+ htim15.Init.Prescaler = 0;
+ htim15.Init.CounterMode = TIM_COUNTERMODE_UP;
+ htim15.Init.Period = 0;
+ htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ htim15.Init.RepetitionCounter = 0;
+ htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if (HAL_TIM_IC_Init(&htim15) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+ sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
+ sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
+ sConfigIC.ICFilter = 0;
+ if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN TIM15_Init 2 */
+
+ /* USER CODE END TIM15_Init 2 */
+
+}
+
+/**
+ * @brief USART6 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USART6_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART6_Init 0 */
+ huart6.Instance = USART6;
+ CLEAR_BIT(USART6->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ HAL_UART_DeInit(&huart6); /* UART state may be unpredictable */
+ /* USER CODE END USART6_Init 0 */
+
+ /* USER CODE BEGIN USART6_Init 1 */
+
+ /* USER CODE END USART6_Init 1 */
+ huart6.Instance = USART6;
+ huart6.Init.BaudRate = 115200;
+ huart6.Init.WordLength = UART_WORDLENGTH_8B;
+ huart6.Init.StopBits = UART_STOPBITS_1;
+ huart6.Init.Parity = UART_PARITY_NONE;
+ huart6.Init.Mode = UART_MODE_RX;
+ huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart6.Init.OverSampling = UART_OVERSAMPLING_16;
+ huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ huart6.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ if (HAL_HalfDuplex_Init(&huart6) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetTxFifoThreshold(&huart6, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetRxFifoThreshold(&huart6, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_EnableFifoMode(&huart6) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USART6_Init 2 */
+
+ /* USER CODE END USART6_Init 2 */
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+void HWPowerDown()
+{
+
+ /*
+ MX_GPIO_Init();
+ MX_ADC1_Init();
+ MX_ADC2_Init();
+ MX_FDCAN1_Init();
+ MX_SPI3_Init();
+ MX_TIM2_Init();
+ MX_TIM4_Init();
+ MX_TIM5_Init();
+ MX_TIM6_Init();
+ MX_TIM7_Init();
+ MX_USART6_UART_Init();
+ */
+ /* Stop UART */
+ HAL_UART_DeInit(&huart6);
+ /* Stop Timers */
+ HAL_TIM_OnePulse_DeInit(&htim7);
+ HAL_TIM_OnePulse_DeInit(&htim6);
+ HAL_TIM_Base_DeInit(&htim5);
+
+ /* Reconfigure all PWM pins */
+
+ GPIO_InitStruct.Pin = SERVO_PWM1_Pin | SERVO_PWM2_Pin | SERVO_PWM3_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(SERVO_PWM2_GPIO_Port, &GPIO_InitStruct);
+
+ /* Stop Servo PWM */
+ HAL_TIM_PWM_DeInit(&htim2);
+
+ /* Stop SPI */
+ HAL_SPI_DeInit(&hspi3);
+ /* Stop FDCAN */
+ HAL_FDCAN_DeInit(&hfdcan1);
+ /* Stop ADC */
+ HAL_ADC_DeInit(&hadc1);
+ /* Stop processor */
+ /* When ready, notify the remote processor that we can be shut down */
+ HAL_IPCC_NotifyCPU(&hipcc, IPCC_CHANNEL_3, IPCC_CHANNEL_DIR_RX);
+ /* And enter stop mode to prevent further activity */
+ HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI);
+
+ while(1) {
+ ;
+ }
+}
+/* USER CODE END 4 */
+
+/* USER CODE BEGIN Header_appmain */
+/* USER CODE END Header_appmain */
+__weak void appmain(void *argument)
+{
+ /* USER CODE BEGIN 5 */
+ /* Infinite loop */
+ for(;;)
+ {
+ osDelay(1000);
+ }
+ /* USER CODE END 5 */
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/mbox_ipcc.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/mbox_ipcc.c
new file mode 100644
index 0000000..857e89d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/mbox_ipcc.c
@@ -0,0 +1,182 @@
+/**
+ ******************************************************************************
+ * @file mbox_ipcc.c
+ * @author MCD Application Team
+ * @brief This file provides code for the configuration
+ * of the mailbox_ipcc_if.c MiddleWare.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Channel direction and usage:
+ *
+ * ======== <-- new msg ---=============--------<------ =======
+ * || || || CHANNEL 1 || || ||
+ * || A7 || ------->-------=============--- buf free--> || M4 ||
+ * || || || ||
+ * ||master|| <-- buf free---=============--------<------ ||slave||
+ * || || || CHANNEL 2 || || ||
+ * ======== ------->-------=============----new msg --> =======
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "openamp/open_amp.h"
+#include "stm32mp1xx_hal.h"
+#include "openamp_conf.h"
+
+/* Within 'USER CODE' section, code will be kept by default at each generation */
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* Private define ------------------------------------------------------------*/
+#define MASTER_CPU_ID 0
+#define REMOTE_CPU_ID 1
+#define IPCC_CPU_A7 MASTER_CPU_ID
+#define IPCC_CPU_M4 REMOTE_CPU_ID
+#define RX_NO_MSG 0
+#define RX_NEW_MSG 1
+#define RX_BUF_FREE 2
+
+/* Private variables ---------------------------------------------------------*/
+extern IPCC_HandleTypeDef hipcc;
+int msg_received_ch1 = RX_NO_MSG;
+int msg_received_ch2 = RX_NO_MSG;
+uint32_t vring0_id = 0; /* used for channel 1 */
+uint32_t vring1_id = 1; /* used for channel 2 */
+
+/* Private function prototypes -----------------------------------------------*/
+void IPCC_channel1_callback(IPCC_HandleTypeDef * hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+void IPCC_channel2_callback(IPCC_HandleTypeDef * hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+
+/**
+ * @brief Initialize MAILBOX with IPCC peripheral
+ * @param None
+ * @retval : Operation result
+ */
+int MAILBOX_Init(void)
+{
+
+ if (HAL_IPCC_ActivateNotification(&hipcc, IPCC_CHANNEL_1, IPCC_CHANNEL_DIR_RX,
+ IPCC_channel1_callback) != HAL_OK) {
+ OPENAMP_log_err("%s: ch_1 RX fail\n", __func__);
+ return -1;
+ }
+
+ if (HAL_IPCC_ActivateNotification(&hipcc, IPCC_CHANNEL_2, IPCC_CHANNEL_DIR_RX,
+ IPCC_channel2_callback) != HAL_OK) {
+ OPENAMP_log_err("%s: ch_2 RX fail\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * @brief Initialize MAILBOX with IPCC peripheral
+ * @param virtio device
+ * @retval : Operation result
+ */
+int MAILBOX_Poll(struct virtio_device *vdev)
+{
+ /* If we got an interrupt, ask for the corresponding virtqueue processing */
+
+ if (msg_received_ch1 == RX_BUF_FREE) {
+ OPENAMP_log_dbg("Running virt0 (ch_1 buf free)\r\n");
+ rproc_virtio_notified(vdev, VRING0_ID);
+ msg_received_ch1 = RX_NO_MSG;
+ return 0;
+ }
+
+ if (msg_received_ch2 == RX_NEW_MSG) {
+ OPENAMP_log_dbg("Running virt1 (ch_2 new msg)\r\n");
+ rproc_virtio_notified(vdev, VRING1_ID);
+ msg_received_ch2 = RX_NO_MSG;
+
+ /* The OpenAMP framework does not notify for free buf: do it here */
+ rproc_virtio_notified(NULL, VRING1_ID);
+ return 0;
+ }
+
+ return -1;
+}
+
+/**
+ * @brief Callback function called by OpenAMP MW to notify message processing
+ * @param VRING id
+ * @retval Operation result
+ */
+int MAILBOX_Notify(void *priv, uint32_t id)
+{
+ uint32_t channel;
+ (void)priv;
+
+ /* Called after virtqueue processing: time to inform the remote */
+ if (id == VRING0_ID) {
+ channel = IPCC_CHANNEL_1;
+ OPENAMP_log_dbg("Send msg on ch_1\r\n");
+ }
+ else if (id == VRING1_ID) {
+ /* Note: the OpenAMP framework never notifies this */
+ channel = IPCC_CHANNEL_2;
+ OPENAMP_log_dbg("Send 'buff free' on ch_2\r\n");
+ }
+ else {
+ OPENAMP_log_err("invalid vring (%d)\r\n", (int)id);
+ return -1;
+ }
+
+ /* Check that the channel is free (otherwise wait until it is) */
+ if (HAL_IPCC_GetChannelStatus(&hipcc, channel, IPCC_CHANNEL_DIR_TX) == IPCC_CHANNEL_STATUS_OCCUPIED) {
+ OPENAMP_log_dbg("Waiting for channel to be freed\r\n");
+ while (HAL_IPCC_GetChannelStatus(&hipcc, channel, IPCC_CHANNEL_DIR_TX) == IPCC_CHANNEL_STATUS_OCCUPIED)
+ ;
+ }
+
+ /* Inform A7 (either new message, or buf free) */
+ HAL_IPCC_NotifyCPU(&hipcc, channel, IPCC_CHANNEL_DIR_TX);
+
+ return 0;
+}
+
+/* Private function ---------------------------------------------------------*/
+/* Callback from IPCC Interrupt Handler: Master Processor informs that there are some free buffers */
+void IPCC_channel1_callback(IPCC_HandleTypeDef * hipcc,
+ uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+ if (msg_received_ch1 != RX_NO_MSG)
+ OPENAMP_log_dbg("IPCC_channel1_callback: previous IRQ not treated (status = %d)\r\n", msg_received_ch1);
+
+ msg_received_ch1 = RX_BUF_FREE;
+
+ /* Inform A7 that we have received the 'buff free' msg */
+ OPENAMP_log_dbg("Ack 'buff free' message on ch1\r\n");
+ HAL_IPCC_NotifyCPU(hipcc, ChannelIndex, IPCC_CHANNEL_DIR_RX);
+}
+
+/* Callback from IPCC Interrupt Handler: new message received from Master Processor */
+void IPCC_channel2_callback(IPCC_HandleTypeDef * hipcc,
+ uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+ if (msg_received_ch2 != RX_NO_MSG)
+ OPENAMP_log_dbg("IPCC_channel2_callback: previous IRQ not treated (status = %d)\r\n", msg_received_ch2);
+
+ msg_received_ch2 = RX_NEW_MSG;
+
+ /* Inform A7 that we have received the new msg */
+ OPENAMP_log_dbg("Ack new message on ch2\r\n");
+ HAL_IPCC_NotifyCPU(hipcc, ChannelIndex, IPCC_CHANNEL_DIR_RX);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp.c
new file mode 100644
index 0000000..7b01aa9
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file openamp.c
+ * @author MCD Application Team
+ * @brief Code for openamp applications
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include "openamp.h"
+#include "rsc_table.h"
+#include "metal/sys.h"
+#include "metal/device.h"
+/* Private define ------------------------------------------------------------*/
+
+#define SHM_DEVICE_NAME "STM32_SHM"
+
+/* Globals */
+
+static struct metal_io_region *shm_io;
+static struct metal_io_region *rsc_io;
+static struct shared_resource_table *rsc_table;
+static struct rpmsg_virtio_shm_pool shpool;
+struct rpmsg_virtio_device rvdev;
+
+static metal_phys_addr_t shm_physmap;
+
+struct metal_device shm_device = {
+ .name = SHM_DEVICE_NAME,
+ .num_regions = 2,
+ .regions = {
+ {.virt = NULL}, /* shared memory */
+ {.virt = NULL}, /* rsc_table memory */
+ },
+ .node = { NULL },
+ .irq_num = 0,
+ .irq_info = NULL
+};
+
+static int OPENAMP_shmem_init(int RPMsgRole)
+{
+ int status = 0;
+ struct metal_device *device;
+ struct metal_init_params metal_params = METAL_INIT_DEFAULTS;
+ void* rsc_tab_addr;
+ int rsc_size;
+
+ metal_init(&metal_params);
+
+ status = metal_register_generic_device(&shm_device);
+ if (status != 0) {
+ return status;
+ }
+
+ status = metal_device_open("generic", SHM_DEVICE_NAME, &device);
+ if (status != 0) {
+ return status;
+ }
+
+ shm_physmap = SHM_START_ADDRESS;
+ metal_io_init(&device->regions[0], (void *)SHM_START_ADDRESS, &shm_physmap,
+ SHM_SIZE, -1, 0, NULL);
+
+ shm_io = metal_device_io_region(device, 0);
+ if (shm_io == NULL) {
+ return -1;
+ }
+
+ /* Initialize resources table variables */
+ resource_table_init(RPMsgRole, &rsc_tab_addr, &rsc_size);
+ rsc_table = (struct shared_resource_table *)rsc_tab_addr;
+ if (!rsc_table)
+ {
+ return -1;
+ }
+
+ metal_io_init(&device->regions[1], rsc_table,
+ (metal_phys_addr_t *)rsc_table, rsc_size, -1U, 0, NULL);
+
+ rsc_io = metal_device_io_region(device, 1);
+ if (rsc_io == NULL) {
+ return -1;
+ }
+
+ return 0;
+}
+
+int MX_OPENAMP_Init(int RPMsgRole, rpmsg_ns_bind_cb ns_bind_cb)
+{
+ struct fw_rsc_vdev_vring *vring_rsc;
+ struct virtio_device *vdev;
+ int status = 0;
+
+ MAILBOX_Init();
+
+ /* Libmetal Initilalization */
+ status = OPENAMP_shmem_init(RPMsgRole);
+ if(status)
+ {
+ return status;
+ }
+
+ vdev = rproc_virtio_create_vdev(RPMsgRole, VDEV_ID, &rsc_table->vdev,
+ rsc_io, NULL, MAILBOX_Notify, NULL);
+ if (vdev == NULL)
+ {
+ return -1;
+ }
+
+ rproc_virtio_wait_remote_ready(vdev);
+ vring_rsc = &rsc_table->vring0;
+ status = rproc_virtio_init_vring(vdev, 0, vring_rsc->notifyid,
+ (void *)vring_rsc->da, shm_io,
+ vring_rsc->num, vring_rsc->align);
+ if (status != 0)
+ {
+ return status;
+ }
+ vring_rsc = &rsc_table->vring1;
+ status = rproc_virtio_init_vring(vdev, 1, vring_rsc->notifyid,
+ (void *)vring_rsc->da, shm_io,
+ vring_rsc->num, vring_rsc->align);
+ if (status != 0)
+ {
+ return status;
+ }
+
+ rpmsg_virtio_init_shm_pool(&shpool, (void *)VRING_BUFF_ADDRESS,
+ (size_t)SHM_SIZE);
+ rpmsg_init_vdev(&rvdev, vdev, ns_bind_cb, shm_io, &shpool);
+
+ return 0;
+}
+
+void OPENAMP_DeInit()
+{
+ rpmsg_deinit_vdev(&rvdev);
+
+ metal_finish();
+}
+
+void OPENAMP_init_ept(struct rpmsg_endpoint *ept)
+{
+ rpmsg_init_ept(ept, "", RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, NULL, NULL);
+}
+
+int OPENAMP_create_endpoint(struct rpmsg_endpoint *ept, const char *name,
+ uint32_t dest, rpmsg_ept_cb cb,
+ rpmsg_ns_unbind_cb unbind_cb)
+{
+ return rpmsg_create_ept(ept, &rvdev.rdev, name, RPMSG_ADDR_ANY, dest, cb,
+ unbind_cb);
+}
+
+void OPENAMP_check_for_message(void)
+{
+ MAILBOX_Poll(rvdev.vdev);
+}
+
+void OPENAMP_Wait_EndPointready(struct rpmsg_endpoint *rp_ept)
+{
+ while(!is_rpmsg_ept_ready(rp_ept))
+ MAILBOX_Poll(rvdev.vdev);
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp_log.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp_log.c
new file mode 100644
index 0000000..d794296
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/openamp_log.c
@@ -0,0 +1,102 @@
+/**
+ ******************************************************************************
+ * @file log.c
+ * @author MCD Application Team
+ * @brief Ressource table
+ *
+ * This file provides services for logging
+ *
+ ******************************************************************************
+ *
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *
+ ******************************************************************************
+ */
+/** @addtogroup LOG
+ * @{
+ */
+
+/** @addtogroup STM32MP1xx_log
+ * @{
+ */
+
+/** @addtogroup STM32MP1xx_Log_Private_Includes
+ * @{
+ */
+#include "openamp_log.h"
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_Log_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_Log_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#if defined (__LOG_TRACE_IO_)
+char system_log_buf[SYSTEM_TRACE_BUF_SZ];
+
+__weak void log_buff(int ch)
+{
+ /* Place your implementation of fputc here */
+ /* e.g. write a character to the USART1 and Loop until the end of transmission */
+ static int offset = 0;
+
+ if (offset + 1 >= SYSTEM_TRACE_BUF_SZ)
+ offset = 0;
+
+ system_log_buf[offset] = ch;
+ system_log_buf[offset++ + 1] = '\0';
+}
+
+#endif
+
+#if defined ( __CC_ARM) || (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define PUTCHAR_PROTOTYPE int stdout_putchar(int ch)
+#elif __GNUC__
+/* With GCC/RAISONANCE, small log_info (option LD Linker->Libraries->Small log_info
+ set to 'Yes') calls __io_putchar() */
+#define PUTCHAR_PROTOTYPE int __attribute__(( weak )) __io_putchar(int ch)
+#else
+#define PUTCHAR_PROTOTYPE int __attribute__(( weak )) fputc(int ch, FILE *f)
+#endif /* __GNUC__ */
+
+#if defined (__LOG_UART_IO_) || defined (__LOG_TRACE_IO_)
+PUTCHAR_PROTOTYPE
+{
+ /* Place your implementation of fputc here */
+ /* e.g. write a character to the USART1 and Loop until the end of transmission */
+#if defined (__LOG_UART_IO_)
+extern UART_HandleTypeDef huart;
+ HAL_UART_Transmit(&huart, (uint8_t *)&ch, 1, HAL_MAX_DELAY);
+#endif
+#if defined (__LOG_TRACE_IO_)
+ log_buff(ch);
+#endif
+ return ch;
+}
+#else
+/* No printf output */
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/rsc_table.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/rsc_table.c
new file mode 100644
index 0000000..fab2f99
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/rsc_table.c
@@ -0,0 +1,174 @@
+/**
+ ******************************************************************************
+ * @file rsc_table.c
+ * @author MCD Application Team
+ * @brief Ressource table
+ *
+ * This file provides a default resource table requested by remote proc to
+ * load the elf file. It also allows to add debug trace using a shared buffer.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup RSC_TABLE
+ * @{
+ */
+
+/** @addtogroup resource_table
+ * @{
+ */
+
+/** @addtogroup resource_table_Private_Includes
+ * @{
+ */
+
+#if defined(__ICCARM__) || defined (__CC_ARM) || defined(__GNUC__)
+#include <stddef.h> /* needed for offsetof definition*/
+#endif
+#include "rsc_table.h"
+#include "openamp/open_amp.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup resource_table_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup resource_table_Private_Defines
+ * @{
+ */
+
+/* Place resource table in special ELF section */
+#if defined(__GNUC__)
+#define __section_t(S) __attribute__((__section__(#S)))
+#define __resource __section_t(.resource_table)
+#endif
+
+#if defined (LINUX_RPROC_MASTER)
+ #ifdef VIRTIO_MASTER_ONLY
+ #define CONST
+ #else
+ #define CONST const
+ #endif
+#else
+ #define CONST
+#endif
+
+#define RPMSG_IPU_C0_FEATURES 1
+#define VRING_COUNT 2
+
+/* VirtIO rpmsg device id */
+#define VIRTIO_ID_RPMSG_ 7
+
+#if defined (__LOG_TRACE_IO_)
+extern char system_log_buf[];
+#endif
+
+#if defined(__GNUC__)
+#if !defined (__CC_ARM) && !defined (LINUX_RPROC_MASTER)
+
+/* Since GCC is not initializing the resource_table at startup, it is declared as volatile to avoid compiler optimization
+ * for the CM4 (see resource_table_init() below)
+ */
+volatile struct shared_resource_table __resource __attribute__((used)) resource_table;
+#else
+CONST struct shared_resource_table __resource __attribute__((used)) resource_table = {
+#endif
+#elif defined(__ICCARM__)
+__root CONST struct shared_resource_table resource_table @ ".resource_table" = {
+#endif
+
+#if defined(__ICCARM__) || defined (__CC_ARM) || defined (LINUX_RPROC_MASTER)
+ .version = 1,
+#if defined (__LOG_TRACE_IO_)
+ .num = 2,
+#else
+ .num = 1,
+#endif
+ .reserved = {0, 0},
+ .offset = {
+ offsetof(struct shared_resource_table, vdev),
+ offsetof(struct shared_resource_table, cm_trace),
+ },
+
+ /* Virtio device entry */
+ .vdev= {
+ RSC_VDEV, VIRTIO_ID_RPMSG_, 0, RPMSG_IPU_C0_FEATURES, 0, 0, 0,
+ VRING_COUNT, {0, 0},
+ },
+
+ /* Vring rsc entry - part of vdev rsc entry */
+ .vring0 = {VRING_TX_ADDRESS, VRING_ALIGNMENT, VRING_NUM_BUFFS, VRING0_ID, 0},
+ .vring1 = {VRING_RX_ADDRESS, VRING_ALIGNMENT, VRING_NUM_BUFFS, VRING1_ID, 0},
+
+#if defined (__LOG_TRACE_IO_)
+ .cm_trace = {
+ RSC_TRACE,
+ (uint32_t)system_log_buf, SYSTEM_TRACE_BUF_SZ, 0, "cm4_log",
+ },
+#endif
+} ;
+#endif
+
+void resource_table_init(int RPMsgRole, void **table_ptr, int *length)
+{
+
+#if !defined (LINUX_RPROC_MASTER)
+#if defined (__GNUC__) && ! defined (__CC_ARM)
+#ifdef VIRTIO_MASTER_ONLY
+
+ /*
+ * Currently the GCC linker doesn't initialize the resource_table global variable at startup
+ * it is done here by the master application.
+ */
+ memset(&resource_table, '\0', sizeof(struct shared_resource_table));
+ resource_table.num = 1;
+ resource_table.version = 1;
+ resource_table.offset[0] = offsetof(struct shared_resource_table, vdev);
+
+ resource_table.vring0.da = VRING_TX_ADDRESS;
+ resource_table.vring0.align = VRING_ALIGNMENT;
+ resource_table.vring0.num = VRING_NUM_BUFFS;
+ resource_table.vring0.notifyid = VRING0_ID;
+
+ resource_table.vring1.da = VRING_RX_ADDRESS;
+ resource_table.vring1.align = VRING_ALIGNMENT;
+ resource_table.vring1.num = VRING_NUM_BUFFS;
+ resource_table.vring1.notifyid = VRING1_ID;
+
+ resource_table.vdev.type = RSC_VDEV;
+ resource_table.vdev.id = VIRTIO_ID_RPMSG_;
+ resource_table.vdev.num_of_vrings=VRING_COUNT;
+ resource_table.vdev.dfeatures = RPMSG_IPU_C0_FEATURES;
+#else
+
+ /* For the slave application let's wait until the resource_table is correctly initialized */
+ while(resource_table.vring1.da != VRING_RX_ADDRESS)
+ {
+
+ }
+#endif
+#endif
+#endif
+
+ (void)RPMsgRole;
+ *length = sizeof(resource_table);
+ *table_ptr = (void *)&resource_table;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_hal_msp.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_hal_msp.c
new file mode 100644
index 0000000..4975eea
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_hal_msp.c
@@ -0,0 +1,857 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name : stm32mp1xx_hal_msp.c
+ * Description : This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+ /**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_HSEM_CLK_ENABLE();
+
+ /* System interrupt init*/
+ /* PendSV_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hadc->Instance==ADC1)
+ {
+ /* USER CODE BEGIN ADC1_MspInit 0 */
+
+ /* USER CODE END ADC1_MspInit 0 */
+ if(IS_ENGINEERING_BOOT_MODE())
+ {
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PER;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_ADC12_CLK_ENABLE();
+
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ /**ADC1 GPIO Configuration
+ PC4 ------> ADC1_INP4
+ */
+ GPIO_InitStruct.Pin = AIO_IN_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ HAL_GPIO_Init(AIO_IN_GPIO_Port, &GPIO_InitStruct);
+
+ /* ADC1 interrupt Init */
+ HAL_NVIC_SetPriority(ADC1_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(ADC1_IRQn);
+ /* USER CODE BEGIN ADC1_MspInit 1 */
+ LL_ADC_REG_StopConversion(ADC1);
+
+ /* USER CODE END ADC1_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ if(hadc->Instance==ADC1)
+ {
+ /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+ /* USER CODE END ADC1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_ADC12_CLK_DISABLE();
+
+ /**ADC1 GPIO Configuration
+ PC4 ------> ADC1_INP4
+ */
+ HAL_GPIO_DeInit(AIO_IN_GPIO_Port, AIO_IN_Pin);
+
+ /* ADC1 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(ADC1_IRQn);
+ /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+ /* USER CODE END ADC1_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief FDCAN MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hfdcan->Instance==FDCAN1)
+ {
+ /* USER CODE BEGIN FDCAN1_MspInit 0 */
+
+ /* USER CODE END FDCAN1_MspInit 0 */
+ if(IS_ENGINEERING_BOOT_MODE())
+ {
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+ PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_FDCAN_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**FDCAN1 GPIO Configuration
+ PA11 ------> FDCAN1_RX
+ PA12 ------> FDCAN1_TX
+ */
+ GPIO_InitStruct.Pin = CAN_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+ HAL_GPIO_Init(CAN_GPIO_Port, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = CANA12_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+ HAL_GPIO_Init(CANA12_GPIO_Port, &GPIO_InitStruct);
+
+ /* FDCAN1 interrupt Init */
+ HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
+ /* USER CODE BEGIN FDCAN1_MspInit 1 */
+
+ /* USER CODE END FDCAN1_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief FDCAN MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hfdcan: FDCAN handle pointer
+* @retval None
+*/
+void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
+{
+ if(hfdcan->Instance==FDCAN1)
+ {
+ /* USER CODE BEGIN FDCAN1_MspDeInit 0 */
+
+ /* USER CODE END FDCAN1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_FDCAN_CLK_DISABLE();
+
+ /**FDCAN1 GPIO Configuration
+ PA11 ------> FDCAN1_RX
+ PA12 ------> FDCAN1_TX
+ */
+ HAL_GPIO_DeInit(GPIOA, CAN_Pin|CANA12_Pin);
+
+ /* FDCAN1 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
+ /* USER CODE BEGIN FDCAN1_MspDeInit 1 */
+
+ /* USER CODE END FDCAN1_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief IPCC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hipcc: IPCC handle pointer
+* @retval None
+*/
+void HAL_IPCC_MspInit(IPCC_HandleTypeDef* hipcc)
+{
+ if(hipcc->Instance==IPCC)
+ {
+ /* USER CODE BEGIN IPCC_MspInit 0 */
+
+ /* USER CODE END IPCC_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_IPCC_CLK_ENABLE();
+ /* IPCC interrupt Init */
+ HAL_NVIC_SetPriority(IPCC_RX1_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(IPCC_RX1_IRQn);
+ HAL_NVIC_SetPriority(IPCC_TX1_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(IPCC_TX1_IRQn);
+ /* USER CODE BEGIN IPCC_MspInit 1 */
+
+ /* USER CODE END IPCC_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief IPCC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hipcc: IPCC handle pointer
+* @retval None
+*/
+void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef* hipcc)
+{
+ if(hipcc->Instance==IPCC)
+ {
+ /* USER CODE BEGIN IPCC_MspDeInit 0 */
+
+ /* USER CODE END IPCC_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_IPCC_CLK_DISABLE();
+
+ /* IPCC interrupt DeInit */
+ HAL_NVIC_DisableIRQ(IPCC_RX1_IRQn);
+ HAL_NVIC_DisableIRQ(IPCC_TX1_IRQn);
+ /* USER CODE BEGIN IPCC_MspDeInit 1 */
+
+ /* USER CODE END IPCC_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(hspi->Instance==SPI3)
+ {
+ /* USER CODE BEGIN SPI3_MspInit 0 */
+ SPI3->IER = 0; /* Sometimes may be incorrect */
+ /* USER CODE END SPI3_MspInit 0 */
+ if(IS_ENGINEERING_BOOT_MODE())
+ {
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI23;
+ PeriphClkInit.Spi23ClockSelection = RCC_SPI23CLKSOURCE_PLL4;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_SPI3_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ /**SPI3 GPIO Configuration
+ PA15 ------> SPI3_NSS
+ PE0 ------> SPI3_SCK
+ PD10 ------> SPI3_MISO
+ PD6 ------> SPI3_MOSI
+ */
+ GPIO_InitStruct.Pin = MOTOR_NSS_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
+ GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+ HAL_GPIO_Init(MOTOR_NSS_GPIO_Port, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = MOTOR_SCK_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
+ GPIO_InitStruct.Alternate = GPIO_AF5_SPI3;
+ HAL_GPIO_Init(MOTOR_SCK_GPIO_Port, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = MOTOR_MISO_Pin|MOTOR_MOSI_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
+ GPIO_InitStruct.Alternate = GPIO_AF5_SPI3;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /* SPI3 interrupt Init */
+ HAL_NVIC_SetPriority(SPI3_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(SPI3_IRQn);
+ /* USER CODE BEGIN SPI3_MspInit 1 */
+
+ /* USER CODE END SPI3_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+ if(hspi->Instance==SPI3)
+ {
+ /* USER CODE BEGIN SPI3_MspDeInit 0 */
+ if (0) /* workaround */
+ /* USER CODE END SPI3_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_SPI3_CLK_DISABLE();
+
+ /**SPI3 GPIO Configuration
+ PA15 ------> SPI3_NSS
+ PE0 ------> SPI3_SCK
+ PD10 ------> SPI3_MISO
+ PD6 ------> SPI3_MOSI
+ */
+ HAL_GPIO_DeInit(MOTOR_NSS_GPIO_Port, MOTOR_NSS_Pin);
+
+ HAL_GPIO_DeInit(MOTOR_SCK_GPIO_Port, MOTOR_SCK_Pin);
+
+ HAL_GPIO_DeInit(GPIOD, MOTOR_MISO_Pin|MOTOR_MOSI_Pin);
+
+ /* SPI3 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(SPI3_IRQn);
+ /* USER CODE BEGIN SPI3_MspDeInit 1 */
+
+ /* USER CODE END SPI3_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief TIM_PWM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
+{
+ if(htim_pwm->Instance==TIM2)
+ {
+ /* USER CODE BEGIN TIM2_MspInit 0 */
+
+ /* USER CODE END TIM2_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM2_CLK_ENABLE();
+ /* USER CODE BEGIN TIM2_MspInit 1 */
+
+ /* USER CODE END TIM2_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief TIM_IC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_ic: TIM_IC handle pointer
+* @retval None
+*/
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* htim_ic)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(htim_ic->Instance==TIM3)
+ {
+ /* USER CODE BEGIN TIM3_MspInit 0 */
+
+ /* USER CODE END TIM3_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM3_CLK_ENABLE();
+
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ /**TIM3 GPIO Configuration
+ PB1 ------> TIM3_CH4
+ */
+ GPIO_InitStruct.Pin = COUNTER_2_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
+ HAL_GPIO_Init(COUNTER_2_GPIO_Port, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN TIM3_MspInit 1 */
+
+ /* USER CODE END TIM3_MspInit 1 */
+ }
+ else if(htim_ic->Instance==TIM4)
+ {
+ /* USER CODE BEGIN TIM4_MspInit 0 */
+
+ /* USER CODE END TIM4_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM4_CLK_ENABLE();
+
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ /**TIM4 GPIO Configuration
+ PB8 ------> TIM4_CH3
+ */
+ GPIO_InitStruct.Pin = COUNTER_3_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
+ HAL_GPIO_Init(COUNTER_3_GPIO_Port, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN TIM4_MspInit 1 */
+
+ /* USER CODE END TIM4_MspInit 1 */
+ }
+ else if(htim_ic->Instance==TIM12)
+ {
+ /* USER CODE BEGIN TIM12_MspInit 0 */
+
+ /* USER CODE END TIM12_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM12_CLK_ENABLE();
+
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ /**TIM12 GPIO Configuration
+ PB14 ------> TIM12_CH1
+ */
+ GPIO_InitStruct.Pin = COUNTER_4_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF2_TIM12;
+ HAL_GPIO_Init(COUNTER_4_GPIO_Port, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN TIM12_MspInit 1 */
+
+ /* USER CODE END TIM12_MspInit 1 */
+ }
+ else if(htim_ic->Instance==TIM15)
+ {
+ /* USER CODE BEGIN TIM15_MspInit 0 */
+
+ /* USER CODE END TIM15_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM15_CLK_ENABLE();
+
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ /**TIM15 GPIO Configuration
+ PE5 ------> TIM15_CH1
+ */
+ GPIO_InitStruct.Pin = COUNTER_1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF4_TIM15;
+ HAL_GPIO_Init(COUNTER_1_GPIO_Port, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN TIM15_MspInit 1 */
+
+ /* USER CODE END TIM15_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+ if(htim_base->Instance==TIM5)
+ {
+ /* USER CODE BEGIN TIM5_MspInit 0 */
+
+ /* USER CODE END TIM5_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM5_CLK_ENABLE();
+ /* USER CODE BEGIN TIM5_MspInit 1 */
+
+ /* USER CODE END TIM5_MspInit 1 */
+ }
+ else if(htim_base->Instance==TIM6)
+ {
+ /* USER CODE BEGIN TIM6_MspInit 0 */
+
+ /* USER CODE END TIM6_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM6_CLK_ENABLE();
+ /* USER CODE BEGIN TIM6_MspInit 1 */
+
+ /* USER CODE END TIM6_MspInit 1 */
+ }
+ else if(htim_base->Instance==TIM7)
+ {
+ /* USER CODE BEGIN TIM7_MspInit 0 */
+
+ /* USER CODE END TIM7_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_TIM7_CLK_ENABLE();
+ /* TIM7 interrupt Init */
+ HAL_NVIC_SetPriority(TIM7_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(TIM7_IRQn);
+ /* USER CODE BEGIN TIM7_MspInit 1 */
+
+ /* USER CODE END TIM7_MspInit 1 */
+ }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(htim->Instance==TIM2)
+ {
+ /* USER CODE BEGIN TIM2_MspPostInit 0 */
+
+ /* USER CODE END TIM2_MspPostInit 0 */
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ /**TIM2 GPIO Configuration
+ PA1 ------> TIM2_CH2
+ PA2 ------> TIM2_CH3
+ PG8 ------> TIM2_CH1
+ */
+ GPIO_InitStruct.Pin = SERVO_PWM2_Pin|SERVO_PWM3_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = SERVO_PWM1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+ HAL_GPIO_Init(SERVO_PWM1_GPIO_Port, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN TIM2_MspPostInit 1 */
+
+ /* USER CODE END TIM2_MspPostInit 1 */
+ }
+
+}
+/**
+* @brief TIM_PWM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
+{
+ if(htim_pwm->Instance==TIM2)
+ {
+ /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+ /* USER CODE END TIM2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM2_CLK_DISABLE();
+ /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+ /* USER CODE END TIM2_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief TIM_IC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_ic: TIM_IC handle pointer
+* @retval None
+*/
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef* htim_ic)
+{
+ if(htim_ic->Instance==TIM3)
+ {
+ /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+ /* USER CODE END TIM3_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM3_CLK_DISABLE();
+
+ /**TIM3 GPIO Configuration
+ PB1 ------> TIM3_CH4
+ */
+ HAL_GPIO_DeInit(COUNTER_2_GPIO_Port, COUNTER_2_Pin);
+
+ /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+ /* USER CODE END TIM3_MspDeInit 1 */
+ }
+ else if(htim_ic->Instance==TIM4)
+ {
+ /* USER CODE BEGIN TIM4_MspDeInit 0 */
+
+ /* USER CODE END TIM4_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM4_CLK_DISABLE();
+
+ /**TIM4 GPIO Configuration
+ PB8 ------> TIM4_CH3
+ */
+ HAL_GPIO_DeInit(COUNTER_3_GPIO_Port, COUNTER_3_Pin);
+
+ /* USER CODE BEGIN TIM4_MspDeInit 1 */
+
+ /* USER CODE END TIM4_MspDeInit 1 */
+ }
+ else if(htim_ic->Instance==TIM12)
+ {
+ /* USER CODE BEGIN TIM12_MspDeInit 0 */
+
+ /* USER CODE END TIM12_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM12_CLK_DISABLE();
+
+ /**TIM12 GPIO Configuration
+ PB14 ------> TIM12_CH1
+ */
+ HAL_GPIO_DeInit(COUNTER_4_GPIO_Port, COUNTER_4_Pin);
+
+ /* USER CODE BEGIN TIM12_MspDeInit 1 */
+
+ /* USER CODE END TIM12_MspDeInit 1 */
+ }
+ else if(htim_ic->Instance==TIM15)
+ {
+ /* USER CODE BEGIN TIM15_MspDeInit 0 */
+
+ /* USER CODE END TIM15_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM15_CLK_DISABLE();
+
+ /**TIM15 GPIO Configuration
+ PE5 ------> TIM15_CH1
+ */
+ HAL_GPIO_DeInit(COUNTER_1_GPIO_Port, COUNTER_1_Pin);
+
+ /* USER CODE BEGIN TIM15_MspDeInit 1 */
+
+ /* USER CODE END TIM15_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+ if(htim_base->Instance==TIM5)
+ {
+ /* USER CODE BEGIN TIM5_MspDeInit 0 */
+
+ /* USER CODE END TIM5_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM5_CLK_DISABLE();
+ /* USER CODE BEGIN TIM5_MspDeInit 1 */
+
+ /* USER CODE END TIM5_MspDeInit 1 */
+ }
+ else if(htim_base->Instance==TIM6)
+ {
+ /* USER CODE BEGIN TIM6_MspDeInit 0 */
+
+ /* USER CODE END TIM6_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM6_CLK_DISABLE();
+ /* USER CODE BEGIN TIM6_MspDeInit 1 */
+
+ /* USER CODE END TIM6_MspDeInit 1 */
+ }
+ else if(htim_base->Instance==TIM7)
+ {
+ /* USER CODE BEGIN TIM7_MspDeInit 0 */
+
+ /* USER CODE END TIM7_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_TIM7_CLK_DISABLE();
+
+ /* TIM7 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(TIM7_IRQn);
+ /* USER CODE BEGIN TIM7_MspDeInit 1 */
+
+ /* USER CODE END TIM7_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ if(huart->Instance==USART6)
+ {
+ /* USER CODE BEGIN USART6_MspInit 0 */
+
+ /* USER CODE END USART6_MspInit 0 */
+ if(IS_ENGINEERING_BOOT_MODE())
+ {
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART6;
+ PeriphClkInit.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_USART6_CLK_ENABLE();
+
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ /**USART6 GPIO Configuration
+ PG14 ------> USART6_TX
+ */
+ GPIO_InitStruct.Pin = IOMUX_DI_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART6;
+ HAL_GPIO_Init(IOMUX_DI_GPIO_Port, &GPIO_InitStruct);
+
+ /* USART6 interrupt Init */
+ HAL_NVIC_SetPriority(USART6_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(USART6_IRQn);
+ /* USER CODE BEGIN USART6_MspInit 1 */
+
+ /* USER CODE END USART6_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+ if(huart->Instance==USART6)
+ {
+ /* USER CODE BEGIN USART6_MspDeInit 0 */
+
+ /* USER CODE END USART6_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART6_CLK_DISABLE();
+
+ /**USART6 GPIO Configuration
+ PG14 ------> USART6_TX
+ */
+ HAL_GPIO_DeInit(IOMUX_DI_GPIO_Port, IOMUX_DI_Pin);
+
+ /* USART6 interrupt DeInit */
+ HAL_NVIC_DisableIRQ(USART6_IRQn);
+ /* USER CODE BEGIN USART6_MspDeInit 1 */
+
+ /* USER CODE END USART6_MspDeInit 1 */
+ }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_it.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_it.c
new file mode 100644
index 0000000..0afe2a3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/stm32mp1xx_it.c
@@ -0,0 +1,228 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under Ultimate Liberty license
+ * SLA0044, the "License"; You may not use this file except in compliance with
+ * the License. You may obtain a copy of the License at:
+ * www.st.com/SLA0044
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32mp1xx_it.h"
+#include "FreeRTOS.h"
+#include "task.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include <semphr.h>
+#include "ftshmem.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern IPCC_HandleTypeDef hipcc;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex-M4 Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+ extern void *pxCurrentTCB;
+ if (pxCurrentTCB == NULL) { /* early start problem */
+ HAL_IncTick();
+ return;
+ }
+
+ extern void FTCountersUpdate();
+ FTCountersUpdate();
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+ if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
+ {
+#endif /* INCLUDE_xTaskGetSchedulerState */
+ xPortSysTickHandler();
+#if (INCLUDE_xTaskGetSchedulerState == 1 )
+ }
+#endif /* INCLUDE_xTaskGetSchedulerState */
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32MP1xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32mp1xx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles IPCC RX1 occupied interrupt.
+ */
+void IPCC_RX1_IRQHandler(void)
+{
+ /* USER CODE BEGIN IPCC_RX1_IRQn 0 */
+ extern SemaphoreHandle_t commandHandle;
+ if (commandHandle)
+ xSemaphoreGiveFromISR(commandHandle, NULL);
+ ftstat->ipccrxcounter++;
+ /* USER CODE END IPCC_RX1_IRQn 0 */
+ HAL_IPCC_RX_IRQHandler(&hipcc);
+ /* USER CODE BEGIN IPCC_RX1_IRQn 1 */
+
+ /* USER CODE END IPCC_RX1_IRQn 1 */
+}
+
+/**
+ * @brief This function handles IPCC TX1 free interrupt.
+ */
+void IPCC_TX1_IRQHandler(void)
+{
+ /* USER CODE BEGIN IPCC_TX1_IRQn 0 */
+ ftstat->ipcctxcounter++;
+ /* USER CODE END IPCC_TX1_IRQn 0 */
+ HAL_IPCC_TX_IRQHandler(&hipcc);
+ /* USER CODE BEGIN IPCC_TX1_IRQn 1 */
+
+ /* USER CODE END IPCC_TX1_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/CM4/Src/syscalls.c b/txt2-M4-rt-core/cubemx/txt/CM4/Src/syscalls.c
new file mode 100644
index 0000000..914f768
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/CM4/Src/syscalls.c
@@ -0,0 +1,207 @@
+/**
+*****************************************************************************
+**
+** File : syscalls.c
+**
+** Author : Auto-generated by System workbench for STM32
+**
+** Abstract : System Workbench Minimal System calls file
+**
+** For more information about which c-functions
+** need which of these lowlevel functions
+** please consult the Newlib libc-manual
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed “as is,†without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit (int status)
+{
+ _kill(status, -1);
+ while (1) {} /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ *ptr++ = __io_getchar();
+ }
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ __io_putchar(*ptr++);
+ }
+ return len;
+}
+
+caddr_t _sbrk(int incr)
+{
+ extern char end asm("end");
+ static char *heap_end;
+ char *prev_heap_end;
+
+ if (heap_end == 0)
+ heap_end = &end;
+
+ prev_heap_end = heap_end;
+ if (heap_end + incr > stack_ptr)
+ {
+// write(1, "Heap and stack collision\n", 25);
+// abort();
+ errno = ENOMEM;
+ return (caddr_t) -1;
+ }
+
+ heap_end += incr;
+
+ return (caddr_t) prev_heap_end;
+}
+
+int _close(int file)
+{
+ return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _isatty(int file)
+{
+ return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+ return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+ /* Pretend like we always fail */
+ return -1;
+}
+
+int _wait(int *status)
+{
+ errno = ECHILD;
+ return -1;
+}
+
+int _unlink(char *name)
+{
+ errno = ENOENT;
+ return -1;
+}
+
+int _times(struct tms *buf)
+{
+ return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _link(char *old, char *new)
+{
+ errno = EMLINK;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+ errno = ENOMEM;
+ return -1;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Common/System/system_stm32mp1xx.c b/txt2-M4-rt-core/cubemx/txt/Common/System/system_stm32mp1xx.c
new file mode 100644
index 0000000..275de67
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Common/System/system_stm32mp1xx.c
@@ -0,0 +1,290 @@
+/**
+ ******************************************************************************
+ * @file system_stm32mp1xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32mp1xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock frequency, it can
+ * be used by the user application to setup
+ * the SysTick timer or configure other
+ * parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ *
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32mp1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32MP1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32mp1xx_hal.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Private_Defines
+ * @{
+ */
+
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on EVAL board as data memory */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) each time HAL_RCC_ClockConfig() is called to configure the system clock
+ frequency
+ Note: If you use this function to configure the system clock;
+ then there is no need to call the first functions listed above,
+ since SystemCoreClock variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = HSI_VALUE;
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (DATA_IN_ExtSRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Private_Functions
+ * @{
+ */
+
+ /**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if defined (CORE_CM4)
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#if defined (VECT_TAB_SRAM)
+ SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif
+ /* Disable all interrupts and events */
+ CLEAR_REG(EXTI_C2->IMR1);
+ CLEAR_REG(EXTI_C2->IMR2);
+ CLEAR_REG(EXTI_C2->IMR3);
+ CLEAR_REG(EXTI_C2->EMR1);
+ CLEAR_REG(EXTI_C2->EMR2);
+ CLEAR_REG(EXTI_C2->EMR3);
+#else
+#error Please #define CORE_CM4
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock frequency (Hz),
+ * it can be used by the user application to setup the SysTick timer or
+ * configure other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called to
+ * update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the
+ * HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the
+ * HSE_VALUE(**)
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the
+ * CSI_VALUE(***)
+ *
+ * - If SYSCLK source is PLL3_P, SystemCoreClock will contain the
+ * HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***)
+ * multiplied/divided by the PLL3 factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+ * (default value 64 MHz) but the real value may vary depending
+ * on the variations in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+ * (default value 24 MHz), user has to ensure that HSE_VALUE is
+ * same as the real frequency of the crystal used. Otherwise, this
+ * function may have wrong result.
+ *
+ * (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
+ * (default value 4 MHz)but the real value may vary depending
+ * on the variations in voltage and temperature.
+ *
+ * - The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllsource, pll3m, pll3fracen;
+ float fracn1, pll3vco;
+
+ switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV));
+ break;
+
+ case 0x01: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case 0x02: /* CSI used as system clock source */
+ SystemCoreClock = CSI_VALUE;
+ break;
+
+ case 0x03: /* PLL3_P used as system clock source */
+ pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
+ pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
+ pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U;
+ fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U));
+ pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF));
+
+ if (pll3m != 0U)
+ {
+ switch (pllsource)
+ {
+ case 0x00: /* HSI used as PLL clock source */
+ pll3vco *= (float)((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m);
+ break;
+
+ case 0x01: /* HSE used as PLL clock source */
+ pll3vco *= (float)(HSE_VALUE / pll3m);
+ break;
+
+ case 0x02: /* CSI used as PLL clock source */
+ pll3vco *= (float)(CSI_VALUE / pll3m);
+ break;
+
+ case 0x03: /* No clock source for PLL */
+ pll3vco = 0;
+ break;
+ }
+ SystemCoreClock = (uint32_t)(pll3vco/ ((float)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U)));
+ }
+ else
+ {
+ SystemCoreClock = 0U;
+ }
+ break;
+ }
+
+ /* Compute mcu_ck */
+ SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV);
+}
+
+
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32mp15xx.s before jump to main.
+ * This function configures the external SRAM mounted on Eval boards
+ * This SRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h
new file mode 100644
index 0000000..837c13d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h
@@ -0,0 +1,32050 @@
+/**
+ ******************************************************************************
+ * @file stm32mp157cxx_cm4.h
+ * @author MCD Application Team
+ * @brief CMSIS stm32mp157cxx_cm4 Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripherals registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32mp157cxx_cm4
+ * @{
+ */
+
+#ifndef __STM32MP157Cxx_CM4_H
+#define __STM32MP157Cxx_CM4_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Bit position definition inside a 32 bits registers
+ */
+#define B(x) \
+ ((uint32_t) 1 << x)
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32MP1XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+ typedef enum IRQn
+ {
+ /****** Cortex-M Processor Exceptions Numbers *******************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
+ /****** STM32 specific Interrupt Numbers ************************************************************************/
+ WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */
+ TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */
+ RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */
+ RESERVED_4 = 4, /*!< RESERVED interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupts */
+ FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
+ FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
+ FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
+ FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
+ EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */
+ RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */
+ EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */
+ ETH1_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */
+ EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */
+ EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */
+ EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */
+ EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */
+ USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */
+ EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */
+ EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH1_IRQn = 80, /*!< Hash global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ ADC2_IRQn = 90, /*!< ADC2 global Interrupts */
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
+ CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
+ I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
+ I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
+ SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
+ OTG_IRQn = 98, /*!< USB On The Go global interrupt */
+ RESERVED_99 = 99, /*!< RESERVED interrupt */
+ IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */
+ IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */
+ DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */
+ IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */
+ IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */
+ CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */
+ HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */
+ I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */
+ I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */
+ GPU_IRQn = 109, /*!< GPU global Interrupt */
+ DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */
+ DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */
+ DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */
+ DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */
+ SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
+ DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */
+ TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
+ TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
+ TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
+ TIM12_IRQn = 119, /*!< TIM12 global Interrupt */
+ MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
+ EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */
+ MDMA_IRQn = 122, /*!< MDMA global Interrupt */
+ DSI_IRQn = 123, /*!< DSI global Interrupt */
+ SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
+ HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */
+ DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */
+ EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */
+ nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */
+ nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */
+ TIM13_IRQn = 130, /*!< TIM13 global interrupt */
+ TIM14_IRQn = 131, /*!< TIM14 global interrupt */
+ DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */
+ RNG1_IRQn = 133, /*!< RNG1 interrupt */
+ RNG2_IRQn = 134, /*!< RNG2 interrupt */
+ I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */
+ I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */
+ SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */
+ LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
+ LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
+ LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
+ LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
+ ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */
+ RESERVED_143 = 143, /*!< RESERVED interrupt */
+ MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */
+ RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */
+ SAI4_IRQn = 146, /*!< SAI4 global interrupt */
+ DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */
+ RESERVED_148 = 148, /*!< RESERVED interrupt */
+ WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
+ MAX_IRQ_n
+ } IRQn_Type;
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+#define SDC /*!< Step Down Converter feature */
+
+/**
+ * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
+#include "system_stm32mp1xx.h"
+
+
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
+ __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
+ __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
+ uint32_t RESERVED1; /*!< Reserved, 0x028 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
+ __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
+ __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
+ __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
+ __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
+ uint32_t RESERVED10; /*!< Reserved, 0x0CC */
+ __IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */
+ uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
+ __IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */
+} ADC_TypeDef;
+
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
+ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
+
+} ADC_Common_TypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
+ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
+ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
+ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
+ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
+ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
+ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
+ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
+ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
+ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
+ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
+ __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
+ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
+ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
+ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
+ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
+ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
+ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
+ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
+ __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
+ __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
+ __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
+ __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
+ __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
+ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
+ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
+ __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
+ __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
+ __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
+ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
+ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
+ __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
+ __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
+ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
+ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
+ __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
+ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
+ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
+ __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
+ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
+ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
+ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
+ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
+ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
+ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
+ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+ __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
+ __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
+ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
+ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
+ __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+ * @brief TTFD Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
+ __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
+ __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
+ __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
+ __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
+ __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
+ __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
+ __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
+ __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
+ __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
+ __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
+ __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
+ __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
+ __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
+ __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
+ __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
+ __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
+ __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
+ __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+ * @brief FD Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
+ __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
+ __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
+ __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
+ __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
+ __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */
+ uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
+ __IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */
+}CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */
+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */
+ uint32_t RESERVED2; /*!< Reserved, 0x00C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */
+ uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
+ __IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */
+} CRC_TypeDef;
+
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
+ uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */
+ __IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */
+} DAC_TypeDef;
+
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+ __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
+} DFSDM_Channel_TypeDef;
+
+
+/**
+ * @brief DFSDM registers
+ */
+typedef struct
+{
+ uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */
+ __IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */
+ __IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */
+ __IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */
+ __IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */
+} DFSDM_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */
+ __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */
+ __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */
+ __IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */
+ __IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */
+ __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */
+ __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */
+ __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */
+ __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */
+ __IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */
+ __IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DCMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */
+ uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */
+ __IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */
+} DCMI_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DMA stream x configuration register */
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+ __IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */
+ __IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */
+ __IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< DMA Channel Status Register */
+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */
+ __IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */
+ uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */
+ __IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */
+ __IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */
+ __IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */
+
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+ * @brief MDMA Controller
+ */
+typedef struct
+{
+ __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */
+ uint32_t RESERVED1; /*!< Reserved, 0x004 */
+// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */
+ __IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */
+// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */
+ uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */
+ __IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */
+ __IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */
+}MDMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
+ __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
+ __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
+ __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
+ __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
+ __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
+ __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
+ __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
+ __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
+ __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
+ __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
+ __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
+}MDMA_Channel_TypeDef;
+
+/**
+ * @brief DSI Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */
+ __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED6; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED10; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */
+ uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+ uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */
+ __IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */
+ __IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */
+ __IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */
+ __IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */
+} DSI_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+typedef struct
+{
+ __IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */
+ __IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */
+ __IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */
+ __IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */
+ __IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */
+ __IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */
+ uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */
+ __IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */
+ __IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */
+ __IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */
+ __IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */
+ uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */
+ __IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */
+ uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */
+ __IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */
+ uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */
+ __IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */
+ uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */
+ __IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */
+ __IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */
+ __IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */
+ uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */
+ __IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */
+ __IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */
+ __IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */
+ uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */
+ __IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */
+ __IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */
+ uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */
+ __IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */
+ __IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */
+ __IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */
+ __IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */
+ uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */
+ __IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */
+ uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */
+ __IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */
+ __IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */
+ uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */
+ __IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */
+ __IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */
+ uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */
+ __IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */
+ __IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */
+ uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */
+ __IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */
+ __IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */
+ __IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */
+ __IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */
+ __IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */
+ __IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */
+ __IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */
+ __IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */
+ uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */
+ __IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */
+ __IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */
+ __IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */
+ __IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */
+ __IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */
+ uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */
+ __IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */
+ __IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */
+ uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */
+ __IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */
+ uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */
+ __IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */
+ __IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */
+ uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */
+ __IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */
+ uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */
+ __IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */
+ __IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */
+ __IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */
+ __IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */
+ uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */
+ __IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */
+ __IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */
+ uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */
+ __IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */
+ __IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */
+ __IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */
+ __IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */
+ uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */
+ __IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */
+ __IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */
+ uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */
+ __IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */
+ __IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */
+ __IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */
+ __IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */
+ uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */
+ __IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */
+ uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */
+ __IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */
+ __IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */
+ __IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */
+ __IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */
+ __IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */
+ __IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */
+ __IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */
+ uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */
+ __IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */
+ uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */
+ __IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */
+ __IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */
+ uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */
+ __IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */
+ uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */
+ __IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */
+ __IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */
+ __IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */
+ __IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */
+ __IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */
+ __IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */
+ uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */
+ __IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */
+ uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */
+ __IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */
+ __IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */
+ __IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */
+ __IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */
+ uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */
+ __IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */
+ __IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */
+ __IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */
+ __IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */
+ __IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */
+ uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */
+ __IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */
+ uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */
+ __IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */
+ uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */
+ __IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */
+ __IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */
+ __IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */
+ uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */
+ __IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */
+ uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */
+ __IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */
+ __IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */
+ __IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */
+ __IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */
+ __IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */
+ __IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */
+ __IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */
+ __IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */
+ uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */
+ __IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */
+ __IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */
+ __IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */
+ __IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */
+ __IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */
+ __IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */
+ uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */
+ __IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */
+ __IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */
+ __IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */
+ __IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */
+ __IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */
+ uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */
+ __IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */
+ __IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */
+ __IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */
+ __IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */
+ uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */
+ __IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */
+ __IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */
+ __IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */
+ uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */
+ __IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */
+ __IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */
+ __IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */
+ uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */
+ __IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */
+ uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */
+ __IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */
+ __IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */
+ uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */
+ __IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */
+ __IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */
+ __IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */
+ __IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */
+ __IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */
+ __IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */
+ uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */
+ __IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */
+ uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */
+ __IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */
+ uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */
+ __IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */
+ uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */
+ __IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */
+ __IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */
+ uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */
+ __IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */
+ uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */
+ __IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */
+ __IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */
+ uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */
+ __IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */
+ uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */
+ __IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */
+ uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */
+ __IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */
+ uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */
+ __IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */
+ uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */
+ __IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */
+ uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */
+ __IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */
+ uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */
+ __IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */
+ uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */
+ __IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */
+ uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */
+ __IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
+ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
+ __IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */
+ __IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */
+ __IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */
+ uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
+ __IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */
+ __IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */
+ __IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */
+ uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */
+ __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
+ __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
+ __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
+ __IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */
+ __IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */
+ __IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */
+ uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */
+ __IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
+ uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
+ __IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
+ __IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
+ __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
+ __IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
+ __IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
+ __IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
+ __IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
+ __IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
+ __IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
+ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
+ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
+ __IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
+ __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
+ __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */
+ __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */
+ __IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */
+ __IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */
+ uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */
+ __IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */
+ __IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */
+ __IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */
+ __IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */
+ __IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */
+ __IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */
+ __IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */
+ __IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */
+ __IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */
+ __IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */
+ __IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */
+ __IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */
+ __IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */
+
+}EXTI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
+ uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
+ uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */
+ __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
+ uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */
+}EXTI_Core_TypeDef;
+
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+ __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ __IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */
+ __IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */
+ uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */
+ __IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */
+ __IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */
+ __IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */
+ uint32_t RESERVED1; /*!< Reserved, 0x25C */
+ __IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */
+ __IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */
+ __IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */
+ __IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */
+ __IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */
+ __IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */
+ __IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */
+ __IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */
+ __IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */
+ uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */
+ __IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */
+ __IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */
+ __IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */
+} FMC_Bank3_TypeDef;
+
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */
+ __IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */
+ __IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */
+ uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */
+ __IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */
+ __IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */
+ __IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */
+ __IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */
+ __IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */
+ __IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */
+ __IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */
+ __IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */
+ __IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */
+ __IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */
+ __IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */
+} GPIO_TypeDef;
+
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */
+ __IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */
+ __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */
+ __IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */
+ __IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */
+ __IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */
+ __IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */
+ __IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */
+ __IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */
+ __IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */
+ __IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */
+ __IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */
+ uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */
+ __IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */
+} SYSCFG_TypeDef;
+
+
+/**
+ * @briefVoltage reference buffer
+ */
+typedef struct
+{
+ __IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */
+ __IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */
+} VREF_TypeDef;
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+ uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
+ __IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+ __IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */
+ uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */
+ __IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */
+ __IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief JPEG Codec
+ */
+typedef struct
+{
+ __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
+ __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
+ __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
+ __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
+ __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
+ __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
+ __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
+ __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
+ uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
+ __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
+ __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
+ __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
+ uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
+ __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
+ __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
+ uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
+ __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
+ __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
+ __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
+ __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
+ __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
+ __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
+ __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
+ __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
+ uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
+ __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
+ __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
+ __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
+ __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+
+/**
+ * @brief LCD
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+ * @brief LCD-TFT Display Controller
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+ * @brief LCD-TFT Display layer x Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
+ uint32_t RESERVED1[3]; /*!< Reserved */
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+
+/**
+ * @brief DDRPHYC DDR Physical Interface Control
+ */
+typedef struct
+{
+ __IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */
+ __IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */
+ __IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */
+ __IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */
+ __IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */
+ __IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */
+ __IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */
+ __IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */
+ __IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */
+ __IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */
+ __IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */
+ __IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */
+ __IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */
+ __IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */
+ __IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */
+ __IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */
+ __IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */
+ __IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */
+ __IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */
+ __IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */
+ __IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */
+ __IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */
+ __IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */
+ __IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */
+ uint32_t RESERVED0[24]; /*!< Reserved */
+ __IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */
+ __IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */
+ __IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */
+ __IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */
+ __IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */
+ __IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */
+ __IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */
+ __IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */
+ uint32_t RESERVED1[8]; /*!< Reserved */
+ __IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */
+ __IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */
+ __IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */
+ __IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */
+ __IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */
+ __IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */
+ __IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */
+ __IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */
+ __IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */
+ __IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */
+ __IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */
+ __IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */
+ __IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */
+ __IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */
+ __IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */
+ __IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */
+ __IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */
+ uint32_t RESERVED2[13]; /*!< Reserved */
+ __IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */
+ __IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */
+ __IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */
+ __IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */
+ __IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */
+ __IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */
+ uint32_t RESERVED3[12]; /*!< Reserved */
+ __IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */
+ __IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */
+ __IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */
+ __IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */
+ __IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */
+ __IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */
+ uint32_t RESERVED4[10]; /*!< Reserved */
+ __IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */
+ __IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */
+ __IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */
+ __IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */
+ __IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */
+ __IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */
+ uint32_t RESERVED5[10]; /*!< Reserved */
+ __IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */
+ __IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */
+ __IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */
+ __IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */
+ __IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */
+ __IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */
+ uint32_t RESERVED6[10]; /*!< Reserved */
+ __IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */
+ __IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */
+ __IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */
+ __IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */
+ __IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */
+ __IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */
+}DDRPHYC_TypeDef;
+
+
+/**
+ * @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL)
+ */
+typedef struct
+{
+ __IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */
+ /* @TODO : TypeDef to be compleated */
+}DDRC_TypeDef;
+
+
+/**
+ * @brief USBPHYC USB HS PHY Control
+ */
+typedef struct
+{
+ __IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */
+ uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */
+ __IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */
+ uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/
+ __IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */
+}USBPHYC_GlobalTypeDef;
+
+
+/**
+ * @brief USBPHYC USB HS PHY Control PHYx
+ */
+typedef struct
+{
+ uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */
+ __IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */
+}USBPHYC_InstanceTypeDef;
+
+
+/**
+ * @brief TZC TrustZone Address Space Controller for DDR
+ */
+typedef struct
+{
+ __IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */
+ __IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */
+ __IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */
+ __IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */
+ uint8_t RESERVED0[0x100 - 0x10];
+ __IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */
+ __IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */
+ __IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */
+ __IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */
+ __IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */
+ __IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */
+ /* @TODO : TypeDef to be compleated if needed*/
+}TZC_TypeDef;
+
+
+
+/**
+ * @brief TZPC TrustZone Protection Controller
+ */
+typedef struct
+{
+ __IO uint32_t TZMA0_SIZE; /*!<TZPC ROM Secure Size Definition register, Address offset: 0x00 */
+ __IO uint32_t TZMA1_SIZE; /*!<TZPC SYSRAM Secure Size Definition register, Address offset: 0x04 */
+ uint32_t RESERVED0[2]; /*!< Reserved */
+ __IO uint32_t DECPROT0; /*!<TZPC Securable peripheral definition register 0, Address offset: 0x10 */
+ __IO uint32_t DECPROT1; /*!<TZPC Securable peripheral definition register 1, Address offset: 0x14 */
+ __IO uint32_t DECPROT2; /*!<TZPC Securable peripheral definition register 2, Address offset: 0x18 */
+ __IO uint32_t DECPROT3; /*!<TZPC Securable peripheral definition register 3, Address offset: 0x1C */
+ __IO uint32_t DECPROT4; /*!<TZPC Securable peripheral definition register 4, Address offset: 0x20 */
+ __IO uint32_t DECPROT5; /*!<TZPC Securable peripheral definition register 5, Address offset: 0x24 */
+ uint32_t RESERVED1[2]; /*!< Reserved */
+ __IO uint32_t DECPROT_LOCK0; /*!<TZPC Securable lock of security register 0, Address offset: 0x30 */
+ __IO uint32_t DECPROT_LOCK1; /*!<TZPC Securable lock of security register 1, Address offset: 0x34 */
+ __IO uint32_t DECPROT_LOCK2; /*!<TZPC Securable lock of security register 2, Address offset: 0x38 */
+ uint32_t RESERVED2[237]; /*!< Reserved */
+ __IO uint32_t HWCFGR; /*!< TZPC IP HW configuration register Address offset:0x3F0 */
+ __IO uint32_t IP_VER; /*!< TZPC IP version register Address offset:0x3F4 */
+ __IO uint32_t ID; /*!< TZPC IP version register Address offset:0x3F8 */
+ __IO uint32_t SID; /*!< TZPC IP version register Address offset:0x3FC */
+}TZPC_TypeDef;
+
+
+
+/**
+ * @brief STGENC System Generic Counter Control
+ */
+typedef struct
+{
+ __IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */
+ /* @TODO : TypeDef to be compleated if needed*/
+}STGENC_TypeDef;
+
+/**
+ * @brief Firewall
+ */
+
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR control register 1, Address offset: 0x00 */
+ __IO uint32_t CSR1; /*!< PWR control status register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< PWR control register 2, Address offset: 0x08 */
+ __IO uint32_t CR3; /*!< PWR control register 3, Address offset: 0x0C */
+ __IO uint32_t MPUCR; /*!< PWR MPU control register, Address offset: 0x10 */
+ __IO uint32_t MCUCR; /*!< PWR MCU control register, Address offset: 0x14 */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x18-0x1C Address offset: 0x18 */
+ __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
+ __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
+ __IO uint32_t MPUWKUPENR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
+ __IO uint32_t MCUWKUPENR; /*!< PWR wakeup enable and polarity register, Address offset: 0x2C */
+ uint32_t RESERVED1[241]; /*!< Reserved, 0x30-0x3F0 Address offset: 0x30 */
+ __IO uint32_t VER; /*!< PWR IP version register, Address offset: 0x3F4 */
+ __IO uint32_t ID; /*!< PWR IP identification register, Address offset: 0x3F8 */
+ __IO uint32_t SID; /*!< PWR size ID register, Address offset: 0x3FC */
+} PWR_TypeDef;
+
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t TZCR; /*!< RCC TrustZone Control Register Address offset: 0x00 */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x04-0x08 Address offset: 0x04 */
+ __IO uint32_t OCENSETR; /*!< RCC Oscillator Clock Enable Set Register Address offset: 0x0C */
+ __IO uint32_t OCENCLRR; /*!< RCC Oscillator Enable Control Clear Register Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t HSICFGR; /*!< RCC HSI Configuration Register Address offset: 0x18 */
+ __IO uint32_t CSICFGR; /*!< RCC CSI Configuration Register Address offset: 0x1C */
+ __IO uint32_t MPCKSELR; /*!< RCC MPU Clock Selection Register Address offset: 0x20 */
+ __IO uint32_t ASSCKSELR; /*!< RCC AXI Sub-System Clock Selection Register Address offset: 0x24 */
+ __IO uint32_t RCK12SELR; /*!< RCC PLL 1 and 2 Ref. Clock Selection Register Address offset: 0x28 */
+ __IO uint32_t MPCKDIVR; /*!< RCC MPU Clock Divider Register Address offset: 0x2C */
+ __IO uint32_t AXIDIVR; /*!< RCC AXI Clock Divider Register Address offset: 0x30 */
+ uint32_t RESERVED2[2]; /*!< Reserved, 0x34-0x38 Address offset: 0x34 */
+ __IO uint32_t APB4DIVR; /*!< RCC APB4 Clock Divider Register Address offset: 0x3C */
+ __IO uint32_t APB5DIVR; /*!< RCC APB5 Clock Divider Register Address offset: 0x40 */
+ __IO uint32_t RTCDIVR; /*!< RCC RTC Clock Division Register Address offset: 0x44 */
+ __IO uint32_t MSSCKSELR; /*!< RCC MCU Sub-System Clock Selection Register Address offset: 0x48 */
+ uint32_t RESERVED3[13]; /*!< Reserved, 0x4C-0x7C Address offset: 0x4C */
+ __IO uint32_t PLL1CR; /*!< RCC PLL1 Control Register Address offset: 0x80 */
+ __IO uint32_t PLL1CFGR1; /*!< RCC PLL1 Configuration Register 1 Address offset: 0x84 */
+ __IO uint32_t PLL1CFGR2; /*!< RCC PLL1 Configuration Register 2 Address offset: 0x88 */
+ __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Register Address offset: 0x8C */
+ __IO uint32_t PLL1CSGR; /*!< RCC PLL1 Clock Spreading Generator Register Address offset: 0x90 */
+ __IO uint32_t PLL2CR; /*!< RCC PLL2 Control Register Address offset: 0x94 */
+ __IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 Address offset: 0x98 */
+ __IO uint32_t PLL2CFGR2; /*!< RCC PLL2 Configuration Register 2 Address offset: 0x9C */
+ __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Register Address offset: 0xA0 */
+ __IO uint32_t PLL2CSGR; /*!< RCC PLL2 Clock Spreading Generator Register Address offset: 0xA4 */
+ uint32_t RESERVED4[6]; /*!< Reserved, 0xA8-0xBC Address offset: 0xA8 */
+ __IO uint32_t I2C46CKSELR; /*!< RCC I2C46 Kernel Clock Selection Register Address offset: 0xC0 */
+ __IO uint32_t SPI6CKSELR; /*!< RCC SPI6 Kernel Clock Selection Register Address offset: 0xC4 */
+ __IO uint32_t UART1CKSELR; /*!< RCC USART1 Kernel Clock Selection Register Address offset: 0xC8 */
+ __IO uint32_t RNG1CKSELR; /*!< RCC RNG1 Kernel Clock Selection Register Address offset: 0xCC */
+ __IO uint32_t CPERCKSELR; /*!< RCC Common Peripheral Clock Selection Register Address offset: 0xD0 */
+ __IO uint32_t STGENCKSELR; /*!< RCC STGEN Clock Selection Register Address offset: 0xD4 */
+ __IO uint32_t DDRITFCR; /*!< RCC control DDR interface, DDRC and DDRPHYC Register Address offset: 0xD8 */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0xDC */
+ uint32_t RESERVED6[8]; /*!< Reserved, 0xE0-0xFC Address offset: 0xE0 */
+ __IO uint32_t MP_BOOTCR; /*!< RCC Hold Boot Control Register Address offset: 0x100 */
+ __IO uint32_t MP_SREQSETR; /*!< RCC Stop Request Set Register Address offset: 0x104 */
+ __IO uint32_t MP_SREQCLRR; /*!< RCC Stop Request Clear Register Address offset: 0x108 */
+ __IO uint32_t MP_GCR; /*!< RCC Global Control Register Address offset: 0x10C */
+ __IO uint32_t MP_APRSTCR; /*!< RCC Application Reset Control Register Address offset: 0x110 */
+ __IO uint32_t MP_APRSTSR; /*!< RCC Application Reset Status Register Address offset: 0x114 */
+ uint32_t RESERVED7[10]; /*!< Reserved, 0x118-0x13C Address offset: 0x118 */
+ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register Address offset: 0x140 */
+ __IO uint32_t RDLSICR; /*!< RCC Reset Duration and LSI Control Register Address offset: 0x144 */
+ uint32_t RESERVED8[14]; /*!< Reserved, 0x148-0x17C Address offset: 0x148 */
+ __IO uint32_t APB4RSTSETR; /*!< RCC APB4 Peripheral Reset Set Register Address offset: 0x180 */
+ __IO uint32_t APB4RSTCLRR; /*!< RCC APB4 Peripheral Reset Clear Register Address offset: 0x184 */
+ __IO uint32_t APB5RSTSETR; /*!< RCC APB5 Peripheral Reset Set Register Address offset: 0x188 */
+ __IO uint32_t APB5RSTCLRR; /*!< RCC APB5 Peripheral Reset Clear Register Address offset: 0x18C */
+ __IO uint32_t AHB5RSTSETR; /*!< RCC AHB5 Peripheral Reset Set Register Address offset: 0x190 */
+ __IO uint32_t AHB5RSTCLRR; /*!< RCC AHB5 Peripheral Reset Clear Register Address offset: 0x194 */
+ __IO uint32_t AHB6RSTSETR; /*!< RCC AHB6 Peripheral Reset Set Register Address offset: 0x198 */
+ __IO uint32_t AHB6RSTCLRR; /*!< RCC AHB6 Peripheral Reset Clear Register Address offset: 0x19C */
+ __IO uint32_t TZAHB6RSTSETR; /*!< RCC AHB6 Peripheral Reset Set Register Address offset: 0x1A0 */
+ __IO uint32_t TZAHB6RSTCLRR; /*!< RCC AHB6 Peripheral Reset Clear Register Address offset: 0x1A4 */
+ uint32_t RESERVED9[22]; /*!< Reserved, 0x1A8-0x1FC Address offset: 0x1A8 */
+ __IO uint32_t MP_APB4ENSETR; /*!< RCC APB4 Periph. Enable For MPU Set Register Address offset: 0x200 */
+ __IO uint32_t MP_APB4ENCLRR; /*!< RCC APB4 Periph. Enable For MPU Clear Register Address offset: 0x204 */
+ __IO uint32_t MP_APB5ENSETR; /*!< RCC APB5 Periph. Enable For MPU Set Register Address offset: 0x208 */
+ __IO uint32_t MP_APB5ENCLRR; /*!< RCC APB5 Periph. Enable For MPU Clear Register Address offset: 0x20C */
+ __IO uint32_t MP_AHB5ENSETR; /*!< RCC AHB5 Periph. Enable For MPU Set Register Address offset: 0x210 */
+ __IO uint32_t MP_AHB5ENCLRR; /*!< RCC AHB5 Periph. Enable For MPU Clear Register Address offset: 0x214 */
+ __IO uint32_t MP_AHB6ENSETR; /*!< RCC AHB6 Periph. Enable For MPU Set Register Address offset: 0x218 */
+ __IO uint32_t MP_AHB6ENCLRR; /*!< RCC AHB6 Periph. Enable For MPU Clear Register Address offset: 0x21C */
+ uint32_t RESERVED10[24]; /*!< Reserved, 0x220-0x27C Address offset: 0x220 */
+ __IO uint32_t MC_APB4ENSETR; /*!< RCC APB4 Periph. Enable For MCU Set Register Address offset: 0x280 */
+ __IO uint32_t MC_APB4ENCLRR; /*!< RCC APB4 Periph. Enable For MCU Clear Register Address offset: 0x284 */
+ __IO uint32_t MC_APB5ENSETR; /*!< RCC APB5 Periph. Enable For MCU Set Register Address offset: 0x288 */
+ __IO uint32_t MC_APB5ENCLRR; /*!< RCC APB5 Periph. Enable For MCU Clear Register Address offset: 0x28C */
+ __IO uint32_t MC_AHB5ENSETR; /*!< RCC AHB5 Periph. Enable For MCU Set Register Address offset: 0x290 */
+ __IO uint32_t MC_AHB5ENCLRR; /*!< RCC AHB5 Periph. Enable For MCU Clear Register Address offset: 0x294 */
+ __IO uint32_t MC_AHB6ENSETR; /*!< RCC AHB6 Periph. Enable For MCU Set Register Address offset: 0x298 */
+ __IO uint32_t MC_AHB6ENCLRR; /*!< RCC AHB6 Periph. Enable For MCU Clear Register Address offset: 0x29C */
+ uint32_t RESERVED11[24]; /*!< Reserved, 0x2A0-0x2FC Address offset: 0x2A0 */
+ __IO uint32_t MP_APB4LPENSETR; /*!< RCC APB4 Sleep Clock Ena. For MPU Set Register Address offset: 0x300 */
+ __IO uint32_t MP_APB4LPENCLRR; /*!< RCC APB4 Sleep Clock Ena. For MPU Clear Register Address offset: 0x304 */
+ __IO uint32_t MP_APB5LPENSETR; /*!< RCC APB5 Sleep Clock Ena. For MPU Set Register Address offset: 0x308 */
+ __IO uint32_t MP_APB5LPENCLRR; /*!< RCC APB5 Sleep Clock Ena. For MPU Clear Register Address offset: 0x30C */
+ __IO uint32_t MP_AHB5LPENSETR; /*!< RCC AHB5 Sleep Clock Ena. For MPU Set Register Address offset: 0x310 */
+ __IO uint32_t MP_AHB5LPENCLRR; /*!< RCC AHB5 Sleep Clock Ena. For MPU Clear Register Address offset: 0x314 */
+ __IO uint32_t MP_AHB6LPENSETR; /*!< RCC AHB6 Sleep Clock Ena. For MPU Set Register Address offset: 0x318 */
+ __IO uint32_t MP_AHB6LPENCLRR; /*!< RCC AHB6 Sleep Clock Ena. For MPU Clear Register Address offset: 0x31C */
+ uint32_t RESERVED12[24]; /*!< Reserved, 0x320-0x30C Address offset: 0x320 */
+ __IO uint32_t MC_APB4LPENSETR; /*!< RCC APB4 Sleep Clock Ena. For MCU Set Register Address offset: 0x380 */
+ __IO uint32_t MC_APB4LPENCLRR; /*!< RCC APB4 Sleep Clock Ena. For MCU Clear Register Address offset: 0x384 */
+ __IO uint32_t MC_APB5LPENSETR; /*!< RCC APB5 Sleep Clock Ena. For MCU Set Register Address offset: 0x388 */
+ __IO uint32_t MC_APB5LPENCLRR; /*!< RCC APB5 Sleep Clock Ena. For MCU Clear Register Address offset: 0x38C */
+ __IO uint32_t MC_AHB5LPENSETR; /*!< RCC AHB5 Sleep Clock Ena. For MCU Set Register Address offset: 0x390 */
+ __IO uint32_t MC_AHB5LPENCLRR; /*!< RCC AHB5 Sleep Clock Ena. For MCU Clear Register Address offset: 0x394 */
+ __IO uint32_t MC_AHB6LPENSETR; /*!< RCC AHB6 Sleep Clock Ena. For MCU Set Register Address offset: 0x398 */
+ __IO uint32_t MC_AHB6LPENCLRR; /*!< RCC AHB6 Sleep Clock Ena. For MCU Clear Register Address offset: 0x39C */
+ uint32_t RESERVED13[24]; /*!< Reserved, 0x3A0-0x3FC Address offset: 0x3A0 */
+ __IO uint32_t BR_RSTSCLRR; /*!< RCC BootRom Reset Status Clear Register Address offset: 0x400 */
+ __IO uint32_t MP_GRSTCSETR; /*!< RCC Global Reset Control Set Register Address offset: 0x404 */
+ __IO uint32_t MP_RSTSCLRR; /*!< RCC MPU Reset Status Clear Register Address offset: 0x408 */
+ __IO uint32_t MP_IWDGFZSETR; /*!< RCC IWDG Clock Freeze Set Register Address offset: 0x40C */
+ __IO uint32_t MP_IWDGFZCLRR; /*!< RCC IWDG Clock Freeze Clear Register Address offset: 0x410 */
+ __IO uint32_t MP_CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x414 */
+ __IO uint32_t MP_CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x418 */
+ __IO uint32_t PWRLPDLYCR; /*!< RCC PWR_LP Delay Control Register Address offset: 0x41C */
+ __IO uint32_t MP_RSTSSETR; /*!< RCC MPU Reset Status Set Register Address offset: 0x420 */
+ uint32_t RESERVED14[247]; /*!< Reserved, 0x424-0x7FC Address offset: 0x424 */
+ __IO uint32_t MCO1CFGR; /*!< RCC MCO1 Configuration Register Address offset: 0x800 */
+ __IO uint32_t MCO2CFGR; /*!< RCC MCO2 Configuration Register Address offset: 0x804 */
+ __IO uint32_t OCRDYR; /*!< RCC Oscillator Clock Ready Register Address offset: 0x808 */
+ __IO uint32_t DBGCFGR; /*!< Debug Configuration Register Address offset: 0x80C */
+ uint32_t RESERVED15[4]; /*!< Reserved, 0x810-0x81C Address offset: 0x810 */
+ __IO uint32_t RCK3SELR; /*!< RCC PLL 3 Ref. Clock Selection Register Address offset: 0x820 */
+ __IO uint32_t RCK4SELR; /*!< RCC PLL4 Ref. Clock Selection Register Address offset: 0x824 */
+ __IO uint32_t TIMG1PRER; /*!< RCC TIM Group 1 Prescaler Register Address offset: 0x828 */
+ __IO uint32_t TIMG2PRER; /*!< RCC TIM Group 2 Prescaler Register Address offset: 0x82C */
+ __IO uint32_t MCUDIVR; /*!< RCC MCU Clock Prescaler Register Address offset: 0x830 */
+ __IO uint32_t APB1DIVR; /*!< RCC APB1 Clock Prescaler Register Address offset: 0x834 */
+ __IO uint32_t APB2DIVR; /*!< RCC APB2 Clock Prescaler Register Address offset: 0x838 */
+ __IO uint32_t APB3DIVR; /*!< RCC APB3 Clock Prescaler Register Address offset: 0x83C */
+ uint32_t RESERVED16[16]; /*!< Reserved, 0x840-0x87C Address offset: 0x840 */
+ __IO uint32_t PLL3CR; /*!< RCC PLL3 Control Register Address offset: 0x880 */
+ __IO uint32_t PLL3CFGR1; /*!< RCC PLL3 Configuration Register 1 Address offset: 0x884 */
+ __IO uint32_t PLL3CFGR2; /*!< RCC PLL3 Configuration Register 2 Address offset: 0x888 */
+ __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Register Address offset: 0x88C */
+ __IO uint32_t PLL3CSGR; /*!< RCC PLL3 Clock Spreading Generator Register Address offset: 0x890 */
+ __IO uint32_t PLL4CR; /*!< RCC PLL4 Control Register Address offset: 0x894 */
+ __IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 Address offset: 0x898 */
+ __IO uint32_t PLL4CFGR2; /*!< RCC PLL4 Configuration Register 2 Address offset: 0x89C */
+ __IO uint32_t PLL4FRACR; /*!< RCC PLL4 Fractional Register Address offset: 0x8A0 */
+ __IO uint32_t PLL4CSGR; /*!< RCC PLL4 Clock Spreading Generator Register Address offset: 0x8A4 */
+ uint32_t RESERVED17[6]; /*!< Reserved, 0x8A8-0x8BC Address offset: 0x8A8 */
+ __IO uint32_t I2C12CKSELR; /*!< RCC I2C1,2 Kernel Clock Selection Register Address offset: 0x8C0 */
+ __IO uint32_t I2C35CKSELR; /*!< RCC I2C3,5 Kernel Clock Selection Register Address offset: 0x8C4 */
+ __IO uint32_t SAI1CKSELR; /*!< RCC SAI1 Kernel Clock Selection Register Address offset: 0x8C8 */
+ __IO uint32_t SAI2CKSELR; /*!< RCC SAI2 Kernel Clock Selection Register Address offset: 0x8CC */
+ __IO uint32_t SAI3CKSELR; /*!< RCC SAI3 Kernel Clock Selection Register Address offset: 0x8D0 */
+ __IO uint32_t SAI4CKSELR; /*!< RCC SAI4 Kernel Clock Selection Register Address offset: 0x8D4 */
+ __IO uint32_t SPI2S1CKSELR; /*!< RCC SPI/I2S1 Kernel Clock Selection Register Address offset: 0x8D8 */
+ __IO uint32_t SPI2S23CKSELR; /*!< RCC SPI/I2S2,3 Kernel Clock Selection Register Address offset: 0x8DC */
+ __IO uint32_t SPI45CKSELR; /*!< RCC SPI4,5 Kernel Clock Selection Register Address offset: 0x8E0 */
+ __IO uint32_t UART6CKSELR; /*!< RCC USART6 Kernel Clock Selection Register Address offset: 0x8E4 */
+ __IO uint32_t UART24CKSELR; /*!< RCC UART2,4 Kernel Clock Selection Register Address offset: 0x8E8 */
+ __IO uint32_t UART35CKSELR; /*!< RCC UART3,5 Kernel Clock Selection Register Address offset: 0x8EC */
+ __IO uint32_t UART78CKSELR; /*!< RCC UART7,8 Kernel Clock Selection Register Address offset: 0x8F0 */
+ __IO uint32_t SDMMC12CKSELR; /*!< RCC SDMMC1&2 Kernel Clock Selection Register Address offset: 0x8F4 */
+ __IO uint32_t SDMMC3CKSELR; /*!< RCC SDMMC3 Kernel Clock Selection Register Address offset: 0x8F8 */
+ __IO uint32_t ETHCKSELR; /*!< RCC Ethernet Kernel Clock Selection Register Address offset: 0x8FC */
+ __IO uint32_t QSPICKSELR; /*!< RCC QUADSPI Kernel Clock Selection Register Address offset: 0x900 */
+ __IO uint32_t FMCCKSELR; /*!< RCC FMC Kernel Clock Selection Register Address offset: 0x904 */
+ uint32_t RESERVED18; /*!< Reserved, Address offset: 0x908 */
+ __IO uint32_t FDCANCKSELR; /*!< RCC FDCAN Kernel Clock Selection Register Address offset: 0x90C */
+ uint32_t RESERVED19; /*!< Reserved, Address offset: 0x910 */
+ __IO uint32_t SPDIFCKSELR; /*!< RCC SPDIF Kernel Clock Selection Register Address offset: 0x914 */
+ __IO uint32_t CECCKSELR; /*!< RCC CEC Kernel Clock Selection Register Address offset: 0x918 */
+ __IO uint32_t USBCKSELR; /*!< RCC USB Kernel Clock Selection Register Address offset: 0x91C */
+ __IO uint32_t RNG2CKSELR; /*!< RCC RNG2 Kernel Clock Selection Register Address offset: 0x920 */
+ __IO uint32_t DSICKSELR; /*!< RCC DSI Kernel Clock Selection Register Address offset: 0x924 */
+ __IO uint32_t ADCCKSELR; /*!< RCC ADC Kernel Clock Selection Register Address offset: 0x928 */
+ __IO uint32_t LPTIM45CKSELR; /*!< RCC LPTIM4&5 Kernel Clock Selection Register Address offset: 0x92C */
+ __IO uint32_t LPTIM23CKSELR; /*!< RCC LPTIM2&3 Kernel Clock Selection Register Address offset: 0x930 */
+ __IO uint32_t LPTIM1CKSELR; /*!< RCC LPTIM1 Kernel Clock Selection Register Address offset: 0x934 */
+ uint32_t RESERVED20[18]; /*!< Reserved, 0x938-0x97C Address offset: 0x938 */
+ __IO uint32_t APB1RSTSETR; /*!< RCC APB1 Peripheral Reset Set Register Address offset: 0x980 */
+ __IO uint32_t APB1RSTCLRR; /*!< RCC APB1 Peripheral Reset Clear Register Address offset: 0x984 */
+ __IO uint32_t APB2RSTSETR; /*!< RCC APB2 Peripheral Reset Set Register Address offset: 0x988 */
+ __IO uint32_t APB2RSTCLRR; /*!< RCC APB2 Peripheral Reset Clear Register Address offset: 0x98C */
+ __IO uint32_t APB3RSTSETR; /*!< RCC APB3 Peripheral Reset Set Register Address offset: 0x990 */
+ __IO uint32_t APB3RSTCLRR; /*!< RCC APB3 Peripheral Reset Clear Register Address offset: 0x994 */
+ __IO uint32_t AHB2RSTSETR; /*!< RCC AHB2 Peripheral Reset Set Register Address offset: 0x998 */
+ __IO uint32_t AHB2RSTCLRR; /*!< RCC AHB2 Peripheral Reset Clear Register Address offset: 0x99C */
+ __IO uint32_t AHB3RSTSETR; /*!< RCC AHB3 Peripheral Reset Set Register Address offset: 0x9A0 */
+ __IO uint32_t AHB3RSTCLRR; /*!< RCC AHB3 Peripheral Reset Clear Register Address offset: 0x9A4 */
+ __IO uint32_t AHB4RSTSETR; /*!< RCC AHB4 Peripheral Reset Set Register Address offset: 0x9A8 */
+ __IO uint32_t AHB4RSTCLRR; /*!< RCC AHB4 Peripheral Reset Clear Register Address offset: 0x9AC */
+ uint32_t RESERVED21[20]; /*!< Reserved, 0x9B0-0x9FC Address offset: 0x9B0 */
+ __IO uint32_t MP_APB1ENSETR; /*!< RCC APB1 Peripheral Enable For MPU Set Register Address offset: 0xA00 */
+ __IO uint32_t MP_APB1ENCLRR; /*!< RCC APB1 Peripheral Enable For MPU Clear Register Address offset: 0xA04 */
+ __IO uint32_t MP_APB2ENSETR; /*!< RCC APB2 Peripheral Enable For MPU Set Register Address offset: 0xA08 */
+ __IO uint32_t MP_APB2ENCLRR; /*!< RCC APB2 Peripheral Enable For MPU Clear Register Address offset: 0xA0C */
+ __IO uint32_t MP_APB3ENSETR; /*!< RCC APB3 Peripheral Enable For MPU Set Register Address offset: 0xA10 */
+ __IO uint32_t MP_APB3ENCLRR; /*!< RCC APB3 Peripheral Enable For MPU Clear Register Address offset: 0xA14 */
+ __IO uint32_t MP_AHB2ENSETR; /*!< RCC AHB2 Peripheral Enable For MPU Set Register Address offset: 0xA18 */
+ __IO uint32_t MP_AHB2ENCLRR; /*!< RCC AHB2 Peripheral Enable For MPU Clear Register Address offset: 0xA1C */
+ __IO uint32_t MP_AHB3ENSETR; /*!< RCC AHB3 Peripheral Enable For MPU Set Register Address offset: 0xA20 */
+ __IO uint32_t MP_AHB3ENCLRR; /*!< RCC AHB3 Peripheral Enable For MPU Clear Register Address offset: 0xA24 */
+ __IO uint32_t MP_AHB4ENSETR; /*!< RCC AHB4 Peripheral Enable For MPU Set Register Address offset: 0xA28 */
+ __IO uint32_t MP_AHB4ENCLRR; /*!< RCC AHB4 Peripheral Enable For MPU Clear Register Address offset: 0xA2C */
+ uint32_t RESERVED22[2]; /*!< Reserved, 0xA30-0xA34 Address offset: 0xA30 */
+ __IO uint32_t MP_MLAHBENSETR; /*!< RCC MLAHB Periph. Enable For MPU Set Register Address offset: 0xA38 */
+ __IO uint32_t MP_MLAHBENCLRR; /*!< RCC MLAHB Periph. Enable For MPU Clear Register Address offset: 0xA3C */
+ uint32_t RESERVED23[16]; /*!< Reserved, 0x940-0xA7C Address offset: 0x940 */
+ __IO uint32_t MC_APB1ENSETR; /*!< RCC APB1 Peripheral Enable For MCU Set Register Address offset: 0xA80 */
+ __IO uint32_t MC_APB1ENCLRR; /*!< RCC APB1 Peripheral Enable For MCU Clear Register Address offset: 0xA84 */
+ __IO uint32_t MC_APB2ENSETR; /*!< RCC APB2 Peripheral Enable For MCU Set Register Address offset: 0xA88 */
+ __IO uint32_t MC_APB2ENCLRR; /*!< RCC APB2 Peripheral Enable For MCU Clear Register Address offset: 0xA8C */
+ __IO uint32_t MC_APB3ENSETR; /*!< RCC APB3 Peripheral Enable For MCU Set Register Address offset: 0xA90 */
+ __IO uint32_t MC_APB3ENCLRR; /*!< RCC APB3 Peripheral Enable For MCU Clear Register Address offset: 0xA94 */
+ __IO uint32_t MC_AHB2ENSETR; /*!< RCC AHB2 Peripheral Enable For MCU Set Register Address offset: 0xA98 */
+ __IO uint32_t MC_AHB2ENCLRR; /*!< RCC AHB2 Peripheral Enable For MCU Clear Register Address offset: 0xA9C */
+ __IO uint32_t MC_AHB3ENSETR; /*!< RCC AHB3 Peripheral Enable For MCU Set Register Address offset: 0xAA0 */
+ __IO uint32_t MC_AHB3ENCLRR; /*!< RCC AHB3 Peripheral Enable For MCU Clear Register Address offset: 0xAA4 */
+ __IO uint32_t MC_AHB4ENSETR; /*!< RCC AHB4 Peripheral Enable For MCU Set Register Address offset: 0xAA8 */
+ __IO uint32_t MC_AHB4ENCLRR; /*!< RCC AHB4 Peripheral Enable For MCU Clear Register Address offset: 0xAAC */
+ __IO uint32_t MC_AXIMENSETR; /*!< RCC AXI Periph. Enable For MCU Set Register Address offset: 0xAB0 */
+ __IO uint32_t MC_AXIMENCLRR; /*!< RCC AXI Periph. Enable For MCU Clear Register Address offset: 0xAB4 */
+ __IO uint32_t MC_MLAHBENSETR; /*!< RCC MLAHB Periph. Enable For MCU Set Register Address offset: 0xAB8 */
+ __IO uint32_t MC_MLAHBENCLRR; /*!< RCC MLAHB Periph. Enable For MCU Clear Register Address offset: 0xABC */
+ uint32_t RESERVED24[16]; /*!< Reserved, 0xAC0-0xAFC Address offset: 0xAC0 */
+ __IO uint32_t MP_APB1LPENSETR; /*!< RCC APB1 Sleep Clock Ena. For MPU Set Register Address offset: 0xB00 */
+ __IO uint32_t MP_APB1LPENCLRR; /*!< RCC APB1 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB04 */
+ __IO uint32_t MP_APB2LPENSETR; /*!< RCC APB2 Sleep Clock Ena. For MPU Set Register Address offset: 0xB08 */
+ __IO uint32_t MP_APB2LPENCLRR; /*!< RCC APB2 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB0C */
+ __IO uint32_t MP_APB3LPENSETR; /*!< RCC APB3 Sleep Clock Ena. For MPU Set Register Address offset: 0xB10 */
+ __IO uint32_t MP_APB3LPENCLRR; /*!< RCC APB3 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB14 */
+ __IO uint32_t MP_AHB2LPENSETR; /*!< RCC AHB2 Sleep Clock Ena. For MPU Set Register Address offset: 0xB18 */
+ __IO uint32_t MP_AHB2LPENCLRR; /*!< RCC AHB2 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB1C */
+ __IO uint32_t MP_AHB3LPENSETR; /*!< RCC AHB3 Sleep Clock Ena. For MPU Set Register Address offset: 0xB20 */
+ __IO uint32_t MP_AHB3LPENCLRR; /*!< RCC AHB3 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB24 */
+ __IO uint32_t MP_AHB4LPENSETR; /*!< RCC AHB4 Sleep Clock Ena. For MPU Set Register Address offset: 0xB28 */
+ __IO uint32_t MP_AHB4LPENCLRR; /*!< RCC AHB4 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB2C */
+ __IO uint32_t MP_AXIMLPENSETR; /*!< RCC AXI Sleep Clock Ena. For MPU Set Register Address offset: 0xB30 */
+ __IO uint32_t MP_AXIMLPENCLRR; /*!< RCC AXI Sleep Clock Ena. For MPU Clear Register Address offset: 0xB34 */
+ __IO uint32_t MP_MLAHBLPENSETR; /*!< RCC MLAHB Sleep Clock Ena. For MPU Set Register Address offset: 0xB38 */
+ __IO uint32_t MP_MLAHBLPENCLRR; /*!< RCC MLAHB Sleep Clock Ena. For MPU Clear Register Address offset: 0xB3C */
+ uint32_t RESERVED25[16]; /*!< Reserved, 0xB40-0xB7C Address offset: 0xB40 */
+ __IO uint32_t MC_APB1LPENSETR; /*!< RCC APB1 Sleep Clock Ena. For MCU Set Register Address offset: 0xB80 */
+ __IO uint32_t MC_APB1LPENCLRR; /*!< RCC APB1 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB84 */
+ __IO uint32_t MC_APB2LPENSETR; /*!< RCC APB2 Sleep Clock Ena. For MCU Set Register Address offset: 0xB88 */
+ __IO uint32_t MC_APB2LPENCLRR; /*!< RCC APB2 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB8C */
+ __IO uint32_t MC_APB3LPENSETR; /*!< RCC APB3 Sleep Clock Ena. For MCU Set Register Address offset: 0xB90 */
+ __IO uint32_t MC_APB3LPENCLRR; /*!< RCC APB3 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB94 */
+ __IO uint32_t MC_AHB2LPENSETR; /*!< RCC AHB2 Sleep Clock Ena. For MCU Set Register Address offset: 0xB98 */
+ __IO uint32_t MC_AHB2LPENCLRR; /*!< RCC AHB2 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB9C */
+ __IO uint32_t MC_AHB3LPENSETR; /*!< RCC AHB3 Sleep Clock Ena. For MCU Set Register Address offset: 0xBA0 */
+ __IO uint32_t MC_AHB3LPENCLRR; /*!< RCC AHB3 Sleep Clock Ena. For MCU Clear Register Address offset: 0xBA4 */
+ __IO uint32_t MC_AHB4LPENSETR; /*!< RCC AHB4 Sleep Clock Ena. For MCU Set Register Address offset: 0xBA8 */
+ __IO uint32_t MC_AHB4LPENCLRR; /*!< RCC AHB4 Sleep Clock Ena. For MCU Clear Register Address offset: 0xBAC */
+ __IO uint32_t MC_AXIMLPENSETR; /*!< RCC AXI Sleep Clock Ena. For MCU Set Register Address offset: 0xBB0 */
+ __IO uint32_t MC_AXIMLPENCLRR; /*!< RCC AXI Sleep Clock Ena. For MCU Clear Register Address offset: 0xBB4 */
+ __IO uint32_t MC_MLAHBLPENSETR; /*!< RCC MLAHB Sleep Clock Ena. For MCU Set Register Address offset: 0xBB8 */
+ __IO uint32_t MC_MLAHBLPENCLRR; /*!< RCC MLAHB Sleep Clock Ena. For MCU Clear Register Address offset: 0xBBC */
+ uint32_t RESERVED26[16]; /*!< Reserved, 0xBC0-0xBFC Address offset: 0xBC0 */
+ __IO uint32_t MC_RSTSCLRR; /*!< RCC MCU Reset Status Clear Register Address offset: 0xC00 */
+ uint32_t RESERVED27[4]; /*!< Reserved, 0xC04-0xC10 Address offset: 0xC04 */
+ __IO uint32_t MC_CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0xC14 */
+ __IO uint32_t MC_CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0xC18 */
+ uint32_t RESERVED28[246]; /*!< Reserved, 0xC1C-0xFF0 Address offset: 0xC1C */
+ __IO uint32_t VERR; /*!< RCC Version register Address offset: 0xFF4 */
+ __IO uint32_t IPIDR; /*!< RCC ID register Address offset: 0xFF8 */
+ __IO uint32_t SIDR; /*!< Size ID register Address offset: 0xFFC */
+} RCC_TypeDef;
+
+/**
+ * @brief Hardware Debug Port
+ */
+
+typedef struct
+{
+ __IO uint32_t HDP_CTRL; /*!< HDP Control Register, Address offset: 0x00 */
+ __IO uint32_t HDP_MUX; /*!< HDP Multiplexers Control Register, Address offset: 0x04 */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x08-0x0C Address offset: 0x08 */
+ __IO uint32_t HDP_VAL; /*!< HDP Read Back Value Register, Address offset: 0x10 */
+ __IO uint32_t HDP_GPOSET; /*!< HDP General Purpose Output Set Register, Address offset: 0x14 */
+ __IO uint32_t HDP_GPOCLR; /*!< HDP General Purpose Output Clear Register, Address offset: 0x18 */
+ __IO uint32_t HDP_GPOVAL; /*!< HDP General Purpose Output Value Register, Address offset: 0x1C */
+ uint32_t RESERVED1[245]; /*!< Reserved, 0x20-0x3F4 Address offset: 0x20 */
+ __IO uint32_t VERR; /*!< HDP Version Register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< HDP IP Identification Register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< HDP Size Identification register, Address offset: 0x3FC */
+} HDP_TypeDef;
+
+
+/**
+ * @brief Boot and Security and OTP Control
+ */
+
+typedef struct
+{
+ __IO uint32_t BSEC_OTP_CONFIG; /*!< BSEC OTP Configuration, Address offset: 0x00 */
+ __IO uint32_t BSEC_OTP_CONTROL; /*!< BSEC OTP Control, Address offset: 0x04 */
+ __IO uint32_t BSEC_OTP_WRDATA; /*!< BSEC OTP Write Data, Address offset: 0x08 */
+ __IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */
+ __IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */
+ __IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */
+ __IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */
+ __IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */
+ __IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */
+ __IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */
+ uint32_t RESERVED0x28; /*!< Reserved, Address offset: 0x28 */
+ uint32_t RESERVED0x2C; /*!< Reserved, Address offset: 0x2C */
+ uint32_t RESERVED0x30; /*!< Reserved, Address offset: 0x30 */
+ __IO uint32_t BSEC_OTP_ERROR0; /*!< BSEC OTP Error Status, Address offset: 0x34 */
+ __IO uint32_t BSEC_OTP_ERROR1; /*!< BSEC OTP Error Status, Address offset: 0x38 */
+ __IO uint32_t BSEC_OTP_ERROR2; /*!< BSEC OTP Error Status, Address offset: 0x3C */
+ uint32_t RESERVED0x40; /*!< Reserved, Address offset: 0x40 */
+ uint32_t RESERVED0x44; /*!< Reserved, Address offset: 0x44 */
+ uint32_t RESERVED0x48; /*!< Reserved, Address offset: 0x48 */
+ __IO uint32_t BSEC_OTP_WRLOCK0; /*!< BSEC OTP Lock status, Address offset: 0x4C */
+ __IO uint32_t BSEC_OTP_WRLOCK1; /*!< BSEC OTP Lock status, Address offset: 0x50 */
+ __IO uint32_t BSEC_OTP_WRLOCK2; /*!< BSEC OTP Lock status, Address offset: 0x54 */
+ uint32_t RESERVED0x58; /*!< Reserved, Address offset: 0x58 */
+ uint32_t RESERVED0x5C; /*!< Reserved, Address offset: 0x5C */
+ uint32_t RESERVED0x60; /*!< Reserved, Address offset: 0x60 */
+ __IO uint32_t BSEC_OTP_SPLOCK0; /*!< BSEC OTP prg lock under ctrl by stick bits, Address offset: 0x64 */
+ __IO uint32_t BSEC_OTP_SPLOCK1; /*!< BSEC OTP prg lock under ctrl by stick bits, Address offset: 0x68 */
+ __IO uint32_t BSEC_OTP_SPLOCK2; /*!< BSEC OTP prg lock under ctrl by stick bits, Address offset: 0x6C */
+ uint32_t RESERVED0x70; /*!< Reserved, Address offset: 0x70 */
+ uint32_t RESERVED0x74; /*!< Reserved, Address offset: 0x74 */
+ uint32_t RESERVED0x78; /*!< Reserved, Address offset: 0x78 */
+ __IO uint32_t BSEC_OTP_SWLOCK0; /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x7C */
+ __IO uint32_t BSEC_OTP_SWLOCK1; /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x80 */
+ __IO uint32_t BSEC_OTP_SWLOCK2; /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x84 */
+ uint32_t RESERVED0x88; /*!< Reserved, Address offset: 0x88 */
+ uint32_t RESERVED0x8C; /*!< Reserved, Address offset: 0x8C */
+ uint32_t RESERVED0x90; /*!< Reserved, Address offset: 0x90 */
+ __IO uint32_t BSEC_OTP_SRLOCK0; /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x94 */
+ __IO uint32_t BSEC_OTP_SRLOCK1; /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x98 */
+ __IO uint32_t BSEC_OTP_SRLOCK2; /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x9C */
+ uint32_t RESERVED0xA0; /*!< Reserved, Address offset: 0xA0 */
+ uint32_t RESERVED0xA4; /*!< Reserved, Address offset: 0xA4 */
+ uint32_t RESERVED0xA8; /*!< Reserved, Address offset: 0xA8 */
+ __IO uint32_t BSEC_JTAGIN; /*!< BSEC JTAG Input, Address offset: 0xAC */
+ __IO uint32_t BSEC_JTAGOUT; /*!< BSEC JTAG Output, Address offset: 0xB0 */
+ __IO uint32_t BSEC_SCRATCH; /*!< BSEC SCRATCH, Address offset: 0xB4 */
+ uint32_t RESERVED0xB8[82]; /*!< Reserved, 0x0B8-0x200 Address offset: 0xB8 */
+ __IO uint32_t BSEC_OTP_DATA[96]; /*!< BSEC Shadow Registers, Address offset: 0x200 */
+ uint32_t RESERVED0x380[796]; /*!< Reserved, 0x0380-0xFF0 Address offset: 0x380 */
+ __IO uint32_t HWCFGR; /*!< BSEC IP HW Configuration Register, Address offset: 0xFF0 */
+ __IO uint32_t VERR; /*!< BSEC IP version Register, Address offset: 0xFF4 */
+ __IO uint32_t IPIDR; /*!< BSEC ID Register, Address offset: 0xFF8 */
+ __IO uint32_t SIDR; /*!< BSEC SID Register, Address offset: 0xFFC */
+} BSEC_TypeDef;
+
+
+/**
+ * @brief RTC Specific device feature definitions
+ */
+#define RTC_BACKUP_NB 32u /* Backup registers implemented */
+#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
+ uint32_t RESERVED; /*!< Reserved */
+ __IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */
+ uint32_t RESERVED1; /*!< Reserved */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
+ __IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */
+ __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
+ __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
+ __IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */
+ __IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */
+ uint32_t RESERVED2[227]; /*!< Reserved */
+ __IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Tamper and Backup registers
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TAMP tamper control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */
+ uint32_t RESERVED; /*!< Reserved */
+ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
+ __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */
+ __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
+ __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved */
+ __IO uint32_t SMCR; /*!< TAMP secure mode control register, Address offset: 0x20 */
+ uint32_t RESERVED2[2]; /*!< Reserved, 0x024 - 0x028 */
+ __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
+ __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
+ __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
+ __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
+ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
+ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
+ uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */
+ __IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */
+ uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */
+ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
+ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
+ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
+ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
+ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
+ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
+ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
+ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
+ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
+ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
+ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
+ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
+ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
+ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
+ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
+ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
+ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
+ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
+ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
+ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
+ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
+ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
+ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
+ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
+ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
+ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
+ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
+ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
+ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
+ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
+ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
+ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
+ uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */
+ __IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */
+ __IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */
+
+} TAMP_TypeDef;
+
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+ uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
+ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
+ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
+ uint32_t RESERVED1[233]; /*!< Reserved, 0x4C - 0x3EC */
+ __IO uint32_t HWCFGR; /*!< SAI HW Configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< SAI PVersion register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< SAI Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< SAI Size Identification register, Address offset: 0x3FC */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+
+/**
+ * @brief Process Monitor Block
+ */
+
+typedef struct
+{
+ uint32_t Reserved; /*!< Reserved, Address offset: 0x00 */
+ __IO uint32_t SENS_CTRL; /*!< PMB Sensor control, Address offset: 0x04 */
+ __IO uint32_t REF_COUNTER; /*!< PMB Reference counter, Address offset: 0x08 */
+ __IO uint32_t SENSOR_STATUS; /*!< PMB Sensor Status, Address offset: 0x0C */
+}PMB_TypeDef;
+
+
+/**
+ * @brief SPDIF-RX Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint32_t RESERVED2[246]; /*!< Reserved, 0x1C - 0x3F0 */
+ __IO uint32_t VERR; /*!< SPDIFRX version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< SPDIFRX Identificationn register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< SPDIFRX Size Identification register, Address offset: 0x3FC */
+} SPDIFRX_TypeDef;
+
+
+/**
+ * @brief Secure digital input/output Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
+ __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
+ uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
+ __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
+ __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
+ __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
+ __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
+ uint32_t RESERVED1[1]; /*!< Reserved, 0x60 */
+ __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */
+ __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */
+ uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
+ uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */
+ __IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< SDMMCsize ID register, Address offset: 0x3FC */
+} SDMMC_TypeDef;
+
+
+/**
+ * @brief Delay Block DLYB
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
+ uint32_t Reserved[249]; /* Reserved Address offset: 0x08 - 0x3F0 */
+ __IO uint32_t VERR; /*!< DELAY BLOCK Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< DELAY BLOCK Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< DELAY BLOCK Size ID register, Address offset: 0x3FC */
+} DLYB_TypeDef;
+
+/**
+ * @brief HW Semaphore HSEM
+ */
+
+typedef struct
+{
+ __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
+ __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
+ __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */
+ __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */
+ __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */
+ __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */
+ __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */
+ __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */
+ __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */
+ __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */
+ uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
+ __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
+ __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
+ uint32_t Reserved1[169]; /* Reserved Address offset: 148h-3E8h */
+ __IO uint32_t HWCFGR2; /*!< HSEM Hardware Configuration Register 2 , Address offset: 3ECh */
+ __IO uint32_t HWCFGR1; /*!< HSEM Hardware Configuration Register 1 , Address offset: 3F0h */
+ __IO uint32_t VERR; /*!< HSEM IP Version Register , Address offset: 3F4h */
+ __IO uint32_t IPIDR; /*!< HSEM IP Identification Register , Address offset: 3F8h */
+ __IO uint32_t SIDR; /*!< HSEM Size Identification Register , Address offset: 3FCh */
+} HSEM_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
+ __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
+ __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
+ __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
+} HSEM_Common_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t CFG1; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t CFG2; /*!< SPI Status register, Address offset: 0x0C */
+ __IO uint32_t IER; /*!< SPI data register, Address offset: 0x10 */
+ __IO uint32_t SR; /*!< SPI data register, Address offset: 0x14 */
+ __IO uint32_t IFCR; /*!< SPI data register, Address offset: 0x18 */
+ uint32_t RESERVED0; /*!< SPI data register, Address offset: 0x1C */
+ __IO uint32_t TXDR; /*!< SPI data register, Address offset: 0x20 */
+ uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
+ __IO uint32_t RXDR; /*!< SPI data register, Address offset: 0x30 */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
+ __IO uint32_t CRCPOLY; /*!< SPI data register, Address offset: 0x40 */
+ __IO uint32_t TXCRC; /*!< SPI data register, Address offset: 0x44 */
+ __IO uint32_t RXCRC; /*!< SPI data register, Address offset: 0x48 */
+ __IO uint32_t UDRDR; /*!< SPI data register, Address offset: 0x4C */
+ __IO uint32_t I2SCFGR; /*!< SPI data register, Address offset: 0x50 */
+ uint32_t RESERVED3[231]; /*!< Reserved, 0x54-0x3EC */
+ __IO uint32_t HWCFGR; /*!< SPI HW Configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< SPI Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< SPI identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< SPI Size Identification register, Address offset: 0x3FC */
+} SPI_TypeDef;
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+ uint32_t RESERVED[239]; /*!< Reserved, 0x34-0x3EC */
+ __IO uint32_t HWCFGR; /*!< QUADSPI HW configuration register, Address offset: 0x3F0*/
+ __IO uint32_t VERR; /*!< QUADSPI version register, Address offset: 0x3F4*/
+ __IO uint32_t IPIDR; /*!< QUADSPI dentification register, Address offset: 0x3F8*/
+ __IO uint32_t SIDR; /*!< QUADSPI size identification register, Address offset: 0x3FC*/
+} QUADSPI_TypeDef;
+
+/**
+ * @brief Temperature Sensor
+ */
+/* TMPSENS has been renamed in DTS*/
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< Temperature Sensor Configuration Register 1, Address offset: 0x00 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
+ __IO uint32_t T0VALR1; /*!< Temperature sensor T0 Value Register 1, Address offset: 0x08 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */
+ __IO uint32_t RAMPVALR; /*!< Temperature sensor Ramp Value Register, Address offset: 0x10 */
+ __IO uint32_t ITR1; /*!< Temperature sensor Interrupt Threshold Register 1, Address offset: 0x14 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t DR; /*!< Temperature sensor Data Register, Address offset: 0x1C */
+ __IO uint32_t SR; /*!< Temperature sensor Status Register, Address offset: 0x20 */
+ __IO uint32_t ITENR; /*!< Temperature sensor Interrupt Enable Register, Address offset: 0x24 */
+ __IO uint32_t ICIFR; /*!< Temperature sensor clear interrupt flag register, Address offset: 0x28 */
+ __IO uint32_t OR; /*!< Temperature sensor option register, Address offset: 0x2C */
+}DTS_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
+ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
+ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
+ uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */
+ __IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */
+} TIM_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ uint16_t RESERVED1; /*!< Reserved, 0x20 */
+ __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
+ uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */
+ __IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */
+ __IO uint32_t PIDR; /*!< LPTIM Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< LPTIM Size Identification register, Address offset: 0x3FC */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+typedef struct
+{
+ __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
+ __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
+} COMPOPT_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ uint16_t RESERVED2; /*!< Reserved, 0x12 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ uint16_t RESERVED3; /*!< Reserved, 0x1A */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED4; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED5; /*!< Reserved, 0x2A */
+ __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
+ uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */
+ __IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */
+ __IO uint32_t HWCFGR1; /*!< USART Configuration1 register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< USART Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< USART clock Size Identification register, Address offset: 0x3FC */
+
+} USART_TypeDef;
+
+/**
+ * @brief Single Wire Protocol Master Interface SPWMI
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
+ __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
+ uint32_t RESERVED1; /*!< Reserved, 0x08 */
+ __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
+ __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
+ __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
+ __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
+ __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
+ __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+ uint32_t RESERVED1[249]; /*!< Reserved, 0x0C - 0x3EC */
+ __IO uint32_t HWCFGR; /*!< WWDG HW Config register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< WWDG Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< WWDG Identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< WWDG Size ID register, Address offset: 0x3FC */
+
+} WWDG_TypeDef;
+/**
+ * @brief Crypto Processor
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
+ __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
+ uint32_t RESERVED[216];
+ __IO uint32_t HWCFGR; /*!< CRYP HW Configuration, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< CRYP version register , Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< CRYP Identification register, Address offset: 0x3F8 */
+ __IO uint32_t MID; /*!< CRYP HW Magic ID register, Address offset: 0x3FC */
+} CRYP_TypeDef;
+/**
+ * @brief HASH
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
+ uint32_t RESERVED2[80];
+ __IO uint32_t HR2[8];
+ uint32_t RESERVED3[48];
+ __IO uint32_t HWCFGR; /*!< HASH Hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< HASH Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< HASH identification register, Address offset: 0x3F8 */
+ __IO uint32_t MID; /*!< HASH Hardware Magic ID register, Address offset: 0x3FC */
+} HASH_TypeDef;
+
+/**
+ * @brief HASH_DIGEST
+ */
+
+typedef struct
+{
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
+} HASH_DIGEST_TypeDef;
+
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+ __IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
+ __IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
+} RNG_TypeDef;
+
+/**
+ * @brief Inter-Processor Communication
+ */
+typedef struct
+{
+ __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */
+ __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */
+ __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */
+ __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */
+ __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */
+ __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */
+ __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */
+ __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */
+ __IO uint32_t RESERVED1[244]; /*!< Reserved */
+ __IO uint32_t HWCFGR; /*!< Inter-Processor Communication hardware configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VER; /*!< Inter-Processor Communication version register, Address offset: 0x3F4 */
+ __IO uint32_t ID; /*!< Inter-Processor Communication identification register, Address offset: 0x3F8 */
+ __IO uint32_t SID; /*!< Inter-Processor Communication size identification register, Address offset: 0x3FC */
+} IPCC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */
+ __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */
+ __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */
+} IPCC_CommonTypeDef;
+
+/**
+ * @brief MDIOS
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */
+ __IO uint32_t WRFR; /*!< Write Flag register, Address offset: 0x004 */
+ __IO uint32_t CWRFR; /*!< Clear Write Flag register, Address offset: 0x008 */
+ __IO uint32_t RDFR; /*!< Read Flag register, Address offset: 0x00C */
+ __IO uint32_t CRDFR; /*!< Clear Read Flag register, Address offset: 0x010 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x014 */
+ __IO uint32_t CLRFR; /*!< Clear Flag register, Address offset: 0x018 */
+ uint32_t RESERVED[57]; /*!< Reserved, Address offset: 0x01C - 0x0FC */
+ __IO uint32_t DINR0; /*!< Input Data register 0 Address offset: 0x100 */
+ __IO uint32_t DINR1; /*!< Input Data register 1 Address offset: 0x104 */
+ __IO uint32_t DINR2; /*!< Input Data register 2 Address offset: 0x108 */
+ __IO uint32_t DINR3; /*!< Input Data register 3 Address offset: 0x10C */
+ __IO uint32_t DINR4; /*!< Input Data register 4 Address offset: 0x110 */
+ __IO uint32_t DINR5; /*!< Input Data register 5 Address offset: 0x114 */
+ __IO uint32_t DINR6; /*!< Input Data register 6 Address offset: 0x118 */
+ __IO uint32_t DINR7; /*!< Input Data register 7 Address offset: 0x11C */
+ __IO uint32_t DINR8; /*!< Input Data register 8 Address offset: 0x120 */
+ __IO uint32_t DINR9; /*!< Input Data register 9 Address offset: 0x124 */
+ __IO uint32_t DINR10; /*!< Input Data register 10 Address offset: 0x128 */
+ __IO uint32_t DINR11; /*!< Input Data register 11 Address offset: 0x12C */
+ __IO uint32_t DINR12; /*!< Input Data register 12 Address offset: 0x130 */
+ __IO uint32_t DINR13; /*!< Input Data register 13 Address offset: 0x134 */
+ __IO uint32_t DINR14; /*!< Input Data register 14 Address offset: 0x138 */
+ __IO uint32_t DINR15; /*!< Input Data register 15 Address offset: 0x13C */
+ __IO uint32_t DINR16; /*!< Input Data register 16 Address offset: 0x140 */
+ __IO uint32_t DINR17; /*!< Input Data register 17 Address offset: 0x144 */
+ __IO uint32_t DINR18; /*!< Input Data register 18 Address offset: 0x148 */
+ __IO uint32_t DINR19; /*!< Input Data register 19 Address offset: 0x14C */
+ __IO uint32_t DINR20; /*!< Input Data register 20 Address offset: 0x150 */
+ __IO uint32_t DINR21; /*!< Input Data register 21 Address offset: 0x154 */
+ __IO uint32_t DINR22; /*!< Input Data register 22 Address offset: 0x158 */
+ __IO uint32_t DINR23; /*!< Input Data register 23 Address offset: 0x15C */
+ __IO uint32_t DINR24; /*!< Input Data register 24 Address offset: 0x160 */
+ __IO uint32_t DINR25; /*!< Input Data register 25 Address offset: 0x164 */
+ __IO uint32_t DINR26; /*!< Input Data register 26 Address offset: 0x168 */
+ __IO uint32_t DINR27; /*!< Input Data register 27 Address offset: 0x16C */
+ __IO uint32_t DINR28; /*!< Input Data register 28 Address offset: 0x170 */
+ __IO uint32_t DINR29; /*!< Input Data register 29 Address offset: 0x174 */
+ __IO uint32_t DINR30; /*!< Input Data register 30 Address offset: 0x178 */
+ __IO uint32_t DINR31; /*!< Input Data register 31 Address offset: 0x17C */
+ __IO uint32_t DOUTR0; /*!< Output Data register 0 Address offset: 0x180 */
+ __IO uint32_t DOUTR1; /*!< Output Data register 1 Address offset: 0x184 */
+ __IO uint32_t DOUTR2; /*!< Output Data register 2 Address offset: 0x188 */
+ __IO uint32_t DOUTR3; /*!< Output Data register 3 Address offset: 0x18C */
+ __IO uint32_t DOUTR4; /*!< Output Data register 4 Address offset: 0x190 */
+ __IO uint32_t DOUTR5; /*!< Output Data register 5 Address offset: 0x194 */
+ __IO uint32_t DOUTR6; /*!< Output Data register 6 Address offset: 0x198 */
+ __IO uint32_t DOUTR7; /*!< Output Data register 7 Address offset: 0x19C */
+ __IO uint32_t DOUTR8; /*!< Output Data register 8 Address offset: 0x1A0 */
+ __IO uint32_t DOUTR9; /*!< Output Data register 9 Address offset: 0x1A4 */
+ __IO uint32_t DOUTR10; /*!< Output Data register 10 Address offset: 0x1A8 */
+ __IO uint32_t DOUTR11; /*!< Output Data register 11 Address offset: 0x1AC */
+ __IO uint32_t DOUTR12; /*!< Output Data register 12 Address offset: 0x1B0 */
+ __IO uint32_t DOUTR13; /*!< Output Data register 13 Address offset: 0x1B4 */
+ __IO uint32_t DOUTR14; /*!< Output Data register 14 Address offset: 0x1B8 */
+ __IO uint32_t DOUTR15; /*!< Output Data register 15 Address offset: 0x1BC */
+ __IO uint32_t DOUTR16; /*!< Output Data register 16 Address offset: 0x1C0 */
+ __IO uint32_t DOUTR17; /*!< Output Data register 17 Address offset: 0x1C4 */
+ __IO uint32_t DOUTR18; /*!< Output Data register 18 Address offset: 0x1C8 */
+ __IO uint32_t DOUTR19; /*!< Output Data register 19 Address offset: 0x1CC */
+ __IO uint32_t DOUTR20; /*!< Output Data register 20 Address offset: 0x1D0 */
+ __IO uint32_t DOUTR21; /*!< Output Data register 21 Address offset: 0x1D4 */
+ __IO uint32_t DOUTR22; /*!< Output Data register 22 Address offset: 0x1D8 */
+ __IO uint32_t DOUTR23; /*!< Output Data register 23 Address offset: 0x1DC */
+ __IO uint32_t DOUTR24; /*!< Output Data register 24 Address offset: 0x1E0 */
+ __IO uint32_t DOUTR25; /*!< Output Data register 25 Address offset: 0x1E4 */
+ __IO uint32_t DOUTR26; /*!< Output Data register 26 Address offset: 0x1E8 */
+ __IO uint32_t DOUTR27; /*!< Output Data register 27 Address offset: 0x1EC */
+ __IO uint32_t DOUTR28; /*!< Output Data register 28 Address offset: 0x1F0 */
+ __IO uint32_t DOUTR29; /*!< Output Data register 29 Address offset: 0x1F4 */
+ __IO uint32_t DOUTR30; /*!< Output Data register 30 Address offset: 0x1F8 */
+ __IO uint32_t DOUTR31; /*!< Output Data register 31 Address offset: 0x1FC */
+ uint32_t RESERVED1[124]; /*!< Reserved 0x200 - 0x3EC */
+ __IO uint32_t HWCFGR; /*!< MDIOS HW Configuration register, Address offset: 0x3F0 */
+ __IO uint32_t VERR; /*!< MDIOS Version register, Address offset: 0x3F4 */
+ __IO uint32_t IPIDR; /*!< MDIOS identification register, Address offset: 0x3F8 */
+ __IO uint32_t SIDR; /*!< MDIOS Size ID register, Address offset: 0x3FC */
+} MDIOS_TypeDef;
+
+
+/**
+ * @brief USB_OTG_Core_Registers
+ */
+typedef struct
+{
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
+ __IO uint32_t GI2CCTL; /*!< I2C Access Register 030h */
+ uint32_t Reserved30; /*!< Reserved 034h */
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
+ __IO uint32_t CID; /*!< User ID Register 03Ch */
+ uint32_t Reserved5[4]; /*!< Reserved 040h-048h */
+ uint32_t Reserved6; /*!< Reserved 050h */
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
+ uint32_t Reserved43[42]; /*!< Reserved 058h-0FFh */
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+ * @brief USB_OTG_device_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
+ uint32_t Reserved0C; /*!< Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
+ uint32_t Reserved20; /*!< Reserved 820h */
+ uint32_t Reserved9; /*!< Reserved 824h */
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+ * @brief USB_OTG_IN_Endpoint-Specific_Register
+ */
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+ * @brief USB_OTG_Host_Mode_Register_Structures
+ */
+typedef struct
+{
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
+ uint32_t Reserved40C; /*!< Reserved 40Ch */
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
+ __IO uint32_t HFLBADDR; /*!< Host frame list base address register 41Ch */
+ uint32_t Reserved420[8]; /*!< Reserved 420h */
+ __IO uint32_t HPRT; /*!< Host port control and status register 440h */
+} USB_OTG_HostTypeDef;
+
+/**
+ * @brief USB_OTG_Host_Channel_Specific_Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
+ uint32_t Reserved0; /*!< Reserved 518h */
+ __IO uint32_t HCDMAB; /*!< Host Channel DMA Address Buffer Register 51Ch */
+ uint32_t Reserved[2]; /*!< Reserved */
+} USB_OTG_HostChannelTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @brief USB_EHCI Capability Registers
+ */
+typedef struct
+{
+ __IO uint32_t HCCAPBASE; /*!< Capability Register register, Address offset: 0x00 */
+ __IO uint32_t HCSPARAMS; /*!< Structural Parameter register Address offset: 0x04 */
+ __IO uint32_t HCCPARAMS; /*!< Capability Parameter register, Address offset: 0x08 */
+ uint32_t RESERVED; /*!< USB Command register, Address offset: 0x0C */
+ __IO uint32_t USBCMD; /*!< USB Command register, Address offset: 0x10 */
+ __IO uint32_t USBSTS; /*!< USB Status register, Address offset: 0x14 */
+ __IO uint32_t USBINTR; /*!< USB Interrupt Enable register, Address offset: 0x18 */
+ __IO uint32_t FRINDEX; /*!< USB Frame Index register , Address offset: 0x1C */
+ __IO uint32_t CTRLDSSEGMENT; /*!< 4G Segment Selector register, Address offset: 0x20 */
+ __IO uint32_t PERIODICLISTBASE; /*!< Periodic Frame List Base Address register, Address offset: 0x24 */
+ __IO uint32_t ASYNCLISTADDR; /*!< Asynchronous List Address register, Address offset: 0x28 */
+} USB_EHCI_CapabilityTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @brief GPU host interface registers
+ */
+typedef struct
+{
+ __IO uint32_t CLKCTRLR; /*!< Clock control register Address offset: 0x00 */
+ __IO uint32_t IDLESR; /*!< IDLE status register Address offset: 0x04 */
+ __IO uint32_t AXICFGR; /*!< AXI Configuration register Address offset: 0x08 */
+ __IO uint32_t AXISR; /*!< AXI Status register, Address offset: 0x0C */
+ __IO uint32_t INTRACK; /*!< Interrupt acknowledge register, Address offset: 0x10 */
+ __IO uint32_t INTREN; /*!< Interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t CHIPID; /*!< Chip ID, Address offset: 0x18 */
+ __IO uint32_t CHIPREV; /*!< Chip revision register, Address offset: 0x1C */
+ __IO uint32_t CHIPDATE; /*!< Release date register, Address offset: 0x20 */
+ __IO uint32_t CHIPTIME; /*!< Release Time register, Address offset: 0x24 */
+ __IO uint32_t TOTALCYCLES; /*!< Total number of Cycles register, Address offset: 0x28 */
+ __IO uint32_t PRODUCTID; /*!< Product ID register, Address offset: 0x2C */
+ __IO uint32_t POWERCTRLR; /*!< Power control register, Address offset: 0x30 */
+ __IO uint32_t MMUCTRLR; /*!< MMU control register, Address offset: 0x34 */
+ __IO uint32_t MEMDEBUG; /*!< Memory debug register, Address offset: 0x38 */
+ __IO uint32_t CMDBUFADDR; /*!< Command buffer base address register, Address offset: 0x3C */
+ __IO uint32_t CMDBUFCTRL; /*!< Command buffer control register, Address offset: 0x40 */
+} GPU_Host_InterfaceTypeDef;
+/**
+ * @}
+ */
+
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */
+#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */
+
+#define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */
+#define RETRAM_BASE MCU_AHB_RETRAM
+#define SRAM_BASE MCU_AHB_SRAM
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
+#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */
+
+#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */
+#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */
+#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */
+#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */
+#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */
+
+/*!< Device electronic signature memory map */
+#define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */
+#define PACKAGE_BASE (0x5C005240L) /*!< Package Data register base address */
+#define RPN_BASE (0x5C005204L) /*!< Device Part Number register base address */
+#define DV_BASE (0x50081000L) /*!< Device Version register base address */
+
+/*!< Peripheral memory map */
+#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
+#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000)
+#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000)
+#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000)
+#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000)
+#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000)
+#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000)
+#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000)
+#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000)
+#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000)
+#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000)
+
+
+/*!< MCU_APB1 */
+#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000)
+#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000)
+#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000)
+#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000)
+#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000)
+#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000)
+#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000)
+#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000)
+#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000)
+#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000)
+#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000)
+#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000)
+#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000)
+#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000)
+#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000)
+#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000)
+#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000)
+#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000)
+#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000)
+#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000)
+#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000)
+#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000)
+#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000)
+#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000)
+#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000)
+#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000)
+#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000)
+
+/*!< MCU_APB2 */
+#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000)
+#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000)
+#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000)
+#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000)
+#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000)
+#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000)
+#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000)
+#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000)
+#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000)
+#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
+#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000)
+#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
+#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
+#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
+#define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300)
+#define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380)
+#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000)
+#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000)
+#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100)
+#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000)
+#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000)
+
+/*!< MCU_AHB2 */
+#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000)
+#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000)
+#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000)
+#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000)
+#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100)
+#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300)
+#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000)
+#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000)
+#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000)
+
+
+/*!< MCU_AHB3 */
+#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000)
+#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000)
+#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000)
+#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310)
+#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000)
+#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000)
+#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000)
+#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000)
+
+/*!< MCU_AHB4 */
+#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000)
+#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000)
+#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000)
+#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000)
+#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000)
+#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000)
+#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000)
+#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000)
+#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000)
+#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000)
+#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000)
+#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000)
+#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000)
+#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000)
+#define AIEC_C1_BASE (AIEC_BASE + 0x0080)
+#define AIEC_C2_BASE (AIEC_BASE + 0x00C0)
+/* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/
+#define EXTI_BASE AIEC_BASE
+#define EXTI_C1_BASE AIEC_C1_BASE
+#define EXTI_C2_BASE AIEC_C2_BASE
+
+
+/*!< MCU_APB3 */
+#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000)
+#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000)
+#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000)
+#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000)
+#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000)
+#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000)
+#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000)
+#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
+#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
+#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000)
+#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000)
+#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000)
+
+/*!< MCU_AHB4 _APB_Debug */
+#define DBGMCU_BASE ((uint32_t )0x50081000)
+
+/*!< MCU_AHB5 */
+#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000)
+#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000)
+#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000)
+#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310)
+#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000)
+#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000)
+
+/*!< GPV */
+
+/*!< MPU_AHB6 */
+#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000)
+#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000)
+#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000)
+#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000)
+#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000)
+#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000)
+#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000)
+#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000)
+#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000)
+#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000)
+#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000)
+#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000)
+
+/*!< MPU_APB4 */
+#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000)
+#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000)
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
+#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000)
+#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000)
+#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000)
+#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000)
+#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000)
+#define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100)
+#define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200)
+
+/*!< MPU_APB5 */
+#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000)
+#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000)
+#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000)
+#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000)
+#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000)
+#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000)
+#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000)
+#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000)
+#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000)
+#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000)
+#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000)
+
+
+
+/*!< USB registers base address */
+#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
+#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
+#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
+#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
+#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
+#define USB_OTG_HOST_BASE ((uint32_t )0x400)
+#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
+#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
+#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
+#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
+#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
+#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
+
+
+
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
+
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
+
+#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
+#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
+#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000C)
+#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010)
+#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014)
+#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018)
+#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001C)
+#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020)
+#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024)
+#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028)
+#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002C)
+#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030)
+#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034)
+#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038)
+#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003C)
+
+#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100)
+#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104)
+#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108)
+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010C)
+
+#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080)
+#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
+
+
+
+/*!< FMC Banks registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
+
+#define MDMA_NB_CHANNELS 32
+#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040)
+#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080)
+#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0)
+#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100)
+#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140)
+#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180)
+#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0)
+#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200)
+#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240)
+#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280)
+#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0)
+#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300)
+#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340)
+#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380)
+#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0)
+#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400)
+#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440)
+#define MDMA_Channel17_BASE (MDMA_BASE + 0x00000480)
+#define MDMA_Channel18_BASE (MDMA_BASE + 0x000004C0)
+#define MDMA_Channel19_BASE (MDMA_BASE + 0x00000500)
+#define MDMA_Channel20_BASE (MDMA_BASE + 0x00000540)
+#define MDMA_Channel21_BASE (MDMA_BASE + 0x00000580)
+#define MDMA_Channel22_BASE (MDMA_BASE + 0x000005C0)
+#define MDMA_Channel23_BASE (MDMA_BASE + 0x00000600)
+#define MDMA_Channel24_BASE (MDMA_BASE + 0x00000640)
+#define MDMA_Channel25_BASE (MDMA_BASE + 0x00000680)
+#define MDMA_Channel26_BASE (MDMA_BASE + 0x000006C0)
+#define MDMA_Channel27_BASE (MDMA_BASE + 0x00000700)
+#define MDMA_Channel28_BASE (MDMA_BASE + 0x00000740)
+#define MDMA_Channel29_BASE (MDMA_BASE + 0x00000780)
+#define MDMA_Channel30_BASE (MDMA_BASE + 0x000007C0)
+#define MDMA_Channel31_BASE (MDMA_BASE + 0x00000800)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define LCD ((LCD_TypeDef *) LCD_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
+#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
+#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
+#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define USART6 ((USART_TypeDef *) USART6_BASE)
+#define UART7 ((USART_TypeDef *) UART7_BASE)
+#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
+#define I2C5 ((I2C_TypeDef *) I2C5_BASE)
+#define I2C6 ((I2C_TypeDef *) I2C6_BASE)
+#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
+#define TTFDCAN1 ((TTCAN_TypeDef *) TTFDCAN1_BASE)
+#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
+#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
+#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
+#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF ((VREF_TypeDef *) VREFBUF_BASE)
+
+
+
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define EXTI_C1 ((EXTI_Core_TypeDef *) EXTI_C1_BASE)
+#define EXTI_C2 ((EXTI_Core_TypeDef *) EXTI_C2_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
+#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
+#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
+#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
+#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
+#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
+#define DTS1 ((DTS_TypeDef *) DTS_BASE)
+#define PMB ((PMB_TypeDef *) PMB_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define DFSDM1 ((DFSDM_TypeDef *) DFSDM1_BASE)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
+#define DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
+
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+
+#define HDP ((HDP_TypeDef *) HDP_BASE)
+
+#define BSEC ((BSEC_TypeDef *) BSEC_BASE)
+
+
+#define CRC2 ((CRC_TypeDef *) CRC2_BASE)
+#define CRC1 ((CRC_TypeDef *) CRC1_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+
+#define IPCC ((IPCC_TypeDef *) IPCC_BASE)
+#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE)
+#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))
+#define CRYP2 ((CRYP_TypeDef *) CRYP2_BASE)
+#define CRYP1 ((CRYP_TypeDef *) CRYP1_BASE)
+#define HASH2 ((HASH_TypeDef *) HASH2_BASE)
+#define HASH1 ((HASH_TypeDef *) HASH1_BASE)
+#define HASH2_DIGEST ((HASH_DIGEST_TypeDef *) HASH2_DIGEST_BASE)
+#define HASH1_DIGEST ((HASH_DIGEST_TypeDef *) HASH1_DIGEST_BASE)
+#define HASH ((HASH_TypeDef *) HASH2)
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH2_DIGEST)
+#define RNG2 ((RNG_TypeDef *) RNG2_BASE)
+#define RNG1 ((RNG_TypeDef *) RNG1_BASE)
+#define GPIOZ ((GPIO_TypeDef *) GPIOZ_BASE)
+#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
+
+#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
+#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
+#define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE)
+
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
+
+#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
+#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
+
+#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+
+#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
+
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define SDMMC3 ((SDMMC_TypeDef *) SDMMC3_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
+#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
+#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110U))
+
+
+#define USBPHYC ((USBPHYC_GlobalTypeDef *)USBPHYC_BASE)
+#define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE)
+#define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE)
+
+#define DDRC ((DDRC_TypeDef *)DDRC_BASE)
+#define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE)
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI ((DSI_TypeDef *)DSI_BASE)
+
+#define TZC ((TZC_TypeDef *)TZC_BASE)
+#define TZPC ((TZPC_TypeDef *)TZPC_BASE)
+#define STGENC ((STGENC_TypeDef *)STGENC_BASE)
+
+
+#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
+
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define MDMA ((MDMA_TypeDef *) MDMA_BASE)
+#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
+#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
+#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
+#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
+#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
+#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
+#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
+#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
+#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
+#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
+#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
+#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
+#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
+#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
+#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
+#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
+#define MDMA_Channel16 ((MDMA_Channel_TypeDef *)MDMA_Channel16_BASE)
+#define MDMA_Channel17 ((MDMA_Channel_TypeDef *)MDMA_Channel17_BASE)
+#define MDMA_Channel18 ((MDMA_Channel_TypeDef *)MDMA_Channel18_BASE)
+#define MDMA_Channel19 ((MDMA_Channel_TypeDef *)MDMA_Channel19_BASE)
+#define MDMA_Channel20 ((MDMA_Channel_TypeDef *)MDMA_Channel20_BASE)
+#define MDMA_Channel21 ((MDMA_Channel_TypeDef *)MDMA_Channel21_BASE)
+#define MDMA_Channel22 ((MDMA_Channel_TypeDef *)MDMA_Channel22_BASE)
+#define MDMA_Channel23 ((MDMA_Channel_TypeDef *)MDMA_Channel23_BASE)
+#define MDMA_Channel24 ((MDMA_Channel_TypeDef *)MDMA_Channel24_BASE)
+#define MDMA_Channel25 ((MDMA_Channel_TypeDef *)MDMA_Channel25_BASE)
+#define MDMA_Channel26 ((MDMA_Channel_TypeDef *)MDMA_Channel26_BASE)
+#define MDMA_Channel27 ((MDMA_Channel_TypeDef *)MDMA_Channel27_BASE)
+#define MDMA_Channel28 ((MDMA_Channel_TypeDef *)MDMA_Channel28_BASE)
+#define MDMA_Channel29 ((MDMA_Channel_TypeDef *)MDMA_Channel29_BASE)
+#define MDMA_Channel30 ((MDMA_Channel_TypeDef *)MDMA_Channel30_BASE)
+#define MDMA_Channel31 ((MDMA_Channel_TypeDef *)MDMA_Channel31_BASE)
+
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USBOTG_BASE)
+/* backward compatibility */
+#define USB1_OTG_HS USB_OTG_HS
+#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) 0x00000000)
+#define USB_OTG_FS USB2_OTG_FS
+
+#define USB1_EHCI ((USB_EHCI_CapabilityTypeDef *) USB1HSFSP1_BASE)
+
+#define GPU ((GPU_Host_InterfaceTypeDef *) GPU_BASE)
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Device Electronic Signature */
+/* */
+/******************************************************************************/
+#define PKG_ID_Pos (27U)
+#define PKG_ID_Msk (0x7U << PKG_ID_Pos) /*!< 0x38000000 */
+#define PKG_ID PKG_ID_Msk /*!< Package Type */
+
+#define RPN_ID_Pos (0U)
+#define RPN_ID_Msk (0xFFU << RPN_ID_Pos) /*!< 0x000000FF */
+#define RPN_ID RPN_ID_Msk /*!< Device Part Number */
+
+#define DV_DEV_ID_Pos (0U)
+#define DV_DEV_ID_Msk (0xFFFU << DV_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DV_DEV_ID DV_DEV_ID_Msk /*!< Device ID */
+#define DV_REV_ID_Pos (16U)
+#define DV_REV_ID_Msk (0xFFFFU << DV_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DV_REV_ID DV_REV_ID_Msk /*!< Device Rev ID */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos (3U)
+#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos (5U)
+#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos (6U)
+#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos (7U)
+#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos (8U)
+#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos (9U)
+#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos (10U)
+#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos (3U)
+#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos (5U)
+#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos (6U)
+#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos (7U)
+#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos (8U)
+#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos (9U)
+#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos (10U)
+#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos (3U)
+#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos (5U)
+#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
+#define ADC_CR_BOOST_Pos (8U)
+#define ADC_CR_BOOST_Msk (0x1U << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
+#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode */
+#define ADC_CR_ADCALLIN_Pos (16U)
+#define ADC_CR_ADCALLIN_Msk (0x1U << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
+#define ADC_CR_LINCALRDYW1_Pos (22U)
+#define ADC_CR_LINCALRDYW1_Msk (0x1U << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
+#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
+#define ADC_CR_LINCALRDYW2_Pos (23U)
+#define ADC_CR_LINCALRDYW2_Msk (0x1U << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
+#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
+#define ADC_CR_LINCALRDYW3_Pos (24U)
+#define ADC_CR_LINCALRDYW3_Msk (0x1U << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
+#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_LINCALRDYW4_Pos (25U)
+#define ADC_CR_LINCALRDYW4_Msk (0x1U << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
+#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_LINCALRDYW5_Pos (26U)
+#define ADC_CR_LINCALRDYW5_Msk (0x1U << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
+#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_LINCALRDYW6_Pos (27U)
+#define ADC_CR_LINCALRDYW6_Msk (0x1U << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
+#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos (29U)
+#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCALDIF_Pos (30U)
+#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR_DMNGT_Pos (0U)
+#define ADC_CFGR_DMNGT_Msk (0x3U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
+#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
+#define ADC_CFGR_DMNGT_0 (0x1U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
+#define ADC_CFGR_DMNGT_1 (0x2U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
+
+#define ADC_CFGR_RES_Pos (2U)
+#define ADC_CFGR_RES_Msk (0x7U << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
+#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
+#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR_RES_2 (0x4U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos (5U)
+#define ADC_CFGR_EXTSEL_Msk (0x1FU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0 (0x01U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1 (0x02U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2 (0x04U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3 (0x08U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4 (0x10U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos (10U)
+#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos (12U)
+#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
+#define ADC_CFGR_CONT_Pos (13U)
+#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY_Pos (14U)
+#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
+
+#define ADC_CFGR_DISCEN_Pos (16U)
+#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM_Pos (17U)
+#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos (20U)
+#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos (21U)
+#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
+#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL_Pos (22U)
+#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN_Pos (23U)
+#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN_Pos (24U)
+#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO_Pos (25U)
+#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH_Pos (26U)
+#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos (31U)
+#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
+
+/******************** Bit definition for ADC_CFGR2 register ********************/
+#define ADC_CFGR2_ROVSE_Pos (0U)
+#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos (1U)
+#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/
+#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos (9U)
+#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos (10U)
+#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
+
+#define ADC_CFGR2_RSHIFT1_Pos (11U)
+#define ADC_CFGR2_RSHIFT1_Msk (0x1U << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
+#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
+#define ADC_CFGR2_RSHIFT2_Pos (12U)
+#define ADC_CFGR2_RSHIFT2_Msk (0x1U << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
+#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
+#define ADC_CFGR2_RSHIFT3_Pos (13U)
+#define ADC_CFGR2_RSHIFT3_Msk (0x1U << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
+#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
+#define ADC_CFGR2_RSHIFT4_Pos (14U)
+#define ADC_CFGR2_RSHIFT4_Msk (0x1U << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
+#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
+
+#define ADC_CFGR2_OSR_Pos (16U)
+#define ADC_CFGR2_OSR_Msk (0x3FFU << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */
+#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OSR_0 (0x001U << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */
+#define ADC_CFGR2_OSR_1 (0x002U << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */
+#define ADC_CFGR2_OSR_2 (0x004U << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */
+#define ADC_CFGR2_OSR_3 (0x008U << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */
+#define ADC_CFGR2_OSR_4 (0x010U << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */
+#define ADC_CFGR2_OSR_5 (0x020U << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */
+#define ADC_CFGR2_OSR_6 (0x040U << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */
+#define ADC_CFGR2_OSR_7 (0x080U << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */
+#define ADC_CFGR2_OSR_8 (0x100U << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */
+#define ADC_CFGR2_OSR_9 (0x200U << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos (28U)
+#define ADC_CFGR2_LSHIFT_Msk (0xFU << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0 (0x1U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0_Pos (0U)
+#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos (3U)
+#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos (6U)
+#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos (9U)
+#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos (12U)
+#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos (15U)
+#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos (18U)
+#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos (21U)
+#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos (24U)
+#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos (27U)
+#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10_Pos (0U)
+#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos (3U)
+#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos (6U)
+#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos (9U)
+#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos (12U)
+#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos (15U)
+#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos (18U)
+#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos (21U)
+#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos (24U)
+#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos (27U)
+#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
+#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for ADC_PCSEL register ********************/
+#define ADC_PCSEL_PCSEL_Pos (0U)
+#define ADC_PCSEL_PCSEL_Msk (0xFFFFFU << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0 (0x00001U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1 (0x00002U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2 (0x00004U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3 (0x00008U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4 (0x00010U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5 (0x00020U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6 (0x00040U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7 (0x00080U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8 (0x00100U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9 (0x00200U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10 (0x00400U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11 (0x00800U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12 (0x01000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13 (0x02000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14 (0x04000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15 (0x08000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16 (0x10000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17 (0x20000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18 (0x40000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19 (0x80000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
+
+/******************** Bit definition for ADC_LTR1 register ********************/
+#define ADC_LTR1_LT1_Pos (0U)
+#define ADC_LTR1_LT1_Msk (0x3FFFFFFU << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */
+#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */
+#define ADC_LTR1_LT1_0 (0x0000001U << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */
+#define ADC_LTR1_LT1_1 (0x0000002U << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */
+#define ADC_LTR1_LT1_2 (0x0000004U << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */
+#define ADC_LTR1_LT1_3 (0x0000008U << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */
+#define ADC_LTR1_LT1_4 (0x0000010U << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */
+#define ADC_LTR1_LT1_5 (0x0000020U << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */
+#define ADC_LTR1_LT1_6 (0x0000040U << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */
+#define ADC_LTR1_LT1_7 (0x0000080U << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */
+#define ADC_LTR1_LT1_8 (0x0000100U << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */
+#define ADC_LTR1_LT1_9 (0x0000200U << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */
+#define ADC_LTR1_LT1_10 (0x0000400U << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */
+#define ADC_LTR1_LT1_11 (0x0000800U << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */
+#define ADC_LTR1_LT1_12 (0x0001000U << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */
+#define ADC_LTR1_LT1_13 (0x0002000U << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */
+#define ADC_LTR1_LT1_14 (0x0004000U << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */
+#define ADC_LTR1_LT1_15 (0x0008000U << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */
+#define ADC_LTR1_LT1_16 (0x0010000U << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */
+#define ADC_LTR1_LT1_17 (0x0020000U << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */
+#define ADC_LTR1_LT1_18 (0x0040000U << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */
+#define ADC_LTR1_LT1_19 (0x0080000U << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */
+#define ADC_LTR1_LT1_20 (0x0100000U << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */
+#define ADC_LTR1_LT1_21 (0x0200000U << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */
+#define ADC_LTR1_LT1_22 (0x0400000U << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */
+#define ADC_LTR1_LT1_23 (0x0800000U << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */
+#define ADC_LTR1_LT1_24 (0x1000000U << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */
+#define ADC_LTR1_LT1_25 (0x2000000U << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition for ADC_HTR1 register ********************/
+#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */
+#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */
+#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */
+#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */
+#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */
+#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */
+#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */
+#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */
+#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */
+#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */
+#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */
+#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */
+#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */
+#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */
+#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */
+#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */
+#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */
+#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */
+#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */
+#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */
+#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */
+#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */
+#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */
+#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */
+#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */
+#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */
+#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */
+
+/******************** Bit definition for ADC_LTR2 register ********************/
+#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */
+#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
+#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
+#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
+#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
+#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
+#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
+#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
+#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
+#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */
+#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */
+#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */
+#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */
+#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */
+#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */
+#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */
+#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */
+#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */
+#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */
+#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */
+#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */
+#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */
+#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */
+#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */
+#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */
+#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */
+#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */
+
+/******************** Bit definition for ADC_HTR2 register ********************/
+#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */
+#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */
+#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */
+#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */
+#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */
+#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */
+#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */
+#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */
+#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */
+#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */
+#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */
+#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */
+#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */
+#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */
+#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */
+#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */
+#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */
+#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */
+#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */
+#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */
+#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */
+#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */
+#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */
+#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */
+#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */
+#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */
+#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */
+
+/******************** Bit definition for ADC_LTR3 register ********************/
+#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */
+#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
+#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
+#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
+#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
+#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
+#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
+#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
+#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
+#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */
+#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */
+#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */
+#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */
+#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */
+#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */
+#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */
+#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */
+#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */
+#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */
+#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */
+#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */
+#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */
+#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */
+#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */
+#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */
+#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/
+#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */
+
+/******************** Bit definition for ADC_HTR3 register ********************/
+#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */
+#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */
+#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */
+#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */
+#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */
+#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */
+#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */
+#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */
+#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */
+#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */
+#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */
+#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */
+#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */
+#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */
+#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */
+#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */
+#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */
+#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */
+#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */
+#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */
+#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */
+#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */
+#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */
+#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */
+#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */
+#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */
+#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L_Pos (0U)
+#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos (6U)
+#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos (12U)
+#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos (18U)
+#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos (24U)
+#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5_Pos (0U)
+#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos (6U)
+#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos (12U)
+#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos (18U)
+#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos (24U)
+#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10_Pos (0U)
+#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos (6U)
+#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos (12U)
+#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos (18U)
+#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos (24U)
+#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15_Pos (0U)
+#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos (6U)
+#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA_Pos (0U)
+#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
+#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
+#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
+#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
+#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
+#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
+#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
+#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
+#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
+#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
+#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
+#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
+#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
+#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
+#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
+#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
+#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
+#define ADC_DR_RDATA_16 (0x10000U << ADC_DR_RDATA_Pos) /*!< 0x00010000 */
+#define ADC_DR_RDATA_17 (0x20000U << ADC_DR_RDATA_Pos) /*!< 0x00020000 */
+#define ADC_DR_RDATA_18 (0x40000U << ADC_DR_RDATA_Pos) /*!< 0x00040000 */
+#define ADC_DR_RDATA_19 (0x80000U << ADC_DR_RDATA_Pos) /*!< 0x00080000 */
+#define ADC_DR_RDATA_20 (0x100000U << ADC_DR_RDATA_Pos) /*!< 0x00100000 */
+#define ADC_DR_RDATA_21 (0x200000U << ADC_DR_RDATA_Pos) /*!< 0x00200000 */
+#define ADC_DR_RDATA_22 (0x400000U << ADC_DR_RDATA_Pos) /*!< 0x00400000 */
+#define ADC_DR_RDATA_23 (0x800000U << ADC_DR_RDATA_Pos) /*!< 0x00800000 */
+#define ADC_DR_RDATA_24 (0x1000000U << ADC_DR_RDATA_Pos) /*!< 0x01000000 */
+#define ADC_DR_RDATA_25 (0x2000000U << ADC_DR_RDATA_Pos) /*!< 0x02000000 */
+#define ADC_DR_RDATA_26 (0x4000000U << ADC_DR_RDATA_Pos) /*!< 0x04000000 */
+#define ADC_DR_RDATA_27 (0x8000000U << ADC_DR_RDATA_Pos) /*!< 0x08000000 */
+#define ADC_DR_RDATA_28 (0x10000000U << ADC_DR_RDATA_Pos) /*!< 0x10000000 */
+#define ADC_DR_RDATA_29 (0x20000000U << ADC_DR_RDATA_Pos) /*!< 0x20000000 */
+#define ADC_DR_RDATA_30 (0x40000000U << ADC_DR_RDATA_Pos) /*!< 0x40000000 */
+#define ADC_DR_RDATA_31 (0x80000000U << ADC_DR_RDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL_Pos (0U)
+#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos (2U)
+#define ADC_JSQR_JEXTSEL_Msk (0x1FU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 (0x01U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1 (0x02U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2 (0x04U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3 (0x08U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4 (0x10U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos (7U)
+#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos (9U)
+#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos (15U)
+#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos (21U)
+#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos (27U)
+#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1_Pos (0U)
+#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1 (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2 (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3 (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4 (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5 (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6 (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7 (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8 (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9 (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10 (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11 (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12 (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13 (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14 (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15 (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16 (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17 (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18 (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19 (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20 (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21 (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22 (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23 (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+#define ADC_OFR1_OFFSET1_24 (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSET1_25 (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR1_SSATE_Pos (31U)
+#define ADC_OFR1_SSATE_Msk (0x1U << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
+#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2_Pos (0U)
+#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1 (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2 (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3 (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4 (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5 (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6 (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7 (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8 (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9 (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10 (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11 (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12 (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13 (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14 (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15 (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16 (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17 (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18 (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19 (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20 (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21 (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22 (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23 (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+#define ADC_OFR2_OFFSET2_24 (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSET2_25 (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR2_SSATE_Pos (31U)
+#define ADC_OFR2_SSATE_Msk (0x1U << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
+#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3_Pos (0U)
+#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1 (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2 (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3 (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4 (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5 (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6 (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7 (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8 (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9 (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10 (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11 (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12 (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13 (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14 (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15 (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16 (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17 (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18 (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19 (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20 (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21 (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22 (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23 (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+#define ADC_OFR3_OFFSET3_24 (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSET3_25 (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR3_SSATE_Pos (31U)
+#define ADC_OFR3_SSATE_Msk (0x1U << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
+#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4_Pos (0U)
+#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1 (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2 (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3 (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4 (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5 (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6 (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7 (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8 (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9 (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10 (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11 (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12 (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13 (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14 (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15 (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16 (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17 (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18 (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19 (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20 (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21 (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22 (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23 (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+#define ADC_OFR4_OFFSET4_24 (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSET4_25 (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR4_SSATE_Pos (31U)
+#define ADC_OFR4_SSATE_Msk (0x1U << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
+#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16 (0x10000U << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17 (0x20000U << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18 (0x40000U << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19 (0x80000U << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20 (0x100000U << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21 (0x200000U << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22 (0x400000U << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23 (0x800000U << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24 (0x1000000U << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25 (0x2000000U << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26 (0x4000000U << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27 (0x8000000U << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28 (0x10000000U << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29 (0x20000000U << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30 (0x40000000U << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31 (0x80000000U << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16 (0x10000U << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17 (0x20000U << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18 (0x40000U << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19 (0x80000U << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20 (0x100000U << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21 (0x200000U << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22 (0x400000U << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23 (0x800000U << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24 (0x1000000U << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25 (0x2000000U << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26 (0x4000000U << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27 (0x8000000U << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28 (0x10000000U << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29 (0x20000000U << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30 (0x40000000U << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31 (0x80000000U << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16 (0x10000U << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17 (0x20000U << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18 (0x40000U << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19 (0x80000U << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20 (0x100000U << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21 (0x200000U << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22 (0x400000U << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23 (0x800000U << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24 (0x1000000U << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25 (0x2000000U << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26 (0x4000000U << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27 (0x8000000U << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28 (0x10000000U << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29 (0x20000000U << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30 (0x40000000U << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31 (0x80000000U << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16 (0x10000U << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17 (0x20000U << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18 (0x40000U << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19 (0x80000U << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20 (0x100000U << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21 (0x200000U << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22 (0x400000U << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23 (0x800000U << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24 (0x1000000U << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25 (0x2000000U << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26 (0x4000000U << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27 (0x8000000U << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28 (0x10000000U << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29 (0x20000000U << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30 (0x40000000U << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31 (0x80000000U << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH_Pos (0U)
+#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19 (0x80000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH_Pos (0U)
+#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19 (0x80000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL_Pos (0U)
+#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19 (0x80000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_S_Pos (0U)
+#define ADC_CALFACT_CALFACT_S_Msk (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
+#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1 (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2 (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3 (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4 (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5 (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6 (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7 (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8 (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9 (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_CALFACT_S_10 (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_CALFACT_D_Pos (16U)
+#define ADC_CALFACT_CALFACT_D_Msk (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
+#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1 (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2 (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3 (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4 (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5 (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6 (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7 (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8 (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9 (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT_CALFACT_D_10 (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for ADC_CALFACT2 register ********************/
+#define ADC_CALFACT2_LINCALFACT_Pos (0U)
+#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
+#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_LINCALFACT_0 (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_LINCALFACT_1 (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_LINCALFACT_2 (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_LINCALFACT_3 (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_LINCALFACT_4 (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_LINCALFACT_5 (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_LINCALFACT_6 (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_LINCALFACT_7 (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_LINCALFACT_8 (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_LINCALFACT_9 (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_LINCALFACT_10 (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_LINCALFACT_11 (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_LINCALFACT_12 (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_LINCALFACT_13 (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_LINCALFACT_14 (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_LINCALFACT_15 (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_LINCALFACT_16 (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_LINCALFACT_17 (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_LINCALFACT_18 (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_LINCALFACT_19 (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_LINCALFACT_20 (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_LINCALFACT_21 (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_LINCALFACT_22 (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_LINCALFACT_23 (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_LINCALFACT_24 (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_LINCALFACT_25 (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_LINCALFACT_26 (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_LINCALFACT_27 (0x08000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000001 */
+#define ADC_CALFACT2_LINCALFACT_28 (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_LINCALFACT_29 (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for ADC2_OR - Option Register ********************/
+#define ADC2_OR_VDDCOREEN_Pos (0U)
+#define ADC2_OR_VDDCOREEN_Msk (0x1U << ADC2_OR_VDDCOREEN_Pos) /*!< 0x00000001 */
+#define ADC2_OR_VDDCOREEN ADC2_OR_VDDCOREEN_Msk /*!< ADC2 Option Register - VDDCORE enable bit */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_ADRDY_MST_Pos (0U)
+#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
+#define ADC_CSR_EOSMP_MST_Pos (1U)
+#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
+#define ADC_CSR_EOC_MST_Pos (2U)
+#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
+#define ADC_CSR_EOS_MST_Pos (3U)
+#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
+#define ADC_CSR_OVR_MST_Pos (4U)
+#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
+#define ADC_CSR_JEOC_MST_Pos (5U)
+#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
+#define ADC_CSR_JEOS_MST_Pos (6U)
+#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
+#define ADC_CSR_AWD1_MST_Pos (7U)
+#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC_CSR_AWD2_MST_Pos (8U)
+#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC_CSR_AWD3_MST_Pos (9U)
+#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC_CSR_JQOVF_MST_Pos (10U)
+#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
+#define ADC_CSR_ADRDY_SLV_Pos (16U)
+#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
+#define ADC_CSR_EOSMP_SLV_Pos (17U)
+#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
+#define ADC_CSR_EOC_SLV_Pos (18U)
+#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
+#define ADC_CSR_EOS_SLV_Pos (19U)
+#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
+#define ADC_CSR_OVR_SLV_Pos (20U)
+#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
+#define ADC_CSR_JEOC_SLV_Pos (21U)
+#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
+#define ADC_CSR_JEOS_SLV_Pos (22U)
+#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
+#define ADC_CSR_AWD1_SLV_Pos (23U)
+#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC_CSR_AWD2_SLV_Pos (24U)
+#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC_CSR_AWD3_SLV_Pos (25U)
+#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC_CSR_JQOVF_SLV_Pos (26U)
+#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_DUAL_Pos (0U)
+#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
+#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
+#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos (8U)
+#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
+
+#define ADC_CCR_DAMDF_Pos (14U)
+#define ADC_CCR_DAMDF_Msk (0x3U << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
+#define ADC_CCR_DAMDF_0 (0x1U << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1 (0x2U << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos (16U)
+#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
+#define ADC_CCR_VSENSEEN_Pos (23U)
+#define ADC_CCR_VSENSEEN_Msk (0x1U << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos (24U)
+#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC_CDR_RDATA_MST_Pos (0U)
+#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
+#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos (16U)
+#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
+#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for ADC_CDR2 register ********************/
+#define ADC_CDR2_RDATA_ALT_Pos (0U)
+#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFU << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular Data for dual Mode */
+#define ADC_CDR2_RDATA_ALT_0 (0x00000001U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */
+#define ADC_CDR2_RDATA_ALT_1 (0x00000002U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */
+#define ADC_CDR2_RDATA_ALT_2 (0x00000004U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */
+#define ADC_CDR2_RDATA_ALT_3 (0x00000008U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */
+#define ADC_CDR2_RDATA_ALT_4 (0x00000010U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */
+#define ADC_CDR2_RDATA_ALT_5 (0x00000020U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */
+#define ADC_CDR2_RDATA_ALT_6 (0x00000040U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */
+#define ADC_CDR2_RDATA_ALT_7 (0x00000080U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */
+#define ADC_CDR2_RDATA_ALT_8 (0x00000100U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */
+#define ADC_CDR2_RDATA_ALT_9 (0x00000200U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */
+#define ADC_CDR2_RDATA_ALT_10 (0x00000400U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */
+#define ADC_CDR2_RDATA_ALT_11 (0x00000800U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */
+#define ADC_CDR2_RDATA_ALT_12 (0x00001000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */
+#define ADC_CDR2_RDATA_ALT_13 (0x00002000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */
+#define ADC_CDR2_RDATA_ALT_14 (0x00004000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */
+#define ADC_CDR2_RDATA_ALT_15 (0x00008000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */
+#define ADC_CDR2_RDATA_ALT_16 (0x00010000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */
+#define ADC_CDR2_RDATA_ALT_17 (0x00020000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */
+#define ADC_CDR2_RDATA_ALT_18 (0x00040000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */
+#define ADC_CDR2_RDATA_ALT_19 (0x00080000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */
+#define ADC_CDR2_RDATA_ALT_20 (0x00100000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */
+#define ADC_CDR2_RDATA_ALT_21 (0x00200000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */
+#define ADC_CDR2_RDATA_ALT_22 (0x00400000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */
+#define ADC_CDR2_RDATA_ALT_23 (0x00800000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */
+#define ADC_CDR2_RDATA_ALT_24 (0x01000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */
+#define ADC_CDR2_RDATA_ALT_25 (0x02000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */
+#define ADC_CDR2_RDATA_ALT_26 (0x04000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */
+#define ADC_CDR2_RDATA_ALT_27 (0x08000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */
+#define ADC_CDR2_RDATA_ALT_28 (0x10000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */
+#define ADC_CDR2_RDATA_ALT_29 (0x20000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */
+#define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
+#define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
+
+/******************************************************************************/
+/* */
+/* VREFBUF */
+/* */
+/******************************************************************************/
+/******************* Bit definition for VREFBUF_CSR register ****************/
+#define VREFBUF_CSR_ENVR_Pos (0U)
+#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos (1U)
+#define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
+#define VREFBUF_CSR_VRR_Pos (3U)
+#define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
+#define VREFBUF_CSR_VRS_Pos (4U)
+#define VREFBUF_CSR_VRS_Msk (0x7U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
+
+#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
+#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
+#define VREFBUF_CSR_VRS_OUT2_Msk (0x1U << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
+#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
+#define VREFBUF_CSR_VRS_OUT3_Msk (0x1U << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
+#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
+#define VREFBUF_CSR_VRS_OUT4_Msk (0x3U << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
+
+/******************* Bit definition for VREFBUF_CCR register ****************/
+#define VREFBUF_CCR_TRIM_Pos (0U)
+#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
+
+/******************************************************************************/
+/* */
+/* Flexible Datarate Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/***************** Bit definition for FDCAN_CREL register *******************/
+#define FDCAN_CREL_DAY_Pos (0U)
+#define FDCAN_CREL_DAY_Msk (0xFFU << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
+#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
+#define FDCAN_CREL_MON_Pos (8U)
+#define FDCAN_CREL_MON_Msk (0xFFU << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
+#define FDCAN_CREL_YEAR_Pos (16U)
+#define FDCAN_CREL_YEAR_Msk (0xFU << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
+#define FDCAN_CREL_SUBSTEP_Pos (20U)
+#define FDCAN_CREL_SUBSTEP_Msk (0xFU << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
+#define FDCAN_CREL_STEP_Pos (24U)
+#define FDCAN_CREL_STEP_Msk (0xFU << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
+#define FDCAN_CREL_REL_Pos (28U)
+#define FDCAN_CREL_REL_Msk (0xFU << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
+#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
+
+/***************** Bit definition for FDCAN_ENDN register *******************/
+#define FDCAN_ENDN_ETV_Pos (0U)
+#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFU << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<TEndiannes Test Value */
+
+/***************** Bit definition for FDCAN_DBTP register *******************/
+#define FDCAN_DBTP_DSJW_Pos (0U)
+#define FDCAN_DBTP_DSJW_Msk (0xFU << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
+#define FDCAN_DBTP_DTSEG2_Pos (4U)
+#define FDCAN_DBTP_DTSEG2_Msk (0xFU << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
+#define FDCAN_DBTP_DTSEG1_Pos (8U)
+#define FDCAN_DBTP_DTSEG1_Msk (0x1FU << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
+#define FDCAN_DBTP_DBRP_Pos (16U)
+#define FDCAN_DBTP_DBRP_Msk (0x1FU << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
+#define FDCAN_DBTP_TDC_Pos (23U)
+#define FDCAN_DBTP_TDC_Msk (0x1U << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
+
+/***************** Bit definition for FDCAN_TEST register *******************/
+#define FDCAN_TEST_LBCK_Pos (4U)
+#define FDCAN_TEST_LBCK_Msk (0x1U << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
+#define FDCAN_TEST_TX_Pos (5U)
+#define FDCAN_TEST_TX_Msk (0x3U << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
+#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
+#define FDCAN_TEST_RX_Pos (7U)
+#define FDCAN_TEST_RX_Msk (0x1U << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
+#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
+
+/***************** Bit definition for FDCAN_RWD register ********************/
+#define FDCAN_RWD_WDC_Pos (0U)
+#define FDCAN_RWD_WDC_Msk (0xFFU << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
+#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
+#define FDCAN_RWD_WDV_Pos (8U)
+#define FDCAN_RWD_WDV_Msk (0xFFU << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
+
+/***************** Bit definition for FDCAN_CCCR register ********************/
+#define FDCAN_CCCR_INIT_Pos (0U)
+#define FDCAN_CCCR_INIT_Msk (0x1U << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
+#define FDCAN_CCCR_CCE_Pos (1U)
+#define FDCAN_CCCR_CCE_Msk (0x1U << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
+#define FDCAN_CCCR_ASM_Pos (2U)
+#define FDCAN_CCCR_ASM_Msk (0x1U << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
+#define FDCAN_CCCR_CSA_Pos (3U)
+#define FDCAN_CCCR_CSA_Msk (0x1U << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
+#define FDCAN_CCCR_CSR_Pos (4U)
+#define FDCAN_CCCR_CSR_Msk (0x1U << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
+#define FDCAN_CCCR_MON_Pos (5U)
+#define FDCAN_CCCR_MON_Msk (0x1U << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
+#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
+#define FDCAN_CCCR_DAR_Pos (6U)
+#define FDCAN_CCCR_DAR_Msk (0x1U << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
+#define FDCAN_CCCR_TEST_Pos (7U)
+#define FDCAN_CCCR_TEST_Msk (0x1U << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
+#define FDCAN_CCCR_FDOE_Pos (8U)
+#define FDCAN_CCCR_FDOE_Msk (0x1U << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
+#define FDCAN_CCCR_BRSE_Pos (9U)
+#define FDCAN_CCCR_BRSE_Msk (0x1U << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
+#define FDCAN_CCCR_PXHD_Pos (12U)
+#define FDCAN_CCCR_PXHD_Msk (0x1U << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
+#define FDCAN_CCCR_EFBI_Pos (13U)
+#define FDCAN_CCCR_EFBI_Msk (0x1U << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
+#define FDCAN_CCCR_TXP_Pos (14U)
+#define FDCAN_CCCR_TXP_Msk (0x1U << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
+#define FDCAN_CCCR_NISO_Pos (15U)
+#define FDCAN_CCCR_NISO_Msk (0x1U << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
+
+/***************** Bit definition for FDCAN_NBTP register ********************/
+#define FDCAN_NBTP_NTSEG2_Pos (0U)
+#define FDCAN_NBTP_NTSEG2_Msk (0x7FU << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
+#define FDCAN_NBTP_NTSEG1_Pos (8U)
+#define FDCAN_NBTP_NTSEG1_Msk (0xFFU << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos (16U)
+#define FDCAN_NBTP_NBRP_Msk (0x1FFU << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
+#define FDCAN_NBTP_NSJW_Pos (25U)
+#define FDCAN_NBTP_NSJW_Msk (0x7FU << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
+
+/***************** Bit definition for FDCAN_TSCC register ********************/
+#define FDCAN_TSCC_TSS_Pos (0U)
+#define FDCAN_TSCC_TSS_Msk (0x3U << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
+#define FDCAN_TSCC_TCP_Pos (16U)
+#define FDCAN_TSCC_TCP_Msk (0xFU << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
+
+/***************** Bit definition for FDCAN_TSCV register ********************/
+#define FDCAN_TSCV_TSC_Pos (0U)
+#define FDCAN_TSCV_TSC_Msk (0xFFFFU << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
+
+/***************** Bit definition for FDCAN_TOCC register ********************/
+#define FDCAN_TOCC_ETOC_Pos (0U)
+#define FDCAN_TOCC_ETOC_Msk (0x1U << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
+#define FDCAN_TOCC_TOS_Pos (1U)
+#define FDCAN_TOCC_TOS_Msk (0x3U << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
+#define FDCAN_TOCC_TOP_Pos (16U)
+#define FDCAN_TOCC_TOP_Msk (0xFFFFU << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
+
+/***************** Bit definition for FDCAN_TOCV register ********************/
+#define FDCAN_TOCV_TOC_Pos (0U)
+#define FDCAN_TOCV_TOC_Msk (0xFFFFU << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
+
+/***************** Bit definition for FDCAN_ECR register *********************/
+#define FDCAN_ECR_TEC_Pos (0U)
+#define FDCAN_ECR_TEC_Msk (0xFFU << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
+#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
+#define FDCAN_ECR_REC_Pos (8U)
+#define FDCAN_ECR_REC_Msk (0x7FU << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
+#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
+#define FDCAN_ECR_RP_Pos (15U)
+#define FDCAN_ECR_RP_Msk (0x1U << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
+#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
+#define FDCAN_ECR_CEL_Pos (16U)
+#define FDCAN_ECR_CEL_Msk (0xFFU << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
+
+/***************** Bit definition for FDCAN_PSR register *********************/
+#define FDCAN_PSR_LEC_Pos (0U)
+#define FDCAN_PSR_LEC_Msk (0x7U << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
+#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
+#define FDCAN_PSR_ACT_Pos (3U)
+#define FDCAN_PSR_ACT_Msk (0x3U << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
+#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
+#define FDCAN_PSR_EP_Pos (5U)
+#define FDCAN_PSR_EP_Msk (0x1U << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
+#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
+#define FDCAN_PSR_EW_Pos (6U)
+#define FDCAN_PSR_EW_Msk (0x1U << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
+#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
+#define FDCAN_PSR_BO_Pos (7U)
+#define FDCAN_PSR_BO_Msk (0x1U << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
+#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
+#define FDCAN_PSR_DLEC_Pos (8U)
+#define FDCAN_PSR_DLEC_Msk (0x7U << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
+#define FDCAN_PSR_RESI_Pos (11U)
+#define FDCAN_PSR_RESI_Msk (0x1U << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
+#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
+#define FDCAN_PSR_RBRS_Pos (12U)
+#define FDCAN_PSR_RBRS_Msk (0x1U << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
+#define FDCAN_PSR_REDL_Pos (13U)
+#define FDCAN_PSR_REDL_Msk (0x1U << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
+#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
+#define FDCAN_PSR_PXE_Pos (14U)
+#define FDCAN_PSR_PXE_Msk (0x1U << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
+#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
+#define FDCAN_PSR_TDCV_Pos (16U)
+#define FDCAN_PSR_TDCV_Msk (0x7FU << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
+
+/***************** Bit definition for FDCAN_TDCR register ********************/
+#define FDCAN_TDCR_TDCF_Pos (0U)
+#define FDCAN_TDCR_TDCF_Msk (0x7FU << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
+#define FDCAN_TDCR_TDCO_Pos (8U)
+#define FDCAN_TDCR_TDCO_Msk (0x7FU << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
+
+/***************** Bit definition for FDCAN_IR register **********************/
+#define FDCAN_IR_RF0N_Pos (0U)
+#define FDCAN_IR_RF0N_Msk (0x1U << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
+#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
+#define FDCAN_IR_RF0W_Pos (1U)
+#define FDCAN_IR_RF0W_Msk (0x1U << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
+#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
+#define FDCAN_IR_RF0F_Pos (2U)
+#define FDCAN_IR_RF0F_Msk (0x1U << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
+#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
+#define FDCAN_IR_RF0L_Pos (3U)
+#define FDCAN_IR_RF0L_Msk (0x1U << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
+#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
+#define FDCAN_IR_RF1N_Pos (4U)
+#define FDCAN_IR_RF1N_Msk (0x1U << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
+#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
+#define FDCAN_IR_RF1W_Pos (5U)
+#define FDCAN_IR_RF1W_Msk (0x1U << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
+#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
+#define FDCAN_IR_RF1F_Pos (6U)
+#define FDCAN_IR_RF1F_Msk (0x1U << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
+#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
+#define FDCAN_IR_RF1L_Pos (7U)
+#define FDCAN_IR_RF1L_Msk (0x1U << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
+#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
+#define FDCAN_IR_HPM_Pos (8U)
+#define FDCAN_IR_HPM_Msk (0x1U << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
+#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
+#define FDCAN_IR_TC_Pos (9U)
+#define FDCAN_IR_TC_Msk (0x1U << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
+#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
+#define FDCAN_IR_TCF_Pos (10U)
+#define FDCAN_IR_TCF_Msk (0x1U << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
+#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
+#define FDCAN_IR_TFE_Pos (11U)
+#define FDCAN_IR_TFE_Msk (0x1U << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
+#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
+#define FDCAN_IR_TEFN_Pos (12U)
+#define FDCAN_IR_TEFN_Msk (0x1U << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
+#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
+#define FDCAN_IR_TEFW_Pos (13U)
+#define FDCAN_IR_TEFW_Msk (0x1U << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
+#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
+#define FDCAN_IR_TEFF_Pos (14U)
+#define FDCAN_IR_TEFF_Msk (0x1U << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
+#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
+#define FDCAN_IR_TEFL_Pos (15U)
+#define FDCAN_IR_TEFL_Msk (0x1U << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
+#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
+#define FDCAN_IR_TSW_Pos (16U)
+#define FDCAN_IR_TSW_Msk (0x1U << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
+#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
+#define FDCAN_IR_MRAF_Pos (17U)
+#define FDCAN_IR_MRAF_Msk (0x1U << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
+#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
+#define FDCAN_IR_TOO_Pos (18U)
+#define FDCAN_IR_TOO_Msk (0x1U << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
+#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
+#define FDCAN_IR_DRX_Pos (19U)
+#define FDCAN_IR_DRX_Msk (0x1U << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
+#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
+#define FDCAN_IR_ELO_Pos (22U)
+#define FDCAN_IR_ELO_Msk (0x1U << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
+#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
+#define FDCAN_IR_EP_Pos (23U)
+#define FDCAN_IR_EP_Msk (0x1U << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
+#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
+#define FDCAN_IR_EW_Pos (24U)
+#define FDCAN_IR_EW_Msk (0x1U << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
+#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
+#define FDCAN_IR_BO_Pos (25U)
+#define FDCAN_IR_BO_Msk (0x1U << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
+#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
+#define FDCAN_IR_WDI_Pos (26U)
+#define FDCAN_IR_WDI_Msk (0x1U << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
+#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
+#define FDCAN_IR_PEA_Pos (27U)
+#define FDCAN_IR_PEA_Msk (0x1U << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
+#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
+#define FDCAN_IR_PED_Pos (28U)
+#define FDCAN_IR_PED_Msk (0x1U << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
+#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
+#define FDCAN_IR_ARA_Pos (29U)
+#define FDCAN_IR_ARA_Msk (0x1U << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
+#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
+
+/***************** Bit definition for FDCAN_IE register **********************/
+#define FDCAN_IE_RF0NE_Pos (0U)
+#define FDCAN_IE_RF0NE_Msk (0x1U << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
+#define FDCAN_IE_RF0WE_Pos (1U)
+#define FDCAN_IE_RF0WE_Msk (0x1U << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
+#define FDCAN_IE_RF0FE_Pos (2U)
+#define FDCAN_IE_RF0FE_Msk (0x1U << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
+#define FDCAN_IE_RF0LE_Pos (3U)
+#define FDCAN_IE_RF0LE_Msk (0x1U << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
+#define FDCAN_IE_RF1NE_Pos (4U)
+#define FDCAN_IE_RF1NE_Msk (0x1U << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
+#define FDCAN_IE_RF1WE_Pos (5U)
+#define FDCAN_IE_RF1WE_Msk (0x1U << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
+#define FDCAN_IE_RF1FE_Pos (6U)
+#define FDCAN_IE_RF1FE_Msk (0x1U << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
+#define FDCAN_IE_RF1LE_Pos (7U)
+#define FDCAN_IE_RF1LE_Msk (0x1U << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
+#define FDCAN_IE_HPME_Pos (8U)
+#define FDCAN_IE_HPME_Msk (0x1U << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
+#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
+#define FDCAN_IE_TCE_Pos (9U)
+#define FDCAN_IE_TCE_Msk (0x1U << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
+#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
+#define FDCAN_IE_TCFE_Pos (10U)
+#define FDCAN_IE_TCFE_Msk (0x1U << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
+#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
+#define FDCAN_IE_TFEE_Pos (11U)
+#define FDCAN_IE_TFEE_Msk (0x1U << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
+#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
+#define FDCAN_IE_TEFNE_Pos (12U)
+#define FDCAN_IE_TEFNE_Msk (0x1U << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
+#define FDCAN_IE_TEFWE_Pos (13U)
+#define FDCAN_IE_TEFWE_Msk (0x1U << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
+#define FDCAN_IE_TEFFE_Pos (14U)
+#define FDCAN_IE_TEFFE_Msk (0x1U << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
+#define FDCAN_IE_TEFLE_Pos (15U)
+#define FDCAN_IE_TEFLE_Msk (0x1U << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
+#define FDCAN_IE_TSWE_Pos (16U)
+#define FDCAN_IE_TSWE_Msk (0x1U << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
+#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
+#define FDCAN_IE_MRAFE_Pos (17U)
+#define FDCAN_IE_MRAFE_Msk (0x1U << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
+#define FDCAN_IE_TOOE_Pos (18U)
+#define FDCAN_IE_TOOE_Msk (0x1U << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
+#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
+#define FDCAN_IE_DRXE_Pos (19U)
+#define FDCAN_IE_DRXE_Msk (0x1U << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
+#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_ELOE_Pos (22U)
+#define FDCAN_IE_ELOE_Msk (0x1U << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
+#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
+#define FDCAN_IE_EPE_Pos (23U)
+#define FDCAN_IE_EPE_Msk (0x1U << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
+#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
+#define FDCAN_IE_EWE_Pos (24U)
+#define FDCAN_IE_EWE_Msk (0x1U << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
+#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
+#define FDCAN_IE_BOE_Pos (25U)
+#define FDCAN_IE_BOE_Msk (0x1U << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
+#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
+#define FDCAN_IE_WDIE_Pos (26U)
+#define FDCAN_IE_WDIE_Msk (0x1U << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
+#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
+#define FDCAN_IE_PEAE_Pos (27U)
+#define FDCAN_IE_PEAE_Msk (0x1U << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
+#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
+#define FDCAN_IE_PEDE_Pos (28U)
+#define FDCAN_IE_PEDE_Msk (0x1U << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
+#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
+#define FDCAN_IE_ARAE_Pos (29U)
+#define FDCAN_IE_ARAE_Msk (0x1U << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
+#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
+
+/***************** Bit definition for FDCAN_ILS register **********************/
+#define FDCAN_ILS_RF0NL_Pos (0U)
+#define FDCAN_ILS_RF0NL_Msk (0x1U << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
+#define FDCAN_ILS_RF0WL_Pos (1U)
+#define FDCAN_ILS_RF0WL_Msk (0x1U << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
+#define FDCAN_ILS_RF0FL_Pos (2U)
+#define FDCAN_ILS_RF0FL_Msk (0x1U << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
+#define FDCAN_ILS_RF0LL_Pos (3U)
+#define FDCAN_ILS_RF0LL_Msk (0x1U << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
+#define FDCAN_ILS_RF1NL_Pos (4U)
+#define FDCAN_ILS_RF1NL_Msk (0x1U << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
+#define FDCAN_ILS_RF1WL_Pos (5U)
+#define FDCAN_ILS_RF1WL_Msk (0x1U << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
+#define FDCAN_ILS_RF1FL_Pos (6U)
+#define FDCAN_ILS_RF1FL_Msk (0x1U << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
+#define FDCAN_ILS_RF1LL_Pos (7U)
+#define FDCAN_ILS_RF1LL_Msk (0x1U << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
+#define FDCAN_ILS_HPML_Pos (8U)
+#define FDCAN_ILS_HPML_Msk (0x1U << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
+#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
+#define FDCAN_ILS_TCL_Pos (9U)
+#define FDCAN_ILS_TCL_Msk (0x1U << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
+#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
+#define FDCAN_ILS_TCFL_Pos (10U)
+#define FDCAN_ILS_TCFL_Msk (0x1U << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
+#define FDCAN_ILS_TFEL_Pos (11U)
+#define FDCAN_ILS_TFEL_Msk (0x1U << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
+#define FDCAN_ILS_TEFNL_Pos (12U)
+#define FDCAN_ILS_TEFNL_Msk (0x1U << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
+#define FDCAN_ILS_TEFWL_Pos (13U)
+#define FDCAN_ILS_TEFWL_Msk (0x1U << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
+#define FDCAN_ILS_TEFFL_Pos (14U)
+#define FDCAN_ILS_TEFFL_Msk (0x1U << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
+#define FDCAN_ILS_TEFLL_Pos (15U)
+#define FDCAN_ILS_TEFLL_Msk (0x1U << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
+#define FDCAN_ILS_TSWL_Pos (16U)
+#define FDCAN_ILS_TSWL_Msk (0x1U << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
+#define FDCAN_ILS_MRAFL_Pos (17U)
+#define FDCAN_ILS_MRAFL_Msk (0x1U << FDCAN_ILS_MRAFL_Pos) /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFL FDCAN_ILS_MRAFL_Msk /*!<Message RAM Access Failure Line */
+#define FDCAN_ILS_TOOL_Pos (18U)
+#define FDCAN_ILS_TOOL_Msk (0x1U << FDCAN_ILS_TOOL_Pos) /*!< 0x00040000 */
+#define FDCAN_ILS_TOOL FDCAN_ILS_TOOL_Msk /*!<Timeout Occurred Line */
+#define FDCAN_ILS_DRXL_Pos (19U)
+#define FDCAN_ILS_DRXL_Msk (0x1U << FDCAN_ILS_DRXL_Pos) /*!< 0x00080000 */
+#define FDCAN_ILS_DRXL FDCAN_ILS_DRXL_Msk /*!<Message stored to Dedicated Rx Buffer Line */
+#define FDCAN_ILS_ELOL_Pos (22U)
+#define FDCAN_ILS_ELOL_Msk (0x1U << FDCAN_ILS_ELOL_Pos) /*!< 0x00400000 */
+#define FDCAN_ILS_ELOL FDCAN_ILS_ELOL_Msk /*!<Error Logging Overflow Line */
+#define FDCAN_ILS_EPL_Pos (23U)
+#define FDCAN_ILS_EPL_Msk (0x1U << FDCAN_ILS_EPL_Pos) /*!< 0x00800000 */
+#define FDCAN_ILS_EPL FDCAN_ILS_EPL_Msk /*!<Error Passive Line */
+#define FDCAN_ILS_EWL_Pos (24U)
+#define FDCAN_ILS_EWL_Msk (0x1U << FDCAN_ILS_EWL_Pos) /*!< 0x01000000 */
+#define FDCAN_ILS_EWL FDCAN_ILS_EWL_Msk /*!<Warning Status Line */
+#define FDCAN_ILS_BOL_Pos (25U)
+#define FDCAN_ILS_BOL_Msk (0x1U << FDCAN_ILS_BOL_Pos) /*!< 0x02000000 */
+#define FDCAN_ILS_BOL FDCAN_ILS_BOL_Msk /*!<Bus_Off Status Line */
+#define FDCAN_ILS_WDIL_Pos (26U)
+#define FDCAN_ILS_WDIL_Msk (0x1U << FDCAN_ILS_WDIL_Pos) /*!< 0x04000000 */
+#define FDCAN_ILS_WDIL FDCAN_ILS_WDIL_Msk /*!<Watchdog Interrupt Line */
+#define FDCAN_ILS_PEAL_Pos (27U)
+#define FDCAN_ILS_PEAL_Msk (0x1U << FDCAN_ILS_PEAL_Pos) /*!< 0x08000000 */
+#define FDCAN_ILS_PEAL FDCAN_ILS_PEAL_Msk /*!<Protocol Error in Arbitration Phase Line */
+#define FDCAN_ILS_PEDL_Pos (28U)
+#define FDCAN_ILS_PEDL_Msk (0x1U << FDCAN_ILS_PEDL_Pos) /*!< 0x10000000 */
+#define FDCAN_ILS_PEDL FDCAN_ILS_PEDL_Msk /*!<Protocol Error in Data Phase Line */
+#define FDCAN_ILS_ARAL_Pos (29U)
+#define FDCAN_ILS_ARAL_Msk (0x1U << FDCAN_ILS_ARAL_Pos) /*!< 0x20000000 */
+#define FDCAN_ILS_ARAL FDCAN_ILS_ARAL_Msk /*!<Access to Reserved Address Line */
+
+/** @defgroup FDCAN_Interrupt_Group FDCAN interrupt group
+ * @{
+ */
+#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RF0NL|FDCAN_ILS_RF0FL|FDCAN_ILS_RF0LL|FDCAN_ILS_RF0WL
+ /*!< RX FIFO 0 Interrupts Group:
+ RF0LL: Rx FIFO 0 Message Lost
+ RF0FL: Rx FIFO 0 is Full
+ RF0NL: Rx FIFO 0 Has New Message */
+#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RF1NL|FDCAN_ILS_RF1FL|FDCAN_ILS_RF1LL|FDCAN_ILS_RF1WL
+ /*!< RX FIFO 1 Interrupts Group:
+ RF1LL: Rx FIFO 1 Message Lost
+ RF1FL: Rx FIFO 1 is Full
+ RF1NL: Rx FIFO 1 Has New Message */
+#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_HPML|FDCAN_ILS_TCL|FDCAN_ILS_TCFL
+ /*!< Status Message Interrupts Group:
+ TCFL: Transmission Cancellation Finished
+ TCL: Transmission Completed
+ HPML: High Priority Message */
+#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFEL|FDCAN_ILS_TEFNL|FDCAN_ILS_TEFWL|FDCAN_ILS_TEFLL
+ /*!< TX FIFO Error Interrupts Group:
+ TEFLL: Tx Event FIFO Element Lost
+ TEFFL: Tx Event FIFO Full
+ TEFNL: Tx Event FIFO New Entry
+ TFEL: Tx FIFO Empty Interrupt Line */
+#define FDCAN_IT_GROUP_MISC FDCAN_ILS_TSWL|FDCAN_ILS_MRAFL|FDCAN_ILS_TOOL|FDCAN_ILS_DRXL
+ /*!< Misc. Interrupts Group:
+ TOOL: Timeout Occurred
+ MRAFL: Message RAM Access Failure
+ TSWL: Timestamp Wraparound */
+#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_ELOL|FDCAN_ILS_EPL
+ /*!< Bit and Line Error Interrupts Group:
+ EPL: Error Passive
+ ELOL: Error Logging Overflow */
+#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_EWL|FDCAN_ILS_BOL|FDCAN_ILS_WDIL|FDCAN_ILS_PEAL|FDCAN_ILS_PEDL|FDCAN_ILS_ARAL
+ /*!< Protocol Error Group:
+ ARAL: Access to Reserved Address Line
+ PEDL: Protocol Error in Data Phase Line
+ PEAL: Protocol Error in Arbitration Phase Line
+ WDIL: Watchdog Interrupt Line
+ BOL: Bus_Off Status
+ EWL: Warning Status */
+/**
+ * @}
+ */
+
+/***************** Bit definition for FDCAN_ILE register **********************/
+#define FDCAN_ILE_EINT0_Pos (0U)
+#define FDCAN_ILE_EINT0_Msk (0x1U << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
+#define FDCAN_ILE_EINT1_Pos (1U)
+#define FDCAN_ILE_EINT1_Msk (0x1U << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
+
+/***************** Bit definition for FDCAN_GFC register **********************/
+#define FDCAN_GFC_RRFE_Pos (0U)
+#define FDCAN_GFC_RRFE_Msk (0x1U << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
+#define FDCAN_GFC_RRFS_Pos (1U)
+#define FDCAN_GFC_RRFS_Msk (0x1U << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
+#define FDCAN_GFC_ANFE_Pos (2U)
+#define FDCAN_GFC_ANFE_Msk (0x3U << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
+#define FDCAN_GFC_ANFS_Pos (4U)
+#define FDCAN_GFC_ANFS_Msk (0x3U << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
+
+/***************** Bit definition for FDCAN_SIDFC register ********************/
+#define FDCAN_SIDFC_FLSSA_Pos (2U)
+#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFU << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
+#define FDCAN_SIDFC_LSS_Pos (16U)
+#define FDCAN_SIDFC_LSS_Msk (0xFFU << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
+
+/***************** Bit definition for FDCAN_XIDFC register ********************/
+#define FDCAN_XIDFC_FLESA_Pos (2U)
+#define FDCAN_XIDFC_FLESA_Msk (0x3FFFU << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
+#define FDCAN_XIDFC_LSE_Pos (16U)
+#define FDCAN_XIDFC_LSE_Msk (0xFFU << FDCAN_XIDFC_LSE_Pos) /*!< 0x00FF0000 */
+#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
+
+/***************** Bit definition for FDCAN_XIDAM register ********************/
+#define FDCAN_XIDAM_EIDM_Pos (0U)
+#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFU << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
+
+/***************** Bit definition for FDCAN_HPMS register *********************/
+#define FDCAN_HPMS_BIDX_Pos (0U)
+#define FDCAN_HPMS_BIDX_Msk (0x3FU << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
+#define FDCAN_HPMS_MSI_Pos (6U)
+#define FDCAN_HPMS_MSI_Msk (0x3U << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
+#define FDCAN_HPMS_FIDX_Pos (8U)
+#define FDCAN_HPMS_FIDX_Msk (0x7FU << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
+#define FDCAN_HPMS_FLST_Pos (15U)
+#define FDCAN_HPMS_FLST_Msk (0x1U << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
+
+/***************** Bit definition for FDCAN_NDAT1 register ********************/
+#define FDCAN_NDAT1_ND0_Pos (0U)
+#define FDCAN_NDAT1_ND0_Msk (0x1U << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
+#define FDCAN_NDAT1_ND1_Pos (1U)
+#define FDCAN_NDAT1_ND1_Msk (0x1U << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
+#define FDCAN_NDAT1_ND2_Pos (2U)
+#define FDCAN_NDAT1_ND2_Msk (0x1U << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
+#define FDCAN_NDAT1_ND3_Pos (3U)
+#define FDCAN_NDAT1_ND3_Msk (0x1U << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
+#define FDCAN_NDAT1_ND4_Pos (4U)
+#define FDCAN_NDAT1_ND4_Msk (0x1U << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
+#define FDCAN_NDAT1_ND5_Pos (5U)
+#define FDCAN_NDAT1_ND5_Msk (0x1U << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
+#define FDCAN_NDAT1_ND6_Pos (6U)
+#define FDCAN_NDAT1_ND6_Msk (0x1U << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
+#define FDCAN_NDAT1_ND7_Pos (7U)
+#define FDCAN_NDAT1_ND7_Msk (0x1U << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
+#define FDCAN_NDAT1_ND8_Pos (8U)
+#define FDCAN_NDAT1_ND8_Msk (0x1U << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
+#define FDCAN_NDAT1_ND9_Pos (9U)
+#define FDCAN_NDAT1_ND9_Msk (0x1U << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
+#define FDCAN_NDAT1_ND10_Pos (10U)
+#define FDCAN_NDAT1_ND10_Msk (0x1U << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
+#define FDCAN_NDAT1_ND11_Pos (11U)
+#define FDCAN_NDAT1_ND11_Msk (0x1U << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
+#define FDCAN_NDAT1_ND12_Pos (12U)
+#define FDCAN_NDAT1_ND12_Msk (0x1U << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
+#define FDCAN_NDAT1_ND13_Pos (13U)
+#define FDCAN_NDAT1_ND13_Msk (0x1U << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
+#define FDCAN_NDAT1_ND14_Pos (14U)
+#define FDCAN_NDAT1_ND14_Msk (0x1U << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
+#define FDCAN_NDAT1_ND15_Pos (15U)
+#define FDCAN_NDAT1_ND15_Msk (0x1U << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
+#define FDCAN_NDAT1_ND16_Pos (16U)
+#define FDCAN_NDAT1_ND16_Msk (0x1U << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
+#define FDCAN_NDAT1_ND17_Pos (17U)
+#define FDCAN_NDAT1_ND17_Msk (0x1U << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
+#define FDCAN_NDAT1_ND18_Pos (18U)
+#define FDCAN_NDAT1_ND18_Msk (0x1U << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
+#define FDCAN_NDAT1_ND19_Pos (19U)
+#define FDCAN_NDAT1_ND19_Msk (0x1U << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
+#define FDCAN_NDAT1_ND20_Pos (20U)
+#define FDCAN_NDAT1_ND20_Msk (0x1U << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
+#define FDCAN_NDAT1_ND21_Pos (21U)
+#define FDCAN_NDAT1_ND21_Msk (0x1U << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
+#define FDCAN_NDAT1_ND22_Pos (22U)
+#define FDCAN_NDAT1_ND22_Msk (0x1U << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
+#define FDCAN_NDAT1_ND23_Pos (23U)
+#define FDCAN_NDAT1_ND23_Msk (0x1U << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
+#define FDCAN_NDAT1_ND24_Pos (24U)
+#define FDCAN_NDAT1_ND24_Msk (0x1U << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
+#define FDCAN_NDAT1_ND25_Pos (25U)
+#define FDCAN_NDAT1_ND25_Msk (0x1U << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
+#define FDCAN_NDAT1_ND26_Pos (26U)
+#define FDCAN_NDAT1_ND26_Msk (0x1U << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
+#define FDCAN_NDAT1_ND27_Pos (27U)
+#define FDCAN_NDAT1_ND27_Msk (0x1U << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
+#define FDCAN_NDAT1_ND28_Pos (28U)
+#define FDCAN_NDAT1_ND28_Msk (0x1U << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
+#define FDCAN_NDAT1_ND29_Pos (29U)
+#define FDCAN_NDAT1_ND29_Msk (0x1U << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
+#define FDCAN_NDAT1_ND30_Pos (30U)
+#define FDCAN_NDAT1_ND30_Msk (0x1U << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
+#define FDCAN_NDAT1_ND31_Pos (31U)
+#define FDCAN_NDAT1_ND31_Msk (0x1U << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
+
+/***************** Bit definition for FDCAN_NDAT2 register ********************/
+#define FDCAN_NDAT2_ND32_Pos (0U)
+#define FDCAN_NDAT2_ND32_Msk (0x1U << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
+#define FDCAN_NDAT2_ND33_Pos (1U)
+#define FDCAN_NDAT2_ND33_Msk (0x1U << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
+#define FDCAN_NDAT2_ND34_Pos (2U)
+#define FDCAN_NDAT2_ND34_Msk (0x1U << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
+#define FDCAN_NDAT2_ND35_Pos (3U)
+#define FDCAN_NDAT2_ND35_Msk (0x1U << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
+#define FDCAN_NDAT2_ND36_Pos (4U)
+#define FDCAN_NDAT2_ND36_Msk (0x1U << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
+#define FDCAN_NDAT2_ND37_Pos (5U)
+#define FDCAN_NDAT2_ND37_Msk (0x1U << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
+#define FDCAN_NDAT2_ND38_Pos (6U)
+#define FDCAN_NDAT2_ND38_Msk (0x1U << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
+#define FDCAN_NDAT2_ND39_Pos (7U)
+#define FDCAN_NDAT2_ND39_Msk (0x1U << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
+#define FDCAN_NDAT2_ND40_Pos (8U)
+#define FDCAN_NDAT2_ND40_Msk (0x1U << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
+#define FDCAN_NDAT2_ND41_Pos (9U)
+#define FDCAN_NDAT2_ND41_Msk (0x1U << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
+#define FDCAN_NDAT2_ND42_Pos (10U)
+#define FDCAN_NDAT2_ND42_Msk (0x1U << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
+#define FDCAN_NDAT2_ND43_Pos (11U)
+#define FDCAN_NDAT2_ND43_Msk (0x1U << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
+#define FDCAN_NDAT2_ND44_Pos (12U)
+#define FDCAN_NDAT2_ND44_Msk (0x1U << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
+#define FDCAN_NDAT2_ND45_Pos (13U)
+#define FDCAN_NDAT2_ND45_Msk (0x1U << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
+#define FDCAN_NDAT2_ND46_Pos (14U)
+#define FDCAN_NDAT2_ND46_Msk (0x1U << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
+#define FDCAN_NDAT2_ND47_Pos (15U)
+#define FDCAN_NDAT2_ND47_Msk (0x1U << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
+#define FDCAN_NDAT2_ND48_Pos (16U)
+#define FDCAN_NDAT2_ND48_Msk (0x1U << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
+#define FDCAN_NDAT2_ND49_Pos (17U)
+#define FDCAN_NDAT2_ND49_Msk (0x1U << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
+#define FDCAN_NDAT2_ND50_Pos (18U)
+#define FDCAN_NDAT2_ND50_Msk (0x1U << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
+#define FDCAN_NDAT2_ND51_Pos (19U)
+#define FDCAN_NDAT2_ND51_Msk (0x1U << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
+#define FDCAN_NDAT2_ND52_Pos (20U)
+#define FDCAN_NDAT2_ND52_Msk (0x1U << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
+#define FDCAN_NDAT2_ND53_Pos (21U)
+#define FDCAN_NDAT2_ND53_Msk (0x1U << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
+#define FDCAN_NDAT2_ND54_Pos (22U)
+#define FDCAN_NDAT2_ND54_Msk (0x1U << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
+#define FDCAN_NDAT2_ND55_Pos (23U)
+#define FDCAN_NDAT2_ND55_Msk (0x1U << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
+#define FDCAN_NDAT2_ND56_Pos (24U)
+#define FDCAN_NDAT2_ND56_Msk (0x1U << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
+#define FDCAN_NDAT2_ND57_Pos (25U)
+#define FDCAN_NDAT2_ND57_Msk (0x1U << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
+#define FDCAN_NDAT2_ND58_Pos (26U)
+#define FDCAN_NDAT2_ND58_Msk (0x1U << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
+#define FDCAN_NDAT2_ND59_Pos (27U)
+#define FDCAN_NDAT2_ND59_Msk (0x1U << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
+#define FDCAN_NDAT2_ND60_Pos (28U)
+#define FDCAN_NDAT2_ND60_Msk (0x1U << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
+#define FDCAN_NDAT2_ND61_Pos (29U)
+#define FDCAN_NDAT2_ND61_Msk (0x1U << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
+#define FDCAN_NDAT2_ND62_Pos (30U)
+#define FDCAN_NDAT2_ND62_Msk (0x1U << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
+#define FDCAN_NDAT2_ND63_Pos (31U)
+#define FDCAN_NDAT2_ND63_Msk (0x1U << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
+
+/***************** Bit definition for FDCAN_RXF0C register ********************/
+#define FDCAN_RXF0C_F0SA_Pos (2U)
+#define FDCAN_RXF0C_F0SA_Msk (0x3FFFU << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
+#define FDCAN_RXF0C_F0S_Pos (16U)
+#define FDCAN_RXF0C_F0S_Msk (0x7FU << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
+#define FDCAN_RXF0C_F0WM_Pos (24U)
+#define FDCAN_RXF0C_F0WM_Msk (0x7FU << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
+#define FDCAN_RXF0C_F0OM_Pos (31U)
+#define FDCAN_RXF0C_F0OM_Msk (0x1U << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
+
+/***************** Bit definition for FDCAN_RXF0S register ********************/
+#define FDCAN_RXF0S_F0FL_Pos (0U)
+#define FDCAN_RXF0S_F0FL_Msk (0x7FU << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
+#define FDCAN_RXF0S_F0GI_Pos (8U)
+#define FDCAN_RXF0S_F0GI_Msk (0x3FU << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
+#define FDCAN_RXF0S_F0PI_Pos (16U)
+#define FDCAN_RXF0S_F0PI_Msk (0x3FU << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
+#define FDCAN_RXF0S_F0F_Pos (24U)
+#define FDCAN_RXF0S_F0F_Msk (0x1U << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
+#define FDCAN_RXF0S_RF0L_Pos (25U)
+#define FDCAN_RXF0S_RF0L_Msk (0x1U << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
+
+/***************** Bit definition for FDCAN_RXF0A register ********************/
+#define FDCAN_RXF0A_F0AI_Pos (0U)
+#define FDCAN_RXF0A_F0AI_Msk (0x3FU << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
+
+/***************** Bit definition for FDCAN_RXBC register ********************/
+#define FDCAN_RXBC_RBSA_Pos (2U)
+#define FDCAN_RXBC_RBSA_Msk (0x3FFFU << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
+
+/***************** Bit definition for FDCAN_RXF1C register ********************/
+#define FDCAN_RXF1C_F1SA_Pos (2U)
+#define FDCAN_RXF1C_F1SA_Msk (0x3FFFU << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
+#define FDCAN_RXF1C_F1S_Pos (16U)
+#define FDCAN_RXF1C_F1S_Msk (0x7FU << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
+#define FDCAN_RXF1C_F1WM_Pos (24U)
+#define FDCAN_RXF1C_F1WM_Msk (0x7FU << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
+#define FDCAN_RXF1C_F1OM_Pos (31U)
+#define FDCAN_RXF1C_F1OM_Msk (0x1U << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
+
+/***************** Bit definition for FDCAN_RXF1S register ********************/
+#define FDCAN_RXF1S_F1FL_Pos (0U)
+#define FDCAN_RXF1S_F1FL_Msk (0x7FU << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
+#define FDCAN_RXF1S_F1GI_Pos (8U)
+#define FDCAN_RXF1S_F1GI_Msk (0x3FU << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
+#define FDCAN_RXF1S_F1PI_Pos (16U)
+#define FDCAN_RXF1S_F1PI_Msk (0x3FU << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
+#define FDCAN_RXF1S_F1F_Pos (24U)
+#define FDCAN_RXF1S_F1F_Msk (0x1U << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
+#define FDCAN_RXF1S_RF1L_Pos (25U)
+#define FDCAN_RXF1S_RF1L_Msk (0x1U << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
+#define FDCAN_RXF1S_DMS_Pos (30U)
+#define FDCAN_RXF1S_DMS_Msk (0x3U << FDCAN_RXF1S_DMS_Pos) /*!< 0xC0000000 */
+#define FDCAN_RXF1S_DMS FDCAN_RXF1S_DMS_Msk /*!<Debug Message Status */
+
+/***************** Bit definition for FDCAN_RXF1A register ********************/
+#define FDCAN_RXF1A_F1AI_Pos (0U)
+#define FDCAN_RXF1A_F1AI_Msk (0x3FU << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
+
+/***************** Bit definition for FDCAN_RXESC register ********************/
+#define FDCAN_RXESC_F0DS_Pos (0U)
+#define FDCAN_RXESC_F0DS_Msk (0x7U << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
+#define FDCAN_RXESC_F1DS_Pos (4U)
+#define FDCAN_RXESC_F1DS_Msk (0x7U << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
+#define FDCAN_RXESC_RBDS_Pos (8U)
+#define FDCAN_RXESC_RBDS_Msk (0x7U << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
+
+/***************** Bit definition for FDCAN_TXBC register *********************/
+#define FDCAN_TXBC_TBSA_Pos (2U)
+#define FDCAN_TXBC_TBSA_Msk (0x3FFFU << FDCAN_TXBC_TBSA_Pos) /*!< 0x000000FC */
+#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
+#define FDCAN_TXBC_NDTB_Pos (16U)
+#define FDCAN_TXBC_NDTB_Msk (0x3FU << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
+#define FDCAN_TXBC_TFQS_Pos (24U)
+#define FDCAN_TXBC_TFQS_Msk (0x3FU << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
+#define FDCAN_TXBC_TFQM_Pos (30U)
+#define FDCAN_TXBC_TFQM_Msk (0x1U << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
+
+/***************** Bit definition for FDCAN_TXFQS register *********************/
+#define FDCAN_TXFQS_TFFL_Pos (0U)
+#define FDCAN_TXFQS_TFFL_Msk (0x3FU << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
+#define FDCAN_TXFQS_TFGI_Pos (8U)
+#define FDCAN_TXFQS_TFGI_Msk (0x1FU << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
+#define FDCAN_TXFQS_TFQPI_Pos (16U)
+#define FDCAN_TXFQS_TFQPI_Msk (0x1FU << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
+#define FDCAN_TXFQS_TFQF_Pos (21U)
+#define FDCAN_TXFQS_TFQF_Msk (0x1U << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
+
+/***************** Bit definition for FDCAN_TXESC register *********************/
+#define FDCAN_TXESC_TBDS_Pos (0U)
+#define FDCAN_TXESC_TBDS_Msk (0x7U << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
+
+/***************** Bit definition for FDCAN_TXBRP register *********************/
+#define FDCAN_TXBRP_TRP_Pos (0U)
+#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFU << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
+
+/***************** Bit definition for FDCAN_TXBAR register *********************/
+#define FDCAN_TXBAR_AR_Pos (0U)
+#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFU << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
+
+/***************** Bit definition for FDCAN_TXBCR register *********************/
+#define FDCAN_TXBCR_CR_Pos (0U)
+#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFU << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
+
+/***************** Bit definition for FDCAN_TXBTO register *********************/
+#define FDCAN_TXBTO_TO_Pos (0U)
+#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFU << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
+
+/***************** Bit definition for FDCAN_TXBCF register *********************/
+#define FDCAN_TXBCF_CF_Pos (0U)
+#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFU << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
+
+/***************** Bit definition for FDCAN_TXBTIE register ********************/
+#define FDCAN_TXBTIE_TIE_Pos (0U)
+#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFU << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
+
+/***************** Bit definition for FDCAN_ TXBCIE register *******************/
+#define FDCAN_TXBCIE_CF_Pos (0U)
+#define FDCAN_TXBCIE_CF_Msk (0xFFFFFFFFU << FDCAN_TXBCIE_CF_Pos) /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CF FDCAN_TXBCIE_CF_Msk /*!<Cancellation Finished Interrupt Enable */
+
+/***************** Bit definition for FDCAN_TXEFC register *********************/
+#define FDCAN_TXEFC_EFSA_Pos (2U)
+#define FDCAN_TXEFC_EFSA_Msk (0x3FFFU << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
+#define FDCAN_TXEFC_EFS_Pos (16U)
+#define FDCAN_TXEFC_EFS_Msk (0x3FU << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
+#define FDCAN_TXEFC_EFWM_Pos (24U)
+#define FDCAN_TXEFC_EFWM_Msk (0x3FU << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
+
+/***************** Bit definition for FDCAN_TXEFS register *********************/
+#define FDCAN_TXEFS_EFFL_Pos (0U)
+#define FDCAN_TXEFS_EFFL_Msk (0x3FU << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
+#define FDCAN_TXEFS_EFGI_Pos (8U)
+#define FDCAN_TXEFS_EFGI_Msk (0x1FU << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
+#define FDCAN_TXEFS_EFPI_Pos (16U)
+#define FDCAN_TXEFS_EFPI_Msk (0x1FU << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
+#define FDCAN_TXEFS_EFF_Pos (24U)
+#define FDCAN_TXEFS_EFF_Msk (0x1U << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
+#define FDCAN_TXEFS_TEFL_Pos (25U)
+#define FDCAN_TXEFS_TEFL_Msk (0x1U << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
+
+/***************** Bit definition for FDCAN_TXEFA register *********************/
+#define FDCAN_TXEFA_EFAI_Pos (0U)
+#define FDCAN_TXEFA_EFAI_Msk (0x1FU << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
+
+/***************** Bit definition for FDCAN_TTTMC register *********************/
+#define FDCAN_TTTMC_TMSA_Pos (2U)
+#define FDCAN_TTTMC_TMSA_Msk (0x3FFFU << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
+#define FDCAN_TTTMC_TME_Pos (16U)
+#define FDCAN_TTTMC_TME_Msk (0x7FU << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
+
+/***************** Bit definition for FDCAN_TTRMC register *********************/
+#define FDCAN_TTRMC_RID_Pos (0U)
+#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFU << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
+#define FDCAN_TTRMC_XTD_Pos (30U)
+#define FDCAN_TTRMC_XTD_Msk (0x1U << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
+#define FDCAN_TTRMC_RMPS_Pos (31U)
+#define FDCAN_TTRMC_RMPS_Msk (0x1U << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
+
+/***************** Bit definition for FDCAN_TTOCF register *********************/
+#define FDCAN_TTOCF_OM_Pos (0U)
+#define FDCAN_TTOCF_OM_Msk (0x3U << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
+#define FDCAN_TTOCF_GEN_Pos (3U)
+#define FDCAN_TTOCF_GEN_Msk (0x1U << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
+#define FDCAN_TTOCF_TM_Pos (4U)
+#define FDCAN_TTOCF_TM_Msk (0x1U << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
+#define FDCAN_TTOCF_LDSDL_Pos (5U)
+#define FDCAN_TTOCF_LDSDL_Msk (0x7U << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
+#define FDCAN_TTOCF_IRTO_Pos (8U)
+#define FDCAN_TTOCF_IRTO_Msk (0x7FU << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
+#define FDCAN_TTOCF_EECS_Pos (15U)
+#define FDCAN_TTOCF_EECS_Msk (0x1U << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
+#define FDCAN_TTOCF_AWL_Pos (16U)
+#define FDCAN_TTOCF_AWL_Msk (0xFFU << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
+#define FDCAN_TTOCF_EGTF_Pos (24U)
+#define FDCAN_TTOCF_EGTF_Msk (0x1U << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
+#define FDCAN_TTOCF_ECC_Pos (25U)
+#define FDCAN_TTOCF_ECC_Msk (0x1U << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
+#define FDCAN_TTOCF_EVTP_Pos (26U)
+#define FDCAN_TTOCF_EVTP_Msk (0x1U << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
+
+/***************** Bit definition for FDCAN_TTMLM register *********************/
+#define FDCAN_TTMLM_CCM_Pos (0U)
+#define FDCAN_TTMLM_CCM_Msk (0x3FU << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
+#define FDCAN_TTMLM_CSS_Pos (6U)
+#define FDCAN_TTMLM_CSS_Msk (0x3U << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
+#define FDCAN_TTMLM_TXEW_Pos (8U)
+#define FDCAN_TTMLM_TXEW_Msk (0xFU << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
+#define FDCAN_TTMLM_ENTT_Pos (16U)
+#define FDCAN_TTMLM_ENTT_Msk (0xFFFU << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
+
+/***************** Bit definition for FDCAN_TURCF register *********************/
+#define FDCAN_TURCF_NCL_Pos (0U)
+#define FDCAN_TURCF_NCL_Msk (0xFFFFU << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
+#define FDCAN_TURCF_DC_Pos (16U)
+#define FDCAN_TURCF_DC_Msk (0x3FFFU << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
+#define FDCAN_TURCF_ELT_Pos (31U)
+#define FDCAN_TURCF_ELT_Msk (0x1U << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
+
+/***************** Bit definition for FDCAN_TTOCN register ********************/
+#define FDCAN_TTOCN_SGT_Pos (0U)
+#define FDCAN_TTOCN_SGT_Msk (0x1U << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
+#define FDCAN_TTOCN_ECS_Pos (1U)
+#define FDCAN_TTOCN_ECS_Msk (0x1U << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
+#define FDCAN_TTOCN_SWP_Pos (2U)
+#define FDCAN_TTOCN_SWP_Msk (0x1U << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
+#define FDCAN_TTOCN_SWS_Pos (3U)
+#define FDCAN_TTOCN_SWS_Msk (0x3U << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
+#define FDCAN_TTOCN_RTIE_Pos (5U)
+#define FDCAN_TTOCN_RTIE_Msk (0x1U << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos (6U)
+#define FDCAN_TTOCN_TMC_Msk (0x3U << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
+#define FDCAN_TTOCN_TTIE_Pos (8U)
+#define FDCAN_TTOCN_TTIE_Msk (0x1U << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_GCS_Pos (9U)
+#define FDCAN_TTOCN_GCS_Msk (0x1U << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
+#define FDCAN_TTOCN_FGP_Pos (10U)
+#define FDCAN_TTOCN_FGP_Msk (0x1U << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
+#define FDCAN_TTOCN_TMG_Pos (11U)
+#define FDCAN_TTOCN_TMG_Msk (0x1U << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
+#define FDCAN_TTOCN_NIG_Pos (12U)
+#define FDCAN_TTOCN_NIG_Msk (0x1U << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
+#define FDCAN_TTOCN_ESCN_Pos (13U)
+#define FDCAN_TTOCN_ESCN_Msk (0x1U << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
+#define FDCAN_TTOCN_LCKC_Pos (15U)
+#define FDCAN_TTOCN_LCKC_Msk (0x1U << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
+
+/***************** Bit definition for FDCAN_TTGTP register ********************/
+#define FDCAN_TTGTP_TP_Pos (0U)
+#define FDCAN_TTGTP_TP_Msk (0xFFFFU << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
+#define FDCAN_TTGTP_CTP_Pos (16U)
+#define FDCAN_TTGTP_CTP_Msk (0xFFFFU << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
+
+/***************** Bit definition for FDCAN_TTTMK register ********************/
+#define FDCAN_TTTMK_TM_Pos (0U)
+#define FDCAN_TTTMK_TM_Msk (0xFFFFU << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
+#define FDCAN_TTTMK_TICC_Pos (16U)
+#define FDCAN_TTTMK_TICC_Msk (0x7FU << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
+#define FDCAN_TTTMK_LCKM_Pos (31U)
+#define FDCAN_TTTMK_LCKM_Msk (0x1U << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
+
+/***************** Bit definition for FDCAN_TTIR register ********************/
+#define FDCAN_TTIR_SBC_Pos (0U)
+#define FDCAN_TTIR_SBC_Msk (0x1U << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
+#define FDCAN_TTIR_SMC_Pos (1U)
+#define FDCAN_TTIR_SMC_Msk (0x1U << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
+#define FDCAN_TTIR_CSM_Pos (2U)
+#define FDCAN_TTIR_CSM_Msk (0x1U << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
+#define FDCAN_TTIR_SOG_Pos (3U)
+#define FDCAN_TTIR_SOG_Msk (0x1U << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
+#define FDCAN_TTIR_RTMI_Pos (4U)
+#define FDCAN_TTIR_RTMI_Msk (0x1U << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
+#define FDCAN_TTIR_TTMI_Pos (5U)
+#define FDCAN_TTIR_TTMI_Msk (0x1U << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
+#define FDCAN_TTIR_SWE_Pos (6U)
+#define FDCAN_TTIR_SWE_Msk (0x1U << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
+#define FDCAN_TTIR_GTW_Pos (7U)
+#define FDCAN_TTIR_GTW_Msk (0x1U << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
+#define FDCAN_TTIR_GTD_Pos (8U)
+#define FDCAN_TTIR_GTD_Msk (0x1U << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
+#define FDCAN_TTIR_GTE_Pos (9U)
+#define FDCAN_TTIR_GTE_Msk (0x1U << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
+#define FDCAN_TTIR_TXU_Pos (10U)
+#define FDCAN_TTIR_TXU_Msk (0x1U << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
+#define FDCAN_TTIR_TXO_Pos (11U)
+#define FDCAN_TTIR_TXO_Msk (0x1U << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
+#define FDCAN_TTIR_SE1_Pos (12U)
+#define FDCAN_TTIR_SE1_Msk (0x1U << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
+#define FDCAN_TTIR_SE2_Pos (13U)
+#define FDCAN_TTIR_SE2_Msk (0x1U << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
+#define FDCAN_TTIR_ELC_Pos (14U)
+#define FDCAN_TTIR_ELC_Msk (0x1U << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
+#define FDCAN_TTIR_IWT_Pos (15U)
+#define FDCAN_TTIR_IWT_Msk (0x1U << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
+#define FDCAN_TTIR_WT_Pos (16U)
+#define FDCAN_TTIR_WT_Msk (0x1U << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
+#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
+#define FDCAN_TTIR_AW_Pos (17U)
+#define FDCAN_TTIR_AW_Msk (0x1U << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
+#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
+#define FDCAN_TTIR_CER_Pos (18U)
+#define FDCAN_TTIR_CER_Msk (0x1U << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
+#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
+
+/***************** Bit definition for FDCAN_TTIE register ********************/
+#define FDCAN_TTIE_SBCE_Pos (0U)
+#define FDCAN_TTIE_SBCE_Msk (0x1U << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
+#define FDCAN_TTIE_SMCE_Pos (1U)
+#define FDCAN_TTIE_SMCE_Msk (0x1U << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
+#define FDCAN_TTIE_CSME_Pos (2U)
+#define FDCAN_TTIE_CSME_Msk (0x1U << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
+#define FDCAN_TTIE_SOGE_Pos (3U)
+#define FDCAN_TTIE_SOGE_Msk (0x1U << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
+#define FDCAN_TTIE_RTMIE_Pos (4U)
+#define FDCAN_TTIE_RTMIE_Msk (0x1U << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
+#define FDCAN_TTIE_TTMIE_Pos (5U)
+#define FDCAN_TTIE_TTMIE_Msk (0x1U << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos (6U)
+#define FDCAN_TTIE_SWEE_Msk (0x1U << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
+#define FDCAN_TTIE_GTWE_Pos (7U)
+#define FDCAN_TTIE_GTWE_Msk (0x1U << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
+#define FDCAN_TTIE_GTDE_Pos (8U)
+#define FDCAN_TTIE_GTDE_Msk (0x1U << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
+#define FDCAN_TTIE_GTEE_Pos (9U)
+#define FDCAN_TTIE_GTEE_Msk (0x1U << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
+#define FDCAN_TTIE_TXUE_Pos (10U)
+#define FDCAN_TTIE_TXUE_Msk (0x1U << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
+#define FDCAN_TTIE_TXOE_Pos (11U)
+#define FDCAN_TTIE_TXOE_Msk (0x1U << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
+#define FDCAN_TTIE_SE1E_Pos (12U)
+#define FDCAN_TTIE_SE1E_Msk (0x1U << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
+#define FDCAN_TTIE_SE2E_Pos (13U)
+#define FDCAN_TTIE_SE2E_Msk (0x1U << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
+#define FDCAN_TTIE_ELCE_Pos (14U)
+#define FDCAN_TTIE_ELCE_Msk (0x1U << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
+#define FDCAN_TTIE_IWTE_Pos (15U)
+#define FDCAN_TTIE_IWTE_Msk (0x1U << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
+#define FDCAN_TTIE_WTE_Pos (16U)
+#define FDCAN_TTIE_WTE_Msk (0x1U << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
+#define FDCAN_TTIE_AWE_Pos (17U)
+#define FDCAN_TTIE_AWE_Msk (0x1U << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
+#define FDCAN_TTIE_CERE_Pos (18U)
+#define FDCAN_TTIE_CERE_Msk (0x1U << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
+
+/***************** Bit definition for FDCAN_TTILS register ********************/
+#define FDCAN_TTILS_SBCS_Pos (0U)
+#define FDCAN_TTILS_SBCS_Msk (0x1U << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
+#define FDCAN_TTILS_SMCS_Pos (1U)
+#define FDCAN_TTILS_SMCS_Msk (0x1U << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
+#define FDCAN_TTILS_CSMS_Pos (2U)
+#define FDCAN_TTILS_CSMS_Msk (0x1U << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
+#define FDCAN_TTILS_SOGS_Pos (3U)
+#define FDCAN_TTILS_SOGS_Msk (0x1U << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
+#define FDCAN_TTILS_RTMIS_Pos (4U)
+#define FDCAN_TTILS_RTMIS_Msk (0x1U << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
+#define FDCAN_TTILS_TTMIS_Pos (5U)
+#define FDCAN_TTILS_TTMIS_Msk (0x1U << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
+#define FDCAN_TTILS_SWES_Pos (6U)
+#define FDCAN_TTILS_SWES_Msk (0x1U << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
+#define FDCAN_TTILS_GTWS_Pos (7U)
+#define FDCAN_TTILS_GTWS_Msk (0x1U << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
+#define FDCAN_TTILS_GTDS_Pos (8U)
+#define FDCAN_TTILS_GTDS_Msk (0x1U << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
+#define FDCAN_TTILS_GTES_Pos (9U)
+#define FDCAN_TTILS_GTES_Msk (0x1U << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
+#define FDCAN_TTILS_TXUS_Pos (10U)
+#define FDCAN_TTILS_TXUS_Msk (0x1U << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
+#define FDCAN_TTILS_TXOS_Pos (11U)
+#define FDCAN_TTILS_TXOS_Msk (0x1U << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
+#define FDCAN_TTILS_SE1S_Pos (12U)
+#define FDCAN_TTILS_SE1S_Msk (0x1U << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
+#define FDCAN_TTILS_SE2S_Pos (13U)
+#define FDCAN_TTILS_SE2S_Msk (0x1U << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
+#define FDCAN_TTILS_ELCS_Pos (14U)
+#define FDCAN_TTILS_ELCS_Msk (0x1U << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
+#define FDCAN_TTILS_IWTS_Pos (15U)
+#define FDCAN_TTILS_IWTS_Msk (0x1U << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
+#define FDCAN_TTILS_WTS_Pos (16U)
+#define FDCAN_TTILS_WTS_Msk (0x1U << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
+#define FDCAN_TTILS_AWS_Pos (17U)
+#define FDCAN_TTILS_AWS_Msk (0x1U << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
+#define FDCAN_TTILS_CERS_Pos (18U)
+#define FDCAN_TTILS_CERS_Msk (0x1U << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
+
+/***************** Bit definition for FDCAN_TTOST register ********************/
+#define FDCAN_TTOST_EL_Pos (0U)
+#define FDCAN_TTOST_EL_Msk (0x3U << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
+#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
+#define FDCAN_TTOST_MS_Pos (2U)
+#define FDCAN_TTOST_MS_Msk (0x3U << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
+#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
+#define FDCAN_TTOST_SYS_Pos (4U)
+#define FDCAN_TTOST_SYS_Msk (0x3U << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
+#define FDCAN_TTOST_QGTP_Pos (6U)
+#define FDCAN_TTOST_QGTP_Msk (0x1U << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
+#define FDCAN_TTOST_QCS_Pos (7U)
+#define FDCAN_TTOST_QCS_Msk (0x1U << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
+#define FDCAN_TTOST_RTO_Pos (8U)
+#define FDCAN_TTOST_RTO_Msk (0xFFU << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
+#define FDCAN_TTOST_WGTD_Pos (22U)
+#define FDCAN_TTOST_WGTD_Msk (0x1U << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
+#define FDCAN_TTOST_GFI_Pos (23U)
+#define FDCAN_TTOST_GFI_Msk (0x1U << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
+#define FDCAN_TTOST_TMP_Pos (24U)
+#define FDCAN_TTOST_TMP_Msk (0x7U << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
+#define FDCAN_TTOST_GSI_Pos (27U)
+#define FDCAN_TTOST_GSI_Msk (0x1U << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
+#define FDCAN_TTOST_WFE_Pos (28U)
+#define FDCAN_TTOST_WFE_Msk (0x1U << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
+#define FDCAN_TTOST_AWE_Pos (29U)
+#define FDCAN_TTOST_AWE_Msk (0x1U << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
+#define FDCAN_TTOST_WECS_Pos (30U)
+#define FDCAN_TTOST_WECS_Msk (0x1U << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
+#define FDCAN_TTOST_SPL_Pos (31U)
+#define FDCAN_TTOST_SPL_Msk (0x1U << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
+
+/***************** Bit definition for FDCAN_TURNA register ********************/
+#define FDCAN_TURNA_NAV_Pos (0U)
+#define FDCAN_TURNA_NAV_Msk (0x3FFFFU << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
+
+/***************** Bit definition for FDCAN_TTLGT register ********************/
+#define FDCAN_TTLGT_LT_Pos (0U)
+#define FDCAN_TTLGT_LT_Msk (0xFFFFU << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
+#define FDCAN_TTLGT_GT_Pos (16U)
+#define FDCAN_TTLGT_GT_Msk (0xFFFFU << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
+
+/***************** Bit definition for FDCAN_TTCTC register ********************/
+#define FDCAN_TTCTC_CT_Pos (0U)
+#define FDCAN_TTCTC_CT_Msk (0xFFFFU << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
+#define FDCAN_TTCTC_CC_Pos (16U)
+#define FDCAN_TTCTC_CC_Msk (0x3FU << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
+
+/***************** Bit definition for FDCAN_TTCPT register ********************/
+#define FDCAN_TTCPT_CCV_Pos (0U)
+#define FDCAN_TTCPT_CCV_Msk (0x3FU << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
+#define FDCAN_TTCPT_SWV_Pos (16U)
+#define FDCAN_TTCPT_SWV_Msk (0xFFFFU << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
+
+/***************** Bit definition for FDCAN_TTCSM register ********************/
+#define FDCAN_TTCSM_CSM_Pos (0U)
+#define FDCAN_TTCSM_CSM_Msk (0xFFFFU << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
+
+/***************** Bit definition for FDCAN_TTTS register *********************/
+#define FDCAN_TTTS_SWTSEL_Pos (0U)
+#define FDCAN_TTTS_SWTSEL_Msk (0x3U << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
+#define FDCAN_TTTS_EVTSEL_Pos (4U)
+#define FDCAN_TTTS_EVTSEL_Msk (0x3U << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
+
+/********************************************************************************/
+/* */
+/* FDCANCCU (Clock Calibration unit) */
+/* */
+/********************************************************************************/
+
+/***************** Bit definition for FDCANCCU_CREL register ******************/
+#define FDCANCCU_CREL_DAY_Pos (0U)
+#define FDCANCCU_CREL_DAY_Msk (0xFFU << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
+#define FDCANCCU_CREL_MON_Pos (8U)
+#define FDCANCCU_CREL_MON_Msk (0xFFU << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
+#define FDCANCCU_CREL_YEAR_Pos (16U)
+#define FDCANCCU_CREL_YEAR_Msk (0xFU << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
+#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk (0xFU << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
+#define FDCANCCU_CREL_STEP_Pos (24U)
+#define FDCANCCU_CREL_STEP_Msk (0xFU << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
+#define FDCANCCU_CREL_REL_Pos (28U)
+#define FDCANCCU_CREL_REL_Msk (0xFU << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
+
+/***************** Bit definition for FDCANCCU_CCFG register ******************/
+#define FDCANCCU_CCFG_TQBT_Pos (0U)
+#define FDCANCCU_CCFG_TQBT_Msk (0x1FU << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
+#define FDCANCCU_CCFG_BCC_Pos (6U)
+#define FDCANCCU_CCFG_BCC_Msk (0x1U << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
+#define FDCANCCU_CCFG_CFL_Pos (7U)
+#define FDCANCCU_CCFG_CFL_Msk (0x1U << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
+#define FDCANCCU_CCFG_OCPM_Pos (8U)
+#define FDCANCCU_CCFG_OCPM_Msk (0xFFU << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
+#define FDCANCCU_CCFG_CDIV_Pos (16U)
+#define FDCANCCU_CCFG_CDIV_Msk (0xFU << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
+#define FDCANCCU_CCFG_SWR_Pos (31U)
+#define FDCANCCU_CCFG_SWR_Msk (0x1U << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
+
+/***************** Bit definition for FDCANCCU_CSTAT register *****************/
+#define FDCANCCU_CSTAT_OCPC_Pos (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFU << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
+#define FDCANCCU_CSTAT_TQC_Pos (18U)
+#define FDCANCCU_CSTAT_TQC_Msk (0x7FFU << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
+#define FDCANCCU_CSTAT_CALS_Pos (30U)
+#define FDCANCCU_CSTAT_CALS_Msk (0x3U << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
+
+/****************** Bit definition for FDCANCCU_CWD register ******************/
+#define FDCANCCU_CWD_WDC_Pos (0U)
+#define FDCANCCU_CWD_WDC_Msk (0xFFFFU << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
+#define FDCANCCU_CWD_WDV_Pos (16U)
+#define FDCANCCU_CWD_WDV_Msk (0xFFFFU << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
+
+/****************** Bit definition for FDCANCCU_IR register *******************/
+#define FDCANCCU_IR_CWE_Pos (0U)
+#define FDCANCCU_IR_CWE_Msk (0x1U << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
+#define FDCANCCU_IR_CSC_Pos (1U)
+#define FDCANCCU_IR_CSC_Msk (0x1U << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
+
+/****************** Bit definition for FDCANCCU_IE register *******************/
+#define FDCANCCU_IE_CWEE_Pos (0U)
+#define FDCANCCU_IE_CWEE_Msk (0x1U << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
+#define FDCANCCU_IE_CSCE_Pos (1U)
+#define FDCANCCU_IE_CSCE_Msk (0x1U << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
+
+/******************************************************************************/
+/* */
+/* HDMI-CEC (CEC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CEC_CR register *********************/
+#define CEC_CR_CECEN_Pos (0U)
+#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
+#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
+#define CEC_CR_TXSOM_Pos (1U)
+#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
+#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
+#define CEC_CR_TXEOM_Pos (2U)
+#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
+#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
+
+/******************* Bit definition for CEC_CFGR register *******************/
+#define CEC_CFGR_SFT_Pos (0U)
+#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
+#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
+#define CEC_CFGR_RXTOL_Pos (3U)
+#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
+#define CEC_CFGR_BRESTP_Pos (4U)
+#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
+#define CEC_CFGR_BREGEN_Pos (5U)
+#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
+#define CEC_CFGR_LBPEGEN_Pos (6U)
+#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
+#define CEC_CFGR_SFTOPT_Pos (8U)
+#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
+#define CEC_CFGR_BRDNOGEN_Pos (7U)
+#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
+#define CEC_CFGR_OAR_Pos (16U)
+#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
+#define CEC_CFGR_LSTN_Pos (31U)
+#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
+#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
+
+/******************* Bit definition for CEC_TXDR register *******************/
+#define CEC_TXDR_TXD_Pos (0U)
+#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
+#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
+
+/******************* Bit definition for CEC_RXDR register *******************/
+#define CEC_TXDR_RXD_Pos (0U)
+#define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
+#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
+
+/******************* Bit definition for CEC_ISR register ********************/
+#define CEC_ISR_RXBR_Pos (0U)
+#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
+#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
+#define CEC_ISR_RXEND_Pos (1U)
+#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
+#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
+#define CEC_ISR_RXOVR_Pos (2U)
+#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
+#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
+#define CEC_ISR_BRE_Pos (3U)
+#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
+#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
+#define CEC_ISR_SBPE_Pos (4U)
+#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
+#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
+#define CEC_ISR_LBPE_Pos (5U)
+#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
+#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
+#define CEC_ISR_RXACKE_Pos (6U)
+#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
+#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
+#define CEC_ISR_ARBLST_Pos (7U)
+#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
+#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
+#define CEC_ISR_TXBR_Pos (8U)
+#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
+#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
+#define CEC_ISR_TXEND_Pos (9U)
+#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
+#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
+#define CEC_ISR_TXUDR_Pos (10U)
+#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
+#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
+#define CEC_ISR_TXERR_Pos (11U)
+#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
+#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
+#define CEC_ISR_TXACKE_Pos (12U)
+#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
+#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
+
+/******************* Bit definition for CEC_IER register ********************/
+#define CEC_IER_RXBRIE_Pos (0U)
+#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
+#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
+#define CEC_IER_RXENDIE_Pos (1U)
+#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
+#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
+#define CEC_IER_RXOVRIE_Pos (2U)
+#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
+#define CEC_IER_BREIE_Pos (3U)
+#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
+#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
+#define CEC_IER_SBPEIE_Pos (4U)
+#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
+#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
+#define CEC_IER_LBPEIE_Pos (5U)
+#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
+#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
+#define CEC_IER_RXACKEIE_Pos (6U)
+#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
+#define CEC_IER_ARBLSTIE_Pos (7U)
+#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
+#define CEC_IER_TXBRIE_Pos (8U)
+#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
+#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
+#define CEC_IER_TXENDIE_Pos (9U)
+#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
+#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
+#define CEC_IER_TXUDRIE_Pos (10U)
+#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
+#define CEC_IER_TXERRIE_Pos (11U)
+#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
+#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
+#define CEC_IER_TXACKEIE_Pos (12U)
+#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR_Pos (0U)
+#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Crypto Processor */
+/* */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register ********************/
+#define CRYP_CR_ALGODIR_Pos (2U)
+#define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
+#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
+
+#define CRYP_CR_ALGOMODE_Pos (3U)
+#define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
+#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
+#define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
+#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
+#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
+#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
+#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
+#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
+#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
+#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
+#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
+#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
+#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
+#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
+#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
+#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1U << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
+#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
+#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
+#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001U << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
+#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
+#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
+#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
+#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
+
+#define CRYP_CR_DATATYPE_Pos (6U)
+#define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
+#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
+#define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
+#define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
+#define CRYP_CR_KEYSIZE_Pos (8U)
+#define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
+#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
+#define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
+#define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
+#define CRYP_CR_FFLUSH_Pos (14U)
+#define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
+#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
+#define CRYP_CR_CRYPEN_Pos (15U)
+#define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
+#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
+
+#define CRYP_CR_GCM_CCMPH_Pos (16U)
+#define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
+#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
+#define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
+#define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
+#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
+#define CRYP_CR_NPBLB_Pos (20U)
+#define CRYP_CR_NPBLB_Msk (0xFU << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
+#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
+
+/****************** Bits definition for CRYP_SR register *********************/
+#define CRYP_SR_IFEM_Pos (0U)
+#define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
+#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
+#define CRYP_SR_IFNF_Pos (1U)
+#define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
+#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
+#define CRYP_SR_OFNE_Pos (2U)
+#define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
+#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
+#define CRYP_SR_OFFU_Pos (3U)
+#define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
+#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
+#define CRYP_SR_BUSY_Pos (4U)
+#define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
+#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
+/****************** Bits definition for CRYP_DMACR register ******************/
+#define CRYP_DMACR_DIEN_Pos (0U)
+#define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
+#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
+#define CRYP_DMACR_DOEN_Pos (1U)
+#define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
+#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
+/***************** Bits definition for CRYP_IMSCR register ******************/
+#define CRYP_IMSCR_INIM_Pos (0U)
+#define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
+#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
+#define CRYP_IMSCR_OUTIM_Pos (1U)
+#define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
+#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
+/****************** Bits definition for CRYP_RISR register *******************/
+#define CRYP_RISR_OUTRIS_Pos (0U)
+#define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
+#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
+#define CRYP_RISR_INRIS_Pos (1U)
+#define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
+#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
+/****************** Bits definition for CRYP_MISR register *******************/
+#define CRYP_MISR_INMIS_Pos (0U)
+#define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
+#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
+#define CRYP_MISR_OUTMIS_Pos (1U)
+#define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
+#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
+
+/********************** Bit definition for CRYP_HWCFGR register ***************/
+#define CRYP_HWCFGR_CFG1_Pos (0U)
+#define CRYP_HWCFGR_CFG1_Msk (0xFU << CRYP_HWCFGR_CFG1_Pos) /*!< 0x0000000F */
+#define CRYP_HWCFGR_CFG1 CRYP_HWCFGR_CFG1_Msk /*!< HW Generic 1 */
+#define CRYP_HWCFGR_CFG2_Pos (4U)
+#define CRYP_HWCFGR_CFG2_Msk (0xFU << CRYP_HWCFGR_CFG2_Pos) /*!< 0x000000F0 */
+#define CRYP_HWCFGR_CFG2 CRYP_HWCFGR_CFG2_Msk /*!< HW Generic 2 */
+#define CRYP_HWCFGR_CFG3_Pos (8U)
+#define CRYP_HWCFGR_CFG3_Msk (0xFU << CRYP_HWCFGR_CFG3_Pos) /*!< 0x00000F00 */
+#define CRYP_HWCFGR_CFG3 CRYP_HWCFGR_CFG3_Msk /*!< HW Generic 3 */
+#define CRYP_HWCFGR_CFG4_Pos (12U)
+#define CRYP_HWCFGR_CFG4_Msk (0xFU << CRYP_HWCFGR_CFG4_Pos) /*!< 0x0000F000 */
+#define CRYP_HWCFGR_CFG4 CRYP_HWCFGR_CFG4_Msk /*!< HW Generic 4 */
+
+/********************** Bit definition for CRYP_VERR register *****************/
+#define CRYP_VERR_VER_Pos (0U)
+#define CRYP_VERR_VER_Msk (0xFFU << CRYP_VERR_VER_Pos) /*!< 0x000000FF */
+#define CRYP_VERR_VER CRYP_VERR_VER_Msk /*!< Revision number */
+
+/********************** Bit definition for CRYP_IPIDR register ****************/
+#define CRYP_IPIDR_IPID_Pos (0U)
+#define CRYP_IPIDR_IPID_Msk (0xFFFFFFFFU << CRYP_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_IPIDR_IPID CRYP_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for CRYP_SIDR register *****************/
+#define CRYP_MID_MID_Pos (0U)
+#define CRYP_MID_MID_Msk (0xFFFFFFFFU << CRYP_MID_MID_Pos) /*!< 0xFFFFFFFF */
+#define CRYP_MID_MID CRYP_MID_MID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos (1U)
+#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (2U)
+#define DAC_CR_TSEL1_Msk (0xFU << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3 (0x8U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
+#define DAC_CR_CEN1_Pos (14U)
+#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
+#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
+#define DAC_CR_HFSEL_Pos (15U)
+#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
+#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<High frequency interface mode enable >*/
+
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos (17U)
+#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (18U)
+#define DAC_CR_TSEL2_Msk (0xFU << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3 (0x8U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
+#define DAC_CR_CEN2_Pos (30U)
+#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
+#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (0U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos (14U)
+#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos (15U)
+#define DAC_SR_BWST1_Msk (0x4001U << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
+#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos (30U)
+#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos (31U)
+#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
+#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
+
+/******************* Bit definition for DAC_CCR register ********************/
+#define DAC_CCR_OTRIM1_Pos (0U)
+#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos (16U)
+#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
+
+/******************* Bit definition for DAC_MCR register *******************/
+#define DAC_MCR_MODE1_Pos (0U)
+#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
+#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos (16U)
+#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
+#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for DAC_SHSR1 register ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
+
+/****************** Bit definition for DAC_SHSR2 register ******************/
+#define DAC_SHSR1_TSAMPLE2_Pos (0U)
+#define DAC_SHSR1_TSAMPLE2_Msk (0x3FFU << DAC_SHSR1_TSAMPLE2_Pos) /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE2 DAC_SHSR1_TSAMPLE2_Msk /*!<DAC channel2 sample time */
+
+/****************** Bit definition for DAC_SHHR register ******************/
+#define DAC_SHHR_THOLD1_Pos (0U)
+#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos (16U)
+#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
+
+/****************** Bit definition for DAC_SHRR register ******************/
+#define DAC_SHRR_TREFRESH1_Pos (0U)
+#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos (16U)
+#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
+
+/********************** Bit definition for DAC_HWCFGR0 register ***************/
+#define DAC_HWCFGR0_DUAL_Pos (0U)
+#define DAC_HWCFGR0_DUAL_Msk (0xFF << DAC_HWCFGR0_DUAL_Pos) /*!< 0x0000000F */
+#define DAC_HWCFGR0_DUAL DAC_HWCFGR0_DUAL_Msk /*!< Dual DAC capability */
+#define DAC_HWCFGR0_LFSR_Pos (4U)
+#define DAC_HWCFGR0_LFSR_Msk (0xFU << DAC_HWCFGR0_LFSR_Pos) /*!< 0x000000F0 */
+#define DAC_HWCFGR0_LFSR DAC_HWCFGR0_LFSR_Msk /*!< Pseudonoise wave generation capability */
+#define DAC_HWCFGR0_TRIANGLE_Pos (8U)
+#define DAC_HWCFGR0_TRIANGLE_Msk (0xFU << DAC_HWCFGR0_TRIANGLE_Pos) /*!< 0x00000F00 */
+#define DAC_HWCFGR0_TRIANGLE DAC_HWCFGR0_TRIANGLE_Msk /*!< Triangle wave generation capability */
+#define DAC_HWCFGR0_SAMPLE_Pos (12U)
+#define DAC_HWCFGR0_SAMPLE_Msk (0xFU << DAC_HWCFGR0_SAMPLE_Pos) /*!< 0x0000F000 */
+#define DAC_HWCFGR0_SAMPLE DAC_HWCFGR0_SAMPLE_Msk /*!< Sample and Hold mode capability */
+#define DAC_HWCFGR0_OR_CFG_Pos (16U)
+#define DAC_HWCFGR0_OR_CFG_Msk (0xFFU << DAC_HWCFGR0_OR_CFG_Pos) /*!< 0x00FF0000 */
+#define DAC_HWCFGR0_OR_CFG DAC_HWCFGR0_OR_CFG_Msk /*!< option register bit width */
+
+/******************** Bit definition for DAC_VERR register********************/
+#define DAC_VERR_MINREV_Pos (0U)
+#define DAC_VERR_MINREV_Msk (0xFU << DAC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define DAC_VERR_MINREV DAC_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
+#define DAC_VERR_MAJREV_Pos (4U)
+#define DAC_VERR_MAJREV_Msk (0xFU << DAC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define DAC_VERR_MAJREV DAC_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
+
+/********************** Bit definition for DAC_IPIDR register ****************/
+#define DAC_IPIDR_IPID_Pos (0U)
+#define DAC_IPIDR_IPID_Msk (0xFFFFFFFFU << DAC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define DAC_IPIDR_IPID DAC_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for DAC_SIDR register *****************/
+#define DAC_SIDR_SID_Pos (0U)
+#define DAC_SIDR_SID_Msk (0xFFFFFFFFU << DAC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define DAC_SIDR_SID DAC_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* DBG */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
+#define DBGMCU_CR_DBG_WDFZCTL_Pos (24U)
+#define DBGMCU_CR_DBG_WDFZCTL_Msk (0x1U << DBGMCU_CR_DBG_WDFZCTL_Pos) /*!< 0x01000000 */
+#define DBGMCU_CR_DBG_WDFZCTL DBGMCU_CR_DBG_WDFZCTL_Msk
+#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
+#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1U << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
+
+/******************** Bit definition for APB4FZ register ************/
+#define DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Pos (2U)
+#define DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Msk (0x1U << DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB4_FZ_DBG_IWDG2_STOP DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Msk
+
+/******************** Bit definition for APB1FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_WWDG1_STOP DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (18U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (19U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00080000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (20U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00100000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_I2C5_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C5_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C5_STOP DBGMCU_APB1_FZ_DBG_I2C5_STOP_Msk
+
+/******************** Bit definition for APB2FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (6U)
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (7U)
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (8U)
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
+#define DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Pos (15U)
+#define DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Pos) /*!< 0x00008000 */
+#define DBGMCU_APB2_FZ_DBG_FDCAN_STOP DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Msk
+
+/******************** Bit definition for APB3FZ register ************/
+#define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Pos (1U)
+#define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Msk
+#define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Pos (2U)
+#define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Msk
+#define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Pos (3U)
+#define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Msk
+#define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Pos (4U)
+#define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Msk
+
+/******************** Bit definition for APB5FZ register ************/
+#define DBGMCU_APB5_FZ_DBG_I2C4_STOP_Pos (2U)
+#define DBGMCU_APB5_FZ_DBG_I2C4_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_I2C4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB5_FZ_DBG_I2C4_STOP DBGMCU_APB5_FZ_DBG_I2C4_STOP_Msk
+#define DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Pos (3U)
+#define DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB5_FZ_DBG_IWDG1_STOP DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Msk
+#define DBGMCU_APB5_FZ_DBG_RTC_STOP_Pos (4U)
+#define DBGMCU_APB5_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB5_FZ_DBG_RTC_STOP DBGMCU_APB5_FZ_DBG_RTC_STOP_Msk
+#define DBGMCU_APB5_FZ_DBG_I2C6_STOP_Pos (9U)
+#define DBGMCU_APB5_FZ_DBG_I2C6_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_I2C6_STOP_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB5_FZ_DBG_I2C6_STOP DBGMCU_APB5_FZ_DBG_I2C6_STOP_Msk
+
+/******************************************************************************/
+/* */
+/* DCMI */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DCMI_CR register ******************/
+#define DCMI_CR_CAPTURE_Pos (0U)
+#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos (1U)
+#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
+#define DCMI_CR_CM DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos (2U)
+#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
+#define DCMI_CR_CROP DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos (3U)
+#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
+#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos (4U)
+#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
+#define DCMI_CR_ESS DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos (5U)
+#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos (6U)
+#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
+#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos (7U)
+#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
+#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
+#define DCMI_CR_CRE_Pos (12U)
+#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
+#define DCMI_CR_CRE DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos (14U)
+#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
+#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos (16U)
+#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
+#define DCMI_CR_BSM DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
+#define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos (18U)
+#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
+#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos (19U)
+#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
+#define DCMI_CR_LSM DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos (20U)
+#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
+#define DCMI_CR_OELS DCMI_CR_OELS_Msk
+
+/******************** Bits definition for DCMI_SR register ******************/
+#define DCMI_SR_HSYNC_Pos (0U)
+#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
+#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos (1U)
+#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
+#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos (2U)
+#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
+#define DCMI_SR_FNE DCMI_SR_FNE_Msk
+
+/******************** Bits definition for DCMI_RIS register ****************/
+#define DCMI_RIS_FRAME_RIS_Pos (0U)
+#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos (1U)
+#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos (2U)
+#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos (4U)
+#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
+
+/******************** Bits definition for DCMI_IER register *****************/
+#define DCMI_IER_FRAME_IE_Pos (0U)
+#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos (1U)
+#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos (2U)
+#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos (3U)
+#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos (4U)
+#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
+
+
+/******************** Bits definition for DCMI_MIS register *****************/
+#define DCMI_MIS_FRAME_MIS_Pos (0U)
+#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos (1U)
+#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos (2U)
+#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos (4U)
+#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
+
+
+/******************** Bits definition for DCMI_ICR register *****************/
+#define DCMI_ICR_FRAME_ISC_Pos (0U)
+#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos (1U)
+#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos (2U)
+#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos (4U)
+#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
+
+
+/******************** Bits definition for DCMI_ESCR register ******************/
+#define DCMI_ESCR_FSC_Pos (0U)
+#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
+#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos (8U)
+#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos (16U)
+#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos (24U)
+#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
+
+/******************** Bits definition for DCMI_ESUR register ******************/
+#define DCMI_ESUR_FSU_Pos (0U)
+#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
+#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos (8U)
+#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos (16U)
+#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos (24U)
+#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
+
+/******************** Bits definition for DCMI_CWSTRT register ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos (16U)
+#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
+
+/******************** Bits definition for DCMI_CWSIZE register ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos (16U)
+#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
+
+/******************** Bits definition for DCMI_DR register ******************/
+#define DCMI_DR_BYTE0_Pos (0U)
+#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
+#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos (8U)
+#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos (16U)
+#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos (24U)
+#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/* */
+/* Digital Filter for Sigma Delta Modulators */
+/* */
+/******************************************************************************/
+
+/**************** DFSDM channel configuration registers ********************/
+
+/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos (0U)
+#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
+
+/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)/*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/**************** Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos (0U)
+#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
+
+/**************** Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)/*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)/*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
+
+/**************** Bit definition for DFSDM_CHDLYR register *******************/
+#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
+#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F */
+#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */
+
+/************************ DFSDM module registers ****************************/
+
+/***************** Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos (29U)
+#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos (24U)
+#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos (18U)
+#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
+#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
+#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos (0U)
+#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
+
+/***************** Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos (8U)
+#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
+
+/***************** Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos (24U)
+#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos (16U)
+#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos (14U)
+#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos (13U)
+#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos (4U)
+#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos (3U)
+#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos (2U)
+#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos (1U)
+#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos (0U)
+#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
+
+/***************** Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
+#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
+
+/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
+
+/***************** Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos (29U)
+#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos (16U)
+#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos (0U)
+#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)/*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)/*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)/*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)/*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/*************** Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)/*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)/*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)/*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)/*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)/*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/********************** Bit definition for DFSDM_HWCFGR register ***************/
+#define DFSDM_HWCFGR_NBT_Pos (0U)
+#define DFSDM_HWCFGR_NBT_Msk (0xFFU << DFSDM_HWCFGR_NBT_Pos) /*!< 0x000000FF */
+#define DFSDM_HWCFGR_NBT DFSDM_HWCFGR_NBT_Msk /*!< Number of implemented transceivers */
+#define DFSDM_HWCFGR_NBF_Pos (8U)
+#define DFSDM_HWCFGR_NBF_Msk (0xFFU << DFSDM_HWCFGR_NBF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_HWCFGR_NBF DFSDM_HWCFGR_NBF_Msk /*!< NNumber of implemented filters */
+
+/********************** Bit definition for DFSDM_VERR register *****************/
+#define DFSDM_VERR_MINREV_Pos (0U)
+#define DFSDM_VERR_MINREV_Msk (0xFU << DFSDM_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define DFSDM_VERR_MINREV DFSDM_VERR_MINREV_Msk /*!< Minor Revision number */
+#define DFSDM_VERR_MAJREV_Pos (4U)
+#define DFSDM_VERR_MAJREV_Msk (0xFU << DFSDM_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define DFSDM_VERR_MAJREV DFSDM_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for DFSDM_IPIDR register ****************/
+#define DFSDM_IPIDR_IPID_Pos (0U)
+#define DFSDM_IPIDR_IPID_Msk (0xFFFFFFFFU << DFSDM_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define DFSDM_IPIDR_IPID DFSDM_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for DFSDM_SIDR register *****************/
+#define DFSDM_SIDR_SID_Pos (0U)
+#define DFSDM_SIDR_SID_Msk (0xFFFFFFFFU << DFSDM_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define DFSDM_SIDR_SID DFSDM_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Ethernet MAC Registers bits definitions */
+/* */
+/******************************************************************************/
+/*************** Bit definition for ETH_MACCR register ***************/
+#define ETH_MACCR_RE_Pos (0U)
+#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE ETH_MACCR_RE_Msk /*!< Receiver Enable */
+#define ETH_MACCR_TE_Pos (1U)
+#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE ETH_MACCR_TE_Msk /*!< Transmitter Enable */
+#define ETH_MACCR_PRELEN_Pos (2U)
+#define ETH_MACCR_PRELEN_Msk (0x3U << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_0 (0x1U << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_1 (0x2U << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_DC_Pos (4U)
+#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */
+#define ETH_MACCR_BL_Pos (5U)
+#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */
+#define ETH_MACCR_BL_0 (0x1U << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_1 (0x2U << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_DR_Pos (8U)
+#define ETH_MACCR_DR_Msk (0x1U << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */
+#define ETH_MACCR_DCRS_Pos (9U)
+#define ETH_MACCR_DCRS_Msk (0x1U << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /*!< Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DO_Pos (10U)
+#define ETH_MACCR_DO_Msk (0x1U << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO ETH_MACCR_DO_Msk /*!< Disable Receive Own */
+#define ETH_MACCR_ECRSFD_Pos (11U)
+#define ETH_MACCR_ECRSFD_Msk (0x1U << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /*!< Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_LM_Pos (12U)
+#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM ETH_MACCR_LM_Msk /*!< Loopback Mode */
+#define ETH_MACCR_DM_Pos (13U)
+#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM ETH_MACCR_DM_Msk /*!< Duplex Mode */
+#define ETH_MACCR_FES_Pos (14U)
+#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES ETH_MACCR_FES_Msk /*!< MAC Speed */
+#define ETH_MACCR_PS_Pos (15U)
+#define ETH_MACCR_PS_Msk (0x1U << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
+#define ETH_MACCR_PS ETH_MACCR_PS_Msk /*!< Port Select */
+#define ETH_MACCR_JE_Pos (16U)
+#define ETH_MACCR_JE_Msk (0x1U << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE ETH_MACCR_JE_Msk /*!< Jumbo Packet Enable */
+#define ETH_MACCR_JD_Pos (17U)
+#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD ETH_MACCR_JD_Msk /*!< Jabber Disable */
+#define ETH_MACCR_BE_Pos (18U)
+#define ETH_MACCR_BE_Msk (0x1U << ETH_MACCR_BE_Pos) /*!< 0x00040000 */
+#define ETH_MACCR_BE ETH_MACCR_BE_Msk /*!< Packet Burst Enable */
+#define ETH_MACCR_WD_Pos (19U)
+#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD ETH_MACCR_WD_Msk /*!< Watchdog Disable */
+#define ETH_MACCR_ACS_Pos (20U)
+#define ETH_MACCR_ACS_Msk (0x1U << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /*!< Automatic Pad or CRC Stripping */
+#define ETH_MACCR_CST_Pos (21U)
+#define ETH_MACCR_CST_Msk (0x1U << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST ETH_MACCR_CST_Msk /*!< CRC stripping for Type packets */
+#define ETH_MACCR_S2KP_Pos (22U)
+#define ETH_MACCR_S2KP_Msk (0x1U << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /*!< IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_GPSLCE_Pos (23U)
+#define ETH_MACCR_GPSLCE_Msk (0x1U << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /*!< Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_IPG_Pos (24U)
+#define ETH_MACCR_IPG_Msk (0x7U << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */
+#define ETH_MACCR_IPG_0 (0x1U << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */
+#define ETH_MACCR_IPG_1 (0x2U << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */
+#define ETH_MACCR_IPG_2 (0x4U << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */
+#define ETH_MACCR_IPC_Pos (27U)
+#define ETH_MACCR_IPC_Msk (0x1U << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */
+#define ETH_MACCR_SARC_Pos (28U)
+#define ETH_MACCR_SARC_Msk (0x7U << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /*!< Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_0 (0x1U << ETH_MACCR_SARC_Pos) /*!< 0x10000000 */
+#define ETH_MACCR_SARC_1 (0x2U << ETH_MACCR_SARC_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_2 (0x4U << ETH_MACCR_SARC_Pos) /*!< 0x40000000 */
+#define ETH_MACCR_ARPEN_Pos (31U)
+#define ETH_MACCR_ARPEN_Msk (0x1U << ETH_MACCR_ARPEN_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARPEN ETH_MACCR_ARPEN_Msk /*!< ARP Offload Enable */
+
+/************** Bit definition for ETH_MACECR register ***************/
+#define ETH_MACECR_GPSL_Pos (0U)
+#define ETH_MACECR_GPSL_Msk (0x3FFFU << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /*!< Giant Packet Size Limit */
+#define ETH_MACECR_GPSL_0 (0x1U << ETH_MACECR_GPSL_Pos) /*!< 0x00000001 */
+#define ETH_MACECR_GPSL_1 (0x2U << ETH_MACECR_GPSL_Pos) /*!< 0x00000002 */
+#define ETH_MACECR_GPSL_2 (0x4U << ETH_MACECR_GPSL_Pos) /*!< 0x00000004 */
+#define ETH_MACECR_GPSL_3 (0x8U << ETH_MACECR_GPSL_Pos) /*!< 0x00000008 */
+#define ETH_MACECR_GPSL_4 (0x10U << ETH_MACECR_GPSL_Pos) /*!< 0x00000010 */
+#define ETH_MACECR_GPSL_5 (0x20U << ETH_MACECR_GPSL_Pos) /*!< 0x00000020 */
+#define ETH_MACECR_GPSL_6 (0x40U << ETH_MACECR_GPSL_Pos) /*!< 0x00000040 */
+#define ETH_MACECR_GPSL_7 (0x80U << ETH_MACECR_GPSL_Pos) /*!< 0x00000080 */
+#define ETH_MACECR_GPSL_8 (0x100U << ETH_MACECR_GPSL_Pos) /*!< 0x00000100 */
+#define ETH_MACECR_GPSL_9 (0x200U << ETH_MACECR_GPSL_Pos) /*!< 0x00000200 */
+#define ETH_MACECR_GPSL_10 (0x400U << ETH_MACECR_GPSL_Pos) /*!< 0x00000400 */
+#define ETH_MACECR_GPSL_11 (0x800U << ETH_MACECR_GPSL_Pos) /*!< 0x00000800 */
+#define ETH_MACECR_GPSL_12 (0x1000U << ETH_MACECR_GPSL_Pos) /*!< 0x00001000 */
+#define ETH_MACECR_GPSL_13 (0x2000U << ETH_MACECR_GPSL_Pos) /*!< 0x00002000 */
+#define ETH_MACECR_DCRCC_Pos (16U)
+#define ETH_MACECR_DCRCC_Msk (0x1U << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /*!< Disable CRC Checking for Received Packets */
+#define ETH_MACECR_SPEN_Pos (17U)
+#define ETH_MACECR_SPEN_Msk (0x1U << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /*!< Slow Protocol Detection Enable */
+#define ETH_MACECR_USP_Pos (18U)
+#define ETH_MACECR_USP_Msk (0x1U << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP ETH_MACECR_USP_Msk /*!< Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_EIPGEN_Pos (24U)
+#define ETH_MACECR_EIPGEN_Msk (0x1U << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_EIPG_Pos (25U)
+#define ETH_MACECR_EIPG_Msk (0x1FU << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPG_0 (0x1U << ETH_MACECR_EIPG_Pos) /*!< 0x02000000 */
+#define ETH_MACECR_EIPG_1 (0x2U << ETH_MACECR_EIPG_Pos) /*!< 0x04000000 */
+#define ETH_MACECR_EIPG_2 (0x4U << ETH_MACECR_EIPG_Pos) /*!< 0x08000000 */
+#define ETH_MACECR_EIPG_3 (0x8U << ETH_MACECR_EIPG_Pos) /*!< 0x10000000 */
+#define ETH_MACECR_EIPG_4 (0x10U << ETH_MACECR_EIPG_Pos) /*!< 0x20000000 */
+
+/************** Bit definition for ETH_MACPFR register ***************/
+#define ETH_MACPFR_PR_Pos (0U)
+#define ETH_MACPFR_PR_Msk (0x1U << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /*!< Promiscuous Mode */
+#define ETH_MACPFR_HUC_Pos (1U)
+#define ETH_MACPFR_HUC_Msk (0x1U << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /*!< Hash Unicast */
+#define ETH_MACPFR_HMC_Pos (2U)
+#define ETH_MACPFR_HMC_Msk (0x1U << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /*!< Hash Multicast */
+#define ETH_MACPFR_DAIF_Pos (3U)
+#define ETH_MACPFR_DAIF_Msk (0x1U << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /*!< DA Inverse Filtering */
+#define ETH_MACPFR_PM_Pos (4U)
+#define ETH_MACPFR_PM_Msk (0x1U << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /*!< Pass All Multicast */
+#define ETH_MACPFR_DBF_Pos (5U)
+#define ETH_MACPFR_DBF_Msk (0x1U << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /*!< Disable Broadcast Packets */
+#define ETH_MACPFR_PCF_Pos (6U)
+#define ETH_MACPFR_PCF_Msk (0x3U << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */
+#define ETH_MACPFR_PCF_0 (0x1U << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_1 (0x2U << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_SAIF_Pos (8U)
+#define ETH_MACPFR_SAIF_Msk (0x1U << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */
+#define ETH_MACPFR_SAF_Pos (9U)
+#define ETH_MACPFR_SAF_Msk (0x1U << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /*!< Source Address Filter Enable */
+#define ETH_MACPFR_HPF_Pos (10U)
+#define ETH_MACPFR_HPF_Msk (0x1U << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /*!< Hash or Perfect Filter */
+#define ETH_MACPFR_VTFE_Pos (16U)
+#define ETH_MACPFR_VTFE_Msk (0x1U << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /*!< VLAN Tag Filter Enable */
+#define ETH_MACPFR_IPFE_Pos (20U)
+#define ETH_MACPFR_IPFE_Msk (0x1U << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /*!< Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_DNTU_Pos (21U)
+#define ETH_MACPFR_DNTU_Msk (0x1U << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_RA_Pos (31U)
+#define ETH_MACPFR_RA_Msk (0x1U << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /*!< Receive All */
+
+/************** Bit definition for ETH_MACWTR register ***************/
+#define ETH_MACWTR_WTO_Pos (0U)
+#define ETH_MACWTR_WTO_Msk (0xFU << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */
+#define ETH_MACWTR_WTO_0 (0x1U << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */
+#define ETH_MACWTR_WTO_1 (0x2U << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */
+#define ETH_MACWTR_WTO_2 (0x4U << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */
+#define ETH_MACWTR_WTO_3 (0x8U << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */
+#define ETH_MACWTR_PWE_Pos (8U)
+#define ETH_MACWTR_PWE_Msk (0x1U << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */
+
+/************** Bit definition for ETH_MACHT0R register **************/
+#define ETH_MACHT0R_HT31T0_Pos (0U)
+#define ETH_MACHT0R_HT31T0_Msk (0xFFFFFFFFU << ETH_MACHT0R_HT31T0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT0R_HT31T0 ETH_MACHT0R_HT31T0_Msk /*!< MAC Hash Table First 32 Bits */
+#define ETH_MACHT0R_HT31T0_0 (0x1U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000001 */
+#define ETH_MACHT0R_HT31T0_1 (0x2U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000002 */
+#define ETH_MACHT0R_HT31T0_2 (0x4U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000004 */
+#define ETH_MACHT0R_HT31T0_3 (0x8U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000008 */
+#define ETH_MACHT0R_HT31T0_4 (0x10U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000010 */
+#define ETH_MACHT0R_HT31T0_5 (0x20U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000020 */
+#define ETH_MACHT0R_HT31T0_6 (0x40U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000040 */
+#define ETH_MACHT0R_HT31T0_7 (0x80U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000080 */
+#define ETH_MACHT0R_HT31T0_8 (0x100U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000100 */
+#define ETH_MACHT0R_HT31T0_9 (0x200U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000200 */
+#define ETH_MACHT0R_HT31T0_10 (0x400U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000400 */
+#define ETH_MACHT0R_HT31T0_11 (0x800U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000800 */
+#define ETH_MACHT0R_HT31T0_12 (0x1000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00001000 */
+#define ETH_MACHT0R_HT31T0_13 (0x2000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00002000 */
+#define ETH_MACHT0R_HT31T0_14 (0x4000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00004000 */
+#define ETH_MACHT0R_HT31T0_15 (0x8000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00008000 */
+#define ETH_MACHT0R_HT31T0_16 (0x10000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00010000 */
+#define ETH_MACHT0R_HT31T0_17 (0x20000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00020000 */
+#define ETH_MACHT0R_HT31T0_18 (0x40000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00040000 */
+#define ETH_MACHT0R_HT31T0_19 (0x80000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00080000 */
+#define ETH_MACHT0R_HT31T0_20 (0x100000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00100000 */
+#define ETH_MACHT0R_HT31T0_21 (0x200000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00200000 */
+#define ETH_MACHT0R_HT31T0_22 (0x400000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00400000 */
+#define ETH_MACHT0R_HT31T0_23 (0x800000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00800000 */
+#define ETH_MACHT0R_HT31T0_24 (0x1000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x01000000 */
+#define ETH_MACHT0R_HT31T0_25 (0x2000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x02000000 */
+#define ETH_MACHT0R_HT31T0_26 (0x4000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x04000000 */
+#define ETH_MACHT0R_HT31T0_27 (0x8000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x08000000 */
+#define ETH_MACHT0R_HT31T0_28 (0x10000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x10000000 */
+#define ETH_MACHT0R_HT31T0_29 (0x20000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x20000000 */
+#define ETH_MACHT0R_HT31T0_30 (0x40000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x40000000 */
+#define ETH_MACHT0R_HT31T0_31 (0x80000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACHT1R register **************/
+#define ETH_MACHT1R_HT63T32_Pos (0U)
+#define ETH_MACHT1R_HT63T32_Msk (0xFFFFFFFFU << ETH_MACHT1R_HT63T32_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHT1R_HT63T32 ETH_MACHT1R_HT63T32_Msk /*!< MAC Hash Table Second 32 Bits */
+#define ETH_MACHT1R_HT63T32_0 (0x1U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000001 */
+#define ETH_MACHT1R_HT63T32_1 (0x2U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000002 */
+#define ETH_MACHT1R_HT63T32_2 (0x4U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000004 */
+#define ETH_MACHT1R_HT63T32_3 (0x8U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000008 */
+#define ETH_MACHT1R_HT63T32_4 (0x10U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000010 */
+#define ETH_MACHT1R_HT63T32_5 (0x20U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000020 */
+#define ETH_MACHT1R_HT63T32_6 (0x40U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000040 */
+#define ETH_MACHT1R_HT63T32_7 (0x80U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000080 */
+#define ETH_MACHT1R_HT63T32_8 (0x100U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000100 */
+#define ETH_MACHT1R_HT63T32_9 (0x200U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000200 */
+#define ETH_MACHT1R_HT63T32_10 (0x400U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000400 */
+#define ETH_MACHT1R_HT63T32_11 (0x800U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000800 */
+#define ETH_MACHT1R_HT63T32_12 (0x1000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00001000 */
+#define ETH_MACHT1R_HT63T32_13 (0x2000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00002000 */
+#define ETH_MACHT1R_HT63T32_14 (0x4000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00004000 */
+#define ETH_MACHT1R_HT63T32_15 (0x8000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00008000 */
+#define ETH_MACHT1R_HT63T32_16 (0x10000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00010000 */
+#define ETH_MACHT1R_HT63T32_17 (0x20000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00020000 */
+#define ETH_MACHT1R_HT63T32_18 (0x40000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00040000 */
+#define ETH_MACHT1R_HT63T32_19 (0x80000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00080000 */
+#define ETH_MACHT1R_HT63T32_20 (0x100000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00100000 */
+#define ETH_MACHT1R_HT63T32_21 (0x200000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00200000 */
+#define ETH_MACHT1R_HT63T32_22 (0x400000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00400000 */
+#define ETH_MACHT1R_HT63T32_23 (0x800000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00800000 */
+#define ETH_MACHT1R_HT63T32_24 (0x1000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x01000000 */
+#define ETH_MACHT1R_HT63T32_25 (0x2000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x02000000 */
+#define ETH_MACHT1R_HT63T32_26 (0x4000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x04000000 */
+#define ETH_MACHT1R_HT63T32_27 (0x8000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x08000000 */
+#define ETH_MACHT1R_HT63T32_28 (0x10000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x10000000 */
+#define ETH_MACHT1R_HT63T32_29 (0x20000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x20000000 */
+#define ETH_MACHT1R_HT63T32_30 (0x40000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x40000000 */
+#define ETH_MACHT1R_HT63T32_31 (0x80000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACVTR register ***************/
+#define ETH_MACVTR_VL_Pos (0U)
+#define ETH_MACVTR_VL_Msk (0xFFFFU << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */
+#define ETH_MACVTR_VL_0 (0x1U << ETH_MACVTR_VL_Pos) /*!< 0x00000001 */
+#define ETH_MACVTR_VL_1 (0x2U << ETH_MACVTR_VL_Pos) /*!< 0x00000002 */
+#define ETH_MACVTR_VL_2 (0x4U << ETH_MACVTR_VL_Pos) /*!< 0x00000004 */
+#define ETH_MACVTR_VL_3 (0x8U << ETH_MACVTR_VL_Pos) /*!< 0x00000008 */
+#define ETH_MACVTR_VL_4 (0x10U << ETH_MACVTR_VL_Pos) /*!< 0x00000010 */
+#define ETH_MACVTR_VL_5 (0x20U << ETH_MACVTR_VL_Pos) /*!< 0x00000020 */
+#define ETH_MACVTR_VL_6 (0x40U << ETH_MACVTR_VL_Pos) /*!< 0x00000040 */
+#define ETH_MACVTR_VL_7 (0x80U << ETH_MACVTR_VL_Pos) /*!< 0x00000080 */
+#define ETH_MACVTR_VL_8 (0x100U << ETH_MACVTR_VL_Pos) /*!< 0x00000100 */
+#define ETH_MACVTR_VL_9 (0x200U << ETH_MACVTR_VL_Pos) /*!< 0x00000200 */
+#define ETH_MACVTR_VL_10 (0x400U << ETH_MACVTR_VL_Pos) /*!< 0x00000400 */
+#define ETH_MACVTR_VL_11 (0x800U << ETH_MACVTR_VL_Pos) /*!< 0x00000800 */
+#define ETH_MACVTR_VL_12 (0x1000U << ETH_MACVTR_VL_Pos) /*!< 0x00001000 */
+#define ETH_MACVTR_VL_13 (0x2000U << ETH_MACVTR_VL_Pos) /*!< 0x00002000 */
+#define ETH_MACVTR_VL_14 (0x4000U << ETH_MACVTR_VL_Pos) /*!< 0x00004000 */
+#define ETH_MACVTR_VL_15 (0x8000U << ETH_MACVTR_VL_Pos) /*!< 0x00008000 */
+#define ETH_MACVTR_ETV_Pos (16U)
+#define ETH_MACVTR_ETV_Msk (0x1U << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTR_VTIM_Pos (17U)
+#define ETH_MACVTR_VTIM_Msk (0x1U << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /*!< VLAN Tag Inverse Match Enable */
+#define ETH_MACVTR_ESVL_Pos (18U)
+#define ETH_MACVTR_ESVL_Msk (0x1U << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */
+#define ETH_MACVTR_ERSVLM_Pos (19U)
+#define ETH_MACVTR_ERSVLM_Msk (0x1U << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */
+#define ETH_MACVTR_DOVLTC_Pos (20U)
+#define ETH_MACVTR_DOVLTC_Msk (0x1U << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /*!< Disable VLAN Type Check */
+#define ETH_MACVTR_EVLS_Pos (21U)
+#define ETH_MACVTR_EVLS_Msk (0x3U << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EVLS_0 (0x1U << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTR_EVLS_1 (0x2U << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTR_EVLRXS_Pos (24U)
+#define ETH_MACVTR_EVLRXS_Msk (0x1U << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */
+#define ETH_MACVTR_VTHM_Pos (25U)
+#define ETH_MACVTR_VTHM_Msk (0x1U << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /*!< VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTR_EDVLP_Pos (26U)
+#define ETH_MACVTR_EDVLP_Msk (0x1U << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /*!< Enable Double VLAN Processing */
+#define ETH_MACVTR_ERIVLT_Pos (27U)
+#define ETH_MACVTR_ERIVLT_Msk (0x1U << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /*!< Enable Inner VLAN Tag */
+#define ETH_MACVTR_EIVLS_Pos (28U)
+#define ETH_MACVTR_EIVLS_Msk (0x3U << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EIVLS_0 (0x1U << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTR_EIVLS_1 (0x2U << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTR_EIVLRXS_Pos (31U)
+#define ETH_MACVTR_EIVLRXS_Msk (0x1U << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */
+
+/************** Bit definition for ETH_MACVHTR register **************/
+#define ETH_MACVHTR_VLHT_Pos (0U)
+#define ETH_MACVHTR_VLHT_Msk (0xFFFFU << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /*!< VLAN Hash Table */
+#define ETH_MACVHTR_VLHT_0 (0x1U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000001 */
+#define ETH_MACVHTR_VLHT_1 (0x2U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000002 */
+#define ETH_MACVHTR_VLHT_2 (0x4U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000004 */
+#define ETH_MACVHTR_VLHT_3 (0x8U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000008 */
+#define ETH_MACVHTR_VLHT_4 (0x10U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000010 */
+#define ETH_MACVHTR_VLHT_5 (0x20U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000020 */
+#define ETH_MACVHTR_VLHT_6 (0x40U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000040 */
+#define ETH_MACVHTR_VLHT_7 (0x80U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000080 */
+#define ETH_MACVHTR_VLHT_8 (0x100U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000100 */
+#define ETH_MACVHTR_VLHT_9 (0x200U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000200 */
+#define ETH_MACVHTR_VLHT_10 (0x400U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000400 */
+#define ETH_MACVHTR_VLHT_11 (0x800U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000800 */
+#define ETH_MACVHTR_VLHT_12 (0x1000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00001000 */
+#define ETH_MACVHTR_VLHT_13 (0x2000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00002000 */
+#define ETH_MACVHTR_VLHT_14 (0x4000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00004000 */
+#define ETH_MACVHTR_VLHT_15 (0x8000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00008000 */
+
+/************** Bit definition for ETH_MACVIR register ***************/
+#define ETH_MACVIR_VLT_Pos (0U)
+#define ETH_MACVIR_VLT_Msk (0xFFFFU << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_0 (0x1U << ETH_MACVIR_VLT_Pos) /*!< 0x00000001 */
+#define ETH_MACVIR_VLT_1 (0x2U << ETH_MACVIR_VLT_Pos) /*!< 0x00000002 */
+#define ETH_MACVIR_VLT_2 (0x4U << ETH_MACVIR_VLT_Pos) /*!< 0x00000004 */
+#define ETH_MACVIR_VLT_3 (0x8U << ETH_MACVIR_VLT_Pos) /*!< 0x00000008 */
+#define ETH_MACVIR_VLT_4 (0x10U << ETH_MACVIR_VLT_Pos) /*!< 0x00000010 */
+#define ETH_MACVIR_VLT_5 (0x20U << ETH_MACVIR_VLT_Pos) /*!< 0x00000020 */
+#define ETH_MACVIR_VLT_6 (0x40U << ETH_MACVIR_VLT_Pos) /*!< 0x00000040 */
+#define ETH_MACVIR_VLT_7 (0x80U << ETH_MACVIR_VLT_Pos) /*!< 0x00000080 */
+#define ETH_MACVIR_VLT_8 (0x100U << ETH_MACVIR_VLT_Pos) /*!< 0x00000100 */
+#define ETH_MACVIR_VLT_9 (0x200U << ETH_MACVIR_VLT_Pos) /*!< 0x00000200 */
+#define ETH_MACVIR_VLT_10 (0x400U << ETH_MACVIR_VLT_Pos) /*!< 0x00000400 */
+#define ETH_MACVIR_VLT_11 (0x800U << ETH_MACVIR_VLT_Pos) /*!< 0x00000800 */
+#define ETH_MACVIR_VLT_12 (0x1000U << ETH_MACVIR_VLT_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_13 (0x2000U << ETH_MACVIR_VLT_Pos) /*!< 0x00002000 */
+#define ETH_MACVIR_VLT_14 (0x4000U << ETH_MACVIR_VLT_Pos) /*!< 0x00004000 */
+#define ETH_MACVIR_VLT_15 (0x8000U << ETH_MACVIR_VLT_Pos) /*!< 0x00008000 */
+#define ETH_MACVIR_VLC_Pos (16U)
+#define ETH_MACVIR_VLC_Msk (0x3U << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_0 (0x1U << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_1 (0x2U << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLP_Pos (18U)
+#define ETH_MACVIR_VLP_Msk (0x1U << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */
+#define ETH_MACVIR_CSVL_Pos (19U)
+#define ETH_MACVIR_CSVL_Msk (0x1U << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLTI_Pos (20U)
+#define ETH_MACVIR_VLTI_Msk (0x1U << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /*!< VLAN Tag Input */
+
+/************** Bit definition for ETH_MACIVIR register **************/
+#define ETH_MACIVIR_VLT_Pos (0U)
+#define ETH_MACIVIR_VLT_Msk (0xFFFFU << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_0 (0x1U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000001 */
+#define ETH_MACIVIR_VLT_1 (0x2U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000002 */
+#define ETH_MACIVIR_VLT_2 (0x4U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000004 */
+#define ETH_MACIVIR_VLT_3 (0x8U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000008 */
+#define ETH_MACIVIR_VLT_4 (0x10U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000010 */
+#define ETH_MACIVIR_VLT_5 (0x20U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000020 */
+#define ETH_MACIVIR_VLT_6 (0x40U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000040 */
+#define ETH_MACIVIR_VLT_7 (0x80U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000080 */
+#define ETH_MACIVIR_VLT_8 (0x100U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000100 */
+#define ETH_MACIVIR_VLT_9 (0x200U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000200 */
+#define ETH_MACIVIR_VLT_10 (0x400U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000400 */
+#define ETH_MACIVIR_VLT_11 (0x800U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000800 */
+#define ETH_MACIVIR_VLT_12 (0x1000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_13 (0x2000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00002000 */
+#define ETH_MACIVIR_VLT_14 (0x4000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00004000 */
+#define ETH_MACIVIR_VLT_15 (0x8000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00008000 */
+#define ETH_MACIVIR_VLC_Pos (16U)
+#define ETH_MACIVIR_VLC_Msk (0x3U << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_0 (0x1U << ETH_MACIVIR_VLC_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_1 (0x2U << ETH_MACIVIR_VLC_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLP_Pos (18U)
+#define ETH_MACIVIR_VLP_Msk (0x1U << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /*!< VLAN Priority Control */
+#define ETH_MACIVIR_CSVL_Pos (19U)
+#define ETH_MACIVIR_CSVL_Msk (0x1U << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLTI_Pos (20U)
+#define ETH_MACIVIR_VLTI_Msk (0x1U << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /*!< VLAN Tag Input */
+
+/************ Bit definition for ETH_MACQ0TXFCR register *************/
+#define ETH_MACQ0TXFCR_FCB_BPA_Pos (0U)
+#define ETH_MACQ0TXFCR_FCB_BPA_Msk (0x1U << ETH_MACQ0TXFCR_FCB_BPA_Pos) /*!< 0x00000001 */
+#define ETH_MACQ0TXFCR_FCB_BPA ETH_MACQ0TXFCR_FCB_BPA_Msk /*!< Flow Control Busy or Backpressure Activate */
+#define ETH_MACQ0TXFCR_TFE_Pos (1U)
+#define ETH_MACQ0TXFCR_TFE_Msk (0x1U << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACQ0TXFCR_TFE ETH_MACQ0TXFCR_TFE_Msk /*!< Transmit Flow Control Enable */
+#define ETH_MACQ0TXFCR_PLT_Pos (4U)
+#define ETH_MACQ0TXFCR_PLT_Msk (0x7U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */
+#define ETH_MACQ0TXFCR_PLT_0 (0x1U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */
+#define ETH_MACQ0TXFCR_PLT_1 (0x2U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */
+#define ETH_MACQ0TXFCR_PLT_2 (0x4U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */
+#define ETH_MACQ0TXFCR_DZPQ_Pos (7U)
+#define ETH_MACQ0TXFCR_DZPQ_Msk (0x1U << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */
+#define ETH_MACQ0TXFCR_PT_Pos (16U)
+#define ETH_MACQ0TXFCR_PT_Msk (0xFFFFU << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACQ0TXFCR_PT ETH_MACQ0TXFCR_PT_Msk /*!< Pause Time */
+#define ETH_MACQ0TXFCR_PT_0 (0x1U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00010000 */
+#define ETH_MACQ0TXFCR_PT_1 (0x2U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00020000 */
+#define ETH_MACQ0TXFCR_PT_2 (0x4U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00040000 */
+#define ETH_MACQ0TXFCR_PT_3 (0x8U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00080000 */
+#define ETH_MACQ0TXFCR_PT_4 (0x10U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00100000 */
+#define ETH_MACQ0TXFCR_PT_5 (0x20U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00200000 */
+#define ETH_MACQ0TXFCR_PT_6 (0x40U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00400000 */
+#define ETH_MACQ0TXFCR_PT_7 (0x80U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00800000 */
+#define ETH_MACQ0TXFCR_PT_8 (0x100U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x01000000 */
+#define ETH_MACQ0TXFCR_PT_9 (0x200U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x02000000 */
+#define ETH_MACQ0TXFCR_PT_10 (0x400U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x04000000 */
+#define ETH_MACQ0TXFCR_PT_11 (0x800U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x08000000 */
+#define ETH_MACQ0TXFCR_PT_12 (0x1000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x10000000 */
+#define ETH_MACQ0TXFCR_PT_13 (0x2000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x20000000 */
+#define ETH_MACQ0TXFCR_PT_14 (0x4000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x40000000 */
+#define ETH_MACQ0TXFCR_PT_15 (0x8000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACRXFCR register **************/
+#define ETH_MACRXFCR_RFE_Pos (0U)
+#define ETH_MACRXFCR_RFE_Msk (0x1U << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRXFCR_RFE ETH_MACRXFCR_RFE_Msk /*!< Receive Flow Control Enable */
+#define ETH_MACRXFCR_UP_Pos (1U)
+#define ETH_MACRXFCR_UP_Msk (0x1U << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRXFCR_UP ETH_MACRXFCR_UP_Msk /*!< Unicast Pause Packet Detect */
+
+/************* Bit definition for ETH_MACTXQPMR register *************/
+#define ETH_MACTXQPMR_PSTQ0_Pos (0U)
+#define ETH_MACTXQPMR_PSTQ0_Msk (0xFFU << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x000000FF */
+#define ETH_MACTXQPMR_PSTQ0 ETH_MACTXQPMR_PSTQ0_Msk /*!< Priorities Selected in Transmit Queue 0 */
+#define ETH_MACTXQPMR_PSTQ0_0 (0x1U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000001 */
+#define ETH_MACTXQPMR_PSTQ0_1 (0x2U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000002 */
+#define ETH_MACTXQPMR_PSTQ0_2 (0x4U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000004 */
+#define ETH_MACTXQPMR_PSTQ0_3 (0x8U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000008 */
+#define ETH_MACTXQPMR_PSTQ0_4 (0x10U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000010 */
+#define ETH_MACTXQPMR_PSTQ0_5 (0x20U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000020 */
+#define ETH_MACTXQPMR_PSTQ0_6 (0x40U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000040 */
+#define ETH_MACTXQPMR_PSTQ0_7 (0x80U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000080 */
+#define ETH_MACTXQPMR_PSTQ1_Pos (8U)
+#define ETH_MACTXQPMR_PSTQ1_Msk (0xFFU << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x0000FF00 */
+#define ETH_MACTXQPMR_PSTQ1 ETH_MACTXQPMR_PSTQ1_Msk /*!< Priorities Selected in Transmit Queue 1 */
+#define ETH_MACTXQPMR_PSTQ1_0 (0x1U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000100 */
+#define ETH_MACTXQPMR_PSTQ1_1 (0x2U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000200 */
+#define ETH_MACTXQPMR_PSTQ1_2 (0x4U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000400 */
+#define ETH_MACTXQPMR_PSTQ1_3 (0x8U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000800 */
+#define ETH_MACTXQPMR_PSTQ1_4 (0x10U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00001000 */
+#define ETH_MACTXQPMR_PSTQ1_5 (0x20U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00002000 */
+#define ETH_MACTXQPMR_PSTQ1_6 (0x40U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00004000 */
+#define ETH_MACTXQPMR_PSTQ1_7 (0x80U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00008000 */
+
+/************* Bit definition for ETH_MACRXQC0R register *************/
+#define ETH_MACRXQC0R_RXQ0EN_Pos (0U)
+#define ETH_MACRXQC0R_RXQ0EN_Msk (0x3U << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
+#define ETH_MACRXQC0R_RXQ0EN ETH_MACRXQC0R_RXQ0EN_Msk /*!< Receive Queue 0 Enable */
+#define ETH_MACRXQC0R_RXQ0EN_0 (0x1U << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC0R_RXQ0EN_1 (0x2U << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQC0R_RXQ1EN_Pos (2U)
+#define ETH_MACRXQC0R_RXQ1EN_Msk (0x3U << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
+#define ETH_MACRXQC0R_RXQ1EN ETH_MACRXQC0R_RXQ1EN_Msk /*!< Receive Queue 1 Enable */
+#define ETH_MACRXQC0R_RXQ1EN_0 (0x1U << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x00000004 */
+#define ETH_MACRXQC0R_RXQ1EN_1 (0x2U << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x00000008 */
+
+/************* Bit definition for ETH_MACRXQC1R register *************/
+#define ETH_MACRXQC1R_AVCPQ_Pos (0U)
+#define ETH_MACRXQC1R_AVCPQ_Msk (0x7U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
+#define ETH_MACRXQC1R_AVCPQ ETH_MACRXQC1R_AVCPQ_Msk /*!< AV Untagged Control Packets Queue */
+#define ETH_MACRXQC1R_AVCPQ_0 (0x1U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC1R_AVCPQ_1 (0x2U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQC1R_AVCPQ_2 (0x4U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000004 */
+#define ETH_MACRXQC1R_AVPTPQ_Pos (4U)
+#define ETH_MACRXQC1R_AVPTPQ_Msk (0x7U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000070 */
+#define ETH_MACRXQC1R_AVPTPQ ETH_MACRXQC1R_AVPTPQ_Msk /*!< AV PTP Packets Queue */
+#define ETH_MACRXQC1R_AVPTPQ_0 (0x1U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000010 */
+#define ETH_MACRXQC1R_AVPTPQ_1 (0x2U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000020 */
+#define ETH_MACRXQC1R_AVPTPQ_2 (0x4U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000040 */
+#define ETH_MACRXQC1R_UPQ_Pos (12U)
+#define ETH_MACRXQC1R_UPQ_Msk (0x7U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
+#define ETH_MACRXQC1R_UPQ ETH_MACRXQC1R_UPQ_Msk /*!< Untagged Packet Queue */
+#define ETH_MACRXQC1R_UPQ_0 (0x1U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00001000 */
+#define ETH_MACRXQC1R_UPQ_1 (0x2U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00002000 */
+#define ETH_MACRXQC1R_UPQ_2 (0x4U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00004000 */
+#define ETH_MACRXQC1R_MCBCQ_Pos (16U)
+#define ETH_MACRXQC1R_MCBCQ_Msk (0x7U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
+#define ETH_MACRXQC1R_MCBCQ ETH_MACRXQC1R_MCBCQ_Msk /*!< Multicast and Broadcast Queue */
+#define ETH_MACRXQC1R_MCBCQ_0 (0x1U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00010000 */
+#define ETH_MACRXQC1R_MCBCQ_1 (0x2U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00020000 */
+#define ETH_MACRXQC1R_MCBCQ_2 (0x4U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00040000 */
+#define ETH_MACRXQC1R_MCBCQEN_Pos (20U)
+#define ETH_MACRXQC1R_MCBCQEN_Msk (0x1U << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
+#define ETH_MACRXQC1R_MCBCQEN ETH_MACRXQC1R_MCBCQEN_Msk /*!< Multicast and Broadcast Queue Enable */
+#define ETH_MACRXQC1R_TACPQE_Pos (21U)
+#define ETH_MACRXQC1R_TACPQE_Msk (0x1U << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
+#define ETH_MACRXQC1R_TACPQE ETH_MACRXQC1R_TACPQE_Msk /*!< Tagged AV Control Packets Queuing Enable. */
+
+/************* Bit definition for ETH_MACRXQC2R register *************/
+#define ETH_MACRXQC2R_PSRQ0_Pos (0U)
+#define ETH_MACRXQC2R_PSRQ0_Msk (0xFFU << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
+#define ETH_MACRXQC2R_PSRQ0 ETH_MACRXQC2R_PSRQ0_Msk /*!< Priorities Selected in the Receive Queue 0 */
+#define ETH_MACRXQC2R_PSRQ0_0 (0x1U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000001 */
+#define ETH_MACRXQC2R_PSRQ0_1 (0x2U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000002 */
+#define ETH_MACRXQC2R_PSRQ0_2 (0x4U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000004 */
+#define ETH_MACRXQC2R_PSRQ0_3 (0x8U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000008 */
+#define ETH_MACRXQC2R_PSRQ0_4 (0x10U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000010 */
+#define ETH_MACRXQC2R_PSRQ0_5 (0x20U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000020 */
+#define ETH_MACRXQC2R_PSRQ0_6 (0x40U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000040 */
+#define ETH_MACRXQC2R_PSRQ0_7 (0x80U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000080 */
+#define ETH_MACRXQC2R_PSRQ1_Pos (8U)
+#define ETH_MACRXQC2R_PSRQ1_Msk (0xFFU << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
+#define ETH_MACRXQC2R_PSRQ1 ETH_MACRXQC2R_PSRQ1_Msk /*!< Priorities Selected in the Receive Queue 1 */
+#define ETH_MACRXQC2R_PSRQ1_0 (0x1U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000100 */
+#define ETH_MACRXQC2R_PSRQ1_1 (0x2U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000200 */
+#define ETH_MACRXQC2R_PSRQ1_2 (0x4U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000400 */
+#define ETH_MACRXQC2R_PSRQ1_3 (0x8U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000800 */
+#define ETH_MACRXQC2R_PSRQ1_4 (0x10U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00001000 */
+#define ETH_MACRXQC2R_PSRQ1_5 (0x20U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00002000 */
+#define ETH_MACRXQC2R_PSRQ1_6 (0x40U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00004000 */
+#define ETH_MACRXQC2R_PSRQ1_7 (0x80U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00008000 */
+
+/************** Bit definition for ETH_MACISR register ***************/
+#define ETH_MACISR_RGSMIIIS_Pos (0U)
+#define ETH_MACISR_RGSMIIIS_Msk (0x1U << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
+#define ETH_MACISR_RGSMIIIS ETH_MACISR_RGSMIIIS_Msk /*!< RGMII or SMII Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos (3U)
+#define ETH_MACISR_PHYIS_Msk (0x1U << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /*!< PHY Interrupt */
+#define ETH_MACISR_PMTIS_Pos (4U)
+#define ETH_MACISR_PMTIS_Msk (0x1U << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /*!< PMT Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos (5U)
+#define ETH_MACISR_LPIIS_Msk (0x1U << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /*!< LPI Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos (8U)
+#define ETH_MACISR_MMCIS_Msk (0x1U << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /*!< MMC Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos (9U)
+#define ETH_MACISR_MMCRXIS_Msk (0x1U << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /*!< MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos (10U)
+#define ETH_MACISR_MMCTXIS_Msk (0x1U << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /*!< MMC Transmit Interrupt Status */
+#define ETH_MACISR_TSIS_Pos (12U)
+#define ETH_MACISR_TSIS_Msk (0x1U << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /*!< Timestamp Interrupt Status */
+#define ETH_MACISR_TXSTSIS_Pos (13U)
+#define ETH_MACISR_TXSTSIS_Msk (0x1U << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /*!< Transmit Status Interrupt */
+#define ETH_MACISR_RXSTSIS_Pos (14U)
+#define ETH_MACISR_RXSTSIS_Msk (0x1U << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /*!< Receive Status Interrupt */
+
+/************** Bit definition for ETH_MACIER register ***************/
+#define ETH_MACIER_RGSMIIIE_Pos (0U)
+#define ETH_MACIER_RGSMIIIE_Msk (0x1U << ETH_MACIER_RGSMIIIE_Pos) /*!< 0x00000001 */
+#define ETH_MACIER_RGSMIIIE ETH_MACIER_RGSMIIIE_Msk /*!< RGMII or SMII Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos (3U)
+#define ETH_MACIER_PHYIE_Msk (0x1U << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /*!< PHY Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos (4U)
+#define ETH_MACIER_PMTIE_Msk (0x1U << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /*!< PMT Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos (5U)
+#define ETH_MACIER_LPIIE_Msk (0x1U << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /*!< LPI Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos (12U)
+#define ETH_MACIER_TSIE_Msk (0x1U << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /*!< Timestamp Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos (13U)
+#define ETH_MACIER_TXSTSIE_Msk (0x1U << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /*!< Transmit Status Interrupt Enable */
+#define ETH_MACIER_RXSTSIE_Pos (14U)
+#define ETH_MACIER_RXSTSIE_Msk (0x1U << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /*!< Receive Status Interrupt Enable */
+
+/************* Bit definition for ETH_MACRXTXSR register *************/
+#define ETH_MACRXTXSR_TJT_Pos (0U)
+#define ETH_MACRXTXSR_TJT_Msk (0x1U << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /*!< Transmit Jabber Timeout */
+#define ETH_MACRXTXSR_NCARR_Pos (1U)
+#define ETH_MACRXTXSR_NCARR_Msk (0x1U << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /*!< No Carrier */
+#define ETH_MACRXTXSR_LCARR_Pos (2U)
+#define ETH_MACRXTXSR_LCARR_Msk (0x1U << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /*!< Loss of Carrier */
+#define ETH_MACRXTXSR_EXDEF_Pos (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk (0x1U << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /*!< Excessive Deferral */
+#define ETH_MACRXTXSR_LCOL_Pos (4U)
+#define ETH_MACRXTXSR_LCOL_Msk (0x1U << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /*!< Late Collision */
+#define ETH_MACRXTXSR_EXCOL_Pos (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk (0x1U << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /*!< Excessive Collisions */
+#define ETH_MACRXTXSR_RWT_Pos (8U)
+#define ETH_MACRXTXSR_RWT_Msk (0x1U << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /*!< Receive Watchdog Timeout */
+
+/************** Bit definition for ETH_MACPCSR register **************/
+#define ETH_MACPCSR_PWRDWN_Pos (0U)
+#define ETH_MACPCSR_PWRDWN_Msk (0x1U << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /*!< Power Down */
+#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk (0x1U << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /*!< Magic Packet Enable */
+#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk (0x1U << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /*!< Remote wakeup Packet Enable */
+#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk (0x1U << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /*!< Magic Packet Received */
+#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk (0x1U << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /*!< Remote wakeup Packet Received */
+#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk (0x1U << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /*!< Global Unicast */
+#define ETH_MACPCSR_RWKPFE_Pos (10U)
+#define ETH_MACPCSR_RWKPFE_Msk (0x1U << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /*!< Remote wakeup Packet Forwarding Enable */
+#define ETH_MACPCSR_RWKPTR_Pos (24U)
+#define ETH_MACPCSR_RWKPTR_Msk (0x1FU << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /*!< Remote wakeup FIFO Pointer */
+#define ETH_MACPCSR_RWKPTR_0 (0x1U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x01000000 */
+#define ETH_MACPCSR_RWKPTR_1 (0x2U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x02000000 */
+#define ETH_MACPCSR_RWKPTR_2 (0x4U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x04000000 */
+#define ETH_MACPCSR_RWKPTR_3 (0x8U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x08000000 */
+#define ETH_MACPCSR_RWKPTR_4 (0x10U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x10000000 */
+#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk (0x1U << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /*!< Remote wakeup Packet Filter Register Pointer Reset */
+
+/************* Bit definition for ETH_MACRWKPFR register *************/
+#define ETH_MACRWKPFR_MACRWKPFR_Pos (0U)
+#define ETH_MACRWKPFR_MACRWKPFR_Msk (0xFFFFFFFFU << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWKPFR_MACRWKPFR ETH_MACRWKPFR_MACRWKPFR_Msk /*!< Remote wakeup packet filter */
+#define ETH_MACRWKPFR_MACRWKPFR_0 (0x1U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000001 */
+#define ETH_MACRWKPFR_MACRWKPFR_1 (0x2U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000002 */
+#define ETH_MACRWKPFR_MACRWKPFR_2 (0x4U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000004 */
+#define ETH_MACRWKPFR_MACRWKPFR_3 (0x8U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000008 */
+#define ETH_MACRWKPFR_MACRWKPFR_4 (0x10U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000010 */
+#define ETH_MACRWKPFR_MACRWKPFR_5 (0x20U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000020 */
+#define ETH_MACRWKPFR_MACRWKPFR_6 (0x40U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000040 */
+#define ETH_MACRWKPFR_MACRWKPFR_7 (0x80U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000080 */
+#define ETH_MACRWKPFR_MACRWKPFR_8 (0x100U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000100 */
+#define ETH_MACRWKPFR_MACRWKPFR_9 (0x200U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000200 */
+#define ETH_MACRWKPFR_MACRWKPFR_10 (0x400U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000400 */
+#define ETH_MACRWKPFR_MACRWKPFR_11 (0x800U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000800 */
+#define ETH_MACRWKPFR_MACRWKPFR_12 (0x1000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00001000 */
+#define ETH_MACRWKPFR_MACRWKPFR_13 (0x2000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00002000 */
+#define ETH_MACRWKPFR_MACRWKPFR_14 (0x4000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00004000 */
+#define ETH_MACRWKPFR_MACRWKPFR_15 (0x8000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00008000 */
+#define ETH_MACRWKPFR_MACRWKPFR_16 (0x10000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00010000 */
+#define ETH_MACRWKPFR_MACRWKPFR_17 (0x20000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00020000 */
+#define ETH_MACRWKPFR_MACRWKPFR_18 (0x40000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00040000 */
+#define ETH_MACRWKPFR_MACRWKPFR_19 (0x80000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00080000 */
+#define ETH_MACRWKPFR_MACRWKPFR_20 (0x100000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00100000 */
+#define ETH_MACRWKPFR_MACRWKPFR_21 (0x200000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00200000 */
+#define ETH_MACRWKPFR_MACRWKPFR_22 (0x400000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00400000 */
+#define ETH_MACRWKPFR_MACRWKPFR_23 (0x800000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00800000 */
+#define ETH_MACRWKPFR_MACRWKPFR_24 (0x1000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x01000000 */
+#define ETH_MACRWKPFR_MACRWKPFR_25 (0x2000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x02000000 */
+#define ETH_MACRWKPFR_MACRWKPFR_26 (0x4000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x04000000 */
+#define ETH_MACRWKPFR_MACRWKPFR_27 (0x8000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x08000000 */
+#define ETH_MACRWKPFR_MACRWKPFR_28 (0x10000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x10000000 */
+#define ETH_MACRWKPFR_MACRWKPFR_29 (0x20000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x20000000 */
+#define ETH_MACRWKPFR_MACRWKPFR_30 (0x40000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x40000000 */
+#define ETH_MACRWKPFR_MACRWKPFR_31 (0x80000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACLCSR register **************/
+#define ETH_MACLCSR_TLPIEN_Pos (0U)
+#define ETH_MACLCSR_TLPIEN_Msk (0x1U << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /*!< Transmit LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos (1U)
+#define ETH_MACLCSR_TLPIEX_Msk (0x1U << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /*!< Transmit LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos (2U)
+#define ETH_MACLCSR_RLPIEN_Msk (0x1U << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /*!< Receive LPI Entry */
+#define ETH_MACLCSR_RLPIEX_Pos (3U)
+#define ETH_MACLCSR_RLPIEX_Msk (0x1U << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /*!< Receive LPI Exit */
+#define ETH_MACLCSR_TLPIST_Pos (8U)
+#define ETH_MACLCSR_TLPIST_Msk (0x1U << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /*!< Transmit LPI State */
+#define ETH_MACLCSR_RLPIST_Pos (9U)
+#define ETH_MACLCSR_RLPIST_Msk (0x1U << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /*!< Receive LPI State */
+#define ETH_MACLCSR_LPIEN_Pos (16U)
+#define ETH_MACLCSR_LPIEN_Msk (0x1U << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /*!< LPI Enable */
+#define ETH_MACLCSR_PLS_Pos (17U)
+#define ETH_MACLCSR_PLS_Msk (0x1U << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /*!< PHY Link Status */
+#define ETH_MACLCSR_PLSEN_Pos (18U)
+#define ETH_MACLCSR_PLSEN_Msk (0x1U << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
+#define ETH_MACLCSR_PLSEN ETH_MACLCSR_PLSEN_Msk /*!< PHY Link Status Enable */
+#define ETH_MACLCSR_LPITXA_Pos (19U)
+#define ETH_MACLCSR_LPITXA_Msk (0x1U << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /*!< LPI Tx Automate */
+#define ETH_MACLCSR_LPITE_Pos (20U)
+#define ETH_MACLCSR_LPITE_Msk (0x1U << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */
+
+/************** Bit definition for ETH_MACLTCR register **************/
+#define ETH_MACLTCR_TWT_Pos (0U)
+#define ETH_MACLTCR_TWT_Msk (0xFFFFU << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /*!< LPI TW Timer */
+#define ETH_MACLTCR_TWT_0 (0x1U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000001 */
+#define ETH_MACLTCR_TWT_1 (0x2U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000002 */
+#define ETH_MACLTCR_TWT_2 (0x4U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000004 */
+#define ETH_MACLTCR_TWT_3 (0x8U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000008 */
+#define ETH_MACLTCR_TWT_4 (0x10U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000010 */
+#define ETH_MACLTCR_TWT_5 (0x20U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000020 */
+#define ETH_MACLTCR_TWT_6 (0x40U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000040 */
+#define ETH_MACLTCR_TWT_7 (0x80U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000080 */
+#define ETH_MACLTCR_TWT_8 (0x100U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000100 */
+#define ETH_MACLTCR_TWT_9 (0x200U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000200 */
+#define ETH_MACLTCR_TWT_10 (0x400U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000400 */
+#define ETH_MACLTCR_TWT_11 (0x800U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000800 */
+#define ETH_MACLTCR_TWT_12 (0x1000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00001000 */
+#define ETH_MACLTCR_TWT_13 (0x2000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00002000 */
+#define ETH_MACLTCR_TWT_14 (0x4000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00004000 */
+#define ETH_MACLTCR_TWT_15 (0x8000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00008000 */
+#define ETH_MACLTCR_LST_Pos (16U)
+#define ETH_MACLTCR_LST_Msk (0x3FFU << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /*!< LPI LS Timer */
+#define ETH_MACLTCR_LST_0 (0x1U << ETH_MACLTCR_LST_Pos) /*!< 0x00010000 */
+#define ETH_MACLTCR_LST_1 (0x2U << ETH_MACLTCR_LST_Pos) /*!< 0x00020000 */
+#define ETH_MACLTCR_LST_2 (0x4U << ETH_MACLTCR_LST_Pos) /*!< 0x00040000 */
+#define ETH_MACLTCR_LST_3 (0x8U << ETH_MACLTCR_LST_Pos) /*!< 0x00080000 */
+#define ETH_MACLTCR_LST_4 (0x10U << ETH_MACLTCR_LST_Pos) /*!< 0x00100000 */
+#define ETH_MACLTCR_LST_5 (0x20U << ETH_MACLTCR_LST_Pos) /*!< 0x00200000 */
+#define ETH_MACLTCR_LST_6 (0x40U << ETH_MACLTCR_LST_Pos) /*!< 0x00400000 */
+#define ETH_MACLTCR_LST_7 (0x80U << ETH_MACLTCR_LST_Pos) /*!< 0x00800000 */
+#define ETH_MACLTCR_LST_8 (0x100U << ETH_MACLTCR_LST_Pos) /*!< 0x01000000 */
+#define ETH_MACLTCR_LST_9 (0x200U << ETH_MACLTCR_LST_Pos) /*!< 0x02000000 */
+
+/************** Bit definition for ETH_MACLETR register **************/
+#define ETH_MACLETR_LPIET_Pos (3U)
+#define ETH_MACLETR_LPIET_Msk (0x1FFFFU << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFF8 */
+#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /*!< LPI Entry Timer */
+#define ETH_MACLETR_LPIET_0 (0x1U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000008 */
+#define ETH_MACLETR_LPIET_1 (0x2U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000010 */
+#define ETH_MACLETR_LPIET_2 (0x4U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000020 */
+#define ETH_MACLETR_LPIET_3 (0x8U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000040 */
+#define ETH_MACLETR_LPIET_4 (0x10U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000080 */
+#define ETH_MACLETR_LPIET_5 (0x20U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000100 */
+#define ETH_MACLETR_LPIET_6 (0x40U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000200 */
+#define ETH_MACLETR_LPIET_7 (0x80U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000400 */
+#define ETH_MACLETR_LPIET_8 (0x100U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000800 */
+#define ETH_MACLETR_LPIET_9 (0x200U << ETH_MACLETR_LPIET_Pos) /*!< 0x00001000 */
+#define ETH_MACLETR_LPIET_10 (0x400U << ETH_MACLETR_LPIET_Pos) /*!< 0x00002000 */
+#define ETH_MACLETR_LPIET_11 (0x800U << ETH_MACLETR_LPIET_Pos) /*!< 0x00004000 */
+#define ETH_MACLETR_LPIET_12 (0x1000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00008000 */
+#define ETH_MACLETR_LPIET_13 (0x2000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00010000 */
+#define ETH_MACLETR_LPIET_14 (0x4000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00020000 */
+#define ETH_MACLETR_LPIET_15 (0x8000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00040000 */
+#define ETH_MACLETR_LPIET_16 (0x10000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00080000 */
+
+/************* Bit definition for ETH_MAC1USTCR register *************/
+#define ETH_MAC1USTCR_TIC_1US_CNTR_Pos (0U)
+#define ETH_MAC1USTCR_TIC_1US_CNTR_Msk (0xFFFU << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC_1US_CNTR ETH_MAC1USTCR_TIC_1US_CNTR_Msk /*!< 1 µs tick Counter */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_0 (0x1U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000001 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_1 (0x2U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000002 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_2 (0x4U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000004 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_3 (0x8U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000008 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_4 (0x10U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000010 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_5 (0x20U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000020 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_6 (0x40U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000040 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_7 (0x80U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000080 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_8 (0x100U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000100 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_9 (0x200U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000200 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_10 (0x400U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000400 */
+#define ETH_MAC1USTCR_TIC_1US_CNTR_11 (0x800U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000800 */
+
+/************* Bit definition for ETH_MACPHYCSR register *************/
+#define ETH_MACPHYCSR_TC_Pos (0U)
+#define ETH_MACPHYCSR_TC_Msk (0x1U << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
+#define ETH_MACPHYCSR_TC ETH_MACPHYCSR_TC_Msk /*!< Transmit Configuration in RGMII, SGMII, or SMII */
+#define ETH_MACPHYCSR_LUD_Pos (1U)
+#define ETH_MACPHYCSR_LUD_Msk (0x1U << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
+#define ETH_MACPHYCSR_LUD ETH_MACPHYCSR_LUD_Msk /*!< Link Up or Down */
+#define ETH_MACPHYCSR_LNKMOD_Pos (16U)
+#define ETH_MACPHYCSR_LNKMOD_Msk (0x1U << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00010000 */
+#define ETH_MACPHYCSR_LNKMOD ETH_MACPHYCSR_LNKMOD_Msk /*!< Link Mode */
+#define ETH_MACPHYCSR_LNKSPEED_Pos (17U)
+#define ETH_MACPHYCSR_LNKSPEED_Msk (0x3U << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
+#define ETH_MACPHYCSR_LNKSPEED ETH_MACPHYCSR_LNKSPEED_Msk /*!< Link Speed */
+#define ETH_MACPHYCSR_LNKSPEED_0 (0x1U << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00020000 */
+#define ETH_MACPHYCSR_LNKSPEED_1 (0x2U << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00040000 */
+#define ETH_MACPHYCSR_LNKSTS_Pos (19U)
+#define ETH_MACPHYCSR_LNKSTS_Msk (0x1U << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
+#define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */
+#define ETH_MACPHYCSR_JABTO_Pos (20U)
+#define ETH_MACPHYCSR_JABTO_Msk (0x1U << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */
+#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */
+#define ETH_MACPHYCSR_FALSCARDET_Pos (21U)
+#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1U << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */
+#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */
+
+/*************** Bit definition for ETH_MACVR register ***************/
+#define ETH_MACVR_SNPSVER_Pos (0U)
+#define ETH_MACVR_SNPSVER_Msk (0xFFU << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /*!< IP version */
+#define ETH_MACVR_SNPSVER_0 (0x1U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000001 */
+#define ETH_MACVR_SNPSVER_1 (0x2U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000002 */
+#define ETH_MACVR_SNPSVER_2 (0x4U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000004 */
+#define ETH_MACVR_SNPSVER_3 (0x8U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000008 */
+#define ETH_MACVR_SNPSVER_4 (0x10U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000010 */
+#define ETH_MACVR_SNPSVER_5 (0x20U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000020 */
+#define ETH_MACVR_SNPSVER_6 (0x40U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000040 */
+#define ETH_MACVR_SNPSVER_7 (0x80U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000080 */
+#define ETH_MACVR_USERVER_Pos (8U)
+#define ETH_MACVR_USERVER_Msk (0xFFU << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /*!< ST-defined version */
+#define ETH_MACVR_USERVER_0 (0x1U << ETH_MACVR_USERVER_Pos) /*!< 0x00000100 */
+#define ETH_MACVR_USERVER_1 (0x2U << ETH_MACVR_USERVER_Pos) /*!< 0x00000200 */
+#define ETH_MACVR_USERVER_2 (0x4U << ETH_MACVR_USERVER_Pos) /*!< 0x00000400 */
+#define ETH_MACVR_USERVER_3 (0x8U << ETH_MACVR_USERVER_Pos) /*!< 0x00000800 */
+#define ETH_MACVR_USERVER_4 (0x10U << ETH_MACVR_USERVER_Pos) /*!< 0x00001000 */
+#define ETH_MACVR_USERVER_5 (0x20U << ETH_MACVR_USERVER_Pos) /*!< 0x00002000 */
+#define ETH_MACVR_USERVER_6 (0x40U << ETH_MACVR_USERVER_Pos) /*!< 0x00004000 */
+#define ETH_MACVR_USERVER_7 (0x80U << ETH_MACVR_USERVER_Pos) /*!< 0x00008000 */
+
+/*************** Bit definition for ETH_MACDR register ***************/
+#define ETH_MACDR_RPESTS_Pos (0U)
+#define ETH_MACDR_RPESTS_Msk (0x1U << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /*!< MAC GMII or MII Receive Protocol Engine Status */
+#define ETH_MACDR_RFCFCSTS_Pos (1U)
+#define ETH_MACDR_RFCFCSTS_Msk (0x3U << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /*!< MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_0 (0x1U << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000002 */
+#define ETH_MACDR_RFCFCSTS_1 (0x2U << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000004 */
+#define ETH_MACDR_TPESTS_Pos (16U)
+#define ETH_MACDR_TPESTS_Msk (0x1U << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /*!< MAC GMII or MII Transmit Protocol Engine Status */
+#define ETH_MACDR_TFCSTS_Pos (17U)
+#define ETH_MACDR_TFCSTS_Msk (0x3U << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /*!< MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_0 (0x1U << ETH_MACDR_TFCSTS_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_1 (0x2U << ETH_MACDR_TFCSTS_Pos) /*!< 0x00040000 */
+
+/************* Bit definition for ETH_MACHWF1R register **************/
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FU << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /*!< MTL Receive FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_0 (0x1U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF1R_RXFIFOSIZE_1 (0x2U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF1R_RXFIFOSIZE_2 (0x4U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF1R_RXFIFOSIZE_3 (0x8U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF1R_RXFIFOSIZE_4 (0x10U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FU << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /*!< MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_TXFIFOSIZE_0 (0x1U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF1R_TXFIFOSIZE_1 (0x2U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF1R_TXFIFOSIZE_2 (0x4U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF1R_TXFIFOSIZE_3 (0x8U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF1R_TXFIFOSIZE_4 (0x10U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000400 */
+#define ETH_MACHWF1R_OSTEN_Pos (11U)
+#define ETH_MACHWF1R_OSTEN_Msk (0x1U << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Enable */
+#define ETH_MACHWF1R_PTOEN_Pos (12U)
+#define ETH_MACHWF1R_PTOEN_Msk (0x1U << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /*!< PTP Offload Enable */
+#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1U << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /*!< IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_ADDR64_Pos (14U)
+#define ETH_MACHWF1R_ADDR64_Msk (0x3U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /*!< Address width */
+#define ETH_MACHWF1R_ADDR64_0 (0x1U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_1 (0x2U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_DCBEN_Pos (16U)
+#define ETH_MACHWF1R_DCBEN_Msk (0x1U << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /*!< DCB Feature Enable */
+#define ETH_MACHWF1R_SPHEN_Pos (17U)
+#define ETH_MACHWF1R_SPHEN_Msk (0x1U << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /*!< Split Header Feature Enable */
+#define ETH_MACHWF1R_TSOEN_Pos (18U)
+#define ETH_MACHWF1R_TSOEN_Msk (0x1U << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /*!< TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk (0x1U << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /*!< DMA Debug Registers Enable */
+#define ETH_MACHWF1R_AVSEL_Pos (20U)
+#define ETH_MACHWF1R_AVSEL_Msk (0x1U << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /*!< AV Feature Enable */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3U << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /*!< Hash Table Size */
+#define ETH_MACHWF1R_HASHTBLSZ_0 (0x1U << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF1R_HASHTBLSZ_1 (0x2U << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFU << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /*!< Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_L3L4FNUM_0 (0x1U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF1R_L3L4FNUM_1 (0x2U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF1R_L3L4FNUM_2 (0x4U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF1R_L3L4FNUM_3 (0x8U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x40000000 */
+
+/************* Bit definition for ETH_MACHWF2R register **************/
+#define ETH_MACHWF2R_RXQCNT_Pos (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk (0xFU << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /*!< Number of MTL Receive Queues */
+#define ETH_MACHWF2R_RXQCNT_0 (0x1U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF2R_RXQCNT_1 (0x2U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF2R_RXQCNT_2 (0x4U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF2R_RXQCNT_3 (0x8U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF2R_TXQCNT_Pos (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk (0xFU << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /*!< Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_TXQCNT_0 (0x1U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF2R_TXQCNT_1 (0x2U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF2R_TXQCNT_2 (0x4U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF2R_TXQCNT_3 (0x8U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF2R_RXCHCNT_Pos (12U)
+#define ETH_MACHWF2R_RXCHCNT_Msk (0xFU << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
+#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /*!< Number of DMA Receive Channels */
+#define ETH_MACHWF2R_RXCHCNT_0 (0x1U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF2R_RXCHCNT_1 (0x2U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF2R_RXCHCNT_2 (0x4U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF2R_RXCHCNT_3 (0x8U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk (0xFU << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /*!< Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_TXCHCNT_0 (0x1U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF2R_TXCHCNT_1 (0x2U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF2R_TXCHCNT_2 (0x4U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF2R_TXCHCNT_3 (0x8U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00200000 */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /*!< Number of PPS Outputs */
+#define ETH_MACHWF2R_PPSOUTNUM_0 (0x1U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF2R_PPSOUTNUM_1 (0x2U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF2R_PPSOUTNUM_2 (0x4U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /*!< Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_AUXSNAPNUM_0 (0x1U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x10000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM_1 (0x2U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x20000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM_2 (0x4U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x40000000 */
+
+/************* Bit definition for ETH_MACMDIOAR register *************/
+#define ETH_MACMDIOAR_GB_Pos (0U)
+#define ETH_MACMDIOAR_GB_Msk (0x1U << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_GB ETH_MACMDIOAR_GB_Msk /*!< GMII Busy */
+#define ETH_MACMDIOAR_C45E_Pos (1U)
+#define ETH_MACMDIOAR_C45E_Msk (0x1U << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /*!< Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_GOC_Pos (2U)
+#define ETH_MACMDIOAR_GOC_Msk (0x3U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_GOC ETH_MACMDIOAR_GOC_Msk /*!< GMII Operation Command */
+#define ETH_MACMDIOAR_GOC_0 (0x1U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIOAR_GOC_1 (0x2U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIOAR_SKAP_Pos (4U)
+#define ETH_MACMDIOAR_SKAP_Msk (0x1U << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /*!< Skip Address Packet */
+#define ETH_MACMDIOAR_CR_Pos (8U)
+#define ETH_MACMDIOAR_CR_Msk (0xFU << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */
+#define ETH_MACMDIOAR_CR_0 (0x1U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_1 (0x2U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_2 (0x4U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_3 (0x8U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_NTC_Pos (12U)
+#define ETH_MACMDIOAR_NTC_Msk (0x7U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */
+#define ETH_MACMDIOAR_NTC_0 (0x1U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00001000 */
+#define ETH_MACMDIOAR_NTC_1 (0x2U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00002000 */
+#define ETH_MACMDIOAR_NTC_2 (0x4U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00004000 */
+#define ETH_MACMDIOAR_RDA_Pos (16U)
+#define ETH_MACMDIOAR_RDA_Msk (0x1FU << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /*!< Register/Device Address */
+#define ETH_MACMDIOAR_RDA_0 (0x1U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00010000 */
+#define ETH_MACMDIOAR_RDA_1 (0x2U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00020000 */
+#define ETH_MACMDIOAR_RDA_2 (0x4U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00040000 */
+#define ETH_MACMDIOAR_RDA_3 (0x8U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00080000 */
+#define ETH_MACMDIOAR_RDA_4 (0x10U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00100000 */
+#define ETH_MACMDIOAR_PA_Pos (21U)
+#define ETH_MACMDIOAR_PA_Msk (0x1FU << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /*!< Physical Layer Address */
+#define ETH_MACMDIOAR_PA_0 (0x1U << ETH_MACMDIOAR_PA_Pos) /*!< 0x00200000 */
+#define ETH_MACMDIOAR_PA_1 (0x2U << ETH_MACMDIOAR_PA_Pos) /*!< 0x00400000 */
+#define ETH_MACMDIOAR_PA_2 (0x4U << ETH_MACMDIOAR_PA_Pos) /*!< 0x00800000 */
+#define ETH_MACMDIOAR_PA_3 (0x8U << ETH_MACMDIOAR_PA_Pos) /*!< 0x01000000 */
+#define ETH_MACMDIOAR_PA_4 (0x10U << ETH_MACMDIOAR_PA_Pos) /*!< 0x02000000 */
+#define ETH_MACMDIOAR_BTB_Pos (26U)
+#define ETH_MACMDIOAR_BTB_Msk (0x1U << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /*!< Back to Back transactions */
+#define ETH_MACMDIOAR_PSE_Pos (27U)
+#define ETH_MACMDIOAR_PSE_Msk (0x1U << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /*!< Preamble Suppression Enable */
+
+/************* Bit definition for ETH_MACMDIODR register *************/
+#define ETH_MACMDIODR_GD_Pos (0U)
+#define ETH_MACMDIODR_GD_Msk (0xFFFFU << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_GD ETH_MACMDIODR_GD_Msk /*!< GMII Data */
+#define ETH_MACMDIODR_GD_0 (0x1U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIODR_GD_1 (0x2U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIODR_GD_2 (0x4U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIODR_GD_3 (0x8U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIODR_GD_4 (0x10U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIODR_GD_5 (0x20U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000020 */
+#define ETH_MACMDIODR_GD_6 (0x40U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000040 */
+#define ETH_MACMDIODR_GD_7 (0x80U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000080 */
+#define ETH_MACMDIODR_GD_8 (0x100U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIODR_GD_9 (0x200U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIODR_GD_10 (0x400U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIODR_GD_11 (0x800U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIODR_GD_12 (0x1000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00001000 */
+#define ETH_MACMDIODR_GD_13 (0x2000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00002000 */
+#define ETH_MACMDIODR_GD_14 (0x4000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00004000 */
+#define ETH_MACMDIODR_GD_15 (0x8000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00008000 */
+#define ETH_MACMDIODR_RA_Pos (16U)
+#define ETH_MACMDIODR_RA_Msk (0xFFFFU << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /*!< Register Address */
+#define ETH_MACMDIODR_RA_0 (0x1U << ETH_MACMDIODR_RA_Pos) /*!< 0x00010000 */
+#define ETH_MACMDIODR_RA_1 (0x2U << ETH_MACMDIODR_RA_Pos) /*!< 0x00020000 */
+#define ETH_MACMDIODR_RA_2 (0x4U << ETH_MACMDIODR_RA_Pos) /*!< 0x00040000 */
+#define ETH_MACMDIODR_RA_3 (0x8U << ETH_MACMDIODR_RA_Pos) /*!< 0x00080000 */
+#define ETH_MACMDIODR_RA_4 (0x10U << ETH_MACMDIODR_RA_Pos) /*!< 0x00100000 */
+#define ETH_MACMDIODR_RA_5 (0x20U << ETH_MACMDIODR_RA_Pos) /*!< 0x00200000 */
+#define ETH_MACMDIODR_RA_6 (0x40U << ETH_MACMDIODR_RA_Pos) /*!< 0x00400000 */
+#define ETH_MACMDIODR_RA_7 (0x80U << ETH_MACMDIODR_RA_Pos) /*!< 0x00800000 */
+#define ETH_MACMDIODR_RA_8 (0x100U << ETH_MACMDIODR_RA_Pos) /*!< 0x01000000 */
+#define ETH_MACMDIODR_RA_9 (0x200U << ETH_MACMDIODR_RA_Pos) /*!< 0x02000000 */
+#define ETH_MACMDIODR_RA_10 (0x400U << ETH_MACMDIODR_RA_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIODR_RA_11 (0x800U << ETH_MACMDIODR_RA_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIODR_RA_12 (0x1000U << ETH_MACMDIODR_RA_Pos) /*!< 0x10000000 */
+#define ETH_MACMDIODR_RA_13 (0x2000U << ETH_MACMDIODR_RA_Pos) /*!< 0x20000000 */
+#define ETH_MACMDIODR_RA_14 (0x4000U << ETH_MACMDIODR_RA_Pos) /*!< 0x40000000 */
+#define ETH_MACMDIODR_RA_15 (0x8000U << ETH_MACMDIODR_RA_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACA0HR register **************/
+#define ETH_MACA0HR_ADDRHI_Pos (0U)
+#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFU << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /*!< MAC Address0[47:32] */
+#define ETH_MACA0HR_ADDRHI_0 (0x1U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000001 */
+#define ETH_MACA0HR_ADDRHI_1 (0x2U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000002 */
+#define ETH_MACA0HR_ADDRHI_2 (0x4U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000004 */
+#define ETH_MACA0HR_ADDRHI_3 (0x8U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000008 */
+#define ETH_MACA0HR_ADDRHI_4 (0x10U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000010 */
+#define ETH_MACA0HR_ADDRHI_5 (0x20U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000020 */
+#define ETH_MACA0HR_ADDRHI_6 (0x40U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000040 */
+#define ETH_MACA0HR_ADDRHI_7 (0x80U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000080 */
+#define ETH_MACA0HR_ADDRHI_8 (0x100U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000100 */
+#define ETH_MACA0HR_ADDRHI_9 (0x200U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000200 */
+#define ETH_MACA0HR_ADDRHI_10 (0x400U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000400 */
+#define ETH_MACA0HR_ADDRHI_11 (0x800U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000800 */
+#define ETH_MACA0HR_ADDRHI_12 (0x1000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00001000 */
+#define ETH_MACA0HR_ADDRHI_13 (0x2000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00002000 */
+#define ETH_MACA0HR_ADDRHI_14 (0x4000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00004000 */
+#define ETH_MACA0HR_ADDRHI_15 (0x8000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00008000 */
+#define ETH_MACA0HR_AE_Pos (31U)
+#define ETH_MACA0HR_AE_Msk (0x1U << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /*!< Address Enable */
+
+/************** Bit definition for ETH_MACA0LR register **************/
+#define ETH_MACA0LR_ADDRLO_Pos (0U)
+#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
+#define ETH_MACA0LR_ADDRLO_0 (0x1U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000001 */
+#define ETH_MACA0LR_ADDRLO_1 (0x2U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000002 */
+#define ETH_MACA0LR_ADDRLO_2 (0x4U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000004 */
+#define ETH_MACA0LR_ADDRLO_3 (0x8U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000008 */
+#define ETH_MACA0LR_ADDRLO_4 (0x10U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000010 */
+#define ETH_MACA0LR_ADDRLO_5 (0x20U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000020 */
+#define ETH_MACA0LR_ADDRLO_6 (0x40U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000040 */
+#define ETH_MACA0LR_ADDRLO_7 (0x80U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000080 */
+#define ETH_MACA0LR_ADDRLO_8 (0x100U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000100 */
+#define ETH_MACA0LR_ADDRLO_9 (0x200U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000200 */
+#define ETH_MACA0LR_ADDRLO_10 (0x400U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000400 */
+#define ETH_MACA0LR_ADDRLO_11 (0x800U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000800 */
+#define ETH_MACA0LR_ADDRLO_12 (0x1000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00001000 */
+#define ETH_MACA0LR_ADDRLO_13 (0x2000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00002000 */
+#define ETH_MACA0LR_ADDRLO_14 (0x4000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00004000 */
+#define ETH_MACA0LR_ADDRLO_15 (0x8000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00008000 */
+#define ETH_MACA0LR_ADDRLO_16 (0x10000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00010000 */
+#define ETH_MACA0LR_ADDRLO_17 (0x20000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00020000 */
+#define ETH_MACA0LR_ADDRLO_18 (0x40000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00040000 */
+#define ETH_MACA0LR_ADDRLO_19 (0x80000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00080000 */
+#define ETH_MACA0LR_ADDRLO_20 (0x100000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00100000 */
+#define ETH_MACA0LR_ADDRLO_21 (0x200000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00200000 */
+#define ETH_MACA0LR_ADDRLO_22 (0x400000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00400000 */
+#define ETH_MACA0LR_ADDRLO_23 (0x800000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00800000 */
+#define ETH_MACA0LR_ADDRLO_24 (0x1000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x01000000 */
+#define ETH_MACA0LR_ADDRLO_25 (0x2000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x02000000 */
+#define ETH_MACA0LR_ADDRLO_26 (0x4000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x04000000 */
+#define ETH_MACA0LR_ADDRLO_27 (0x8000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x08000000 */
+#define ETH_MACA0LR_ADDRLO_28 (0x10000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x10000000 */
+#define ETH_MACA0LR_ADDRLO_29 (0x20000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x20000000 */
+#define ETH_MACA0LR_ADDRLO_30 (0x40000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x40000000 */
+#define ETH_MACA0LR_ADDRLO_31 (0x80000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACA1HR register **************/
+#define ETH_MACA1HR_ADDRHI_Pos (0U)
+#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFU << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */
+#define ETH_MACA1HR_ADDRHI_0 (0x1U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000001 */
+#define ETH_MACA1HR_ADDRHI_1 (0x2U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000002 */
+#define ETH_MACA1HR_ADDRHI_2 (0x4U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000004 */
+#define ETH_MACA1HR_ADDRHI_3 (0x8U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000008 */
+#define ETH_MACA1HR_ADDRHI_4 (0x10U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000010 */
+#define ETH_MACA1HR_ADDRHI_5 (0x20U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000020 */
+#define ETH_MACA1HR_ADDRHI_6 (0x40U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000040 */
+#define ETH_MACA1HR_ADDRHI_7 (0x80U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000080 */
+#define ETH_MACA1HR_ADDRHI_8 (0x100U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000100 */
+#define ETH_MACA1HR_ADDRHI_9 (0x200U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000200 */
+#define ETH_MACA1HR_ADDRHI_10 (0x400U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000400 */
+#define ETH_MACA1HR_ADDRHI_11 (0x800U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000800 */
+#define ETH_MACA1HR_ADDRHI_12 (0x1000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00001000 */
+#define ETH_MACA1HR_ADDRHI_13 (0x2000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00002000 */
+#define ETH_MACA1HR_ADDRHI_14 (0x4000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00004000 */
+#define ETH_MACA1HR_ADDRHI_15 (0x8000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00008000 */
+#define ETH_MACA1HR_MBC_Pos (24U)
+#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /*!< Mask Byte Control */
+#define ETH_MACA1HR_MBC_0 (0x1U << ETH_MACA1HR_MBC_Pos) /*!< 0x01000000 */
+#define ETH_MACA1HR_MBC_1 (0x2U << ETH_MACA1HR_MBC_Pos) /*!< 0x02000000 */
+#define ETH_MACA1HR_MBC_2 (0x4U << ETH_MACA1HR_MBC_Pos) /*!< 0x04000000 */
+#define ETH_MACA1HR_MBC_3 (0x8U << ETH_MACA1HR_MBC_Pos) /*!< 0x08000000 */
+#define ETH_MACA1HR_MBC_4 (0x10U << ETH_MACA1HR_MBC_Pos) /*!< 0x10000000 */
+#define ETH_MACA1HR_MBC_5 (0x20U << ETH_MACA1HR_MBC_Pos) /*!< 0x20000000 */
+#define ETH_MACA1HR_SA_Pos (30U)
+#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /*!< Source Address */
+#define ETH_MACA1HR_AE_Pos (31U)
+#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /*!< Address Enable */
+
+/************** Bit definition for ETH_MACA1LR register **************/
+#define ETH_MACA1LR_ADDRLO_Pos (0U)
+#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
+#define ETH_MACA1LR_ADDRLO_0 (0x1U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000001 */
+#define ETH_MACA1LR_ADDRLO_1 (0x2U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000002 */
+#define ETH_MACA1LR_ADDRLO_2 (0x4U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000004 */
+#define ETH_MACA1LR_ADDRLO_3 (0x8U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000008 */
+#define ETH_MACA1LR_ADDRLO_4 (0x10U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000010 */
+#define ETH_MACA1LR_ADDRLO_5 (0x20U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000020 */
+#define ETH_MACA1LR_ADDRLO_6 (0x40U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000040 */
+#define ETH_MACA1LR_ADDRLO_7 (0x80U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000080 */
+#define ETH_MACA1LR_ADDRLO_8 (0x100U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000100 */
+#define ETH_MACA1LR_ADDRLO_9 (0x200U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000200 */
+#define ETH_MACA1LR_ADDRLO_10 (0x400U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000400 */
+#define ETH_MACA1LR_ADDRLO_11 (0x800U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000800 */
+#define ETH_MACA1LR_ADDRLO_12 (0x1000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00001000 */
+#define ETH_MACA1LR_ADDRLO_13 (0x2000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00002000 */
+#define ETH_MACA1LR_ADDRLO_14 (0x4000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00004000 */
+#define ETH_MACA1LR_ADDRLO_15 (0x8000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00008000 */
+#define ETH_MACA1LR_ADDRLO_16 (0x10000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00010000 */
+#define ETH_MACA1LR_ADDRLO_17 (0x20000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00020000 */
+#define ETH_MACA1LR_ADDRLO_18 (0x40000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00040000 */
+#define ETH_MACA1LR_ADDRLO_19 (0x80000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00080000 */
+#define ETH_MACA1LR_ADDRLO_20 (0x100000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00100000 */
+#define ETH_MACA1LR_ADDRLO_21 (0x200000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00200000 */
+#define ETH_MACA1LR_ADDRLO_22 (0x400000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00400000 */
+#define ETH_MACA1LR_ADDRLO_23 (0x800000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00800000 */
+#define ETH_MACA1LR_ADDRLO_24 (0x1000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x01000000 */
+#define ETH_MACA1LR_ADDRLO_25 (0x2000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x02000000 */
+#define ETH_MACA1LR_ADDRLO_26 (0x4000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x04000000 */
+#define ETH_MACA1LR_ADDRLO_27 (0x8000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x08000000 */
+#define ETH_MACA1LR_ADDRLO_28 (0x10000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x10000000 */
+#define ETH_MACA1LR_ADDRLO_29 (0x20000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x20000000 */
+#define ETH_MACA1LR_ADDRLO_30 (0x40000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x40000000 */
+#define ETH_MACA1LR_ADDRLO_31 (0x80000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACA2HR register **************/
+#define ETH_MACA2HR_ADDRHI_Pos (0U)
+#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFU << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */
+#define ETH_MACA2HR_ADDRHI_0 (0x1U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000001 */
+#define ETH_MACA2HR_ADDRHI_1 (0x2U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000002 */
+#define ETH_MACA2HR_ADDRHI_2 (0x4U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000004 */
+#define ETH_MACA2HR_ADDRHI_3 (0x8U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000008 */
+#define ETH_MACA2HR_ADDRHI_4 (0x10U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000010 */
+#define ETH_MACA2HR_ADDRHI_5 (0x20U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000020 */
+#define ETH_MACA2HR_ADDRHI_6 (0x40U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000040 */
+#define ETH_MACA2HR_ADDRHI_7 (0x80U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000080 */
+#define ETH_MACA2HR_ADDRHI_8 (0x100U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000100 */
+#define ETH_MACA2HR_ADDRHI_9 (0x200U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000200 */
+#define ETH_MACA2HR_ADDRHI_10 (0x400U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000400 */
+#define ETH_MACA2HR_ADDRHI_11 (0x800U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000800 */
+#define ETH_MACA2HR_ADDRHI_12 (0x1000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00001000 */
+#define ETH_MACA2HR_ADDRHI_13 (0x2000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00002000 */
+#define ETH_MACA2HR_ADDRHI_14 (0x4000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00004000 */
+#define ETH_MACA2HR_ADDRHI_15 (0x8000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00008000 */
+#define ETH_MACA2HR_MBC_Pos (24U)
+#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /*!< Mask Byte Control */
+#define ETH_MACA2HR_MBC_0 (0x1U << ETH_MACA2HR_MBC_Pos) /*!< 0x01000000 */
+#define ETH_MACA2HR_MBC_1 (0x2U << ETH_MACA2HR_MBC_Pos) /*!< 0x02000000 */
+#define ETH_MACA2HR_MBC_2 (0x4U << ETH_MACA2HR_MBC_Pos) /*!< 0x04000000 */
+#define ETH_MACA2HR_MBC_3 (0x8U << ETH_MACA2HR_MBC_Pos) /*!< 0x08000000 */
+#define ETH_MACA2HR_MBC_4 (0x10U << ETH_MACA2HR_MBC_Pos) /*!< 0x10000000 */
+#define ETH_MACA2HR_MBC_5 (0x20U << ETH_MACA2HR_MBC_Pos) /*!< 0x20000000 */
+#define ETH_MACA2HR_SA_Pos (30U)
+#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /*!< Source Address */
+#define ETH_MACA2HR_AE_Pos (31U)
+#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /*!< Address Enable */
+
+/************** Bit definition for ETH_MACA2LR register **************/
+#define ETH_MACA2LR_ADDRLO_Pos (0U)
+#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
+#define ETH_MACA2LR_ADDRLO_0 (0x1U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000001 */
+#define ETH_MACA2LR_ADDRLO_1 (0x2U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000002 */
+#define ETH_MACA2LR_ADDRLO_2 (0x4U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000004 */
+#define ETH_MACA2LR_ADDRLO_3 (0x8U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000008 */
+#define ETH_MACA2LR_ADDRLO_4 (0x10U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000010 */
+#define ETH_MACA2LR_ADDRLO_5 (0x20U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000020 */
+#define ETH_MACA2LR_ADDRLO_6 (0x40U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000040 */
+#define ETH_MACA2LR_ADDRLO_7 (0x80U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000080 */
+#define ETH_MACA2LR_ADDRLO_8 (0x100U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000100 */
+#define ETH_MACA2LR_ADDRLO_9 (0x200U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000200 */
+#define ETH_MACA2LR_ADDRLO_10 (0x400U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000400 */
+#define ETH_MACA2LR_ADDRLO_11 (0x800U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000800 */
+#define ETH_MACA2LR_ADDRLO_12 (0x1000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00001000 */
+#define ETH_MACA2LR_ADDRLO_13 (0x2000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00002000 */
+#define ETH_MACA2LR_ADDRLO_14 (0x4000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00004000 */
+#define ETH_MACA2LR_ADDRLO_15 (0x8000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00008000 */
+#define ETH_MACA2LR_ADDRLO_16 (0x10000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00010000 */
+#define ETH_MACA2LR_ADDRLO_17 (0x20000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00020000 */
+#define ETH_MACA2LR_ADDRLO_18 (0x40000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00040000 */
+#define ETH_MACA2LR_ADDRLO_19 (0x80000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00080000 */
+#define ETH_MACA2LR_ADDRLO_20 (0x100000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00100000 */
+#define ETH_MACA2LR_ADDRLO_21 (0x200000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00200000 */
+#define ETH_MACA2LR_ADDRLO_22 (0x400000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00400000 */
+#define ETH_MACA2LR_ADDRLO_23 (0x800000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00800000 */
+#define ETH_MACA2LR_ADDRLO_24 (0x1000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x01000000 */
+#define ETH_MACA2LR_ADDRLO_25 (0x2000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x02000000 */
+#define ETH_MACA2LR_ADDRLO_26 (0x4000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x04000000 */
+#define ETH_MACA2LR_ADDRLO_27 (0x8000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x08000000 */
+#define ETH_MACA2LR_ADDRLO_28 (0x10000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x10000000 */
+#define ETH_MACA2LR_ADDRLO_29 (0x20000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x20000000 */
+#define ETH_MACA2LR_ADDRLO_30 (0x40000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x40000000 */
+#define ETH_MACA2LR_ADDRLO_31 (0x80000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACA3HR register **************/
+#define ETH_MACA3HR_ADDRHI_Pos (0U)
+#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFU << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */
+#define ETH_MACA3HR_ADDRHI_0 (0x1U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000001 */
+#define ETH_MACA3HR_ADDRHI_1 (0x2U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000002 */
+#define ETH_MACA3HR_ADDRHI_2 (0x4U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000004 */
+#define ETH_MACA3HR_ADDRHI_3 (0x8U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000008 */
+#define ETH_MACA3HR_ADDRHI_4 (0x10U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000010 */
+#define ETH_MACA3HR_ADDRHI_5 (0x20U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000020 */
+#define ETH_MACA3HR_ADDRHI_6 (0x40U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000040 */
+#define ETH_MACA3HR_ADDRHI_7 (0x80U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000080 */
+#define ETH_MACA3HR_ADDRHI_8 (0x100U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000100 */
+#define ETH_MACA3HR_ADDRHI_9 (0x200U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000200 */
+#define ETH_MACA3HR_ADDRHI_10 (0x400U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000400 */
+#define ETH_MACA3HR_ADDRHI_11 (0x800U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000800 */
+#define ETH_MACA3HR_ADDRHI_12 (0x1000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00001000 */
+#define ETH_MACA3HR_ADDRHI_13 (0x2000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00002000 */
+#define ETH_MACA3HR_ADDRHI_14 (0x4000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00004000 */
+#define ETH_MACA3HR_ADDRHI_15 (0x8000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00008000 */
+#define ETH_MACA3HR_MBC_Pos (24U)
+#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /*!< Mask Byte Control */
+#define ETH_MACA3HR_MBC_0 (0x1U << ETH_MACA3HR_MBC_Pos) /*!< 0x01000000 */
+#define ETH_MACA3HR_MBC_1 (0x2U << ETH_MACA3HR_MBC_Pos) /*!< 0x02000000 */
+#define ETH_MACA3HR_MBC_2 (0x4U << ETH_MACA3HR_MBC_Pos) /*!< 0x04000000 */
+#define ETH_MACA3HR_MBC_3 (0x8U << ETH_MACA3HR_MBC_Pos) /*!< 0x08000000 */
+#define ETH_MACA3HR_MBC_4 (0x10U << ETH_MACA3HR_MBC_Pos) /*!< 0x10000000 */
+#define ETH_MACA3HR_MBC_5 (0x20U << ETH_MACA3HR_MBC_Pos) /*!< 0x20000000 */
+#define ETH_MACA3HR_SA_Pos (30U)
+#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /*!< Source Address */
+#define ETH_MACA3HR_AE_Pos (31U)
+#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /*!< Address Enable */
+
+/************** Bit definition for ETH_MACA3LR register **************/
+#define ETH_MACA3LR_ADDRLO_Pos (0U)
+#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
+#define ETH_MACA3LR_ADDRLO_0 (0x1U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000001 */
+#define ETH_MACA3LR_ADDRLO_1 (0x2U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000002 */
+#define ETH_MACA3LR_ADDRLO_2 (0x4U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000004 */
+#define ETH_MACA3LR_ADDRLO_3 (0x8U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000008 */
+#define ETH_MACA3LR_ADDRLO_4 (0x10U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000010 */
+#define ETH_MACA3LR_ADDRLO_5 (0x20U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000020 */
+#define ETH_MACA3LR_ADDRLO_6 (0x40U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000040 */
+#define ETH_MACA3LR_ADDRLO_7 (0x80U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000080 */
+#define ETH_MACA3LR_ADDRLO_8 (0x100U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000100 */
+#define ETH_MACA3LR_ADDRLO_9 (0x200U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000200 */
+#define ETH_MACA3LR_ADDRLO_10 (0x400U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000400 */
+#define ETH_MACA3LR_ADDRLO_11 (0x800U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000800 */
+#define ETH_MACA3LR_ADDRLO_12 (0x1000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00001000 */
+#define ETH_MACA3LR_ADDRLO_13 (0x2000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00002000 */
+#define ETH_MACA3LR_ADDRLO_14 (0x4000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00004000 */
+#define ETH_MACA3LR_ADDRLO_15 (0x8000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00008000 */
+#define ETH_MACA3LR_ADDRLO_16 (0x10000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00010000 */
+#define ETH_MACA3LR_ADDRLO_17 (0x20000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00020000 */
+#define ETH_MACA3LR_ADDRLO_18 (0x40000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00040000 */
+#define ETH_MACA3LR_ADDRLO_19 (0x80000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00080000 */
+#define ETH_MACA3LR_ADDRLO_20 (0x100000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00100000 */
+#define ETH_MACA3LR_ADDRLO_21 (0x200000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00200000 */
+#define ETH_MACA3LR_ADDRLO_22 (0x400000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00400000 */
+#define ETH_MACA3LR_ADDRLO_23 (0x800000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00800000 */
+#define ETH_MACA3LR_ADDRLO_24 (0x1000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x01000000 */
+#define ETH_MACA3LR_ADDRLO_25 (0x2000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x02000000 */
+#define ETH_MACA3LR_ADDRLO_26 (0x4000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x04000000 */
+#define ETH_MACA3LR_ADDRLO_27 (0x8000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x08000000 */
+#define ETH_MACA3LR_ADDRLO_28 (0x10000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x10000000 */
+#define ETH_MACA3LR_ADDRLO_29 (0x20000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x20000000 */
+#define ETH_MACA3LR_ADDRLO_30 (0x40000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x40000000 */
+#define ETH_MACA3LR_ADDRLO_31 (0x80000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_MMC_CONTROL register ************/
+#define ETH_MMCCR_CNTRST_Pos (0U)
+#define ETH_MMCCR_CNTRST_Msk (0x1U << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /*!< Counters Reset */
+#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk (0x1U << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /*!< Counter Stop Rollover */
+#define ETH_MMCCR_RSTONRD_Pos (2U)
+#define ETH_MMCCR_RSTONRD_Msk (0x1U << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /*!< Reset on Read */
+#define ETH_MMCCR_CNTFREEZ_Pos (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk (0x1U << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /*!< MMC Counter Freeze */
+#define ETH_MMCCR_CNTPRST_Pos (4U)
+#define ETH_MMCCR_CNTPRST_Msk (0x1U << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /*!< Counters Preset */
+#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1U << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /*!< Full-Half Preset */
+#define ETH_MMCCR_UCDBC_Pos (8U)
+#define ETH_MMCCR_UCDBC_Msk (0x1U << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /*!< Update MMC Counters for Dropped Broadcast Packets */
+
+/*********** Bit definition for ETH_MMC_RX_INTERRUPT register ************/
+#define ETH_MMCRXIR_RXCRCERPIS_Pos (5U)
+#define ETH_MMCRXIR_RXCRCERPIS_Msk (0x1U << ETH_MMCRXIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRXIR_RXCRCERPIS ETH_MMCRXIR_RXCRCERPIS_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Status */
+#define ETH_MMCRXIR_RXALGNERPIS_Pos (6U)
+#define ETH_MMCRXIR_RXALGNERPIS_Msk (0x1U << ETH_MMCRXIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRXIR_RXALGNERPIS ETH_MMCRXIR_RXALGNERPIS_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRXIR_RXUCGPIS_Pos (17U)
+#define ETH_MMCRXIR_RXUCGPIS_Msk (0x1U << ETH_MMCRXIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRXIR_RXUCGPIS ETH_MMCRXIR_RXUCGPIS_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRXIR_RXLPIUSCIS_Pos (26U)
+#define ETH_MMCRXIR_RXLPIUSCIS_Msk (0x1U << ETH_MMCRXIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRXIR_RXLPIUSCIS ETH_MMCRXIR_RXLPIUSCIS_Msk /*!< MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRXIR_RXLPITRCIS_Pos (27U)
+#define ETH_MMCRXIR_RXLPITRCIS_Msk (0x1U << ETH_MMCRXIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRXIR_RXLPITRCIS ETH_MMCRXIR_RXLPITRCIS_Msk /*!< MMC Receive LPI transition counter interrupt status */
+
+/*********** Bit definition for ETH_MMC_TX_INTERRUPT register ************/
+#define ETH_MMCTXIR_TXSCOLGPIS_Pos (14U)
+#define ETH_MMCTXIR_TXSCOLGPIS_Msk (0x1U << ETH_MMCTXIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTXIR_TXSCOLGPIS ETH_MMCTXIR_TXSCOLGPIS_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTXIR_TXMCOLGPIS_Pos (15U)
+#define ETH_MMCTXIR_TXMCOLGPIS_Msk (0x1U << ETH_MMCTXIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTXIR_TXMCOLGPIS ETH_MMCTXIR_TXMCOLGPIS_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTXIR_TXGPKTIS_Pos (21U)
+#define ETH_MMCTXIR_TXGPKTIS_Msk (0x1U << ETH_MMCTXIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTXIR_TXGPKTIS ETH_MMCTXIR_TXGPKTIS_Msk /*!< MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTXIR_TXLPIUSCIS_Pos (26U)
+#define ETH_MMCTXIR_TXLPIUSCIS_Msk (0x1U << ETH_MMCTXIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTXIR_TXLPIUSCIS ETH_MMCTXIR_TXLPIUSCIS_Msk /*!< MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTXIR_TXLPITRCIS_Pos (27U)
+#define ETH_MMCTXIR_TXLPITRCIS_Msk (0x1U << ETH_MMCTXIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTXIR_TXLPITRCIS ETH_MMCTXIR_TXLPITRCIS_Msk /*!< MMC Transmit LPI transition counter interrupt status */
+
+/********** Bit definition for ETH_MMC_RX_INTERRUPT_MASK register ***********/
+#define ETH_MMCRXIMR_RXCRCERPIM_Pos (5U)
+#define ETH_MMCRXIMR_RXCRCERPIM_Msk (0x1U << ETH_MMCRXIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRXIMR_RXCRCERPIM ETH_MMCRXIMR_RXCRCERPIM_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Mask */
+#define ETH_MMCRXIMR_RXALGNERPIM_Pos (6U)
+#define ETH_MMCRXIMR_RXALGNERPIM_Msk (0x1U << ETH_MMCRXIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRXIMR_RXALGNERPIM ETH_MMCRXIMR_RXALGNERPIM_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRXIMR_RXUCGPIM_Pos (17U)
+#define ETH_MMCRXIMR_RXUCGPIM_Msk (0x1U << ETH_MMCRXIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRXIMR_RXUCGPIM ETH_MMCRXIMR_RXUCGPIM_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRXIMR_RXLPIUSCIM_Pos (26U)
+#define ETH_MMCRXIMR_RXLPIUSCIM_Msk (0x1U << ETH_MMCRXIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRXIMR_RXLPIUSCIM ETH_MMCRXIMR_RXLPIUSCIM_Msk /*!< MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRXIMR_RXLPITRCIM_Pos (27U)
+#define ETH_MMCRXIMR_RXLPITRCIM_Msk (0x1U << ETH_MMCRXIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRXIMR_RXLPITRCIM ETH_MMCRXIMR_RXLPITRCIM_Msk /*!< MMC Receive LPI transition counter interrupt Mask */
+
+/********** Bit definition for ETH_MMC_TX_INTERRUPT_MASK register ***********/
+#define ETH_MMCTXIMR_TXSCOLGPIM_Pos (14U)
+#define ETH_MMCTXIMR_TXSCOLGPIM_Msk (0x1U << ETH_MMCTXIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTXIMR_TXSCOLGPIM ETH_MMCTXIMR_TXSCOLGPIM_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTXIMR_TXMCOLGPIM_Pos (15U)
+#define ETH_MMCTXIMR_TXMCOLGPIM_Msk (0x1U << ETH_MMCTXIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTXIMR_TXMCOLGPIM ETH_MMCTXIMR_TXMCOLGPIM_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTXIMR_TXGPKTIM_Pos (21U)
+#define ETH_MMCTXIMR_TXGPKTIM_Msk (0x1U << ETH_MMCTXIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTXIMR_TXGPKTIM ETH_MMCTXIMR_TXGPKTIM_Msk /*!< MMC Transmit Good Packet Counter Interrupt Mask */
+#define ETH_MMCTXIMR_TXLPIUSCIM_Pos (26U)
+#define ETH_MMCTXIMR_TXLPIUSCIM_Msk (0x1U << ETH_MMCTXIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */
+#define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U)
+#define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1U << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */
+
+/*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U)
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_Msk (0xFFFFFFFFU << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG ETH_MMCTXSCGPR_TXSNGLCOLG_Msk /*!< Tx Single Collision Good Packets */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_0 (0x1U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000001 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_1 (0x2U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000002 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_2 (0x4U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000004 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_3 (0x8U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000008 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_4 (0x10U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000010 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_5 (0x20U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000020 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_6 (0x40U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000040 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_7 (0x80U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000080 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_8 (0x100U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000100 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_9 (0x200U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000200 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_10 (0x400U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000400 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_11 (0x800U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000800 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_12 (0x1000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00001000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_13 (0x2000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00002000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_14 (0x4000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00004000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_15 (0x8000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00008000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_16 (0x10000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00010000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_17 (0x20000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00020000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_18 (0x40000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00040000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_19 (0x80000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00080000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_20 (0x100000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00100000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_21 (0x200000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00200000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_22 (0x400000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00400000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_23 (0x800000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00800000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_24 (0x1000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x01000000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_25 (0x2000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x02000000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_26 (0x4000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x04000000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_27 (0x8000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x08000000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_28 (0x10000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x10000000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_29 (0x20000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x20000000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_30 (0x40000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x40000000 */
+#define ETH_MMCTXSCGPR_TXSNGLCOLG_31 (0x80000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x80000000 */
+
+/*********** Bit definition for ETH_MMC_TX_MULTIPLE_COLLISION_GOOD_PACKETS register ************/
+#define ETH_MMCTXMCGPR_TXMULTCOLG_Pos (0U)
+#define ETH_MMCTXMCGPR_TXMULTCOLG_Msk (0xFFFFFFFFU << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTXMCGPR_TXMULTCOLG ETH_MMCTXMCGPR_TXMULTCOLG_Msk /*!< Tx Multiple Collision Good Packets */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_0 (0x1U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000001 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_1 (0x2U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000002 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_2 (0x4U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000004 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_3 (0x8U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000008 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_4 (0x10U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000010 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_5 (0x20U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000020 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_6 (0x40U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000040 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_7 (0x80U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000080 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_8 (0x100U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000100 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_9 (0x200U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000200 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_10 (0x400U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000400 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_11 (0x800U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000800 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_12 (0x1000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00001000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_13 (0x2000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00002000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_14 (0x4000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00004000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_15 (0x8000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00008000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_16 (0x10000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00010000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_17 (0x20000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00020000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_18 (0x40000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00040000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_19 (0x80000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00080000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_20 (0x100000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00100000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_21 (0x200000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00200000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_22 (0x400000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00400000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_23 (0x800000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00800000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_24 (0x1000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x01000000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_25 (0x2000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x02000000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_26 (0x4000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x04000000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_27 (0x8000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x08000000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_28 (0x10000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x10000000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_29 (0x20000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x20000000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_30 (0x40000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x40000000 */
+#define ETH_MMCTXMCGPR_TXMULTCOLG_31 (0x80000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_MMC_TX_PACKET_COUNT_GOOD register *************/
+#define ETH_MMCTXPCGR_TXPKTG_Pos (0U)
+#define ETH_MMCTXPCGR_TXPKTG_Msk (0xFFFFFFFFU << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTXPCGR_TXPKTG ETH_MMCTXPCGR_TXPKTG_Msk /*!< Tx Packet Count Good */
+#define ETH_MMCTXPCGR_TXPKTG_0 (0x1U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000001 */
+#define ETH_MMCTXPCGR_TXPKTG_1 (0x2U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000002 */
+#define ETH_MMCTXPCGR_TXPKTG_2 (0x4U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000004 */
+#define ETH_MMCTXPCGR_TXPKTG_3 (0x8U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000008 */
+#define ETH_MMCTXPCGR_TXPKTG_4 (0x10U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000010 */
+#define ETH_MMCTXPCGR_TXPKTG_5 (0x20U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000020 */
+#define ETH_MMCTXPCGR_TXPKTG_6 (0x40U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000040 */
+#define ETH_MMCTXPCGR_TXPKTG_7 (0x80U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000080 */
+#define ETH_MMCTXPCGR_TXPKTG_8 (0x100U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000100 */
+#define ETH_MMCTXPCGR_TXPKTG_9 (0x200U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000200 */
+#define ETH_MMCTXPCGR_TXPKTG_10 (0x400U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000400 */
+#define ETH_MMCTXPCGR_TXPKTG_11 (0x800U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000800 */
+#define ETH_MMCTXPCGR_TXPKTG_12 (0x1000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00001000 */
+#define ETH_MMCTXPCGR_TXPKTG_13 (0x2000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00002000 */
+#define ETH_MMCTXPCGR_TXPKTG_14 (0x4000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00004000 */
+#define ETH_MMCTXPCGR_TXPKTG_15 (0x8000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00008000 */
+#define ETH_MMCTXPCGR_TXPKTG_16 (0x10000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00010000 */
+#define ETH_MMCTXPCGR_TXPKTG_17 (0x20000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00020000 */
+#define ETH_MMCTXPCGR_TXPKTG_18 (0x40000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00040000 */
+#define ETH_MMCTXPCGR_TXPKTG_19 (0x80000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00080000 */
+#define ETH_MMCTXPCGR_TXPKTG_20 (0x100000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00100000 */
+#define ETH_MMCTXPCGR_TXPKTG_21 (0x200000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00200000 */
+#define ETH_MMCTXPCGR_TXPKTG_22 (0x400000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00400000 */
+#define ETH_MMCTXPCGR_TXPKTG_23 (0x800000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00800000 */
+#define ETH_MMCTXPCGR_TXPKTG_24 (0x1000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x01000000 */
+#define ETH_MMCTXPCGR_TXPKTG_25 (0x2000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x02000000 */
+#define ETH_MMCTXPCGR_TXPKTG_26 (0x4000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x04000000 */
+#define ETH_MMCTXPCGR_TXPKTG_27 (0x8000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x08000000 */
+#define ETH_MMCTXPCGR_TXPKTG_28 (0x10000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x10000000 */
+#define ETH_MMCTXPCGR_TXPKTG_29 (0x20000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x20000000 */
+#define ETH_MMCTXPCGR_TXPKTG_30 (0x40000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x40000000 */
+#define ETH_MMCTXPCGR_TXPKTG_31 (0x80000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x80000000 */
+
+/*********** Bit definition for ETH_MMC_RX_CRC_ERROR_PACKETS register ***********/
+#define ETH_MMCRXCRCEPR_RXCRCERR_Pos (0U)
+#define ETH_MMCRXCRCEPR_RXCRCERR_Msk (0xFFFFFFFFU << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRXCRCEPR_RXCRCERR ETH_MMCRXCRCEPR_RXCRCERR_Msk /*!< Rx CRC Error Packets */
+#define ETH_MMCRXCRCEPR_RXCRCERR_0 (0x1U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000001 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_1 (0x2U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000002 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_2 (0x4U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000004 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_3 (0x8U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000008 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_4 (0x10U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000010 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_5 (0x20U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000020 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_6 (0x40U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000040 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_7 (0x80U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000080 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_8 (0x100U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000100 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_9 (0x200U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000200 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_10 (0x400U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000400 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_11 (0x800U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000800 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_12 (0x1000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00001000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_13 (0x2000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00002000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_14 (0x4000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00004000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_15 (0x8000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00008000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_16 (0x10000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00010000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_17 (0x20000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00020000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_18 (0x40000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00040000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_19 (0x80000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00080000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_20 (0x100000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00100000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_21 (0x200000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00200000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_22 (0x400000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00400000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_23 (0x800000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00800000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_24 (0x1000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x01000000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_25 (0x2000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x02000000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_26 (0x4000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x04000000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_27 (0x8000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x08000000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_28 (0x10000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x10000000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_29 (0x20000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x20000000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_30 (0x40000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x40000000 */
+#define ETH_MMCRXCRCEPR_RXCRCERR_31 (0x80000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x80000000 */
+
+/*********** Bit definition for ETH_MMC_RX_ALIGNMENT_ERROR_PACKETS register ***********/
+#define ETH_MMCRXAEPR_RXALGNERR_Pos (0U)
+#define ETH_MMCRXAEPR_RXALGNERR_Msk (0xFFFFFFFFU << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRXAEPR_RXALGNERR ETH_MMCRXAEPR_RXALGNERR_Msk /*!< Rx Alignment Error Packets */
+#define ETH_MMCRXAEPR_RXALGNERR_0 (0x1U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000001 */
+#define ETH_MMCRXAEPR_RXALGNERR_1 (0x2U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000002 */
+#define ETH_MMCRXAEPR_RXALGNERR_2 (0x4U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000004 */
+#define ETH_MMCRXAEPR_RXALGNERR_3 (0x8U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000008 */
+#define ETH_MMCRXAEPR_RXALGNERR_4 (0x10U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000010 */
+#define ETH_MMCRXAEPR_RXALGNERR_5 (0x20U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000020 */
+#define ETH_MMCRXAEPR_RXALGNERR_6 (0x40U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000040 */
+#define ETH_MMCRXAEPR_RXALGNERR_7 (0x80U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000080 */
+#define ETH_MMCRXAEPR_RXALGNERR_8 (0x100U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000100 */
+#define ETH_MMCRXAEPR_RXALGNERR_9 (0x200U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000200 */
+#define ETH_MMCRXAEPR_RXALGNERR_10 (0x400U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000400 */
+#define ETH_MMCRXAEPR_RXALGNERR_11 (0x800U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000800 */
+#define ETH_MMCRXAEPR_RXALGNERR_12 (0x1000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00001000 */
+#define ETH_MMCRXAEPR_RXALGNERR_13 (0x2000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00002000 */
+#define ETH_MMCRXAEPR_RXALGNERR_14 (0x4000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00004000 */
+#define ETH_MMCRXAEPR_RXALGNERR_15 (0x8000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00008000 */
+#define ETH_MMCRXAEPR_RXALGNERR_16 (0x10000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00010000 */
+#define ETH_MMCRXAEPR_RXALGNERR_17 (0x20000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00020000 */
+#define ETH_MMCRXAEPR_RXALGNERR_18 (0x40000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00040000 */
+#define ETH_MMCRXAEPR_RXALGNERR_19 (0x80000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00080000 */
+#define ETH_MMCRXAEPR_RXALGNERR_20 (0x100000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00100000 */
+#define ETH_MMCRXAEPR_RXALGNERR_21 (0x200000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00200000 */
+#define ETH_MMCRXAEPR_RXALGNERR_22 (0x400000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00400000 */
+#define ETH_MMCRXAEPR_RXALGNERR_23 (0x800000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00800000 */
+#define ETH_MMCRXAEPR_RXALGNERR_24 (0x1000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x01000000 */
+#define ETH_MMCRXAEPR_RXALGNERR_25 (0x2000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x02000000 */
+#define ETH_MMCRXAEPR_RXALGNERR_26 (0x4000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x04000000 */
+#define ETH_MMCRXAEPR_RXALGNERR_27 (0x8000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x08000000 */
+#define ETH_MMCRXAEPR_RXALGNERR_28 (0x10000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x10000000 */
+#define ETH_MMCRXAEPR_RXALGNERR_29 (0x20000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x20000000 */
+#define ETH_MMCRXAEPR_RXALGNERR_30 (0x40000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x40000000 */
+#define ETH_MMCRXAEPR_RXALGNERR_31 (0x80000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x80000000 */
+
+/*********** Bit definition for ETH_MMC_RX_UNICAST_PACKETS_GOOD register ************/
+#define ETH_MMCRXUPGR_RXUCASTG_Pos (0U)
+#define ETH_MMCRXUPGR_RXUCASTG_Msk (0xFFFFFFFFU << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRXUPGR_RXUCASTG ETH_MMCRXUPGR_RXUCASTG_Msk /*!< Rx Unicast Packets Good */
+#define ETH_MMCRXUPGR_RXUCASTG_0 (0x1U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000001 */
+#define ETH_MMCRXUPGR_RXUCASTG_1 (0x2U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000002 */
+#define ETH_MMCRXUPGR_RXUCASTG_2 (0x4U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000004 */
+#define ETH_MMCRXUPGR_RXUCASTG_3 (0x8U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000008 */
+#define ETH_MMCRXUPGR_RXUCASTG_4 (0x10U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000010 */
+#define ETH_MMCRXUPGR_RXUCASTG_5 (0x20U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000020 */
+#define ETH_MMCRXUPGR_RXUCASTG_6 (0x40U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000040 */
+#define ETH_MMCRXUPGR_RXUCASTG_7 (0x80U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000080 */
+#define ETH_MMCRXUPGR_RXUCASTG_8 (0x100U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000100 */
+#define ETH_MMCRXUPGR_RXUCASTG_9 (0x200U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000200 */
+#define ETH_MMCRXUPGR_RXUCASTG_10 (0x400U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000400 */
+#define ETH_MMCRXUPGR_RXUCASTG_11 (0x800U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000800 */
+#define ETH_MMCRXUPGR_RXUCASTG_12 (0x1000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00001000 */
+#define ETH_MMCRXUPGR_RXUCASTG_13 (0x2000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00002000 */
+#define ETH_MMCRXUPGR_RXUCASTG_14 (0x4000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00004000 */
+#define ETH_MMCRXUPGR_RXUCASTG_15 (0x8000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00008000 */
+#define ETH_MMCRXUPGR_RXUCASTG_16 (0x10000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00010000 */
+#define ETH_MMCRXUPGR_RXUCASTG_17 (0x20000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00020000 */
+#define ETH_MMCRXUPGR_RXUCASTG_18 (0x40000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00040000 */
+#define ETH_MMCRXUPGR_RXUCASTG_19 (0x80000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00080000 */
+#define ETH_MMCRXUPGR_RXUCASTG_20 (0x100000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00100000 */
+#define ETH_MMCRXUPGR_RXUCASTG_21 (0x200000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00200000 */
+#define ETH_MMCRXUPGR_RXUCASTG_22 (0x400000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00400000 */
+#define ETH_MMCRXUPGR_RXUCASTG_23 (0x800000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00800000 */
+#define ETH_MMCRXUPGR_RXUCASTG_24 (0x1000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x01000000 */
+#define ETH_MMCRXUPGR_RXUCASTG_25 (0x2000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x02000000 */
+#define ETH_MMCRXUPGR_RXUCASTG_26 (0x4000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x04000000 */
+#define ETH_MMCRXUPGR_RXUCASTG_27 (0x8000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x08000000 */
+#define ETH_MMCRXUPGR_RXUCASTG_28 (0x10000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x10000000 */
+#define ETH_MMCRXUPGR_RXUCASTG_29 (0x20000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x20000000 */
+#define ETH_MMCRXUPGR_RXUCASTG_30 (0x40000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x40000000 */
+#define ETH_MMCRXUPGR_RXUCASTG_31 (0x80000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MMC_TX_LPI_USEC_CNTR register *************/
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_Pos (0U)
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_Msk (0xFFFFFFFFU << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC ETH_MMCTXLPIMSTR_TXLPIUSC_Msk /*!< Tx LPI Microseconds Counter */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_0 (0x1U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000001 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_1 (0x2U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000002 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_2 (0x4U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000004 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_3 (0x8U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000008 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_4 (0x10U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000010 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_5 (0x20U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000020 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_6 (0x40U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000040 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_7 (0x80U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000080 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_8 (0x100U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000100 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_9 (0x200U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000200 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_10 (0x400U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000400 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_11 (0x800U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000800 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_12 (0x1000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00001000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_13 (0x2000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00002000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_14 (0x4000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00004000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_15 (0x8000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00008000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_16 (0x10000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00010000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_17 (0x20000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00020000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_18 (0x40000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00040000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_19 (0x80000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00080000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_20 (0x100000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00100000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_21 (0x200000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00200000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_22 (0x400000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00400000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_23 (0x800000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00800000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_24 (0x1000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x01000000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_25 (0x2000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x02000000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_26 (0x4000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x04000000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_27 (0x8000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x08000000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_28 (0x10000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x10000000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_29 (0x20000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x20000000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_30 (0x40000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x40000000 */
+#define ETH_MMCTXLPIMSTR_TXLPIUSC_31 (0x80000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MMC_TX_LPI_TRAN_CNTR register *************/
+#define ETH_MMCTXLPITCR_TXLPITRC_Pos (0U)
+#define ETH_MMCTXLPITCR_TXLPITRC_Msk (0xFFFFFFFFU << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTXLPITCR_TXLPITRC ETH_MMCTXLPITCR_TXLPITRC_Msk /*!< Tx LPI Transition counter */
+#define ETH_MMCTXLPITCR_TXLPITRC_0 (0x1U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000001 */
+#define ETH_MMCTXLPITCR_TXLPITRC_1 (0x2U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000002 */
+#define ETH_MMCTXLPITCR_TXLPITRC_2 (0x4U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000004 */
+#define ETH_MMCTXLPITCR_TXLPITRC_3 (0x8U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000008 */
+#define ETH_MMCTXLPITCR_TXLPITRC_4 (0x10U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000010 */
+#define ETH_MMCTXLPITCR_TXLPITRC_5 (0x20U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000020 */
+#define ETH_MMCTXLPITCR_TXLPITRC_6 (0x40U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000040 */
+#define ETH_MMCTXLPITCR_TXLPITRC_7 (0x80U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000080 */
+#define ETH_MMCTXLPITCR_TXLPITRC_8 (0x100U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000100 */
+#define ETH_MMCTXLPITCR_TXLPITRC_9 (0x200U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000200 */
+#define ETH_MMCTXLPITCR_TXLPITRC_10 (0x400U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000400 */
+#define ETH_MMCTXLPITCR_TXLPITRC_11 (0x800U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000800 */
+#define ETH_MMCTXLPITCR_TXLPITRC_12 (0x1000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00001000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_13 (0x2000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00002000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_14 (0x4000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00004000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_15 (0x8000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00008000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_16 (0x10000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00010000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_17 (0x20000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00020000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_18 (0x40000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00040000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_19 (0x80000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00080000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_20 (0x100000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00100000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_21 (0x200000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00200000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_22 (0x400000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00400000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_23 (0x800000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00800000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_24 (0x1000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x01000000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_25 (0x2000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x02000000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_26 (0x4000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x04000000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_27 (0x8000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x08000000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_28 (0x10000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x10000000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_29 (0x20000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x20000000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_30 (0x40000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x40000000 */
+#define ETH_MMCTXLPITCR_TXLPITRC_31 (0x80000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MMC_RX_LPI_USEC_CNTR register *************/
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_Pos (0U)
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_Msk (0xFFFFFFFFU << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC ETH_MMCRXLPIMSTR_RXLPIUSC_Msk /*!< Rx LPI Microseconds Counter */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_0 (0x1U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000001 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_1 (0x2U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000002 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_2 (0x4U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000004 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_3 (0x8U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000008 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_4 (0x10U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000010 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_5 (0x20U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000020 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_6 (0x40U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000040 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_7 (0x80U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000080 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_8 (0x100U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000100 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_9 (0x200U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000200 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_10 (0x400U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000400 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_11 (0x800U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000800 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_12 (0x1000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00001000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_13 (0x2000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00002000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_14 (0x4000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00004000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_15 (0x8000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00008000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_16 (0x10000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00010000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_17 (0x20000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00020000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_18 (0x40000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00040000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_19 (0x80000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00080000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_20 (0x100000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00100000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_21 (0x200000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00200000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_22 (0x400000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00400000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_23 (0x800000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00800000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_24 (0x1000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x01000000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_25 (0x2000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x02000000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_26 (0x4000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x04000000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_27 (0x8000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x08000000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_28 (0x10000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x10000000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_29 (0x20000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x20000000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_30 (0x40000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x40000000 */
+#define ETH_MMCRXLPIMSTR_RXLPIUSC_31 (0x80000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MMC_RX_LPI_TRAN_CNTR register *************/
+#define ETH_MMCRXLPITCR_RXLPITRC_Pos (0U)
+#define ETH_MMCRXLPITCR_RXLPITRC_Msk (0xFFFFFFFFU << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRXLPITCR_RXLPITRC ETH_MMCRXLPITCR_RXLPITRC_Msk /*!< Rx LPI Transition counter */
+#define ETH_MMCRXLPITCR_RXLPITRC_0 (0x1U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000001 */
+#define ETH_MMCRXLPITCR_RXLPITRC_1 (0x2U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000002 */
+#define ETH_MMCRXLPITCR_RXLPITRC_2 (0x4U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000004 */
+#define ETH_MMCRXLPITCR_RXLPITRC_3 (0x8U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000008 */
+#define ETH_MMCRXLPITCR_RXLPITRC_4 (0x10U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000010 */
+#define ETH_MMCRXLPITCR_RXLPITRC_5 (0x20U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000020 */
+#define ETH_MMCRXLPITCR_RXLPITRC_6 (0x40U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000040 */
+#define ETH_MMCRXLPITCR_RXLPITRC_7 (0x80U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000080 */
+#define ETH_MMCRXLPITCR_RXLPITRC_8 (0x100U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000100 */
+#define ETH_MMCRXLPITCR_RXLPITRC_9 (0x200U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000200 */
+#define ETH_MMCRXLPITCR_RXLPITRC_10 (0x400U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000400 */
+#define ETH_MMCRXLPITCR_RXLPITRC_11 (0x800U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000800 */
+#define ETH_MMCRXLPITCR_RXLPITRC_12 (0x1000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00001000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_13 (0x2000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00002000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_14 (0x4000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00004000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_15 (0x8000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00008000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_16 (0x10000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00010000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_17 (0x20000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00020000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_18 (0x40000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00040000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_19 (0x80000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00080000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_20 (0x100000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00100000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_21 (0x200000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00200000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_22 (0x400000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00400000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_23 (0x800000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00800000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_24 (0x1000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x01000000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_25 (0x2000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x02000000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_26 (0x4000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x04000000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_27 (0x8000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x08000000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_28 (0x10000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x10000000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_29 (0x20000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x20000000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_30 (0x40000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x40000000 */
+#define ETH_MMCRXLPITCR_RXLPITRC_31 (0x80000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_MACL3L4C0R register *************/
+#define ETH_MACL3L4C0R_L3PEN0_Pos (0U)
+#define ETH_MACL3L4C0R_L3PEN0_Msk (0x1U << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4C0R_L3PEN0 ETH_MACL3L4C0R_L3PEN0_Msk /*!< Layer 3 Protocol Enable */
+#define ETH_MACL3L4C0R_L3SAM0_Pos (2U)
+#define ETH_MACL3L4C0R_L3SAM0_Msk (0x1U << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4C0R_L3SAM0 ETH_MACL3L4C0R_L3SAM0_Msk /*!< Layer 3 IP SA Match Enable */
+#define ETH_MACL3L4C0R_L3SAIM0_Pos (3U)
+#define ETH_MACL3L4C0R_L3SAIM0_Msk (0x1U << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4C0R_L3SAIM0 ETH_MACL3L4C0R_L3SAIM0_Msk /*!< Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3DAM0_Pos (4U)
+#define ETH_MACL3L4C0R_L3DAM0_Msk (0x1U << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4C0R_L3DAM0 ETH_MACL3L4C0R_L3DAM0_Msk /*!< Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4C0R_L3DAIM0_Pos (5U)
+#define ETH_MACL3L4C0R_L3DAIM0_Msk (0x1U << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4C0R_L3DAIM0 ETH_MACL3L4C0R_L3DAIM0_Msk /*!< Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4C0R_L3HSBM0_Pos (6U)
+#define ETH_MACL3L4C0R_L3HSBM0_Msk (0x1FU << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4C0R_L3HSBM0 ETH_MACL3L4C0R_L3HSBM0_Msk /*!< Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3HSBM0_0 (0x1U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000040 */
+#define ETH_MACL3L4C0R_L3HSBM0_1 (0x2U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000080 */
+#define ETH_MACL3L4C0R_L3HSBM0_2 (0x4U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000100 */
+#define ETH_MACL3L4C0R_L3HSBM0_3 (0x8U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000200 */
+#define ETH_MACL3L4C0R_L3HSBM0_4 (0x10U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000400 */
+#define ETH_MACL3L4C0R_L3HDBM0_Pos (11U)
+#define ETH_MACL3L4C0R_L3HDBM0_Msk (0x1FU << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4C0R_L3HDBM0 ETH_MACL3L4C0R_L3HDBM0_Msk /*!< Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4C0R_L3HDBM0_0 (0x1U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00000800 */
+#define ETH_MACL3L4C0R_L3HDBM0_1 (0x2U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00001000 */
+#define ETH_MACL3L4C0R_L3HDBM0_2 (0x4U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00002000 */
+#define ETH_MACL3L4C0R_L3HDBM0_3 (0x8U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00004000 */
+#define ETH_MACL3L4C0R_L3HDBM0_4 (0x10U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00008000 */
+#define ETH_MACL3L4C0R_L4PEN0_Pos (16U)
+#define ETH_MACL3L4C0R_L4PEN0_Msk (0x1U << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4C0R_L4PEN0 ETH_MACL3L4C0R_L4PEN0_Msk /*!< Layer 4 Protocol Enable */
+#define ETH_MACL3L4C0R_L4SPM0_Pos (18U)
+#define ETH_MACL3L4C0R_L4SPM0_Msk (0x1U << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4C0R_L4SPM0 ETH_MACL3L4C0R_L4SPM0_Msk /*!< Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4C0R_L4SPIM0_Pos (19U)
+#define ETH_MACL3L4C0R_L4SPIM0_Msk (0x1U << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4C0R_L4SPIM0 ETH_MACL3L4C0R_L4SPIM0_Msk /*!< Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4C0R_L4DPM0_Pos (20U)
+#define ETH_MACL3L4C0R_L4DPM0_Msk (0x1U << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4C0R_L4DPM0 ETH_MACL3L4C0R_L4DPM0_Msk /*!< Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4C0R_L4DPIM0_Pos (21U)
+#define ETH_MACL3L4C0R_L4DPIM0_Msk (0x1U << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4C0R_L4DPIM0 ETH_MACL3L4C0R_L4DPIM0_Msk /*!< Layer 4 Destination Port Inverse Match Enable */
+
+/************* Bit definition for ETH_MACL4A0R register **************/
+#define ETH_MACL4A0R_L4SP0_Pos (0U)
+#define ETH_MACL4A0R_L4SP0_Msk (0xFFFFU << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4A0R_L4SP0 ETH_MACL4A0R_L4SP0_Msk /*!< Layer 4 Source Port Number Field */
+#define ETH_MACL4A0R_L4SP0_0 (0x1U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000001 */
+#define ETH_MACL4A0R_L4SP0_1 (0x2U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000002 */
+#define ETH_MACL4A0R_L4SP0_2 (0x4U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000004 */
+#define ETH_MACL4A0R_L4SP0_3 (0x8U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000008 */
+#define ETH_MACL4A0R_L4SP0_4 (0x10U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000010 */
+#define ETH_MACL4A0R_L4SP0_5 (0x20U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000020 */
+#define ETH_MACL4A0R_L4SP0_6 (0x40U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000040 */
+#define ETH_MACL4A0R_L4SP0_7 (0x80U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000080 */
+#define ETH_MACL4A0R_L4SP0_8 (0x100U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000100 */
+#define ETH_MACL4A0R_L4SP0_9 (0x200U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000200 */
+#define ETH_MACL4A0R_L4SP0_10 (0x400U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000400 */
+#define ETH_MACL4A0R_L4SP0_11 (0x800U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000800 */
+#define ETH_MACL4A0R_L4SP0_12 (0x1000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00001000 */
+#define ETH_MACL4A0R_L4SP0_13 (0x2000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00002000 */
+#define ETH_MACL4A0R_L4SP0_14 (0x4000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00004000 */
+#define ETH_MACL4A0R_L4SP0_15 (0x8000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00008000 */
+#define ETH_MACL4A0R_L4DP0_Pos (16U)
+#define ETH_MACL4A0R_L4DP0_Msk (0xFFFFU << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4A0R_L4DP0 ETH_MACL4A0R_L4DP0_Msk /*!< Layer 4 Destination Port Number Field */
+#define ETH_MACL4A0R_L4DP0_0 (0x1U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00010000 */
+#define ETH_MACL4A0R_L4DP0_1 (0x2U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00020000 */
+#define ETH_MACL4A0R_L4DP0_2 (0x4U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00040000 */
+#define ETH_MACL4A0R_L4DP0_3 (0x8U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00080000 */
+#define ETH_MACL4A0R_L4DP0_4 (0x10U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00100000 */
+#define ETH_MACL4A0R_L4DP0_5 (0x20U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00200000 */
+#define ETH_MACL4A0R_L4DP0_6 (0x40U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00400000 */
+#define ETH_MACL4A0R_L4DP0_7 (0x80U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00800000 */
+#define ETH_MACL4A0R_L4DP0_8 (0x100U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x01000000 */
+#define ETH_MACL4A0R_L4DP0_9 (0x200U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x02000000 */
+#define ETH_MACL4A0R_L4DP0_10 (0x400U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x04000000 */
+#define ETH_MACL4A0R_L4DP0_11 (0x800U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x08000000 */
+#define ETH_MACL4A0R_L4DP0_12 (0x1000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x10000000 */
+#define ETH_MACL4A0R_L4DP0_13 (0x2000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x20000000 */
+#define ETH_MACL4A0R_L4DP0_14 (0x4000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x40000000 */
+#define ETH_MACL4A0R_L4DP0_15 (0x8000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A00R register *************/
+#define ETH_MACL3A00R_L3A00_Pos (0U)
+#define ETH_MACL3A00R_L3A00_Msk (0xFFFFFFFFU << ETH_MACL3A00R_L3A00_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A00R_L3A00 ETH_MACL3A00R_L3A00_Msk /*!< Layer 3 Address 0 Field */
+#define ETH_MACL3A00R_L3A00_0 (0x1U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A00R_L3A00_1 (0x2U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A00R_L3A00_2 (0x4U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A00R_L3A00_3 (0x8U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A00R_L3A00_4 (0x10U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A00R_L3A00_5 (0x20U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A00R_L3A00_6 (0x40U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A00R_L3A00_7 (0x80U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A00R_L3A00_8 (0x100U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A00R_L3A00_9 (0x200U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A00R_L3A00_10 (0x400U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A00R_L3A00_11 (0x800U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A00R_L3A00_12 (0x1000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A00R_L3A00_13 (0x2000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A00R_L3A00_14 (0x4000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A00R_L3A00_15 (0x8000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A00R_L3A00_16 (0x10000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A00R_L3A00_17 (0x20000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A00R_L3A00_18 (0x40000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A00R_L3A00_19 (0x80000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A00R_L3A00_20 (0x100000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A00R_L3A00_21 (0x200000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A00R_L3A00_22 (0x400000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A00R_L3A00_23 (0x800000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A00R_L3A00_24 (0x1000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A00R_L3A00_25 (0x2000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A00R_L3A00_26 (0x4000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A00R_L3A00_27 (0x8000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A00R_L3A00_28 (0x10000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A00R_L3A00_29 (0x20000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A00R_L3A00_30 (0x40000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A00R_L3A00_31 (0x80000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A10R register *************/
+#define ETH_MACL3A10R_L3A10_Pos (0U)
+#define ETH_MACL3A10R_L3A10_Msk (0xFFFFFFFFU << ETH_MACL3A10R_L3A10_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A10R_L3A10 ETH_MACL3A10R_L3A10_Msk /*!< Layer 3 Address 1 Field */
+#define ETH_MACL3A10R_L3A10_0 (0x1U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A10R_L3A10_1 (0x2U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A10R_L3A10_2 (0x4U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A10R_L3A10_3 (0x8U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A10R_L3A10_4 (0x10U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A10R_L3A10_5 (0x20U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A10R_L3A10_6 (0x40U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A10R_L3A10_7 (0x80U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A10R_L3A10_8 (0x100U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A10R_L3A10_9 (0x200U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A10R_L3A10_10 (0x400U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A10R_L3A10_11 (0x800U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A10R_L3A10_12 (0x1000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A10R_L3A10_13 (0x2000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A10R_L3A10_14 (0x4000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A10R_L3A10_15 (0x8000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A10R_L3A10_16 (0x10000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A10R_L3A10_17 (0x20000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A10R_L3A10_18 (0x40000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A10R_L3A10_19 (0x80000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A10R_L3A10_20 (0x100000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A10R_L3A10_21 (0x200000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A10R_L3A10_22 (0x400000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A10R_L3A10_23 (0x800000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A10R_L3A10_24 (0x1000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A10R_L3A10_25 (0x2000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A10R_L3A10_26 (0x4000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A10R_L3A10_27 (0x8000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A10R_L3A10_28 (0x10000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A10R_L3A10_29 (0x20000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A10R_L3A10_30 (0x40000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A10R_L3A10_31 (0x80000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A20 register **************/
+#define ETH_MACL3A20_L3A20_Pos (0U)
+#define ETH_MACL3A20_L3A20_Msk (0xFFFFFFFFU << ETH_MACL3A20_L3A20_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A20_L3A20 ETH_MACL3A20_L3A20_Msk /*!< Layer 3 Address 2 Field */
+#define ETH_MACL3A20_L3A20_0 (0x1U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A20_L3A20_1 (0x2U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A20_L3A20_2 (0x4U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A20_L3A20_3 (0x8U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A20_L3A20_4 (0x10U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A20_L3A20_5 (0x20U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A20_L3A20_6 (0x40U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A20_L3A20_7 (0x80U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A20_L3A20_8 (0x100U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A20_L3A20_9 (0x200U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A20_L3A20_10 (0x400U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A20_L3A20_11 (0x800U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A20_L3A20_12 (0x1000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A20_L3A20_13 (0x2000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A20_L3A20_14 (0x4000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A20_L3A20_15 (0x8000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A20_L3A20_16 (0x10000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A20_L3A20_17 (0x20000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A20_L3A20_18 (0x40000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A20_L3A20_19 (0x80000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A20_L3A20_20 (0x100000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A20_L3A20_21 (0x200000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A20_L3A20_22 (0x400000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A20_L3A20_23 (0x800000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A20_L3A20_24 (0x1000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A20_L3A20_25 (0x2000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A20_L3A20_26 (0x4000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A20_L3A20_27 (0x8000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A20_L3A20_28 (0x10000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A20_L3A20_29 (0x20000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A20_L3A20_30 (0x40000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A20_L3A20_31 (0x80000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A30 register **************/
+#define ETH_MACL3A30_L3A30_Pos (0U)
+#define ETH_MACL3A30_L3A30_Msk (0xFFFFFFFFU << ETH_MACL3A30_L3A30_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A30_L3A30 ETH_MACL3A30_L3A30_Msk /*!< Layer 3 Address 3 Field */
+#define ETH_MACL3A30_L3A30_0 (0x1U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A30_L3A30_1 (0x2U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A30_L3A30_2 (0x4U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A30_L3A30_3 (0x8U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A30_L3A30_4 (0x10U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A30_L3A30_5 (0x20U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A30_L3A30_6 (0x40U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A30_L3A30_7 (0x80U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A30_L3A30_8 (0x100U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A30_L3A30_9 (0x200U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A30_L3A30_10 (0x400U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A30_L3A30_11 (0x800U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A30_L3A30_12 (0x1000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A30_L3A30_13 (0x2000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A30_L3A30_14 (0x4000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A30_L3A30_15 (0x8000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A30_L3A30_16 (0x10000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A30_L3A30_17 (0x20000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A30_L3A30_18 (0x40000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A30_L3A30_19 (0x80000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A30_L3A30_20 (0x100000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A30_L3A30_21 (0x200000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A30_L3A30_22 (0x400000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A30_L3A30_23 (0x800000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A30_L3A30_24 (0x1000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A30_L3A30_25 (0x2000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A30_L3A30_26 (0x4000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A30_L3A30_27 (0x8000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A30_L3A30_28 (0x10000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A30_L3A30_29 (0x20000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A30_L3A30_30 (0x40000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A30_L3A30_31 (0x80000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_MACL3L4C1R register *************/
+#define ETH_MACL3L4C1R_L3PEN1_Pos (0U)
+#define ETH_MACL3L4C1R_L3PEN1_Msk (0x1U << ETH_MACL3L4C1R_L3PEN1_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4C1R_L3PEN1 ETH_MACL3L4C1R_L3PEN1_Msk /*!< Layer 3 Protocol Enable */
+#define ETH_MACL3L4C1R_L3SAM1_Pos (2U)
+#define ETH_MACL3L4C1R_L3SAM1_Msk (0x1U << ETH_MACL3L4C1R_L3SAM1_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4C1R_L3SAM1 ETH_MACL3L4C1R_L3SAM1_Msk /*!< Layer 3 IP SA Match Enable */
+#define ETH_MACL3L4C1R_L3SAIM1_Pos (3U)
+#define ETH_MACL3L4C1R_L3SAIM1_Msk (0x1U << ETH_MACL3L4C1R_L3SAIM1_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4C1R_L3SAIM1 ETH_MACL3L4C1R_L3SAIM1_Msk /*!< Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4C1R_L3DAM1_Pos (4U)
+#define ETH_MACL3L4C1R_L3DAM1_Msk (0x1U << ETH_MACL3L4C1R_L3DAM1_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4C1R_L3DAM1 ETH_MACL3L4C1R_L3DAM1_Msk /*!< Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4C1R_L3DAIM1_Pos (5U)
+#define ETH_MACL3L4C1R_L3DAIM1_Msk (0x1U << ETH_MACL3L4C1R_L3DAIM1_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4C1R_L3DAIM1 ETH_MACL3L4C1R_L3DAIM1_Msk /*!< Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4C1R_L3HSBM1_Pos (6U)
+#define ETH_MACL3L4C1R_L3HSBM1_Msk (0x1FU << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4C1R_L3HSBM1 ETH_MACL3L4C1R_L3HSBM1_Msk /*!< Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4C1R_L3HSBM1_0 (0x1U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000040 */
+#define ETH_MACL3L4C1R_L3HSBM1_1 (0x2U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000080 */
+#define ETH_MACL3L4C1R_L3HSBM1_2 (0x4U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000100 */
+#define ETH_MACL3L4C1R_L3HSBM1_3 (0x8U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000200 */
+#define ETH_MACL3L4C1R_L3HSBM1_4 (0x10U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000400 */
+#define ETH_MACL3L4C1R_L3HDBM1_Pos (11U)
+#define ETH_MACL3L4C1R_L3HDBM1_Msk (0x1FU << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4C1R_L3HDBM1 ETH_MACL3L4C1R_L3HDBM1_Msk /*!< Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4C1R_L3HDBM1_0 (0x1U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00000800 */
+#define ETH_MACL3L4C1R_L3HDBM1_1 (0x2U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00001000 */
+#define ETH_MACL3L4C1R_L3HDBM1_2 (0x4U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00002000 */
+#define ETH_MACL3L4C1R_L3HDBM1_3 (0x8U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00004000 */
+#define ETH_MACL3L4C1R_L3HDBM1_4 (0x10U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00008000 */
+#define ETH_MACL3L4C1R_L4PEN1_Pos (16U)
+#define ETH_MACL3L4C1R_L4PEN1_Msk (0x1U << ETH_MACL3L4C1R_L4PEN1_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4C1R_L4PEN1 ETH_MACL3L4C1R_L4PEN1_Msk /*!< Layer 4 Protocol Enable */
+#define ETH_MACL3L4C1R_L4SPM1_Pos (18U)
+#define ETH_MACL3L4C1R_L4SPM1_Msk (0x1U << ETH_MACL3L4C1R_L4SPM1_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4C1R_L4SPM1 ETH_MACL3L4C1R_L4SPM1_Msk /*!< Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4C1R_L4SPIM1_Pos (19U)
+#define ETH_MACL3L4C1R_L4SPIM1_Msk (0x1U << ETH_MACL3L4C1R_L4SPIM1_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4C1R_L4SPIM1 ETH_MACL3L4C1R_L4SPIM1_Msk /*!< Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4C1R_L4DPM1_Pos (20U)
+#define ETH_MACL3L4C1R_L4DPM1_Msk (0x1U << ETH_MACL3L4C1R_L4DPM1_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4C1R_L4DPM1 ETH_MACL3L4C1R_L4DPM1_Msk /*!< Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4C1R_L4DPIM1_Pos (21U)
+#define ETH_MACL3L4C1R_L4DPIM1_Msk (0x1U << ETH_MACL3L4C1R_L4DPIM1_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4C1R_L4DPIM1 ETH_MACL3L4C1R_L4DPIM1_Msk /*!< Layer 4 Destination Port Inverse Match Enable */
+
+/************* Bit definition for ETH_MACL4A1R register **************/
+#define ETH_MACL4A1R_L4SP1_Pos (0U)
+#define ETH_MACL4A1R_L4SP1_Msk (0xFFFFU << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4A1R_L4SP1 ETH_MACL4A1R_L4SP1_Msk /*!< Layer 4 Source Port Number Field */
+#define ETH_MACL4A1R_L4SP1_0 (0x1U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000001 */
+#define ETH_MACL4A1R_L4SP1_1 (0x2U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000002 */
+#define ETH_MACL4A1R_L4SP1_2 (0x4U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000004 */
+#define ETH_MACL4A1R_L4SP1_3 (0x8U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000008 */
+#define ETH_MACL4A1R_L4SP1_4 (0x10U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000010 */
+#define ETH_MACL4A1R_L4SP1_5 (0x20U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000020 */
+#define ETH_MACL4A1R_L4SP1_6 (0x40U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000040 */
+#define ETH_MACL4A1R_L4SP1_7 (0x80U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000080 */
+#define ETH_MACL4A1R_L4SP1_8 (0x100U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000100 */
+#define ETH_MACL4A1R_L4SP1_9 (0x200U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000200 */
+#define ETH_MACL4A1R_L4SP1_10 (0x400U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000400 */
+#define ETH_MACL4A1R_L4SP1_11 (0x800U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000800 */
+#define ETH_MACL4A1R_L4SP1_12 (0x1000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00001000 */
+#define ETH_MACL4A1R_L4SP1_13 (0x2000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00002000 */
+#define ETH_MACL4A1R_L4SP1_14 (0x4000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00004000 */
+#define ETH_MACL4A1R_L4SP1_15 (0x8000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00008000 */
+#define ETH_MACL4A1R_L4DP1_Pos (16U)
+#define ETH_MACL4A1R_L4DP1_Msk (0xFFFFU << ETH_MACL4A1R_L4DP1_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4A1R_L4DP1 ETH_MACL4A1R_L4DP1_Msk /*!< Layer 4 Destination Port Number Field */
+#define ETH_MACL4A1R_L4DP1_0 (0x1U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00010000 */
+#define ETH_MACL4A1R_L4DP1_1 (0x2U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00020000 */
+#define ETH_MACL4A1R_L4DP1_2 (0x4U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00040000 */
+#define ETH_MACL4A1R_L4DP1_3 (0x8U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00080000 */
+#define ETH_MACL4A1R_L4DP1_4 (0x10U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00100000 */
+#define ETH_MACL4A1R_L4DP1_5 (0x20U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00200000 */
+#define ETH_MACL4A1R_L4DP1_6 (0x40U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00400000 */
+#define ETH_MACL4A1R_L4DP1_7 (0x80U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00800000 */
+#define ETH_MACL4A1R_L4DP1_8 (0x100U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x01000000 */
+#define ETH_MACL4A1R_L4DP1_9 (0x200U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x02000000 */
+#define ETH_MACL4A1R_L4DP1_10 (0x400U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x04000000 */
+#define ETH_MACL4A1R_L4DP1_11 (0x800U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x08000000 */
+#define ETH_MACL4A1R_L4DP1_12 (0x1000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x10000000 */
+#define ETH_MACL4A1R_L4DP1_13 (0x2000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x20000000 */
+#define ETH_MACL4A1R_L4DP1_14 (0x4000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x40000000 */
+#define ETH_MACL4A1R_L4DP1_15 (0x8000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A01R register *************/
+#define ETH_MACL3A01R_L3A01_Pos (0U)
+#define ETH_MACL3A01R_L3A01_Msk (0xFFFFFFFFU << ETH_MACL3A01R_L3A01_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A01R_L3A01 ETH_MACL3A01R_L3A01_Msk /*!< Layer 3 Address 0 Field */
+#define ETH_MACL3A01R_L3A01_0 (0x1U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A01R_L3A01_1 (0x2U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A01R_L3A01_2 (0x4U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A01R_L3A01_3 (0x8U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A01R_L3A01_4 (0x10U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A01R_L3A01_5 (0x20U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A01R_L3A01_6 (0x40U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A01R_L3A01_7 (0x80U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A01R_L3A01_8 (0x100U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A01R_L3A01_9 (0x200U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A01R_L3A01_10 (0x400U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A01R_L3A01_11 (0x800U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A01R_L3A01_12 (0x1000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A01R_L3A01_13 (0x2000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A01R_L3A01_14 (0x4000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A01R_L3A01_15 (0x8000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A01R_L3A01_16 (0x10000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A01R_L3A01_17 (0x20000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A01R_L3A01_18 (0x40000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A01R_L3A01_19 (0x80000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A01R_L3A01_20 (0x100000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A01R_L3A01_21 (0x200000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A01R_L3A01_22 (0x400000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A01R_L3A01_23 (0x800000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A01R_L3A01_24 (0x1000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A01R_L3A01_25 (0x2000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A01R_L3A01_26 (0x4000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A01R_L3A01_27 (0x8000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A01R_L3A01_28 (0x10000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A01R_L3A01_29 (0x20000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A01R_L3A01_30 (0x40000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A01R_L3A01_31 (0x80000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A11R register *************/
+#define ETH_MACL3A11R_L3A11_Pos (0U)
+#define ETH_MACL3A11R_L3A11_Msk (0xFFFFFFFFU << ETH_MACL3A11R_L3A11_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A11R_L3A11 ETH_MACL3A11R_L3A11_Msk /*!< Layer 3 Address 1 Field */
+#define ETH_MACL3A11R_L3A11_0 (0x1U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A11R_L3A11_1 (0x2U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A11R_L3A11_2 (0x4U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A11R_L3A11_3 (0x8U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A11R_L3A11_4 (0x10U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A11R_L3A11_5 (0x20U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A11R_L3A11_6 (0x40U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A11R_L3A11_7 (0x80U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A11R_L3A11_8 (0x100U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A11R_L3A11_9 (0x200U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A11R_L3A11_10 (0x400U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A11R_L3A11_11 (0x800U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A11R_L3A11_12 (0x1000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A11R_L3A11_13 (0x2000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A11R_L3A11_14 (0x4000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A11R_L3A11_15 (0x8000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A11R_L3A11_16 (0x10000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A11R_L3A11_17 (0x20000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A11R_L3A11_18 (0x40000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A11R_L3A11_19 (0x80000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A11R_L3A11_20 (0x100000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A11R_L3A11_21 (0x200000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A11R_L3A11_22 (0x400000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A11R_L3A11_23 (0x800000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A11R_L3A11_24 (0x1000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A11R_L3A11_25 (0x2000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A11R_L3A11_26 (0x4000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A11R_L3A11_27 (0x8000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A11R_L3A11_28 (0x10000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A11R_L3A11_29 (0x20000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A11R_L3A11_30 (0x40000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A11R_L3A11_31 (0x80000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A21R register *************/
+#define ETH_MACL3A21R_L3A21_Pos (0U)
+#define ETH_MACL3A21R_L3A21_Msk (0xFFFFFFFFU << ETH_MACL3A21R_L3A21_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A21R_L3A21 ETH_MACL3A21R_L3A21_Msk /*!< Layer 3 Address 2 Field */
+#define ETH_MACL3A21R_L3A21_0 (0x1U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A21R_L3A21_1 (0x2U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A21R_L3A21_2 (0x4U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A21R_L3A21_3 (0x8U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A21R_L3A21_4 (0x10U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A21R_L3A21_5 (0x20U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A21R_L3A21_6 (0x40U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A21R_L3A21_7 (0x80U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A21R_L3A21_8 (0x100U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A21R_L3A21_9 (0x200U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A21R_L3A21_10 (0x400U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A21R_L3A21_11 (0x800U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A21R_L3A21_12 (0x1000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A21R_L3A21_13 (0x2000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A21R_L3A21_14 (0x4000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A21R_L3A21_15 (0x8000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A21R_L3A21_16 (0x10000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A21R_L3A21_17 (0x20000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A21R_L3A21_18 (0x40000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A21R_L3A21_19 (0x80000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A21R_L3A21_20 (0x100000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A21R_L3A21_21 (0x200000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A21R_L3A21_22 (0x400000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A21R_L3A21_23 (0x800000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A21R_L3A21_24 (0x1000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A21R_L3A21_25 (0x2000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A21R_L3A21_26 (0x4000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A21R_L3A21_27 (0x8000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A21R_L3A21_28 (0x10000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A21R_L3A21_29 (0x20000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A21R_L3A21_30 (0x40000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A21R_L3A21_31 (0x80000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACL3A31R register *************/
+#define ETH_MACL3A31R_L3A31_Pos (0U)
+#define ETH_MACL3A31R_L3A31_Msk (0xFFFFFFFFU << ETH_MACL3A31R_L3A31_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A31R_L3A31 ETH_MACL3A31R_L3A31_Msk /*!< Layer 3 Address 3 Field */
+#define ETH_MACL3A31R_L3A31_0 (0x1U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000001 */
+#define ETH_MACL3A31R_L3A31_1 (0x2U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000002 */
+#define ETH_MACL3A31R_L3A31_2 (0x4U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000004 */
+#define ETH_MACL3A31R_L3A31_3 (0x8U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000008 */
+#define ETH_MACL3A31R_L3A31_4 (0x10U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000010 */
+#define ETH_MACL3A31R_L3A31_5 (0x20U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000020 */
+#define ETH_MACL3A31R_L3A31_6 (0x40U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000040 */
+#define ETH_MACL3A31R_L3A31_7 (0x80U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000080 */
+#define ETH_MACL3A31R_L3A31_8 (0x100U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000100 */
+#define ETH_MACL3A31R_L3A31_9 (0x200U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000200 */
+#define ETH_MACL3A31R_L3A31_10 (0x400U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000400 */
+#define ETH_MACL3A31R_L3A31_11 (0x800U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000800 */
+#define ETH_MACL3A31R_L3A31_12 (0x1000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00001000 */
+#define ETH_MACL3A31R_L3A31_13 (0x2000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00002000 */
+#define ETH_MACL3A31R_L3A31_14 (0x4000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00004000 */
+#define ETH_MACL3A31R_L3A31_15 (0x8000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00008000 */
+#define ETH_MACL3A31R_L3A31_16 (0x10000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00010000 */
+#define ETH_MACL3A31R_L3A31_17 (0x20000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00020000 */
+#define ETH_MACL3A31R_L3A31_18 (0x40000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00040000 */
+#define ETH_MACL3A31R_L3A31_19 (0x80000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00080000 */
+#define ETH_MACL3A31R_L3A31_20 (0x100000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00100000 */
+#define ETH_MACL3A31R_L3A31_21 (0x200000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00200000 */
+#define ETH_MACL3A31R_L3A31_22 (0x400000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00400000 */
+#define ETH_MACL3A31R_L3A31_23 (0x800000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00800000 */
+#define ETH_MACL3A31R_L3A31_24 (0x1000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x01000000 */
+#define ETH_MACL3A31R_L3A31_25 (0x2000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x02000000 */
+#define ETH_MACL3A31R_L3A31_26 (0x4000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x04000000 */
+#define ETH_MACL3A31R_L3A31_27 (0x8000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x08000000 */
+#define ETH_MACL3A31R_L3A31_28 (0x10000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x10000000 */
+#define ETH_MACL3A31R_L3A31_29 (0x20000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x20000000 */
+#define ETH_MACL3A31R_L3A31_30 (0x40000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x40000000 */
+#define ETH_MACL3A31R_L3A31_31 (0x80000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACARPAR register **************/
+#define ETH_MACARPAR_ARPPA_Pos (0U)
+#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFU << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /*!< ARP Protocol Address */
+#define ETH_MACARPAR_ARPPA_0 (0x1U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000001 */
+#define ETH_MACARPAR_ARPPA_1 (0x2U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000002 */
+#define ETH_MACARPAR_ARPPA_2 (0x4U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000004 */
+#define ETH_MACARPAR_ARPPA_3 (0x8U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000008 */
+#define ETH_MACARPAR_ARPPA_4 (0x10U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000010 */
+#define ETH_MACARPAR_ARPPA_5 (0x20U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000020 */
+#define ETH_MACARPAR_ARPPA_6 (0x40U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000040 */
+#define ETH_MACARPAR_ARPPA_7 (0x80U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000080 */
+#define ETH_MACARPAR_ARPPA_8 (0x100U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000100 */
+#define ETH_MACARPAR_ARPPA_9 (0x200U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000200 */
+#define ETH_MACARPAR_ARPPA_10 (0x400U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000400 */
+#define ETH_MACARPAR_ARPPA_11 (0x800U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000800 */
+#define ETH_MACARPAR_ARPPA_12 (0x1000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00001000 */
+#define ETH_MACARPAR_ARPPA_13 (0x2000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00002000 */
+#define ETH_MACARPAR_ARPPA_14 (0x4000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00004000 */
+#define ETH_MACARPAR_ARPPA_15 (0x8000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00008000 */
+#define ETH_MACARPAR_ARPPA_16 (0x10000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00010000 */
+#define ETH_MACARPAR_ARPPA_17 (0x20000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00020000 */
+#define ETH_MACARPAR_ARPPA_18 (0x40000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00040000 */
+#define ETH_MACARPAR_ARPPA_19 (0x80000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00080000 */
+#define ETH_MACARPAR_ARPPA_20 (0x100000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00100000 */
+#define ETH_MACARPAR_ARPPA_21 (0x200000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00200000 */
+#define ETH_MACARPAR_ARPPA_22 (0x400000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00400000 */
+#define ETH_MACARPAR_ARPPA_23 (0x800000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00800000 */
+#define ETH_MACARPAR_ARPPA_24 (0x1000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x01000000 */
+#define ETH_MACARPAR_ARPPA_25 (0x2000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x02000000 */
+#define ETH_MACARPAR_ARPPA_26 (0x4000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x04000000 */
+#define ETH_MACARPAR_ARPPA_27 (0x8000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x08000000 */
+#define ETH_MACARPAR_ARPPA_28 (0x10000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x10000000 */
+#define ETH_MACARPAR_ARPPA_29 (0x20000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x20000000 */
+#define ETH_MACARPAR_ARPPA_30 (0x40000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x40000000 */
+#define ETH_MACARPAR_ARPPA_31 (0x80000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACTSCR register **************/
+#define ETH_MACTSCR_TSENA_Pos (0U)
+#define ETH_MACTSCR_TSENA_Msk (0x1U << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /*!< Enable Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk (0x1U << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /*!< Fine or Coarse Timestamp Update */
+#define ETH_MACTSCR_TSINIT_Pos (2U)
+#define ETH_MACTSCR_TSINIT_Msk (0x1U << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /*!< Initialize Timestamp */
+#define ETH_MACTSCR_TSUPDT_Pos (3U)
+#define ETH_MACTSCR_TSUPDT_Msk (0x1U << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /*!< Update Timestamp */
+#define ETH_MACTSCR_TSADDREG_Pos (5U)
+#define ETH_MACTSCR_TSADDREG_Msk (0x1U << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /*!< Update Addend Register */
+#define ETH_MACTSCR_TSENALL_Pos (8U)
+#define ETH_MACTSCR_TSENALL_Msk (0x1U << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /*!< Enable Timestamp for All Packets */
+#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1U << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /*!< Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk (0x1U << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /*!< Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSIPENA_Pos (11U)
+#define ETH_MACTSCR_TSIPENA_Msk (0x1U << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /*!< Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1U << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1U << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk (0x1U << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /*!< Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk (0x1U << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /*!< Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3U << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /*!< Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_SNAPTYPSEL_0 (0x1U << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00010000 */
+#define ETH_MACTSCR_SNAPTYPSEL_1 (0x2U << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00020000 */
+#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk (0x1U << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_CSC_Pos (19U)
+#define ETH_MACTSCR_CSC_Msk (0x1U << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk (0x1U << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_AV8021ASMEN_Pos (28U)
+#define ETH_MACTSCR_AV8021ASMEN_Msk (0x1U << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
+#define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */
+
+/************** Bit definition for ETH_MACSSIR register **************/
+#define ETH_MACSSIR_SNSINC_Pos (8U)
+#define ETH_MACSSIR_SNSINC_Msk (0xFFU << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */
+#define ETH_MACSSIR_SNSINC_0 (0x1U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */
+#define ETH_MACSSIR_SNSINC_1 (0x2U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */
+#define ETH_MACSSIR_SNSINC_2 (0x4U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */
+#define ETH_MACSSIR_SNSINC_3 (0x8U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */
+#define ETH_MACSSIR_SNSINC_4 (0x10U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */
+#define ETH_MACSSIR_SNSINC_5 (0x20U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */
+#define ETH_MACSSIR_SNSINC_6 (0x40U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */
+#define ETH_MACSSIR_SNSINC_7 (0x80U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */
+#define ETH_MACSSIR_SSINC_Pos (16U)
+#define ETH_MACSSIR_SSINC_Msk (0xFFU << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */
+#define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */
+#define ETH_MACSSIR_SSINC_0 (0x1U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00010000 */
+#define ETH_MACSSIR_SSINC_1 (0x2U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00020000 */
+#define ETH_MACSSIR_SSINC_2 (0x4U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00040000 */
+#define ETH_MACSSIR_SSINC_3 (0x8U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00080000 */
+#define ETH_MACSSIR_SSINC_4 (0x10U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00100000 */
+#define ETH_MACSSIR_SSINC_5 (0x20U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00200000 */
+#define ETH_MACSSIR_SSINC_6 (0x40U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00400000 */
+#define ETH_MACSSIR_SSINC_7 (0x80U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00800000 */
+
+/************** Bit definition for ETH_MACSTSR register **************/
+#define ETH_MACSTSR_TSS_Pos (0U)
+#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFU << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /*!< Timestamp Second */
+#define ETH_MACSTSR_TSS_0 (0x1U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000001 */
+#define ETH_MACSTSR_TSS_1 (0x2U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000002 */
+#define ETH_MACSTSR_TSS_2 (0x4U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000004 */
+#define ETH_MACSTSR_TSS_3 (0x8U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000008 */
+#define ETH_MACSTSR_TSS_4 (0x10U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000010 */
+#define ETH_MACSTSR_TSS_5 (0x20U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000020 */
+#define ETH_MACSTSR_TSS_6 (0x40U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000040 */
+#define ETH_MACSTSR_TSS_7 (0x80U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000080 */
+#define ETH_MACSTSR_TSS_8 (0x100U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000100 */
+#define ETH_MACSTSR_TSS_9 (0x200U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000200 */
+#define ETH_MACSTSR_TSS_10 (0x400U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000400 */
+#define ETH_MACSTSR_TSS_11 (0x800U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000800 */
+#define ETH_MACSTSR_TSS_12 (0x1000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00001000 */
+#define ETH_MACSTSR_TSS_13 (0x2000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00002000 */
+#define ETH_MACSTSR_TSS_14 (0x4000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00004000 */
+#define ETH_MACSTSR_TSS_15 (0x8000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00008000 */
+#define ETH_MACSTSR_TSS_16 (0x10000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00010000 */
+#define ETH_MACSTSR_TSS_17 (0x20000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00020000 */
+#define ETH_MACSTSR_TSS_18 (0x40000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00040000 */
+#define ETH_MACSTSR_TSS_19 (0x80000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00080000 */
+#define ETH_MACSTSR_TSS_20 (0x100000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00100000 */
+#define ETH_MACSTSR_TSS_21 (0x200000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00200000 */
+#define ETH_MACSTSR_TSS_22 (0x400000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00400000 */
+#define ETH_MACSTSR_TSS_23 (0x800000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00800000 */
+#define ETH_MACSTSR_TSS_24 (0x1000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x01000000 */
+#define ETH_MACSTSR_TSS_25 (0x2000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x02000000 */
+#define ETH_MACSTSR_TSS_26 (0x4000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x04000000 */
+#define ETH_MACSTSR_TSS_27 (0x8000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x08000000 */
+#define ETH_MACSTSR_TSS_28 (0x10000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x10000000 */
+#define ETH_MACSTSR_TSS_29 (0x20000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x20000000 */
+#define ETH_MACSTSR_TSS_30 (0x40000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x40000000 */
+#define ETH_MACSTSR_TSS_31 (0x80000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACSTNR register **************/
+#define ETH_MACSTNR_TSSS_Pos (0U)
+#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFU << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /*!< Timestamp Sub-seconds */
+#define ETH_MACSTNR_TSSS_0 (0x1U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000001 */
+#define ETH_MACSTNR_TSSS_1 (0x2U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000002 */
+#define ETH_MACSTNR_TSSS_2 (0x4U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000004 */
+#define ETH_MACSTNR_TSSS_3 (0x8U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000008 */
+#define ETH_MACSTNR_TSSS_4 (0x10U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000010 */
+#define ETH_MACSTNR_TSSS_5 (0x20U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000020 */
+#define ETH_MACSTNR_TSSS_6 (0x40U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000040 */
+#define ETH_MACSTNR_TSSS_7 (0x80U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000080 */
+#define ETH_MACSTNR_TSSS_8 (0x100U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000100 */
+#define ETH_MACSTNR_TSSS_9 (0x200U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000200 */
+#define ETH_MACSTNR_TSSS_10 (0x400U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000400 */
+#define ETH_MACSTNR_TSSS_11 (0x800U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000800 */
+#define ETH_MACSTNR_TSSS_12 (0x1000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00001000 */
+#define ETH_MACSTNR_TSSS_13 (0x2000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00002000 */
+#define ETH_MACSTNR_TSSS_14 (0x4000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00004000 */
+#define ETH_MACSTNR_TSSS_15 (0x8000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00008000 */
+#define ETH_MACSTNR_TSSS_16 (0x10000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00010000 */
+#define ETH_MACSTNR_TSSS_17 (0x20000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00020000 */
+#define ETH_MACSTNR_TSSS_18 (0x40000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00040000 */
+#define ETH_MACSTNR_TSSS_19 (0x80000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00080000 */
+#define ETH_MACSTNR_TSSS_20 (0x100000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00100000 */
+#define ETH_MACSTNR_TSSS_21 (0x200000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00200000 */
+#define ETH_MACSTNR_TSSS_22 (0x400000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00400000 */
+#define ETH_MACSTNR_TSSS_23 (0x800000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00800000 */
+#define ETH_MACSTNR_TSSS_24 (0x1000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x01000000 */
+#define ETH_MACSTNR_TSSS_25 (0x2000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x02000000 */
+#define ETH_MACSTNR_TSSS_26 (0x4000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x04000000 */
+#define ETH_MACSTNR_TSSS_27 (0x8000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x08000000 */
+#define ETH_MACSTNR_TSSS_28 (0x10000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x10000000 */
+#define ETH_MACSTNR_TSSS_29 (0x20000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x20000000 */
+#define ETH_MACSTNR_TSSS_30 (0x40000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x40000000 */
+
+/************* Bit definition for ETH_MACSTSUR register **************/
+#define ETH_MACSTSUR_TSS_Pos (0U)
+#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFU << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /*!< Timestamp Seconds */
+#define ETH_MACSTSUR_TSS_0 (0x1U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000001 */
+#define ETH_MACSTSUR_TSS_1 (0x2U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000002 */
+#define ETH_MACSTSUR_TSS_2 (0x4U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000004 */
+#define ETH_MACSTSUR_TSS_3 (0x8U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000008 */
+#define ETH_MACSTSUR_TSS_4 (0x10U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000010 */
+#define ETH_MACSTSUR_TSS_5 (0x20U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000020 */
+#define ETH_MACSTSUR_TSS_6 (0x40U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000040 */
+#define ETH_MACSTSUR_TSS_7 (0x80U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000080 */
+#define ETH_MACSTSUR_TSS_8 (0x100U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000100 */
+#define ETH_MACSTSUR_TSS_9 (0x200U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000200 */
+#define ETH_MACSTSUR_TSS_10 (0x400U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000400 */
+#define ETH_MACSTSUR_TSS_11 (0x800U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000800 */
+#define ETH_MACSTSUR_TSS_12 (0x1000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00001000 */
+#define ETH_MACSTSUR_TSS_13 (0x2000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00002000 */
+#define ETH_MACSTSUR_TSS_14 (0x4000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00004000 */
+#define ETH_MACSTSUR_TSS_15 (0x8000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00008000 */
+#define ETH_MACSTSUR_TSS_16 (0x10000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00010000 */
+#define ETH_MACSTSUR_TSS_17 (0x20000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00020000 */
+#define ETH_MACSTSUR_TSS_18 (0x40000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00040000 */
+#define ETH_MACSTSUR_TSS_19 (0x80000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00080000 */
+#define ETH_MACSTSUR_TSS_20 (0x100000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00100000 */
+#define ETH_MACSTSUR_TSS_21 (0x200000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00200000 */
+#define ETH_MACSTSUR_TSS_22 (0x400000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00400000 */
+#define ETH_MACSTSUR_TSS_23 (0x800000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00800000 */
+#define ETH_MACSTSUR_TSS_24 (0x1000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x01000000 */
+#define ETH_MACSTSUR_TSS_25 (0x2000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x02000000 */
+#define ETH_MACSTSUR_TSS_26 (0x4000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x04000000 */
+#define ETH_MACSTSUR_TSS_27 (0x8000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x08000000 */
+#define ETH_MACSTSUR_TSS_28 (0x10000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x10000000 */
+#define ETH_MACSTSUR_TSS_29 (0x20000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x20000000 */
+#define ETH_MACSTSUR_TSS_30 (0x40000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x40000000 */
+#define ETH_MACSTSUR_TSS_31 (0x80000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACSTNUR register **************/
+#define ETH_MACSTNUR_TSSS_Pos (0U)
+#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFU << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /*!< Timestamp Sub-seconds */
+#define ETH_MACSTNUR_TSSS_0 (0x1U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000001 */
+#define ETH_MACSTNUR_TSSS_1 (0x2U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000002 */
+#define ETH_MACSTNUR_TSSS_2 (0x4U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000004 */
+#define ETH_MACSTNUR_TSSS_3 (0x8U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000008 */
+#define ETH_MACSTNUR_TSSS_4 (0x10U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000010 */
+#define ETH_MACSTNUR_TSSS_5 (0x20U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000020 */
+#define ETH_MACSTNUR_TSSS_6 (0x40U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000040 */
+#define ETH_MACSTNUR_TSSS_7 (0x80U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000080 */
+#define ETH_MACSTNUR_TSSS_8 (0x100U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000100 */
+#define ETH_MACSTNUR_TSSS_9 (0x200U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000200 */
+#define ETH_MACSTNUR_TSSS_10 (0x400U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000400 */
+#define ETH_MACSTNUR_TSSS_11 (0x800U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000800 */
+#define ETH_MACSTNUR_TSSS_12 (0x1000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00001000 */
+#define ETH_MACSTNUR_TSSS_13 (0x2000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00002000 */
+#define ETH_MACSTNUR_TSSS_14 (0x4000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00004000 */
+#define ETH_MACSTNUR_TSSS_15 (0x8000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00008000 */
+#define ETH_MACSTNUR_TSSS_16 (0x10000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00010000 */
+#define ETH_MACSTNUR_TSSS_17 (0x20000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00020000 */
+#define ETH_MACSTNUR_TSSS_18 (0x40000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00040000 */
+#define ETH_MACSTNUR_TSSS_19 (0x80000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00080000 */
+#define ETH_MACSTNUR_TSSS_20 (0x100000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00100000 */
+#define ETH_MACSTNUR_TSSS_21 (0x200000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00200000 */
+#define ETH_MACSTNUR_TSSS_22 (0x400000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00400000 */
+#define ETH_MACSTNUR_TSSS_23 (0x800000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00800000 */
+#define ETH_MACSTNUR_TSSS_24 (0x1000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x01000000 */
+#define ETH_MACSTNUR_TSSS_25 (0x2000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x02000000 */
+#define ETH_MACSTNUR_TSSS_26 (0x4000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x04000000 */
+#define ETH_MACSTNUR_TSSS_27 (0x8000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x08000000 */
+#define ETH_MACSTNUR_TSSS_28 (0x10000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x10000000 */
+#define ETH_MACSTNUR_TSSS_29 (0x20000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x20000000 */
+#define ETH_MACSTNUR_TSSS_30 (0x40000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x40000000 */
+#define ETH_MACSTNUR_ADDSUB_Pos (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk (0x1U << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /*!< Add or Subtract Time */
+
+/************** Bit definition for ETH_MACTSAR register **************/
+#define ETH_MACTSAR_TSAR_Pos (0U)
+#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFU << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /*!< Timestamp Addend Register */
+#define ETH_MACTSAR_TSAR_0 (0x1U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000001 */
+#define ETH_MACTSAR_TSAR_1 (0x2U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000002 */
+#define ETH_MACTSAR_TSAR_2 (0x4U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000004 */
+#define ETH_MACTSAR_TSAR_3 (0x8U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000008 */
+#define ETH_MACTSAR_TSAR_4 (0x10U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000010 */
+#define ETH_MACTSAR_TSAR_5 (0x20U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000020 */
+#define ETH_MACTSAR_TSAR_6 (0x40U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000040 */
+#define ETH_MACTSAR_TSAR_7 (0x80U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000080 */
+#define ETH_MACTSAR_TSAR_8 (0x100U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000100 */
+#define ETH_MACTSAR_TSAR_9 (0x200U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSAR_TSAR_10 (0x400U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000400 */
+#define ETH_MACTSAR_TSAR_11 (0x800U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000800 */
+#define ETH_MACTSAR_TSAR_12 (0x1000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00001000 */
+#define ETH_MACTSAR_TSAR_13 (0x2000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00002000 */
+#define ETH_MACTSAR_TSAR_14 (0x4000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00004000 */
+#define ETH_MACTSAR_TSAR_15 (0x8000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00008000 */
+#define ETH_MACTSAR_TSAR_16 (0x10000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00010000 */
+#define ETH_MACTSAR_TSAR_17 (0x20000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00020000 */
+#define ETH_MACTSAR_TSAR_18 (0x40000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSAR_TSAR_19 (0x80000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00080000 */
+#define ETH_MACTSAR_TSAR_20 (0x100000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00100000 */
+#define ETH_MACTSAR_TSAR_21 (0x200000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00200000 */
+#define ETH_MACTSAR_TSAR_22 (0x400000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00400000 */
+#define ETH_MACTSAR_TSAR_23 (0x800000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00800000 */
+#define ETH_MACTSAR_TSAR_24 (0x1000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x01000000 */
+#define ETH_MACTSAR_TSAR_25 (0x2000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x02000000 */
+#define ETH_MACTSAR_TSAR_26 (0x4000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x04000000 */
+#define ETH_MACTSAR_TSAR_27 (0x8000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x08000000 */
+#define ETH_MACTSAR_TSAR_28 (0x10000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x10000000 */
+#define ETH_MACTSAR_TSAR_29 (0x20000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x20000000 */
+#define ETH_MACTSAR_TSAR_30 (0x40000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x40000000 */
+#define ETH_MACTSAR_TSAR_31 (0x80000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACTSSR register **************/
+#define ETH_MACTSSR_TSSOVF_Pos (0U)
+#define ETH_MACTSSR_TSSOVF_Msk (0x1U << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /*!< Timestamp Seconds Overflow */
+#define ETH_MACTSSR_TSTARGT0_Pos (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk (0x1U << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /*!< Timestamp Target Time Reached */
+#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1U << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /*!< Auxiliary Timestamp Trigger Snapshot */
+#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1U << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /*!< Timestamp Target Time Error */
+#define ETH_MACTSSR_TXTSSIS_Pos (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk (0x1U << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /*!< Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_ATSSTN_Pos (16U)
+#define ETH_MACTSSR_ATSSTN_Msk (0xFU << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /*!< Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_ATSSTN_0 (0x1U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00010000 */
+#define ETH_MACTSSR_ATSSTN_1 (0x2U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00020000 */
+#define ETH_MACTSSR_ATSSTN_2 (0x4U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00040000 */
+#define ETH_MACTSSR_ATSSTN_3 (0x8U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00080000 */
+#define ETH_MACTSSR_ATSSTM_Pos (24U)
+#define ETH_MACTSSR_ATSSTM_Msk (0x1U << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /*!< Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSNS_Pos (25U)
+#define ETH_MACTSSR_ATSNS_Msk (0x1FU << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /*!< Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSNS_0 (0x1U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x02000000 */
+#define ETH_MACTSSR_ATSNS_1 (0x2U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x04000000 */
+#define ETH_MACTSSR_ATSNS_2 (0x4U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x08000000 */
+#define ETH_MACTSSR_ATSNS_3 (0x8U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x10000000 */
+#define ETH_MACTSSR_ATSNS_4 (0x10U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x20000000 */
+
+/************ Bit definition for ETH_MACTXTSSNR register *************/
+#define ETH_MACTXTSSNR_TXTSSLO_Pos (0U)
+#define ETH_MACTXTSSNR_TXTSSLO_Msk (0x7FFFFFFFU << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTXTSSNR_TXTSSLO ETH_MACTXTSSNR_TXTSSLO_Msk /*!< Transmit Timestamp Status Low */
+#define ETH_MACTXTSSNR_TXTSSLO_0 (0x1U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000001 */
+#define ETH_MACTXTSSNR_TXTSSLO_1 (0x2U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000002 */
+#define ETH_MACTXTSSNR_TXTSSLO_2 (0x4U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000004 */
+#define ETH_MACTXTSSNR_TXTSSLO_3 (0x8U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000008 */
+#define ETH_MACTXTSSNR_TXTSSLO_4 (0x10U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000010 */
+#define ETH_MACTXTSSNR_TXTSSLO_5 (0x20U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000020 */
+#define ETH_MACTXTSSNR_TXTSSLO_6 (0x40U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000040 */
+#define ETH_MACTXTSSNR_TXTSSLO_7 (0x80U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000080 */
+#define ETH_MACTXTSSNR_TXTSSLO_8 (0x100U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000100 */
+#define ETH_MACTXTSSNR_TXTSSLO_9 (0x200U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000200 */
+#define ETH_MACTXTSSNR_TXTSSLO_10 (0x400U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000400 */
+#define ETH_MACTXTSSNR_TXTSSLO_11 (0x800U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000800 */
+#define ETH_MACTXTSSNR_TXTSSLO_12 (0x1000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00001000 */
+#define ETH_MACTXTSSNR_TXTSSLO_13 (0x2000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00002000 */
+#define ETH_MACTXTSSNR_TXTSSLO_14 (0x4000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00004000 */
+#define ETH_MACTXTSSNR_TXTSSLO_15 (0x8000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00008000 */
+#define ETH_MACTXTSSNR_TXTSSLO_16 (0x10000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00010000 */
+#define ETH_MACTXTSSNR_TXTSSLO_17 (0x20000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00020000 */
+#define ETH_MACTXTSSNR_TXTSSLO_18 (0x40000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00040000 */
+#define ETH_MACTXTSSNR_TXTSSLO_19 (0x80000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00080000 */
+#define ETH_MACTXTSSNR_TXTSSLO_20 (0x100000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00100000 */
+#define ETH_MACTXTSSNR_TXTSSLO_21 (0x200000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00200000 */
+#define ETH_MACTXTSSNR_TXTSSLO_22 (0x400000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00400000 */
+#define ETH_MACTXTSSNR_TXTSSLO_23 (0x800000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00800000 */
+#define ETH_MACTXTSSNR_TXTSSLO_24 (0x1000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x01000000 */
+#define ETH_MACTXTSSNR_TXTSSLO_25 (0x2000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x02000000 */
+#define ETH_MACTXTSSNR_TXTSSLO_26 (0x4000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x04000000 */
+#define ETH_MACTXTSSNR_TXTSSLO_27 (0x8000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x08000000 */
+#define ETH_MACTXTSSNR_TXTSSLO_28 (0x10000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x10000000 */
+#define ETH_MACTXTSSNR_TXTSSLO_29 (0x20000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x20000000 */
+#define ETH_MACTXTSSNR_TXTSSLO_30 (0x40000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x40000000 */
+#define ETH_MACTXTSSNR_TXTSSMIS_Pos (31U)
+#define ETH_MACTXTSSNR_TXTSSMIS_Msk (0x1U << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTXTSSNR_TXTSSMIS ETH_MACTXTSSNR_TXTSSMIS_Msk /*!< Transmit Timestamp Status Missed */
+
+/************ Bit definition for ETH_MACTXTSSSR register *************/
+#define ETH_MACTXTSSSR_TXTSSHI_Pos (0U)
+#define ETH_MACTXTSSSR_TXTSSHI_Msk (0xFFFFFFFFU << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTXTSSSR_TXTSSHI ETH_MACTXTSSSR_TXTSSHI_Msk /*!< Transmit Timestamp Status High */
+#define ETH_MACTXTSSSR_TXTSSHI_0 (0x1U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000001 */
+#define ETH_MACTXTSSSR_TXTSSHI_1 (0x2U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000002 */
+#define ETH_MACTXTSSSR_TXTSSHI_2 (0x4U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000004 */
+#define ETH_MACTXTSSSR_TXTSSHI_3 (0x8U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000008 */
+#define ETH_MACTXTSSSR_TXTSSHI_4 (0x10U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000010 */
+#define ETH_MACTXTSSSR_TXTSSHI_5 (0x20U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000020 */
+#define ETH_MACTXTSSSR_TXTSSHI_6 (0x40U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000040 */
+#define ETH_MACTXTSSSR_TXTSSHI_7 (0x80U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000080 */
+#define ETH_MACTXTSSSR_TXTSSHI_8 (0x100U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000100 */
+#define ETH_MACTXTSSSR_TXTSSHI_9 (0x200U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000200 */
+#define ETH_MACTXTSSSR_TXTSSHI_10 (0x400U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000400 */
+#define ETH_MACTXTSSSR_TXTSSHI_11 (0x800U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000800 */
+#define ETH_MACTXTSSSR_TXTSSHI_12 (0x1000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00001000 */
+#define ETH_MACTXTSSSR_TXTSSHI_13 (0x2000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00002000 */
+#define ETH_MACTXTSSSR_TXTSSHI_14 (0x4000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00004000 */
+#define ETH_MACTXTSSSR_TXTSSHI_15 (0x8000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00008000 */
+#define ETH_MACTXTSSSR_TXTSSHI_16 (0x10000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00010000 */
+#define ETH_MACTXTSSSR_TXTSSHI_17 (0x20000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00020000 */
+#define ETH_MACTXTSSSR_TXTSSHI_18 (0x40000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00040000 */
+#define ETH_MACTXTSSSR_TXTSSHI_19 (0x80000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00080000 */
+#define ETH_MACTXTSSSR_TXTSSHI_20 (0x100000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00100000 */
+#define ETH_MACTXTSSSR_TXTSSHI_21 (0x200000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00200000 */
+#define ETH_MACTXTSSSR_TXTSSHI_22 (0x400000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00400000 */
+#define ETH_MACTXTSSSR_TXTSSHI_23 (0x800000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00800000 */
+#define ETH_MACTXTSSSR_TXTSSHI_24 (0x1000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x01000000 */
+#define ETH_MACTXTSSSR_TXTSSHI_25 (0x2000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x02000000 */
+#define ETH_MACTXTSSSR_TXTSSHI_26 (0x4000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x04000000 */
+#define ETH_MACTXTSSSR_TXTSSHI_27 (0x8000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x08000000 */
+#define ETH_MACTXTSSSR_TXTSSHI_28 (0x10000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x10000000 */
+#define ETH_MACTXTSSSR_TXTSSHI_29 (0x20000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x20000000 */
+#define ETH_MACTXTSSSR_TXTSSHI_30 (0x40000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x40000000 */
+#define ETH_MACTXTSSSR_TXTSSHI_31 (0x80000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACACR register ***************/
+#define ETH_MACACR_ATSFC_Pos (0U)
+#define ETH_MACACR_ATSFC_Msk (0x1U << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /*!< Auxiliary Snapshot FIFO Clear */
+#define ETH_MACACR_ATSEN0_Pos (4U)
+#define ETH_MACACR_ATSEN0_Msk (0x1U << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /*!< Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSEN1_Pos (5U)
+#define ETH_MACACR_ATSEN1_Msk (0x1U << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /*!< Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN2_Pos (6U)
+#define ETH_MACACR_ATSEN2_Msk (0x1U << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /*!< Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN3_Pos (7U)
+#define ETH_MACACR_ATSEN3_Msk (0x1U << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /*!< Auxiliary Snapshot 3 Enable */
+
+/************* Bit definition for ETH_MACATSNR register **************/
+#define ETH_MACATSNR_AUXTSLO_Pos (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFU << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /*!< Auxiliary Timestamp */
+#define ETH_MACATSNR_AUXTSLO_0 (0x1U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000001 */
+#define ETH_MACATSNR_AUXTSLO_1 (0x2U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000002 */
+#define ETH_MACATSNR_AUXTSLO_2 (0x4U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000004 */
+#define ETH_MACATSNR_AUXTSLO_3 (0x8U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000008 */
+#define ETH_MACATSNR_AUXTSLO_4 (0x10U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000010 */
+#define ETH_MACATSNR_AUXTSLO_5 (0x20U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000020 */
+#define ETH_MACATSNR_AUXTSLO_6 (0x40U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000040 */
+#define ETH_MACATSNR_AUXTSLO_7 (0x80U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000080 */
+#define ETH_MACATSNR_AUXTSLO_8 (0x100U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000100 */
+#define ETH_MACATSNR_AUXTSLO_9 (0x200U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000200 */
+#define ETH_MACATSNR_AUXTSLO_10 (0x400U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000400 */
+#define ETH_MACATSNR_AUXTSLO_11 (0x800U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000800 */
+#define ETH_MACATSNR_AUXTSLO_12 (0x1000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00001000 */
+#define ETH_MACATSNR_AUXTSLO_13 (0x2000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00002000 */
+#define ETH_MACATSNR_AUXTSLO_14 (0x4000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00004000 */
+#define ETH_MACATSNR_AUXTSLO_15 (0x8000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00008000 */
+#define ETH_MACATSNR_AUXTSLO_16 (0x10000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00010000 */
+#define ETH_MACATSNR_AUXTSLO_17 (0x20000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00020000 */
+#define ETH_MACATSNR_AUXTSLO_18 (0x40000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00040000 */
+#define ETH_MACATSNR_AUXTSLO_19 (0x80000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00080000 */
+#define ETH_MACATSNR_AUXTSLO_20 (0x100000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00100000 */
+#define ETH_MACATSNR_AUXTSLO_21 (0x200000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00200000 */
+#define ETH_MACATSNR_AUXTSLO_22 (0x400000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00400000 */
+#define ETH_MACATSNR_AUXTSLO_23 (0x800000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00800000 */
+#define ETH_MACATSNR_AUXTSLO_24 (0x1000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x01000000 */
+#define ETH_MACATSNR_AUXTSLO_25 (0x2000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x02000000 */
+#define ETH_MACATSNR_AUXTSLO_26 (0x4000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x04000000 */
+#define ETH_MACATSNR_AUXTSLO_27 (0x8000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x08000000 */
+#define ETH_MACATSNR_AUXTSLO_28 (0x10000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x10000000 */
+#define ETH_MACATSNR_AUXTSLO_29 (0x20000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x20000000 */
+#define ETH_MACATSNR_AUXTSLO_30 (0x40000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x40000000 */
+
+/************* Bit definition for ETH_MACATSSR register **************/
+#define ETH_MACATSSR_AUXTSHI_Pos (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFU << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /*!< Auxiliary Timestamp */
+#define ETH_MACATSSR_AUXTSHI_0 (0x1U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000001 */
+#define ETH_MACATSSR_AUXTSHI_1 (0x2U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000002 */
+#define ETH_MACATSSR_AUXTSHI_2 (0x4U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000004 */
+#define ETH_MACATSSR_AUXTSHI_3 (0x8U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000008 */
+#define ETH_MACATSSR_AUXTSHI_4 (0x10U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000010 */
+#define ETH_MACATSSR_AUXTSHI_5 (0x20U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000020 */
+#define ETH_MACATSSR_AUXTSHI_6 (0x40U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000040 */
+#define ETH_MACATSSR_AUXTSHI_7 (0x80U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000080 */
+#define ETH_MACATSSR_AUXTSHI_8 (0x100U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000100 */
+#define ETH_MACATSSR_AUXTSHI_9 (0x200U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000200 */
+#define ETH_MACATSSR_AUXTSHI_10 (0x400U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000400 */
+#define ETH_MACATSSR_AUXTSHI_11 (0x800U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000800 */
+#define ETH_MACATSSR_AUXTSHI_12 (0x1000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00001000 */
+#define ETH_MACATSSR_AUXTSHI_13 (0x2000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00002000 */
+#define ETH_MACATSSR_AUXTSHI_14 (0x4000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00004000 */
+#define ETH_MACATSSR_AUXTSHI_15 (0x8000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00008000 */
+#define ETH_MACATSSR_AUXTSHI_16 (0x10000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00010000 */
+#define ETH_MACATSSR_AUXTSHI_17 (0x20000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00020000 */
+#define ETH_MACATSSR_AUXTSHI_18 (0x40000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00040000 */
+#define ETH_MACATSSR_AUXTSHI_19 (0x80000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00080000 */
+#define ETH_MACATSSR_AUXTSHI_20 (0x100000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00100000 */
+#define ETH_MACATSSR_AUXTSHI_21 (0x200000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00200000 */
+#define ETH_MACATSSR_AUXTSHI_22 (0x400000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00400000 */
+#define ETH_MACATSSR_AUXTSHI_23 (0x800000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00800000 */
+#define ETH_MACATSSR_AUXTSHI_24 (0x1000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x01000000 */
+#define ETH_MACATSSR_AUXTSHI_25 (0x2000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x02000000 */
+#define ETH_MACATSSR_AUXTSHI_26 (0x4000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x04000000 */
+#define ETH_MACATSSR_AUXTSHI_27 (0x8000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x08000000 */
+#define ETH_MACATSSR_AUXTSHI_28 (0x10000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x10000000 */
+#define ETH_MACATSSR_AUXTSHI_29 (0x20000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x20000000 */
+#define ETH_MACATSSR_AUXTSHI_30 (0x40000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x40000000 */
+#define ETH_MACATSSR_AUXTSHI_31 (0x80000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACTSIACR register *************/
+#define ETH_MACTSIACR_OSTIAC_Pos (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFU << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingress Asymmetry Correction */
+#define ETH_MACTSIACR_OSTIAC_0 (0x1U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000001 */
+#define ETH_MACTSIACR_OSTIAC_1 (0x2U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000002 */
+#define ETH_MACTSIACR_OSTIAC_2 (0x4U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000004 */
+#define ETH_MACTSIACR_OSTIAC_3 (0x8U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000008 */
+#define ETH_MACTSIACR_OSTIAC_4 (0x10U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000010 */
+#define ETH_MACTSIACR_OSTIAC_5 (0x20U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000020 */
+#define ETH_MACTSIACR_OSTIAC_6 (0x40U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000040 */
+#define ETH_MACTSIACR_OSTIAC_7 (0x80U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000080 */
+#define ETH_MACTSIACR_OSTIAC_8 (0x100U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000100 */
+#define ETH_MACTSIACR_OSTIAC_9 (0x200U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000200 */
+#define ETH_MACTSIACR_OSTIAC_10 (0x400U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000400 */
+#define ETH_MACTSIACR_OSTIAC_11 (0x800U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000800 */
+#define ETH_MACTSIACR_OSTIAC_12 (0x1000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00001000 */
+#define ETH_MACTSIACR_OSTIAC_13 (0x2000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00002000 */
+#define ETH_MACTSIACR_OSTIAC_14 (0x4000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00004000 */
+#define ETH_MACTSIACR_OSTIAC_15 (0x8000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00008000 */
+#define ETH_MACTSIACR_OSTIAC_16 (0x10000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00010000 */
+#define ETH_MACTSIACR_OSTIAC_17 (0x20000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00020000 */
+#define ETH_MACTSIACR_OSTIAC_18 (0x40000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00040000 */
+#define ETH_MACTSIACR_OSTIAC_19 (0x80000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSIACR_OSTIAC_20 (0x100000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00100000 */
+#define ETH_MACTSIACR_OSTIAC_21 (0x200000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00200000 */
+#define ETH_MACTSIACR_OSTIAC_22 (0x400000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00400000 */
+#define ETH_MACTSIACR_OSTIAC_23 (0x800000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00800000 */
+#define ETH_MACTSIACR_OSTIAC_24 (0x1000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x01000000 */
+#define ETH_MACTSIACR_OSTIAC_25 (0x2000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x02000000 */
+#define ETH_MACTSIACR_OSTIAC_26 (0x4000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x04000000 */
+#define ETH_MACTSIACR_OSTIAC_27 (0x8000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x08000000 */
+#define ETH_MACTSIACR_OSTIAC_28 (0x10000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x10000000 */
+#define ETH_MACTSIACR_OSTIAC_29 (0x20000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x20000000 */
+#define ETH_MACTSIACR_OSTIAC_30 (0x40000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x40000000 */
+#define ETH_MACTSIACR_OSTIAC_31 (0x80000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACTSEACR register *************/
+#define ETH_MACTSEACR_OSTEAC_Pos (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFU << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress Asymmetry Correction */
+#define ETH_MACTSEACR_OSTEAC_0 (0x1U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000001 */
+#define ETH_MACTSEACR_OSTEAC_1 (0x2U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000002 */
+#define ETH_MACTSEACR_OSTEAC_2 (0x4U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000004 */
+#define ETH_MACTSEACR_OSTEAC_3 (0x8U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000008 */
+#define ETH_MACTSEACR_OSTEAC_4 (0x10U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000010 */
+#define ETH_MACTSEACR_OSTEAC_5 (0x20U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000020 */
+#define ETH_MACTSEACR_OSTEAC_6 (0x40U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000040 */
+#define ETH_MACTSEACR_OSTEAC_7 (0x80U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000080 */
+#define ETH_MACTSEACR_OSTEAC_8 (0x100U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000100 */
+#define ETH_MACTSEACR_OSTEAC_9 (0x200U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000200 */
+#define ETH_MACTSEACR_OSTEAC_10 (0x400U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000400 */
+#define ETH_MACTSEACR_OSTEAC_11 (0x800U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000800 */
+#define ETH_MACTSEACR_OSTEAC_12 (0x1000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00001000 */
+#define ETH_MACTSEACR_OSTEAC_13 (0x2000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00002000 */
+#define ETH_MACTSEACR_OSTEAC_14 (0x4000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00004000 */
+#define ETH_MACTSEACR_OSTEAC_15 (0x8000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00008000 */
+#define ETH_MACTSEACR_OSTEAC_16 (0x10000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00010000 */
+#define ETH_MACTSEACR_OSTEAC_17 (0x20000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00020000 */
+#define ETH_MACTSEACR_OSTEAC_18 (0x40000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00040000 */
+#define ETH_MACTSEACR_OSTEAC_19 (0x80000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSEACR_OSTEAC_20 (0x100000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00100000 */
+#define ETH_MACTSEACR_OSTEAC_21 (0x200000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00200000 */
+#define ETH_MACTSEACR_OSTEAC_22 (0x400000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00400000 */
+#define ETH_MACTSEACR_OSTEAC_23 (0x800000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00800000 */
+#define ETH_MACTSEACR_OSTEAC_24 (0x1000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x01000000 */
+#define ETH_MACTSEACR_OSTEAC_25 (0x2000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x02000000 */
+#define ETH_MACTSEACR_OSTEAC_26 (0x4000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x04000000 */
+#define ETH_MACTSEACR_OSTEAC_27 (0x8000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x08000000 */
+#define ETH_MACTSEACR_OSTEAC_28 (0x10000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x10000000 */
+#define ETH_MACTSEACR_OSTEAC_29 (0x20000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x20000000 */
+#define ETH_MACTSEACR_OSTEAC_30 (0x40000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x40000000 */
+#define ETH_MACTSEACR_OSTEAC_31 (0x80000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACTSICNR register *************/
+#define ETH_MACTSICNR_TSIC_Pos (0U)
+#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFU << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /*!< Timestamp Ingress Correction */
+#define ETH_MACTSICNR_TSIC_0 (0x1U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000001 */
+#define ETH_MACTSICNR_TSIC_1 (0x2U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000002 */
+#define ETH_MACTSICNR_TSIC_2 (0x4U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000004 */
+#define ETH_MACTSICNR_TSIC_3 (0x8U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000008 */
+#define ETH_MACTSICNR_TSIC_4 (0x10U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000010 */
+#define ETH_MACTSICNR_TSIC_5 (0x20U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000020 */
+#define ETH_MACTSICNR_TSIC_6 (0x40U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000040 */
+#define ETH_MACTSICNR_TSIC_7 (0x80U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000080 */
+#define ETH_MACTSICNR_TSIC_8 (0x100U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000100 */
+#define ETH_MACTSICNR_TSIC_9 (0x200U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000200 */
+#define ETH_MACTSICNR_TSIC_10 (0x400U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000400 */
+#define ETH_MACTSICNR_TSIC_11 (0x800U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000800 */
+#define ETH_MACTSICNR_TSIC_12 (0x1000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00001000 */
+#define ETH_MACTSICNR_TSIC_13 (0x2000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00002000 */
+#define ETH_MACTSICNR_TSIC_14 (0x4000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00004000 */
+#define ETH_MACTSICNR_TSIC_15 (0x8000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00008000 */
+#define ETH_MACTSICNR_TSIC_16 (0x10000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00010000 */
+#define ETH_MACTSICNR_TSIC_17 (0x20000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00020000 */
+#define ETH_MACTSICNR_TSIC_18 (0x40000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00040000 */
+#define ETH_MACTSICNR_TSIC_19 (0x80000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSICNR_TSIC_20 (0x100000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00100000 */
+#define ETH_MACTSICNR_TSIC_21 (0x200000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00200000 */
+#define ETH_MACTSICNR_TSIC_22 (0x400000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00400000 */
+#define ETH_MACTSICNR_TSIC_23 (0x800000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00800000 */
+#define ETH_MACTSICNR_TSIC_24 (0x1000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x01000000 */
+#define ETH_MACTSICNR_TSIC_25 (0x2000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x02000000 */
+#define ETH_MACTSICNR_TSIC_26 (0x4000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x04000000 */
+#define ETH_MACTSICNR_TSIC_27 (0x8000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x08000000 */
+#define ETH_MACTSICNR_TSIC_28 (0x10000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x10000000 */
+#define ETH_MACTSICNR_TSIC_29 (0x20000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x20000000 */
+#define ETH_MACTSICNR_TSIC_30 (0x40000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x40000000 */
+#define ETH_MACTSICNR_TSIC_31 (0x80000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACTSECNR register *************/
+#define ETH_MACTSECNR_TSEC_Pos (0U)
+#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFU << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /*!< Timestamp Egress Correction */
+#define ETH_MACTSECNR_TSEC_0 (0x1U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000001 */
+#define ETH_MACTSECNR_TSEC_1 (0x2U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000002 */
+#define ETH_MACTSECNR_TSEC_2 (0x4U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000004 */
+#define ETH_MACTSECNR_TSEC_3 (0x8U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000008 */
+#define ETH_MACTSECNR_TSEC_4 (0x10U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000010 */
+#define ETH_MACTSECNR_TSEC_5 (0x20U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000020 */
+#define ETH_MACTSECNR_TSEC_6 (0x40U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000040 */
+#define ETH_MACTSECNR_TSEC_7 (0x80U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000080 */
+#define ETH_MACTSECNR_TSEC_8 (0x100U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000100 */
+#define ETH_MACTSECNR_TSEC_9 (0x200U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000200 */
+#define ETH_MACTSECNR_TSEC_10 (0x400U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000400 */
+#define ETH_MACTSECNR_TSEC_11 (0x800U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000800 */
+#define ETH_MACTSECNR_TSEC_12 (0x1000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00001000 */
+#define ETH_MACTSECNR_TSEC_13 (0x2000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00002000 */
+#define ETH_MACTSECNR_TSEC_14 (0x4000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00004000 */
+#define ETH_MACTSECNR_TSEC_15 (0x8000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00008000 */
+#define ETH_MACTSECNR_TSEC_16 (0x10000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00010000 */
+#define ETH_MACTSECNR_TSEC_17 (0x20000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00020000 */
+#define ETH_MACTSECNR_TSEC_18 (0x40000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00040000 */
+#define ETH_MACTSECNR_TSEC_19 (0x80000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSECNR_TSEC_20 (0x100000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00100000 */
+#define ETH_MACTSECNR_TSEC_21 (0x200000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00200000 */
+#define ETH_MACTSECNR_TSEC_22 (0x400000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00400000 */
+#define ETH_MACTSECNR_TSEC_23 (0x800000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00800000 */
+#define ETH_MACTSECNR_TSEC_24 (0x1000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x01000000 */
+#define ETH_MACTSECNR_TSEC_25 (0x2000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x02000000 */
+#define ETH_MACTSECNR_TSEC_26 (0x4000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x04000000 */
+#define ETH_MACTSECNR_TSEC_27 (0x8000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x08000000 */
+#define ETH_MACTSECNR_TSEC_28 (0x10000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x10000000 */
+#define ETH_MACTSECNR_TSEC_29 (0x20000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x20000000 */
+#define ETH_MACTSECNR_TSEC_30 (0x40000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x40000000 */
+#define ETH_MACTSECNR_TSEC_31 (0x80000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACPPSCR register **************/
+#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk (0xFU << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /*!< PPS Output Frequency Control */
+#define ETH_MACPPSCR_PPSCTRL_0 (0x1U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000001 */
+#define ETH_MACPPSCR_PPSCTRL_1 (0x2U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000002 */
+#define ETH_MACPPSCR_PPSCTRL_2 (0x4U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000004 */
+#define ETH_MACPPSCR_PPSCTRL_3 (0x8U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000008 */
+#define ETH_MACPPSCR_PPSEN0_Pos (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk (0x1U << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /*!< Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /*!< Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_TRGTMODSEL0_0 (0x1U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000020 */
+#define ETH_MACPPSCR_TRGTMODSEL0_1 (0x2U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000040 */
+#define ETH_MACPPSCR_PPSCMD_Pos (0U)
+#define ETH_MACPPSCR_PPSCMD_Msk (0xFU << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCMD ETH_MACPPSCR_PPSCMD_Msk /*!< Flexible PPS Output (ptp_pps_o[0]) Control */
+#define ETH_MACPPSCR_PPSCMD_0 (0x1U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000001 */
+#define ETH_MACPPSCR_PPSCMD_1 (0x2U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000002 */
+#define ETH_MACPPSCR_PPSCMD_2 (0x4U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000004 */
+#define ETH_MACPPSCR_PPSCMD_3 (0x8U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000008 */
+#define ETH_MACPPSCR_PPSEN0_Pos (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk (0x1U << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /*!< Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /*!< Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_TRGTMODSEL0_0 (0x1U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000020 */
+#define ETH_MACPPSCR_TRGTMODSEL0_1 (0x2U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000040 */
+
+/************ Bit definition for ETH_MACPPSTTSR register *************/
+#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
+#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFU << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /*!< PPS Target Time Seconds Register */
+#define ETH_MACPPSTTSR_TSTRH0_0 (0x1U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000001 */
+#define ETH_MACPPSTTSR_TSTRH0_1 (0x2U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000002 */
+#define ETH_MACPPSTTSR_TSTRH0_2 (0x4U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000004 */
+#define ETH_MACPPSTTSR_TSTRH0_3 (0x8U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000008 */
+#define ETH_MACPPSTTSR_TSTRH0_4 (0x10U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSTTSR_TSTRH0_5 (0x20U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000020 */
+#define ETH_MACPPSTTSR_TSTRH0_6 (0x40U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000040 */
+#define ETH_MACPPSTTSR_TSTRH0_7 (0x80U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSTTSR_TSTRH0_8 (0x100U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000100 */
+#define ETH_MACPPSTTSR_TSTRH0_9 (0x200U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000200 */
+#define ETH_MACPPSTTSR_TSTRH0_10 (0x400U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000400 */
+#define ETH_MACPPSTTSR_TSTRH0_11 (0x800U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000800 */
+#define ETH_MACPPSTTSR_TSTRH0_12 (0x1000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00001000 */
+#define ETH_MACPPSTTSR_TSTRH0_13 (0x2000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00002000 */
+#define ETH_MACPPSTTSR_TSTRH0_14 (0x4000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00004000 */
+#define ETH_MACPPSTTSR_TSTRH0_15 (0x8000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00008000 */
+#define ETH_MACPPSTTSR_TSTRH0_16 (0x10000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00010000 */
+#define ETH_MACPPSTTSR_TSTRH0_17 (0x20000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00020000 */
+#define ETH_MACPPSTTSR_TSTRH0_18 (0x40000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00040000 */
+#define ETH_MACPPSTTSR_TSTRH0_19 (0x80000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00080000 */
+#define ETH_MACPPSTTSR_TSTRH0_20 (0x100000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00100000 */
+#define ETH_MACPPSTTSR_TSTRH0_21 (0x200000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00200000 */
+#define ETH_MACPPSTTSR_TSTRH0_22 (0x400000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00400000 */
+#define ETH_MACPPSTTSR_TSTRH0_23 (0x800000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00800000 */
+#define ETH_MACPPSTTSR_TSTRH0_24 (0x1000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x01000000 */
+#define ETH_MACPPSTTSR_TSTRH0_25 (0x2000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x02000000 */
+#define ETH_MACPPSTTSR_TSTRH0_26 (0x4000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x04000000 */
+#define ETH_MACPPSTTSR_TSTRH0_27 (0x8000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x08000000 */
+#define ETH_MACPPSTTSR_TSTRH0_28 (0x10000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSTTSR_TSTRH0_29 (0x20000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x20000000 */
+#define ETH_MACPPSTTSR_TSTRH0_30 (0x40000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x40000000 */
+#define ETH_MACPPSTTSR_TSTRH0_31 (0x80000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_MACPPSTTNR register *************/
+#define ETH_MACPPSTTNR_TTSL0_Pos (0U)
+#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFU << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /*!< Target Time Low for PPS Register */
+#define ETH_MACPPSTTNR_TTSL0_0 (0x1U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000001 */
+#define ETH_MACPPSTTNR_TTSL0_1 (0x2U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000002 */
+#define ETH_MACPPSTTNR_TTSL0_2 (0x4U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000004 */
+#define ETH_MACPPSTTNR_TTSL0_3 (0x8U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000008 */
+#define ETH_MACPPSTTNR_TTSL0_4 (0x10U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSTTNR_TTSL0_5 (0x20U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000020 */
+#define ETH_MACPPSTTNR_TTSL0_6 (0x40U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000040 */
+#define ETH_MACPPSTTNR_TTSL0_7 (0x80U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSTTNR_TTSL0_8 (0x100U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000100 */
+#define ETH_MACPPSTTNR_TTSL0_9 (0x200U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000200 */
+#define ETH_MACPPSTTNR_TTSL0_10 (0x400U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000400 */
+#define ETH_MACPPSTTNR_TTSL0_11 (0x800U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000800 */
+#define ETH_MACPPSTTNR_TTSL0_12 (0x1000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00001000 */
+#define ETH_MACPPSTTNR_TTSL0_13 (0x2000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00002000 */
+#define ETH_MACPPSTTNR_TTSL0_14 (0x4000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00004000 */
+#define ETH_MACPPSTTNR_TTSL0_15 (0x8000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00008000 */
+#define ETH_MACPPSTTNR_TTSL0_16 (0x10000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00010000 */
+#define ETH_MACPPSTTNR_TTSL0_17 (0x20000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00020000 */
+#define ETH_MACPPSTTNR_TTSL0_18 (0x40000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00040000 */
+#define ETH_MACPPSTTNR_TTSL0_19 (0x80000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00080000 */
+#define ETH_MACPPSTTNR_TTSL0_20 (0x100000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00100000 */
+#define ETH_MACPPSTTNR_TTSL0_21 (0x200000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00200000 */
+#define ETH_MACPPSTTNR_TTSL0_22 (0x400000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00400000 */
+#define ETH_MACPPSTTNR_TTSL0_23 (0x800000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00800000 */
+#define ETH_MACPPSTTNR_TTSL0_24 (0x1000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x01000000 */
+#define ETH_MACPPSTTNR_TTSL0_25 (0x2000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x02000000 */
+#define ETH_MACPPSTTNR_TTSL0_26 (0x4000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x04000000 */
+#define ETH_MACPPSTTNR_TTSL0_27 (0x8000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x08000000 */
+#define ETH_MACPPSTTNR_TTSL0_28 (0x10000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSTTNR_TTSL0_29 (0x20000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x20000000 */
+#define ETH_MACPPSTTNR_TTSL0_30 (0x40000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x40000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1U << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /*!< PPS Target Time Register Busy */
+
+/************* Bit definition for ETH_MACPPSIR register **************/
+#define ETH_MACPPSIR_PPSINT0_Pos (0U)
+#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFU << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /*!< PPS Output Signal Interval */
+#define ETH_MACPPSIR_PPSINT0_0 (0x1U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000001 */
+#define ETH_MACPPSIR_PPSINT0_1 (0x2U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000002 */
+#define ETH_MACPPSIR_PPSINT0_2 (0x4U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000004 */
+#define ETH_MACPPSIR_PPSINT0_3 (0x8U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000008 */
+#define ETH_MACPPSIR_PPSINT0_4 (0x10U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSIR_PPSINT0_5 (0x20U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000020 */
+#define ETH_MACPPSIR_PPSINT0_6 (0x40U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000040 */
+#define ETH_MACPPSIR_PPSINT0_7 (0x80U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSIR_PPSINT0_8 (0x100U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000100 */
+#define ETH_MACPPSIR_PPSINT0_9 (0x200U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000200 */
+#define ETH_MACPPSIR_PPSINT0_10 (0x400U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000400 */
+#define ETH_MACPPSIR_PPSINT0_11 (0x800U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000800 */
+#define ETH_MACPPSIR_PPSINT0_12 (0x1000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00001000 */
+#define ETH_MACPPSIR_PPSINT0_13 (0x2000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00002000 */
+#define ETH_MACPPSIR_PPSINT0_14 (0x4000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00004000 */
+#define ETH_MACPPSIR_PPSINT0_15 (0x8000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00008000 */
+#define ETH_MACPPSIR_PPSINT0_16 (0x10000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00010000 */
+#define ETH_MACPPSIR_PPSINT0_17 (0x20000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00020000 */
+#define ETH_MACPPSIR_PPSINT0_18 (0x40000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00040000 */
+#define ETH_MACPPSIR_PPSINT0_19 (0x80000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00080000 */
+#define ETH_MACPPSIR_PPSINT0_20 (0x100000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00100000 */
+#define ETH_MACPPSIR_PPSINT0_21 (0x200000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00200000 */
+#define ETH_MACPPSIR_PPSINT0_22 (0x400000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00400000 */
+#define ETH_MACPPSIR_PPSINT0_23 (0x800000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00800000 */
+#define ETH_MACPPSIR_PPSINT0_24 (0x1000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x01000000 */
+#define ETH_MACPPSIR_PPSINT0_25 (0x2000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x02000000 */
+#define ETH_MACPPSIR_PPSINT0_26 (0x4000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x04000000 */
+#define ETH_MACPPSIR_PPSINT0_27 (0x8000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x08000000 */
+#define ETH_MACPPSIR_PPSINT0_28 (0x10000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSIR_PPSINT0_29 (0x20000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x20000000 */
+#define ETH_MACPPSIR_PPSINT0_30 (0x40000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x40000000 */
+#define ETH_MACPPSIR_PPSINT0_31 (0x80000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACPPSWR register **************/
+#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
+#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFU << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /*!< PPS Output Signal Width */
+#define ETH_MACPPSWR_PPSWIDTH0_0 (0x1U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000001 */
+#define ETH_MACPPSWR_PPSWIDTH0_1 (0x2U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000002 */
+#define ETH_MACPPSWR_PPSWIDTH0_2 (0x4U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000004 */
+#define ETH_MACPPSWR_PPSWIDTH0_3 (0x8U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000008 */
+#define ETH_MACPPSWR_PPSWIDTH0_4 (0x10U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSWR_PPSWIDTH0_5 (0x20U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000020 */
+#define ETH_MACPPSWR_PPSWIDTH0_6 (0x40U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000040 */
+#define ETH_MACPPSWR_PPSWIDTH0_7 (0x80U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000080 */
+#define ETH_MACPPSWR_PPSWIDTH0_8 (0x100U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000100 */
+#define ETH_MACPPSWR_PPSWIDTH0_9 (0x200U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000200 */
+#define ETH_MACPPSWR_PPSWIDTH0_10 (0x400U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000400 */
+#define ETH_MACPPSWR_PPSWIDTH0_11 (0x800U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000800 */
+#define ETH_MACPPSWR_PPSWIDTH0_12 (0x1000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00001000 */
+#define ETH_MACPPSWR_PPSWIDTH0_13 (0x2000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00002000 */
+#define ETH_MACPPSWR_PPSWIDTH0_14 (0x4000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00004000 */
+#define ETH_MACPPSWR_PPSWIDTH0_15 (0x8000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00008000 */
+#define ETH_MACPPSWR_PPSWIDTH0_16 (0x10000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00010000 */
+#define ETH_MACPPSWR_PPSWIDTH0_17 (0x20000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00020000 */
+#define ETH_MACPPSWR_PPSWIDTH0_18 (0x40000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00040000 */
+#define ETH_MACPPSWR_PPSWIDTH0_19 (0x80000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00080000 */
+#define ETH_MACPPSWR_PPSWIDTH0_20 (0x100000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00100000 */
+#define ETH_MACPPSWR_PPSWIDTH0_21 (0x200000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00200000 */
+#define ETH_MACPPSWR_PPSWIDTH0_22 (0x400000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00400000 */
+#define ETH_MACPPSWR_PPSWIDTH0_23 (0x800000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00800000 */
+#define ETH_MACPPSWR_PPSWIDTH0_24 (0x1000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x01000000 */
+#define ETH_MACPPSWR_PPSWIDTH0_25 (0x2000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x02000000 */
+#define ETH_MACPPSWR_PPSWIDTH0_26 (0x4000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x04000000 */
+#define ETH_MACPPSWR_PPSWIDTH0_27 (0x8000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x08000000 */
+#define ETH_MACPPSWR_PPSWIDTH0_28 (0x10000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x10000000 */
+#define ETH_MACPPSWR_PPSWIDTH0_29 (0x20000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x20000000 */
+#define ETH_MACPPSWR_PPSWIDTH0_30 (0x40000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x40000000 */
+#define ETH_MACPPSWR_PPSWIDTH0_31 (0x80000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MACPOCR register **************/
+#define ETH_MACPOCR_PTOEN_Pos (0U)
+#define ETH_MACPOCR_PTOEN_Msk (0x1U << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /*!< PTP Offload Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk (0x1U << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /*!< Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_APDREQEN_Pos (2U)
+#define ETH_MACPOCR_APDREQEN_Msk (0x1U << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /*!< Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1U << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /*!< Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk (0x1U << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /*!< Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_DRRDIS_Pos (6U)
+#define ETH_MACPOCR_DRRDIS_Msk (0x1U << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /*!< Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_DN_Pos (8U)
+#define ETH_MACPOCR_DN_Msk (0xFFU << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /*!< Domain Number */
+#define ETH_MACPOCR_DN_0 (0x1U << ETH_MACPOCR_DN_Pos) /*!< 0x00000100 */
+#define ETH_MACPOCR_DN_1 (0x2U << ETH_MACPOCR_DN_Pos) /*!< 0x00000200 */
+#define ETH_MACPOCR_DN_2 (0x4U << ETH_MACPOCR_DN_Pos) /*!< 0x00000400 */
+#define ETH_MACPOCR_DN_3 (0x8U << ETH_MACPOCR_DN_Pos) /*!< 0x00000800 */
+#define ETH_MACPOCR_DN_4 (0x10U << ETH_MACPOCR_DN_Pos) /*!< 0x00001000 */
+#define ETH_MACPOCR_DN_5 (0x20U << ETH_MACPOCR_DN_Pos) /*!< 0x00002000 */
+#define ETH_MACPOCR_DN_6 (0x40U << ETH_MACPOCR_DN_Pos) /*!< 0x00004000 */
+#define ETH_MACPOCR_DN_7 (0x80U << ETH_MACPOCR_DN_Pos) /*!< 0x00008000 */
+
+/************* Bit definition for ETH_MACSPI0R register **************/
+#define ETH_MACSPI0R_SPI0_Pos (0U)
+#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFU << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /*!< Source Port Identity 0 */
+#define ETH_MACSPI0R_SPI0_0 (0x1U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000001 */
+#define ETH_MACSPI0R_SPI0_1 (0x2U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000002 */
+#define ETH_MACSPI0R_SPI0_2 (0x4U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000004 */
+#define ETH_MACSPI0R_SPI0_3 (0x8U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000008 */
+#define ETH_MACSPI0R_SPI0_4 (0x10U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000010 */
+#define ETH_MACSPI0R_SPI0_5 (0x20U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000020 */
+#define ETH_MACSPI0R_SPI0_6 (0x40U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000040 */
+#define ETH_MACSPI0R_SPI0_7 (0x80U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000080 */
+#define ETH_MACSPI0R_SPI0_8 (0x100U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000100 */
+#define ETH_MACSPI0R_SPI0_9 (0x200U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000200 */
+#define ETH_MACSPI0R_SPI0_10 (0x400U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000400 */
+#define ETH_MACSPI0R_SPI0_11 (0x800U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000800 */
+#define ETH_MACSPI0R_SPI0_12 (0x1000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00001000 */
+#define ETH_MACSPI0R_SPI0_13 (0x2000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00002000 */
+#define ETH_MACSPI0R_SPI0_14 (0x4000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00004000 */
+#define ETH_MACSPI0R_SPI0_15 (0x8000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00008000 */
+#define ETH_MACSPI0R_SPI0_16 (0x10000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00010000 */
+#define ETH_MACSPI0R_SPI0_17 (0x20000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00020000 */
+#define ETH_MACSPI0R_SPI0_18 (0x40000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00040000 */
+#define ETH_MACSPI0R_SPI0_19 (0x80000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00080000 */
+#define ETH_MACSPI0R_SPI0_20 (0x100000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00100000 */
+#define ETH_MACSPI0R_SPI0_21 (0x200000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00200000 */
+#define ETH_MACSPI0R_SPI0_22 (0x400000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00400000 */
+#define ETH_MACSPI0R_SPI0_23 (0x800000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00800000 */
+#define ETH_MACSPI0R_SPI0_24 (0x1000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x01000000 */
+#define ETH_MACSPI0R_SPI0_25 (0x2000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x02000000 */
+#define ETH_MACSPI0R_SPI0_26 (0x4000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x04000000 */
+#define ETH_MACSPI0R_SPI0_27 (0x8000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x08000000 */
+#define ETH_MACSPI0R_SPI0_28 (0x10000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x10000000 */
+#define ETH_MACSPI0R_SPI0_29 (0x20000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x20000000 */
+#define ETH_MACSPI0R_SPI0_30 (0x40000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x40000000 */
+#define ETH_MACSPI0R_SPI0_31 (0x80000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACSPI1R register **************/
+#define ETH_MACSPI1R_SPI1_Pos (0U)
+#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFU << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /*!< Source Port Identity 1 */
+#define ETH_MACSPI1R_SPI1_0 (0x1U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000001 */
+#define ETH_MACSPI1R_SPI1_1 (0x2U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000002 */
+#define ETH_MACSPI1R_SPI1_2 (0x4U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000004 */
+#define ETH_MACSPI1R_SPI1_3 (0x8U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000008 */
+#define ETH_MACSPI1R_SPI1_4 (0x10U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000010 */
+#define ETH_MACSPI1R_SPI1_5 (0x20U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000020 */
+#define ETH_MACSPI1R_SPI1_6 (0x40U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000040 */
+#define ETH_MACSPI1R_SPI1_7 (0x80U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000080 */
+#define ETH_MACSPI1R_SPI1_8 (0x100U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000100 */
+#define ETH_MACSPI1R_SPI1_9 (0x200U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000200 */
+#define ETH_MACSPI1R_SPI1_10 (0x400U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000400 */
+#define ETH_MACSPI1R_SPI1_11 (0x800U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000800 */
+#define ETH_MACSPI1R_SPI1_12 (0x1000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00001000 */
+#define ETH_MACSPI1R_SPI1_13 (0x2000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00002000 */
+#define ETH_MACSPI1R_SPI1_14 (0x4000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00004000 */
+#define ETH_MACSPI1R_SPI1_15 (0x8000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00008000 */
+#define ETH_MACSPI1R_SPI1_16 (0x10000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00010000 */
+#define ETH_MACSPI1R_SPI1_17 (0x20000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00020000 */
+#define ETH_MACSPI1R_SPI1_18 (0x40000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00040000 */
+#define ETH_MACSPI1R_SPI1_19 (0x80000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00080000 */
+#define ETH_MACSPI1R_SPI1_20 (0x100000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00100000 */
+#define ETH_MACSPI1R_SPI1_21 (0x200000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00200000 */
+#define ETH_MACSPI1R_SPI1_22 (0x400000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00400000 */
+#define ETH_MACSPI1R_SPI1_23 (0x800000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00800000 */
+#define ETH_MACSPI1R_SPI1_24 (0x1000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x01000000 */
+#define ETH_MACSPI1R_SPI1_25 (0x2000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x02000000 */
+#define ETH_MACSPI1R_SPI1_26 (0x4000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x04000000 */
+#define ETH_MACSPI1R_SPI1_27 (0x8000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x08000000 */
+#define ETH_MACSPI1R_SPI1_28 (0x10000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x10000000 */
+#define ETH_MACSPI1R_SPI1_29 (0x20000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x20000000 */
+#define ETH_MACSPI1R_SPI1_30 (0x40000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x40000000 */
+#define ETH_MACSPI1R_SPI1_31 (0x80000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x80000000 */
+
+/************* Bit definition for ETH_MACSPI2R register **************/
+#define ETH_MACSPI2R_SPI2_Pos (0U)
+#define ETH_MACSPI2R_SPI2_Msk (0xFFFFU << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /*!< Source Port Identity 2 */
+#define ETH_MACSPI2R_SPI2_0 (0x1U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000001 */
+#define ETH_MACSPI2R_SPI2_1 (0x2U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000002 */
+#define ETH_MACSPI2R_SPI2_2 (0x4U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000004 */
+#define ETH_MACSPI2R_SPI2_3 (0x8U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000008 */
+#define ETH_MACSPI2R_SPI2_4 (0x10U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000010 */
+#define ETH_MACSPI2R_SPI2_5 (0x20U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000020 */
+#define ETH_MACSPI2R_SPI2_6 (0x40U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000040 */
+#define ETH_MACSPI2R_SPI2_7 (0x80U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000080 */
+#define ETH_MACSPI2R_SPI2_8 (0x100U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000100 */
+#define ETH_MACSPI2R_SPI2_9 (0x200U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000200 */
+#define ETH_MACSPI2R_SPI2_10 (0x400U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000400 */
+#define ETH_MACSPI2R_SPI2_11 (0x800U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000800 */
+#define ETH_MACSPI2R_SPI2_12 (0x1000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00001000 */
+#define ETH_MACSPI2R_SPI2_13 (0x2000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00002000 */
+#define ETH_MACSPI2R_SPI2_14 (0x4000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00004000 */
+#define ETH_MACSPI2R_SPI2_15 (0x8000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00008000 */
+
+/************** Bit definition for ETH_MACLMIR register **************/
+#define ETH_MACLMIR_LSI_Pos (0U)
+#define ETH_MACLMIR_LSI_Msk (0xFFU << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /*!< Log Sync Interval */
+#define ETH_MACLMIR_LSI_0 (0x1U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000001 */
+#define ETH_MACLMIR_LSI_1 (0x2U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000002 */
+#define ETH_MACLMIR_LSI_2 (0x4U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000004 */
+#define ETH_MACLMIR_LSI_3 (0x8U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000008 */
+#define ETH_MACLMIR_LSI_4 (0x10U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000010 */
+#define ETH_MACLMIR_LSI_5 (0x20U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000020 */
+#define ETH_MACLMIR_LSI_6 (0x40U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000040 */
+#define ETH_MACLMIR_LSI_7 (0x80U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000080 */
+#define ETH_MACLMIR_DRSYNCR_Pos (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk (0x7U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /*!< Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_DRSYNCR_0 (0x1U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000100 */
+#define ETH_MACLMIR_DRSYNCR_1 (0x2U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000200 */
+#define ETH_MACLMIR_DRSYNCR_2 (0x4U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000400 */
+#define ETH_MACLMIR_LMPDRI_Pos (24U)
+#define ETH_MACLMIR_LMPDRI_Msk (0xFFU << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /*!< Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_LMPDRI_0 (0x1U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x01000000 */
+#define ETH_MACLMIR_LMPDRI_1 (0x2U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x02000000 */
+#define ETH_MACLMIR_LMPDRI_2 (0x4U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x04000000 */
+#define ETH_MACLMIR_LMPDRI_3 (0x8U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x08000000 */
+#define ETH_MACLMIR_LMPDRI_4 (0x10U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x10000000 */
+#define ETH_MACLMIR_LMPDRI_5 (0x20U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x20000000 */
+#define ETH_MACLMIR_LMPDRI_6 (0x40U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x40000000 */
+#define ETH_MACLMIR_LMPDRI_7 (0x80U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_MTLOMR register ***************/
+#define ETH_MTLOMR_DTXSTS_Pos (1U)
+#define ETH_MTLOMR_DTXSTS_Msk (0x1U << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /*!< Drop Transmit Status */
+#define ETH_MTLOMR_RAA_Pos (2U)
+#define ETH_MTLOMR_RAA_Msk (0x1U << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
+#define ETH_MTLOMR_RAA ETH_MTLOMR_RAA_Msk /*!< Receive Arbitration Algorithm */
+#define ETH_MTLOMR_SCHALG_Pos (5U)
+#define ETH_MTLOMR_SCHALG_Msk (0x3U << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000060 */
+#define ETH_MTLOMR_SCHALG ETH_MTLOMR_SCHALG_Msk /*!< Tx Scheduling Algorithm */
+#define ETH_MTLOMR_SCHALG_0 (0x1U << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
+#define ETH_MTLOMR_SCHALG_1 (0x2U << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000040 */
+#define ETH_MTLOMR_CNTPRST_Pos (8U)
+#define ETH_MTLOMR_CNTPRST_Msk (0x1U << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /*!< Counters Preset */
+#define ETH_MTLOMR_CNTCLR_Pos (9U)
+#define ETH_MTLOMR_CNTCLR_Msk (0x1U << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /*!< Counters Reset */
+
+/************** Bit definition for ETH_MTLISR register ***************/
+#define ETH_MTLISR_Q0IS_Pos (0U)
+#define ETH_MTLISR_Q0IS_Msk (0x1U << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_Q0IS ETH_MTLISR_Q0IS_Msk /*!< Queue 0 interrupt status */
+#define ETH_MTLISR_Q1IS_Pos (1U)
+#define ETH_MTLISR_Q1IS_Msk (0x1U << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
+#define ETH_MTLISR_Q1IS ETH_MTLISR_Q1IS_Msk /*!< Queue 1 interrupt status */
+
+/************ Bit definition for ETH_MTLTXQ0OMR register *************/
+#define ETH_MTLTXQ0OMR_FTQ_Pos (0U)
+#define ETH_MTLTXQ0OMR_FTQ_Msk (0x1U << ETH_MTLTXQ0OMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ0OMR_FTQ ETH_MTLTXQ0OMR_FTQ_Msk /*!< Flush Transmit Queue */
+#define ETH_MTLTXQ0OMR_TSF_Pos (1U)
+#define ETH_MTLTXQ0OMR_TSF_Msk (0x1U << ETH_MTLTXQ0OMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ0OMR_TSF ETH_MTLTXQ0OMR_TSF_Msk /*!< Transmit Store and Forward */
+#define ETH_MTLTXQ0OMR_TXQEN_Pos (2U)
+#define ETH_MTLTXQ0OMR_TXQEN_Msk (0x3U << ETH_MTLTXQ0OMR_TXQEN_Pos) /*!< 0x0000000C */
+#define ETH_MTLTXQ0OMR_TXQEN ETH_MTLTXQ0OMR_TXQEN_Msk /*!< Transmit Queue Enable */
+#define ETH_MTLTXQ0OMR_TXQEN_0 (0x1U << ETH_MTLTXQ0OMR_TXQEN_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ0OMR_TXQEN_1 (0x2U << ETH_MTLTXQ0OMR_TXQEN_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ0OMR_TTC_Pos (4U)
+#define ETH_MTLTXQ0OMR_TTC_Msk (0x7U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */
+#define ETH_MTLTXQ0OMR_TTC_0 (0x1U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ0OMR_TTC_1 (0x2U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ0OMR_TTC_2 (0x4U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ0OMR_TQS_Pos (16U)
+#define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFU << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */
+#define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */
+#define ETH_MTLTXQ0OMR_TQS_0 (0x1U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ0OMR_TQS_1 (0x2U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ0OMR_TQS_2 (0x4U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ0OMR_TQS_3 (0x8U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00080000 */
+#define ETH_MTLTXQ0OMR_TQS_4 (0x10U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ0OMR_TQS_5 (0x20U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ0OMR_TQS_6 (0x40U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00400000 */
+#define ETH_MTLTXQ0OMR_TQS_7 (0x80U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00800000 */
+#define ETH_MTLTXQ0OMR_TQS_8 (0x100U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01000000 */
+
+/************* Bit definition for ETH_MTLTXQ0UR register *************/
+#define ETH_MTLTXQ0UR_UFFRMCNT_Pos (0U)
+#define ETH_MTLTXQ0UR_UFFRMCNT_Msk (0x7FFU << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTXQ0UR_UFFRMCNT ETH_MTLTXQ0UR_UFFRMCNT_Msk /*!< Underflow Packet Counter */
+#define ETH_MTLTXQ0UR_UFFRMCNT_0 (0x1U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_1 (0x2U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_2 (0x4U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_3 (0x8U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_4 (0x10U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_5 (0x20U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_6 (0x40U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_7 (0x80U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_8 (0x100U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_9 (0x200U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ0UR_UFFRMCNT_10 (0x400U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ0UR_UFCNTOVF_Pos (11U)
+#define ETH_MTLTXQ0UR_UFCNTOVF_Msk (0x1U << ETH_MTLTXQ0UR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ0UR_UFCNTOVF ETH_MTLTXQ0UR_UFCNTOVF_Msk /*!< Overflow Bit for Underflow Packet Counter */
+
+/************* Bit definition for ETH_MTLTXQ0DR register *************/
+#define ETH_MTLTXQ0DR_TXQPAUSED_Pos (0U)
+#define ETH_MTLTXQ0DR_TXQPAUSED_Msk (0x1U << ETH_MTLTXQ0DR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ0DR_TXQPAUSED ETH_MTLTXQ0DR_TXQPAUSED_Msk /*!< Transmit Queue in Pause */
+#define ETH_MTLTXQ0DR_TRCSTS_Pos (1U)
+#define ETH_MTLTXQ0DR_TRCSTS_Msk (0x3U << ETH_MTLTXQ0DR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTXQ0DR_TRCSTS ETH_MTLTXQ0DR_TRCSTS_Msk /*!< MTL Tx Queue Read Controller Status */
+#define ETH_MTLTXQ0DR_TRCSTS_0 (0x1U << ETH_MTLTXQ0DR_TRCSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ0DR_TRCSTS_1 (0x2U << ETH_MTLTXQ0DR_TRCSTS_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ0DR_TWCSTS_Pos (3U)
+#define ETH_MTLTXQ0DR_TWCSTS_Msk (0x1U << ETH_MTLTXQ0DR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ0DR_TWCSTS ETH_MTLTXQ0DR_TWCSTS_Msk /*!< MTL Tx Queue Write Controller Status */
+#define ETH_MTLTXQ0DR_TXQSTS_Pos (4U)
+#define ETH_MTLTXQ0DR_TXQSTS_Msk (0x1U << ETH_MTLTXQ0DR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ0DR_TXQSTS ETH_MTLTXQ0DR_TXQSTS_Msk /*!< MTL Tx Queue Not Empty Status */
+#define ETH_MTLTXQ0DR_TXSTSFSTS_Pos (5U)
+#define ETH_MTLTXQ0DR_TXSTSFSTS_Msk (0x1U << ETH_MTLTXQ0DR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ0DR_TXSTSFSTS ETH_MTLTXQ0DR_TXSTSFSTS_Msk /*!< MTL Tx Status FIFO Full Status */
+#define ETH_MTLTXQ0DR_PTXQ_Pos (16U)
+#define ETH_MTLTXQ0DR_PTXQ_Msk (0x7U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTXQ0DR_PTXQ ETH_MTLTXQ0DR_PTXQ_Msk /*!< Number of Packets in the Transmit Queue */
+#define ETH_MTLTXQ0DR_PTXQ_0 (0x1U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ0DR_PTXQ_1 (0x2U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ0DR_PTXQ_2 (0x4U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ0DR_STXSTSF_Pos (20U)
+#define ETH_MTLTXQ0DR_STXSTSF_Msk (0x7U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTXQ0DR_STXSTSF ETH_MTLTXQ0DR_STXSTSF_Msk /*!< Number of Status Words in Tx Status FIFO of Queue */
+#define ETH_MTLTXQ0DR_STXSTSF_0 (0x1U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ0DR_STXSTSF_1 (0x2U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ0DR_STXSTSF_2 (0x4U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00400000 */
+
+/************ Bit definition for ETH_MTLTXQ0ESR register *************/
+#define ETH_MTLTXQ0ESR_ABS_Pos (0U)
+#define ETH_MTLTXQ0ESR_ABS_Msk (0xFFFFFFU << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00FFFFFF */
+#define ETH_MTLTXQ0ESR_ABS ETH_MTLTXQ0ESR_ABS_Msk /*!< Average Bits per Slot */
+#define ETH_MTLTXQ0ESR_ABS_0 (0x1U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ0ESR_ABS_1 (0x2U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ0ESR_ABS_2 (0x4U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ0ESR_ABS_3 (0x8U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ0ESR_ABS_4 (0x10U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ0ESR_ABS_5 (0x20U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ0ESR_ABS_6 (0x40U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ0ESR_ABS_7 (0x80U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ0ESR_ABS_8 (0x100U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ0ESR_ABS_9 (0x200U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ0ESR_ABS_10 (0x400U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ0ESR_ABS_11 (0x800U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ0ESR_ABS_12 (0x1000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00001000 */
+#define ETH_MTLTXQ0ESR_ABS_13 (0x2000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00002000 */
+#define ETH_MTLTXQ0ESR_ABS_14 (0x4000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00004000 */
+#define ETH_MTLTXQ0ESR_ABS_15 (0x8000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00008000 */
+#define ETH_MTLTXQ0ESR_ABS_16 (0x10000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ0ESR_ABS_17 (0x20000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ0ESR_ABS_18 (0x40000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ0ESR_ABS_19 (0x80000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00080000 */
+#define ETH_MTLTXQ0ESR_ABS_20 (0x100000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ0ESR_ABS_21 (0x200000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ0ESR_ABS_22 (0x400000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00400000 */
+#define ETH_MTLTXQ0ESR_ABS_23 (0x800000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00800000 */
+
+/************* Bit definition for ETH_MTLQ0ICSR register *************/
+#define ETH_MTLQ0ICSR_TXUNFIS_Pos (0U)
+#define ETH_MTLQ0ICSR_TXUNFIS_Msk (0x1U << ETH_MTLQ0ICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQ0ICSR_TXUNFIS ETH_MTLQ0ICSR_TXUNFIS_Msk /*!< Transmit Queue Underflow Interrupt Status */
+#define ETH_MTLQ0ICSR_ABPSIS_Pos (1U)
+#define ETH_MTLQ0ICSR_ABPSIS_Msk (0x1U << ETH_MTLQ0ICSR_ABPSIS_Pos) /*!< 0x00000002 */
+#define ETH_MTLQ0ICSR_ABPSIS ETH_MTLQ0ICSR_ABPSIS_Msk /*!< Average Bits Per Slot Interrupt Status */
+#define ETH_MTLQ0ICSR_TXUIE_Pos (8U)
+#define ETH_MTLQ0ICSR_TXUIE_Msk (0x1U << ETH_MTLQ0ICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQ0ICSR_TXUIE ETH_MTLQ0ICSR_TXUIE_Msk /*!< Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQ0ICSR_ABPSIE_Pos (9U)
+#define ETH_MTLQ0ICSR_ABPSIE_Msk (0x1U << ETH_MTLQ0ICSR_ABPSIE_Pos) /*!< 0x00000200 */
+#define ETH_MTLQ0ICSR_ABPSIE ETH_MTLQ0ICSR_ABPSIE_Msk /*!< Average Bits Per Slot Interrupt Enable */
+#define ETH_MTLQ0ICSR_RXOVFIS_Pos (16U)
+#define ETH_MTLQ0ICSR_RXOVFIS_Msk (0x1U << ETH_MTLQ0ICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQ0ICSR_RXOVFIS ETH_MTLQ0ICSR_RXOVFIS_Msk /*!< Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQ0ICSR_RXOIE_Pos (24U)
+#define ETH_MTLQ0ICSR_RXOIE_Msk (0x1U << ETH_MTLQ0ICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQ0ICSR_RXOIE ETH_MTLQ0ICSR_RXOIE_Msk /*!< Receive Queue Overflow Interrupt Enable */
+
+/************ Bit definition for ETH_MTLRXQ0OMR register *************/
+#define ETH_MTLRXQ0OMR_RTC_Pos (0U)
+#define ETH_MTLRXQ0OMR_RTC_Msk (0x3U << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */
+#define ETH_MTLRXQ0OMR_RTC_0 (0x1U << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ0OMR_RTC_1 (0x2U << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ0OMR_FUP_Pos (3U)
+#define ETH_MTLRXQ0OMR_FUP_Msk (0x1U << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */
+#define ETH_MTLRXQ0OMR_FEP_Pos (4U)
+#define ETH_MTLRXQ0OMR_FEP_Msk (0x1U << ETH_MTLRXQ0OMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQ0OMR_FEP ETH_MTLRXQ0OMR_FEP_Msk /*!< Forward Error Packets */
+#define ETH_MTLRXQ0OMR_RSF_Pos (5U)
+#define ETH_MTLRXQ0OMR_RSF_Msk (0x1U << ETH_MTLRXQ0OMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQ0OMR_RSF ETH_MTLRXQ0OMR_RSF_Msk /*!< Receive Queue Store and Forward */
+#define ETH_MTLRXQ0OMR_DIS_TCP_EF_Pos (6U)
+#define ETH_MTLRXQ0OMR_DIS_TCP_EF_Msk (0x1U << ETH_MTLRXQ0OMR_DIS_TCP_EF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQ0OMR_DIS_TCP_EF ETH_MTLRXQ0OMR_DIS_TCP_EF_Msk /*!< Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRXQ0OMR_EHFC_Pos (7U)
+#define ETH_MTLRXQ0OMR_EHFC_Msk (0x1U << ETH_MTLRXQ0OMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQ0OMR_EHFC ETH_MTLRXQ0OMR_EHFC_Msk /*!< Enable Hardware Flow Control */
+#define ETH_MTLRXQ0OMR_RFA_Pos (8U)
+#define ETH_MTLRXQ0OMR_RFA_Msk (0x7U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRXQ0OMR_RFA ETH_MTLRXQ0OMR_RFA_Msk /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRXQ0OMR_RFA_0 (0x1U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQ0OMR_RFA_1 (0x2U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000200 */
+#define ETH_MTLRXQ0OMR_RFA_2 (0x4U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000400 */
+#define ETH_MTLRXQ0OMR_RFD_Pos (14U)
+#define ETH_MTLRXQ0OMR_RFD_Msk (0x7U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRXQ0OMR_RFD ETH_MTLRXQ0OMR_RFD_Msk /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRXQ0OMR_RFD_0 (0x1U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x00004000 */
+#define ETH_MTLRXQ0OMR_RFD_1 (0x2U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x00008000 */
+#define ETH_MTLRXQ0OMR_RFD_2 (0x4U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x00010000 */
+#define ETH_MTLRXQ0OMR_RQS_Pos (20U)
+#define ETH_MTLRXQ0OMR_RQS_Msk (0xFU << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00F00000 */
+#define ETH_MTLRXQ0OMR_RQS ETH_MTLRXQ0OMR_RQS_Msk /*!< Receive Queue Size */
+#define ETH_MTLRXQ0OMR_RQS_0 (0x1U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00100000 */
+#define ETH_MTLRXQ0OMR_RQS_1 (0x2U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00200000 */
+#define ETH_MTLRXQ0OMR_RQS_2 (0x4U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00400000 */
+#define ETH_MTLRXQ0OMR_RQS_3 (0x8U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00800000 */
+
+/*********** Bit definition for ETH_MTLRXQ0MPOCR register ************/
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos (0U)
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_Msk (0x7FFU << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT ETH_MTLRXQ0MPOCR_OVFPKTCNT_Msk /*!< Overflow Packet Counter */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_0 (0x1U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_1 (0x2U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_2 (0x4U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_3 (0x8U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_4 (0x10U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_5 (0x20U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_6 (0x40U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_7 (0x80U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_8 (0x100U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_9 (0x200U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000200 */
+#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_10 (0x400U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000400 */
+#define ETH_MTLRXQ0MPOCR_OVFCNTOVF_Pos (11U)
+#define ETH_MTLRXQ0MPOCR_OVFCNTOVF_Msk (0x1U << ETH_MTLRXQ0MPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRXQ0MPOCR_OVFCNTOVF ETH_MTLRXQ0MPOCR_OVFCNTOVF_Msk /*!< Overflow Counter Overflow Bit */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos (16U)
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_Msk (0x7FFU << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT ETH_MTLRXQ0MPOCR_MISPKTCNT_Msk /*!< Missed Packet Counter */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_0 (0x1U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00010000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_1 (0x2U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00020000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_2 (0x4U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00040000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_3 (0x8U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00080000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_4 (0x10U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00100000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_5 (0x20U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00200000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_6 (0x40U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00400000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_7 (0x80U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00800000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_8 (0x100U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x01000000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_9 (0x200U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x02000000 */
+#define ETH_MTLRXQ0MPOCR_MISPKTCNT_10 (0x400U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x04000000 */
+#define ETH_MTLRXQ0MPOCR_MISCNTOVF_Pos (27U)
+#define ETH_MTLRXQ0MPOCR_MISCNTOVF_Msk (0x1U << ETH_MTLRXQ0MPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQ0MPOCR_MISCNTOVF ETH_MTLRXQ0MPOCR_MISCNTOVF_Msk /*!< Missed Packet Counter Overflow Bit */
+
+/************* Bit definition for ETH_MTLRXQ0DR register *************/
+#define ETH_MTLRXQ0DR_RWCSTS_Pos (0U)
+#define ETH_MTLRXQ0DR_RWCSTS_Msk (0x1U << ETH_MTLRXQ0DR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ0DR_RWCSTS ETH_MTLRXQ0DR_RWCSTS_Msk /*!< MTL Rx Queue Write Controller Active Status */
+#define ETH_MTLRXQ0DR_RRCSTS_Pos (1U)
+#define ETH_MTLRXQ0DR_RRCSTS_Msk (0x3U << ETH_MTLRXQ0DR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQ0DR_RRCSTS ETH_MTLRXQ0DR_RRCSTS_Msk /*!< MTL Rx Queue Read Controller State */
+#define ETH_MTLRXQ0DR_RRCSTS_0 (0x1U << ETH_MTLRXQ0DR_RRCSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ0DR_RRCSTS_1 (0x2U << ETH_MTLRXQ0DR_RRCSTS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQ0DR_RXQSTS_Pos (4U)
+#define ETH_MTLRXQ0DR_RXQSTS_Msk (0x3U << ETH_MTLRXQ0DR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQ0DR_RXQSTS ETH_MTLRXQ0DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRXQ0DR_RXQSTS_0 (0x1U << ETH_MTLRXQ0DR_RXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQ0DR_RXQSTS_1 (0x2U << ETH_MTLRXQ0DR_RXQSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQ0DR_PRXQ_Pos (16U)
+#define ETH_MTLRXQ0DR_PRXQ_Msk (0x3FFFU << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRXQ0DR_PRXQ ETH_MTLRXQ0DR_PRXQ_Msk /*!< Number of Packets in Receive Queue */
+#define ETH_MTLRXQ0DR_PRXQ_0 (0x1U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLRXQ0DR_PRXQ_1 (0x2U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00020000 */
+#define ETH_MTLRXQ0DR_PRXQ_2 (0x4U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00040000 */
+#define ETH_MTLRXQ0DR_PRXQ_3 (0x8U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00080000 */
+#define ETH_MTLRXQ0DR_PRXQ_4 (0x10U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00100000 */
+#define ETH_MTLRXQ0DR_PRXQ_5 (0x20U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00200000 */
+#define ETH_MTLRXQ0DR_PRXQ_6 (0x40U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00400000 */
+#define ETH_MTLRXQ0DR_PRXQ_7 (0x80U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00800000 */
+#define ETH_MTLRXQ0DR_PRXQ_8 (0x100U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x01000000 */
+#define ETH_MTLRXQ0DR_PRXQ_9 (0x200U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x02000000 */
+#define ETH_MTLRXQ0DR_PRXQ_10 (0x400U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x04000000 */
+#define ETH_MTLRXQ0DR_PRXQ_11 (0x800U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQ0DR_PRXQ_12 (0x1000U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x10000000 */
+#define ETH_MTLRXQ0DR_PRXQ_13 (0x2000U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x20000000 */
+
+/************* Bit definition for ETH_MTLRXQ0CR register *************/
+#define ETH_MTLRXQ0CR_RXQ_WEGT_Pos (0U)
+#define ETH_MTLRXQ0CR_RXQ_WEGT_Msk (0x7U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000007 */
+#define ETH_MTLRXQ0CR_RXQ_WEGT ETH_MTLRXQ0CR_RXQ_WEGT_Msk /*!< Receive Queue Weight */
+#define ETH_MTLRXQ0CR_RXQ_WEGT_0 (0x1U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ0CR_RXQ_WEGT_1 (0x2U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ0CR_RXQ_WEGT_2 (0x4U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Pos (3U)
+#define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Msk (0x1U << ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Msk /*!< Receive Queue Packet Arbitration */
+
+/************ Bit definition for ETH_MTLTXQ1OMR register *************/
+#define ETH_MTLTXQ1OMR_FTQ_Pos (0U)
+#define ETH_MTLTXQ1OMR_FTQ_Msk (0x1U << ETH_MTLTXQ1OMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1OMR_FTQ ETH_MTLTXQ1OMR_FTQ_Msk /*!< Flush Transmit Queue */
+#define ETH_MTLTXQ1OMR_TSF_Pos (1U)
+#define ETH_MTLTXQ1OMR_TSF_Msk (0x1U << ETH_MTLTXQ1OMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1OMR_TSF ETH_MTLTXQ1OMR_TSF_Msk /*!< Transmit Store and Forward */
+#define ETH_MTLTXQ1OMR_TXQEN_Pos (2U)
+#define ETH_MTLTXQ1OMR_TXQEN_Msk (0x3U << ETH_MTLTXQ1OMR_TXQEN_Pos) /*!< 0x0000000C */
+#define ETH_MTLTXQ1OMR_TXQEN ETH_MTLTXQ1OMR_TXQEN_Msk /*!< Transmit Queue Enable */
+#define ETH_MTLTXQ1OMR_TXQEN_0 (0x1U << ETH_MTLTXQ1OMR_TXQEN_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1OMR_TXQEN_1 (0x2U << ETH_MTLTXQ1OMR_TXQEN_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1OMR_TTC_Pos (4U)
+#define ETH_MTLTXQ1OMR_TTC_Msk (0x7U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQ1OMR_TTC ETH_MTLTXQ1OMR_TTC_Msk /*!< Transmit Threshold Control */
+#define ETH_MTLTXQ1OMR_TTC_0 (0x1U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1OMR_TTC_1 (0x2U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1OMR_TTC_2 (0x4U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1OMR_TQS_Pos (16U)
+#define ETH_MTLTXQ1OMR_TQS_Msk (0x1FFU << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x01FF0000 */
+#define ETH_MTLTXQ1OMR_TQS ETH_MTLTXQ1OMR_TQS_Msk /*!< Transmit Queue Size */
+#define ETH_MTLTXQ1OMR_TQS_0 (0x1U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ1OMR_TQS_1 (0x2U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ1OMR_TQS_2 (0x4U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ1OMR_TQS_3 (0x8U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00080000 */
+#define ETH_MTLTXQ1OMR_TQS_4 (0x10U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ1OMR_TQS_5 (0x20U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ1OMR_TQS_6 (0x40U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00400000 */
+#define ETH_MTLTXQ1OMR_TQS_7 (0x80U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00800000 */
+#define ETH_MTLTXQ1OMR_TQS_8 (0x100U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x01000000 */
+
+/************* Bit definition for ETH_MTLTXQ1UR register *************/
+#define ETH_MTLTXQ1UR_UFFRMCNT_Pos (0U)
+#define ETH_MTLTXQ1UR_UFFRMCNT_Msk (0x7FFU << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTXQ1UR_UFFRMCNT ETH_MTLTXQ1UR_UFFRMCNT_Msk /*!< Underflow Packet Counter */
+#define ETH_MTLTXQ1UR_UFFRMCNT_0 (0x1U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_1 (0x2U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_2 (0x4U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_3 (0x8U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_4 (0x10U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_5 (0x20U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_6 (0x40U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_7 (0x80U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_8 (0x100U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_9 (0x200U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ1UR_UFFRMCNT_10 (0x400U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ1UR_UFCNTOVF_Pos (11U)
+#define ETH_MTLTXQ1UR_UFCNTOVF_Msk (0x1U << ETH_MTLTXQ1UR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ1UR_UFCNTOVF ETH_MTLTXQ1UR_UFCNTOVF_Msk /*!< Overflow Bit for Underflow Packet Counter */
+
+/************* Bit definition for ETH_MTLTXQ1DR register *************/
+#define ETH_MTLTXQ1DR_TXQPAUSED_Pos (0U)
+#define ETH_MTLTXQ1DR_TXQPAUSED_Msk (0x1U << ETH_MTLTXQ1DR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1DR_TXQPAUSED ETH_MTLTXQ1DR_TXQPAUSED_Msk /*!< Transmit Queue in Pause */
+#define ETH_MTLTXQ1DR_TRCSTS_Pos (1U)
+#define ETH_MTLTXQ1DR_TRCSTS_Msk (0x3U << ETH_MTLTXQ1DR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTXQ1DR_TRCSTS ETH_MTLTXQ1DR_TRCSTS_Msk /*!< MTL Tx Queue Read Controller Status */
+#define ETH_MTLTXQ1DR_TRCSTS_0 (0x1U << ETH_MTLTXQ1DR_TRCSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1DR_TRCSTS_1 (0x2U << ETH_MTLTXQ1DR_TRCSTS_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1DR_TWCSTS_Pos (3U)
+#define ETH_MTLTXQ1DR_TWCSTS_Msk (0x1U << ETH_MTLTXQ1DR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1DR_TWCSTS ETH_MTLTXQ1DR_TWCSTS_Msk /*!< MTL Tx Queue Write Controller Status */
+#define ETH_MTLTXQ1DR_TXQSTS_Pos (4U)
+#define ETH_MTLTXQ1DR_TXQSTS_Msk (0x1U << ETH_MTLTXQ1DR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1DR_TXQSTS ETH_MTLTXQ1DR_TXQSTS_Msk /*!< MTL Tx Queue Not Empty Status */
+#define ETH_MTLTXQ1DR_TXSTSFSTS_Pos (5U)
+#define ETH_MTLTXQ1DR_TXSTSFSTS_Msk (0x1U << ETH_MTLTXQ1DR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1DR_TXSTSFSTS ETH_MTLTXQ1DR_TXSTSFSTS_Msk /*!< MTL Tx Status FIFO Full Status */
+#define ETH_MTLTXQ1DR_PTXQ_Pos (16U)
+#define ETH_MTLTXQ1DR_PTXQ_Msk (0x7U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTXQ1DR_PTXQ ETH_MTLTXQ1DR_PTXQ_Msk /*!< Number of Packets in the Transmit Queue */
+#define ETH_MTLTXQ1DR_PTXQ_0 (0x1U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ1DR_PTXQ_1 (0x2U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ1DR_PTXQ_2 (0x4U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ1DR_STXSTSF_Pos (20U)
+#define ETH_MTLTXQ1DR_STXSTSF_Msk (0x7U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTXQ1DR_STXSTSF ETH_MTLTXQ1DR_STXSTSF_Msk /*!< Number of Status Words in Tx Status FIFO of Queue */
+#define ETH_MTLTXQ1DR_STXSTSF_0 (0x1U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ1DR_STXSTSF_1 (0x2U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ1DR_STXSTSF_2 (0x4U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00400000 */
+
+/************ Bit definition for ETH_MTLTXQ1ECR register *************/
+#define ETH_MTLTXQ1ECR_AVALG_Pos (2U)
+#define ETH_MTLTXQ1ECR_AVALG_Msk (0x1U << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1ECR_AVALG ETH_MTLTXQ1ECR_AVALG_Msk /*!< AV Algorithm */
+#define ETH_MTLTXQ1ECR_CC_Pos (3U)
+#define ETH_MTLTXQ1ECR_CC_Msk (0x1U << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1ECR_CC ETH_MTLTXQ1ECR_CC_Msk /*!< Credit Control */
+#define ETH_MTLTXQ1ECR_SLC_Pos (4U)
+#define ETH_MTLTXQ1ECR_SLC_Msk (0x7U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTXQ1ECR_SLC ETH_MTLTXQ1ECR_SLC_Msk /*!< Slot Count */
+#define ETH_MTLTXQ1ECR_SLC_0 (0x1U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1ECR_SLC_1 (0x2U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1ECR_SLC_2 (0x4U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000040 */
+
+/************ Bit definition for ETH_MTLTXQ1ESR register *************/
+#define ETH_MTLTXQ1ESR_ABS_Pos (0U)
+#define ETH_MTLTXQ1ESR_ABS_Msk (0xFFFFFFU << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00FFFFFF */
+#define ETH_MTLTXQ1ESR_ABS ETH_MTLTXQ1ESR_ABS_Msk /*!< Average Bits per Slot */
+#define ETH_MTLTXQ1ESR_ABS_0 (0x1U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1ESR_ABS_1 (0x2U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1ESR_ABS_2 (0x4U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1ESR_ABS_3 (0x8U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1ESR_ABS_4 (0x10U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1ESR_ABS_5 (0x20U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1ESR_ABS_6 (0x40U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1ESR_ABS_7 (0x80U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ1ESR_ABS_8 (0x100U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ1ESR_ABS_9 (0x200U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ1ESR_ABS_10 (0x400U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ1ESR_ABS_11 (0x800U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ1ESR_ABS_12 (0x1000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00001000 */
+#define ETH_MTLTXQ1ESR_ABS_13 (0x2000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00002000 */
+#define ETH_MTLTXQ1ESR_ABS_14 (0x4000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00004000 */
+#define ETH_MTLTXQ1ESR_ABS_15 (0x8000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00008000 */
+#define ETH_MTLTXQ1ESR_ABS_16 (0x10000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ1ESR_ABS_17 (0x20000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ1ESR_ABS_18 (0x40000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ1ESR_ABS_19 (0x80000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00080000 */
+#define ETH_MTLTXQ1ESR_ABS_20 (0x100000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ1ESR_ABS_21 (0x200000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ1ESR_ABS_22 (0x400000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00400000 */
+#define ETH_MTLTXQ1ESR_ABS_23 (0x800000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00800000 */
+
+/************ Bit definition for ETH_MTLTXQ1QWR register *************/
+#define ETH_MTLTXQ1QWR_ISCQW_Pos (0U)
+#define ETH_MTLTXQ1QWR_ISCQW_Msk (0x1FFFFFU << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x001FFFFF */
+#define ETH_MTLTXQ1QWR_ISCQW ETH_MTLTXQ1QWR_ISCQW_Msk /*!< idleSlopeCredit value for queue 1 */
+#define ETH_MTLTXQ1QWR_ISCQW_0 (0x1U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1QWR_ISCQW_1 (0x2U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1QWR_ISCQW_2 (0x4U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1QWR_ISCQW_3 (0x8U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1QWR_ISCQW_4 (0x10U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1QWR_ISCQW_5 (0x20U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1QWR_ISCQW_6 (0x40U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1QWR_ISCQW_7 (0x80U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ1QWR_ISCQW_8 (0x100U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ1QWR_ISCQW_9 (0x200U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ1QWR_ISCQW_10 (0x400U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ1QWR_ISCQW_11 (0x800U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ1QWR_ISCQW_12 (0x1000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00001000 */
+#define ETH_MTLTXQ1QWR_ISCQW_13 (0x2000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00002000 */
+#define ETH_MTLTXQ1QWR_ISCQW_14 (0x4000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00004000 */
+#define ETH_MTLTXQ1QWR_ISCQW_15 (0x8000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00008000 */
+#define ETH_MTLTXQ1QWR_ISCQW_16 (0x10000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ1QWR_ISCQW_17 (0x20000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ1QWR_ISCQW_18 (0x40000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ1QWR_ISCQW_19 (0x80000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00080000 */
+#define ETH_MTLTXQ1QWR_ISCQW_20 (0x100000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00100000 */
+
+/************ Bit definition for ETH_MTLTXQ1SSCR register ************/
+#define ETH_MTLTXQ1SSCR_SSC_Pos (0U)
+#define ETH_MTLTXQ1SSCR_SSC_Msk (0x3FFFU << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
+#define ETH_MTLTXQ1SSCR_SSC ETH_MTLTXQ1SSCR_SSC_Msk /*!< sendSlopeCredit Value */
+#define ETH_MTLTXQ1SSCR_SSC_0 (0x1U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1SSCR_SSC_1 (0x2U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1SSCR_SSC_2 (0x4U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1SSCR_SSC_3 (0x8U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1SSCR_SSC_4 (0x10U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1SSCR_SSC_5 (0x20U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1SSCR_SSC_6 (0x40U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1SSCR_SSC_7 (0x80U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ1SSCR_SSC_8 (0x100U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ1SSCR_SSC_9 (0x200U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ1SSCR_SSC_10 (0x400U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ1SSCR_SSC_11 (0x800U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ1SSCR_SSC_12 (0x1000U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00001000 */
+#define ETH_MTLTXQ1SSCR_SSC_13 (0x2000U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00002000 */
+
+/************ Bit definition for ETH_MTLTXQ1HCR register *************/
+#define ETH_MTLTXQ1HCR_HC_Pos (0U)
+#define ETH_MTLTXQ1HCR_HC_Msk (0x1FFFFFFFU << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1HCR_HC ETH_MTLTXQ1HCR_HC_Msk /*!< hiCredit Value */
+#define ETH_MTLTXQ1HCR_HC_0 (0x1U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1HCR_HC_1 (0x2U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1HCR_HC_2 (0x4U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1HCR_HC_3 (0x8U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1HCR_HC_4 (0x10U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1HCR_HC_5 (0x20U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1HCR_HC_6 (0x40U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1HCR_HC_7 (0x80U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ1HCR_HC_8 (0x100U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ1HCR_HC_9 (0x200U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ1HCR_HC_10 (0x400U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ1HCR_HC_11 (0x800U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ1HCR_HC_12 (0x1000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00001000 */
+#define ETH_MTLTXQ1HCR_HC_13 (0x2000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00002000 */
+#define ETH_MTLTXQ1HCR_HC_14 (0x4000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00004000 */
+#define ETH_MTLTXQ1HCR_HC_15 (0x8000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00008000 */
+#define ETH_MTLTXQ1HCR_HC_16 (0x10000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ1HCR_HC_17 (0x20000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ1HCR_HC_18 (0x40000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ1HCR_HC_19 (0x80000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00080000 */
+#define ETH_MTLTXQ1HCR_HC_20 (0x100000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ1HCR_HC_21 (0x200000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ1HCR_HC_22 (0x400000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00400000 */
+#define ETH_MTLTXQ1HCR_HC_23 (0x800000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00800000 */
+#define ETH_MTLTXQ1HCR_HC_24 (0x1000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x01000000 */
+#define ETH_MTLTXQ1HCR_HC_25 (0x2000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x02000000 */
+#define ETH_MTLTXQ1HCR_HC_26 (0x4000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x04000000 */
+#define ETH_MTLTXQ1HCR_HC_27 (0x8000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x08000000 */
+#define ETH_MTLTXQ1HCR_HC_28 (0x10000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x10000000 */
+
+/************ Bit definition for ETH_MTLTXQ1LCR register *************/
+#define ETH_MTLTXQ1LCR_LC_Pos (0U)
+#define ETH_MTLTXQ1LCR_LC_Msk (0x1FFFFFFFU << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
+#define ETH_MTLTXQ1LCR_LC ETH_MTLTXQ1LCR_LC_Msk /*!< loCredit Value */
+#define ETH_MTLTXQ1LCR_LC_0 (0x1U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000001 */
+#define ETH_MTLTXQ1LCR_LC_1 (0x2U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000002 */
+#define ETH_MTLTXQ1LCR_LC_2 (0x4U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000004 */
+#define ETH_MTLTXQ1LCR_LC_3 (0x8U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000008 */
+#define ETH_MTLTXQ1LCR_LC_4 (0x10U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000010 */
+#define ETH_MTLTXQ1LCR_LC_5 (0x20U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000020 */
+#define ETH_MTLTXQ1LCR_LC_6 (0x40U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000040 */
+#define ETH_MTLTXQ1LCR_LC_7 (0x80U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000080 */
+#define ETH_MTLTXQ1LCR_LC_8 (0x100U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000100 */
+#define ETH_MTLTXQ1LCR_LC_9 (0x200U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000200 */
+#define ETH_MTLTXQ1LCR_LC_10 (0x400U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000400 */
+#define ETH_MTLTXQ1LCR_LC_11 (0x800U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000800 */
+#define ETH_MTLTXQ1LCR_LC_12 (0x1000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00001000 */
+#define ETH_MTLTXQ1LCR_LC_13 (0x2000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00002000 */
+#define ETH_MTLTXQ1LCR_LC_14 (0x4000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00004000 */
+#define ETH_MTLTXQ1LCR_LC_15 (0x8000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00008000 */
+#define ETH_MTLTXQ1LCR_LC_16 (0x10000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00010000 */
+#define ETH_MTLTXQ1LCR_LC_17 (0x20000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00020000 */
+#define ETH_MTLTXQ1LCR_LC_18 (0x40000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00040000 */
+#define ETH_MTLTXQ1LCR_LC_19 (0x80000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00080000 */
+#define ETH_MTLTXQ1LCR_LC_20 (0x100000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00100000 */
+#define ETH_MTLTXQ1LCR_LC_21 (0x200000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00200000 */
+#define ETH_MTLTXQ1LCR_LC_22 (0x400000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00400000 */
+#define ETH_MTLTXQ1LCR_LC_23 (0x800000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00800000 */
+#define ETH_MTLTXQ1LCR_LC_24 (0x1000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x01000000 */
+#define ETH_MTLTXQ1LCR_LC_25 (0x2000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x02000000 */
+#define ETH_MTLTXQ1LCR_LC_26 (0x4000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x04000000 */
+#define ETH_MTLTXQ1LCR_LC_27 (0x8000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x08000000 */
+#define ETH_MTLTXQ1LCR_LC_28 (0x10000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x10000000 */
+
+/************* Bit definition for ETH_MTLQ1ICSR register *************/
+#define ETH_MTLQ1ICSR_TXUNFIS_Pos (0U)
+#define ETH_MTLQ1ICSR_TXUNFIS_Msk (0x1U << ETH_MTLQ1ICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQ1ICSR_TXUNFIS ETH_MTLQ1ICSR_TXUNFIS_Msk /*!< Transmit Queue Underflow Interrupt Status */
+#define ETH_MTLQ1ICSR_ABPSIS_Pos (1U)
+#define ETH_MTLQ1ICSR_ABPSIS_Msk (0x1U << ETH_MTLQ1ICSR_ABPSIS_Pos) /*!< 0x00000002 */
+#define ETH_MTLQ1ICSR_ABPSIS ETH_MTLQ1ICSR_ABPSIS_Msk /*!< Average Bits Per Slot Interrupt Status */
+#define ETH_MTLQ1ICSR_TXUIE_Pos (8U)
+#define ETH_MTLQ1ICSR_TXUIE_Msk (0x1U << ETH_MTLQ1ICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQ1ICSR_TXUIE ETH_MTLQ1ICSR_TXUIE_Msk /*!< Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQ1ICSR_ABPSIE_Pos (9U)
+#define ETH_MTLQ1ICSR_ABPSIE_Msk (0x1U << ETH_MTLQ1ICSR_ABPSIE_Pos) /*!< 0x00000200 */
+#define ETH_MTLQ1ICSR_ABPSIE ETH_MTLQ1ICSR_ABPSIE_Msk /*!< Average Bits Per Slot Interrupt Enable */
+#define ETH_MTLQ1ICSR_RXOVFIS_Pos (16U)
+#define ETH_MTLQ1ICSR_RXOVFIS_Msk (0x1U << ETH_MTLQ1ICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQ1ICSR_RXOVFIS ETH_MTLQ1ICSR_RXOVFIS_Msk /*!< Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQ1ICSR_RXOIE_Pos (24U)
+#define ETH_MTLQ1ICSR_RXOIE_Msk (0x1U << ETH_MTLQ1ICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQ1ICSR_RXOIE ETH_MTLQ1ICSR_RXOIE_Msk /*!< Receive Queue Overflow Interrupt Enable */
+
+/************ Bit definition for ETH_MTLRXQ1OMR register *************/
+#define ETH_MTLRXQ1OMR_RTC_Pos (0U)
+#define ETH_MTLRXQ1OMR_RTC_Msk (0x3U << ETH_MTLRXQ1OMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRXQ1OMR_RTC ETH_MTLRXQ1OMR_RTC_Msk /*!< Receive Queue Threshold Control */
+#define ETH_MTLRXQ1OMR_RTC_0 (0x1U << ETH_MTLRXQ1OMR_RTC_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ1OMR_RTC_1 (0x2U << ETH_MTLRXQ1OMR_RTC_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ1OMR_FUP_Pos (3U)
+#define ETH_MTLRXQ1OMR_FUP_Msk (0x1U << ETH_MTLRXQ1OMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQ1OMR_FUP ETH_MTLRXQ1OMR_FUP_Msk /*!< Forward Undersized Good Packets */
+#define ETH_MTLRXQ1OMR_FEP_Pos (4U)
+#define ETH_MTLRXQ1OMR_FEP_Msk (0x1U << ETH_MTLRXQ1OMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQ1OMR_FEP ETH_MTLRXQ1OMR_FEP_Msk /*!< Forward Error Packets */
+#define ETH_MTLRXQ1OMR_RSF_Pos (5U)
+#define ETH_MTLRXQ1OMR_RSF_Msk (0x1U << ETH_MTLRXQ1OMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQ1OMR_RSF ETH_MTLRXQ1OMR_RSF_Msk /*!< Receive Queue Store and Forward */
+#define ETH_MTLRXQ1OMR_DIS_TCP_EF_Pos (6U)
+#define ETH_MTLRXQ1OMR_DIS_TCP_EF_Msk (0x1U << ETH_MTLRXQ1OMR_DIS_TCP_EF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQ1OMR_DIS_TCP_EF ETH_MTLRXQ1OMR_DIS_TCP_EF_Msk /*!< Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRXQ1OMR_EHFC_Pos (7U)
+#define ETH_MTLRXQ1OMR_EHFC_Msk (0x1U << ETH_MTLRXQ1OMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQ1OMR_EHFC ETH_MTLRXQ1OMR_EHFC_Msk /*!< Enable Hardware Flow Control */
+#define ETH_MTLRXQ1OMR_RFA_Pos (8U)
+#define ETH_MTLRXQ1OMR_RFA_Msk (0x7U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRXQ1OMR_RFA ETH_MTLRXQ1OMR_RFA_Msk /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRXQ1OMR_RFA_0 (0x1U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQ1OMR_RFA_1 (0x2U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000200 */
+#define ETH_MTLRXQ1OMR_RFA_2 (0x4U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000400 */
+#define ETH_MTLRXQ1OMR_RFD_Pos (14U)
+#define ETH_MTLRXQ1OMR_RFD_Msk (0x7U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRXQ1OMR_RFD ETH_MTLRXQ1OMR_RFD_Msk /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRXQ1OMR_RFD_0 (0x1U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x00004000 */
+#define ETH_MTLRXQ1OMR_RFD_1 (0x2U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x00008000 */
+#define ETH_MTLRXQ1OMR_RFD_2 (0x4U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x00010000 */
+#define ETH_MTLRXQ1OMR_RQS_Pos (20U)
+#define ETH_MTLRXQ1OMR_RQS_Msk (0xFU << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00F00000 */
+#define ETH_MTLRXQ1OMR_RQS ETH_MTLRXQ1OMR_RQS_Msk /*!< Receive Queue Size */
+#define ETH_MTLRXQ1OMR_RQS_0 (0x1U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00100000 */
+#define ETH_MTLRXQ1OMR_RQS_1 (0x2U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00200000 */
+#define ETH_MTLRXQ1OMR_RQS_2 (0x4U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00400000 */
+#define ETH_MTLRXQ1OMR_RQS_3 (0x8U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00800000 */
+
+/*********** Bit definition for ETH_MTLRXQ1MPOCR register ************/
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos (0U)
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_Msk (0x7FFU << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT ETH_MTLRXQ1MPOCR_OVFPKTCNT_Msk /*!< Overflow Packet Counter */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_0 (0x1U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_1 (0x2U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_2 (0x4U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_3 (0x8U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_4 (0x10U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_5 (0x20U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_6 (0x40U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000040 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_7 (0x80U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000080 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_8 (0x100U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000100 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_9 (0x200U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000200 */
+#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_10 (0x400U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000400 */
+#define ETH_MTLRXQ1MPOCR_OVFCNTOVF_Pos (11U)
+#define ETH_MTLRXQ1MPOCR_OVFCNTOVF_Msk (0x1U << ETH_MTLRXQ1MPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRXQ1MPOCR_OVFCNTOVF ETH_MTLRXQ1MPOCR_OVFCNTOVF_Msk /*!< Overflow Counter Overflow Bit */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos (16U)
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_Msk (0x7FFU << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT ETH_MTLRXQ1MPOCR_MISPKTCNT_Msk /*!< Missed Packet Counter */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_0 (0x1U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00010000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_1 (0x2U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00020000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_2 (0x4U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00040000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_3 (0x8U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00080000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_4 (0x10U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00100000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_5 (0x20U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00200000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_6 (0x40U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00400000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_7 (0x80U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00800000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_8 (0x100U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x01000000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_9 (0x200U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x02000000 */
+#define ETH_MTLRXQ1MPOCR_MISPKTCNT_10 (0x400U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x04000000 */
+#define ETH_MTLRXQ1MPOCR_MISCNTOVF_Pos (27U)
+#define ETH_MTLRXQ1MPOCR_MISCNTOVF_Msk (0x1U << ETH_MTLRXQ1MPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQ1MPOCR_MISCNTOVF ETH_MTLRXQ1MPOCR_MISCNTOVF_Msk /*!< Missed Packet Counter Overflow Bit */
+
+/************* Bit definition for ETH_MTLRXQ1DR register *************/
+#define ETH_MTLRXQ1DR_RWCSTS_Pos (0U)
+#define ETH_MTLRXQ1DR_RWCSTS_Msk (0x1U << ETH_MTLRXQ1DR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ1DR_RWCSTS ETH_MTLRXQ1DR_RWCSTS_Msk /*!< MTL Rx Queue Write Controller Active Status */
+#define ETH_MTLRXQ1DR_RRCSTS_Pos (1U)
+#define ETH_MTLRXQ1DR_RRCSTS_Msk (0x3U << ETH_MTLRXQ1DR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRXQ1DR_RRCSTS ETH_MTLRXQ1DR_RRCSTS_Msk /*!< MTL Rx Queue Read Controller State */
+#define ETH_MTLRXQ1DR_RRCSTS_0 (0x1U << ETH_MTLRXQ1DR_RRCSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ1DR_RRCSTS_1 (0x2U << ETH_MTLRXQ1DR_RRCSTS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQ1DR_RXQSTS_Pos (4U)
+#define ETH_MTLRXQ1DR_RXQSTS_Msk (0x3U << ETH_MTLRXQ1DR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRXQ1DR_RXQSTS ETH_MTLRXQ1DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRXQ1DR_RXQSTS_0 (0x1U << ETH_MTLRXQ1DR_RXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLRXQ1DR_RXQSTS_1 (0x2U << ETH_MTLRXQ1DR_RXQSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLRXQ1DR_PRXQ_Pos (16U)
+#define ETH_MTLRXQ1DR_PRXQ_Msk (0x3FFFU << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRXQ1DR_PRXQ ETH_MTLRXQ1DR_PRXQ_Msk /*!< Number of Packets in Receive Queue */
+#define ETH_MTLRXQ1DR_PRXQ_0 (0x1U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00010000 */
+#define ETH_MTLRXQ1DR_PRXQ_1 (0x2U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00020000 */
+#define ETH_MTLRXQ1DR_PRXQ_2 (0x4U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00040000 */
+#define ETH_MTLRXQ1DR_PRXQ_3 (0x8U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00080000 */
+#define ETH_MTLRXQ1DR_PRXQ_4 (0x10U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00100000 */
+#define ETH_MTLRXQ1DR_PRXQ_5 (0x20U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00200000 */
+#define ETH_MTLRXQ1DR_PRXQ_6 (0x40U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00400000 */
+#define ETH_MTLRXQ1DR_PRXQ_7 (0x80U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00800000 */
+#define ETH_MTLRXQ1DR_PRXQ_8 (0x100U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x01000000 */
+#define ETH_MTLRXQ1DR_PRXQ_9 (0x200U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x02000000 */
+#define ETH_MTLRXQ1DR_PRXQ_10 (0x400U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x04000000 */
+#define ETH_MTLRXQ1DR_PRXQ_11 (0x800U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x08000000 */
+#define ETH_MTLRXQ1DR_PRXQ_12 (0x1000U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x10000000 */
+#define ETH_MTLRXQ1DR_PRXQ_13 (0x2000U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x20000000 */
+
+/************* Bit definition for ETH_MTLRXQ1CR register *************/
+#define ETH_MTLRXQ1CR_RXQ_WEGT_Pos (0U)
+#define ETH_MTLRXQ1CR_RXQ_WEGT_Msk (0x7U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000007 */
+#define ETH_MTLRXQ1CR_RXQ_WEGT ETH_MTLRXQ1CR_RXQ_WEGT_Msk /*!< Receive Queue Weight */
+#define ETH_MTLRXQ1CR_RXQ_WEGT_0 (0x1U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000001 */
+#define ETH_MTLRXQ1CR_RXQ_WEGT_1 (0x2U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000002 */
+#define ETH_MTLRXQ1CR_RXQ_WEGT_2 (0x4U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000004 */
+#define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Pos (3U)
+#define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Msk (0x1U << ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Pos) /*!< 0x00000008 */
+#define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Msk /*!< Receive Queue Packet Arbitration */
+
+/*************** Bit definition for ETH_DMAMR register ***************/
+#define ETH_DMAMR_SWR_Pos (0U)
+#define ETH_DMAMR_SWR_Msk (0x1U << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /*!< Software Reset */
+#define ETH_DMAMR_TAA_Pos (2U)
+#define ETH_DMAMR_TAA_Msk (0x7U << ETH_DMAMR_TAA_Pos) /*!< 0x0000001C */
+#define ETH_DMAMR_TAA ETH_DMAMR_TAA_Msk /*!< Transmit Arbitration Algorithm */
+#define ETH_DMAMR_TAA_0 (0x1U << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */
+#define ETH_DMAMR_TAA_1 (0x2U << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */
+#define ETH_DMAMR_TAA_2 (0x4U << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */
+#define ETH_DMAMR_TXPR_Pos (11U)
+#define ETH_DMAMR_TXPR_Msk (0x1U << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */
+#define ETH_DMAMR_PR_Pos (12U)
+#define ETH_DMAMR_PR_Msk (0x7U << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
+#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */
+#define ETH_DMAMR_PR_0 (0x1U << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */
+#define ETH_DMAMR_PR_1 (0x2U << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */
+#define ETH_DMAMR_PR_2 (0x4U << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */
+#define ETH_DMAMR_INTM_Pos (16U)
+#define ETH_DMAMR_INTM_Msk (0x3U << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */
+#define ETH_DMAMR_INTM_0 (0x1U << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_1 (0x2U << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+
+/************** Bit definition for ETH_DMASBMR register **************/
+#define ETH_DMASBMR_FB_Pos (0U)
+#define ETH_DMASBMR_FB_Msk (0x1U << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /*!< Fixed Burst Length */
+#define ETH_DMASBMR_BLEN4_Pos (1U)
+#define ETH_DMASBMR_BLEN4_Msk (0x1U << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
+#define ETH_DMASBMR_BLEN4 ETH_DMASBMR_BLEN4_Msk /*!< AXI Burst Length 4 */
+#define ETH_DMASBMR_BLEN8_Pos (2U)
+#define ETH_DMASBMR_BLEN8_Msk (0x1U << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
+#define ETH_DMASBMR_BLEN8 ETH_DMASBMR_BLEN8_Msk /*!< AXI Burst Length 8 */
+#define ETH_DMASBMR_BLEN16_Pos (3U)
+#define ETH_DMASBMR_BLEN16_Msk (0x1U << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
+#define ETH_DMASBMR_BLEN16 ETH_DMASBMR_BLEN16_Msk /*!< AXI Burst Length 16 */
+#define ETH_DMASBMR_BLEN32_Pos (4U)
+#define ETH_DMASBMR_BLEN32_Msk (0x1U << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
+#define ETH_DMASBMR_BLEN32 ETH_DMASBMR_BLEN32_Msk /*!< AXI Burst Length 32 */
+#define ETH_DMASBMR_BLEN64_Pos (5U)
+#define ETH_DMASBMR_BLEN64_Msk (0x1U << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
+#define ETH_DMASBMR_BLEN64 ETH_DMASBMR_BLEN64_Msk /*!< AXI Burst Length 64 */
+#define ETH_DMASBMR_BLEN128_Pos (6U)
+#define ETH_DMASBMR_BLEN128_Msk (0x1U << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
+#define ETH_DMASBMR_BLEN128 ETH_DMASBMR_BLEN128_Msk /*!< AXI Burst Length 128 */
+#define ETH_DMASBMR_BLEN256_Pos (7U)
+#define ETH_DMASBMR_BLEN256_Msk (0x1U << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
+#define ETH_DMASBMR_BLEN256 ETH_DMASBMR_BLEN256_Msk /*!< AXI Burst Length 256 */
+#define ETH_DMASBMR_AAL_Pos (12U)
+#define ETH_DMASBMR_AAL_Msk (0x1U << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */
+#define ETH_DMASBMR_ONEKBBE_Pos (13U)
+#define ETH_DMASBMR_ONEKBBE_Msk (0x1U << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
+#define ETH_DMASBMR_ONEKBBE ETH_DMASBMR_ONEKBBE_Msk /*!< 1 Kbyte Boundary Crossing Enable for the AXI Master */
+#define ETH_DMASBMR_RD_OSR_LMT_Pos (16U)
+#define ETH_DMASBMR_RD_OSR_LMT_Msk (0x3U << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
+#define ETH_DMASBMR_RD_OSR_LMT ETH_DMASBMR_RD_OSR_LMT_Msk /*!< AXI Maximum Read Outstanding Request Limit */
+#define ETH_DMASBMR_RD_OSR_LMT_0 (0x1U << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
+#define ETH_DMASBMR_RD_OSR_LMT_1 (0x2U << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
+#define ETH_DMASBMR_WR_OSR_LMT_Pos (24U)
+#define ETH_DMASBMR_WR_OSR_LMT_Msk (0x3U << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
+#define ETH_DMASBMR_WR_OSR_LMT ETH_DMASBMR_WR_OSR_LMT_Msk /*!< AXI Maximum Write Outstanding Request Limit */
+#define ETH_DMASBMR_WR_OSR_LMT_0 (0x1U << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
+#define ETH_DMASBMR_WR_OSR_LMT_1 (0x2U << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
+#define ETH_DMASBMR_LPI_XIT_PKT_Pos (30U)
+#define ETH_DMASBMR_LPI_XIT_PKT_Msk (0x1U << ETH_DMASBMR_LPI_XIT_PKT_Pos) /*!< 0x40000000 */
+#define ETH_DMASBMR_LPI_XIT_PKT ETH_DMASBMR_LPI_XIT_PKT_Msk /*!< Unlock on Magic Packet or Remote wakeup Packet */
+#define ETH_DMASBMR_EN_LPI_Pos (31U)
+#define ETH_DMASBMR_EN_LPI_Msk (0x1U << ETH_DMASBMR_EN_LPI_Pos) /*!< 0x80000000 */
+#define ETH_DMASBMR_EN_LPI ETH_DMASBMR_EN_LPI_Msk /*!< Enable Low Power Interface (LPI) */
+
+/************** Bit definition for ETH_DMAISR register ***************/
+#define ETH_DMAISR_DC0IS_Pos (0U)
+#define ETH_DMAISR_DC0IS_Msk (0x1U << ETH_DMAISR_DC0IS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DC0IS ETH_DMAISR_DC0IS_Msk /*!< DMA Channel 0 Interrupt Status */
+#define ETH_DMAISR_DC1IS_Pos (1U)
+#define ETH_DMAISR_DC1IS_Msk (0x1U << ETH_DMAISR_DC1IS_Pos) /*!< 0x00000002 */
+#define ETH_DMAISR_DC1IS ETH_DMAISR_DC1IS_Msk /*!< DMA Channel 1 Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos (16U)
+#define ETH_DMAISR_MTLIS_Msk (0x1U << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /*!< MTL Interrupt Status */
+#define ETH_DMAISR_MACIS_Pos (17U)
+#define ETH_DMAISR_MACIS_Msk (0x1U << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /*!< MAC Interrupt Status */
+
+/************** Bit definition for ETH_DMADSR register ***************/
+#define ETH_DMADSR_AXWHSTS_Pos (0U)
+#define ETH_DMADSR_AXWHSTS_Msk (0x1U << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
+#define ETH_DMADSR_AXWHSTS ETH_DMADSR_AXWHSTS_Msk /*!< AXI Master Write Channel */
+#define ETH_DMADSR_AXRHSTS_Pos (1U)
+#define ETH_DMADSR_AXRHSTS_Msk (0x1U << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
+#define ETH_DMADSR_AXRHSTS ETH_DMADSR_AXRHSTS_Msk /*!< AXI Master Read Channel Status */
+#define ETH_DMADSR_RPS0_Pos (8U)
+#define ETH_DMADSR_RPS0_Msk (0xFU << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS0 ETH_DMADSR_RPS0_Msk /*!< DMA Channel 0 Receive Process State */
+#define ETH_DMADSR_RPS0_0 (0x1U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000100 */
+#define ETH_DMADSR_RPS0_1 (0x2U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000200 */
+#define ETH_DMADSR_RPS0_2 (0x4U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000400 */
+#define ETH_DMADSR_RPS0_3 (0x8U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000800 */
+#define ETH_DMADSR_TPS0_Pos (12U)
+#define ETH_DMADSR_TPS0_Msk (0xFU << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS0 ETH_DMADSR_TPS0_Msk /*!< DMA Channel 0 Transmit Process State */
+#define ETH_DMADSR_TPS0_0 (0x1U << ETH_DMADSR_TPS0_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS0_1 (0x2U << ETH_DMADSR_TPS0_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS0_2 (0x4U << ETH_DMADSR_TPS0_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS0_3 (0x8U << ETH_DMADSR_TPS0_Pos) /*!< 0x00008000 */
+#define ETH_DMADSR_RPS1_Pos (16U)
+#define ETH_DMADSR_RPS1_Msk (0xFU << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
+#define ETH_DMADSR_RPS1 ETH_DMADSR_RPS1_Msk /*!< DMA Channel 1 Receive Process State */
+#define ETH_DMADSR_RPS1_0 (0x1U << ETH_DMADSR_RPS1_Pos) /*!< 0x00010000 */
+#define ETH_DMADSR_RPS1_1 (0x2U << ETH_DMADSR_RPS1_Pos) /*!< 0x00020000 */
+#define ETH_DMADSR_RPS1_2 (0x4U << ETH_DMADSR_RPS1_Pos) /*!< 0x00040000 */
+#define ETH_DMADSR_RPS1_3 (0x8U << ETH_DMADSR_RPS1_Pos) /*!< 0x00080000 */
+#define ETH_DMADSR_TPS1_Pos (20U)
+#define ETH_DMADSR_TPS1_Msk (0xFU << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
+#define ETH_DMADSR_TPS1 ETH_DMADSR_TPS1_Msk /*!< DMA Channel 1 Transmit Process State */
+#define ETH_DMADSR_TPS1_0 (0x1U << ETH_DMADSR_TPS1_Pos) /*!< 0x00100000 */
+#define ETH_DMADSR_TPS1_1 (0x2U << ETH_DMADSR_TPS1_Pos) /*!< 0x00200000 */
+#define ETH_DMADSR_TPS1_2 (0x4U << ETH_DMADSR_TPS1_Pos) /*!< 0x00400000 */
+#define ETH_DMADSR_TPS1_3 (0x8U << ETH_DMADSR_TPS1_Pos) /*!< 0x00800000 */
+
+/************ Bit definition for ETH_DMAA4TXACR register *************/
+#define ETH_DMAA4TXACR_TDRC_Pos (0U)
+#define ETH_DMAA4TXACR_TDRC_Msk (0xFU << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4TXACR_TDRC ETH_DMAA4TXACR_TDRC_Msk /*!< Transmit DMA Read Descriptor Cache Control */
+#define ETH_DMAA4TXACR_TDRC_0 (0x1U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000001 */
+#define ETH_DMAA4TXACR_TDRC_1 (0x2U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000002 */
+#define ETH_DMAA4TXACR_TDRC_2 (0x4U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000004 */
+#define ETH_DMAA4TXACR_TDRC_3 (0x8U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000008 */
+#define ETH_DMAA4TXACR_TEC_Pos (8U)
+#define ETH_DMAA4TXACR_TEC_Msk (0xFU << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4TXACR_TEC ETH_DMAA4TXACR_TEC_Msk /*!< Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
+#define ETH_DMAA4TXACR_TEC_0 (0x1U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000100 */
+#define ETH_DMAA4TXACR_TEC_1 (0x2U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000200 */
+#define ETH_DMAA4TXACR_TEC_2 (0x4U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000400 */
+#define ETH_DMAA4TXACR_TEC_3 (0x8U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000800 */
+#define ETH_DMAA4TXACR_THC_Pos (16U)
+#define ETH_DMAA4TXACR_THC_Msk (0xFU << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4TXACR_THC ETH_DMAA4TXACR_THC_Msk /*!< Transmit DMA First Packet Buffer or TSO Header Cache Control */
+#define ETH_DMAA4TXACR_THC_0 (0x1U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00010000 */
+#define ETH_DMAA4TXACR_THC_1 (0x2U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00020000 */
+#define ETH_DMAA4TXACR_THC_2 (0x4U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00040000 */
+#define ETH_DMAA4TXACR_THC_3 (0x8U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00080000 */
+
+/************ Bit definition for ETH_DMAA4RXACR register *************/
+#define ETH_DMAA4RXACR_RDWC_Pos (0U)
+#define ETH_DMAA4RXACR_RDWC_Msk (0xFU << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4RXACR_RDWC ETH_DMAA4RXACR_RDWC_Msk /*!< Receive DMA Write Descriptor Cache Control */
+#define ETH_DMAA4RXACR_RDWC_0 (0x1U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000001 */
+#define ETH_DMAA4RXACR_RDWC_1 (0x2U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000002 */
+#define ETH_DMAA4RXACR_RDWC_2 (0x4U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000004 */
+#define ETH_DMAA4RXACR_RDWC_3 (0x8U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000008 */
+#define ETH_DMAA4RXACR_RPC_Pos (8U)
+#define ETH_DMAA4RXACR_RPC_Msk (0xFU << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4RXACR_RPC ETH_DMAA4RXACR_RPC_Msk /*!< Receive DMA Payload Cache Control */
+#define ETH_DMAA4RXACR_RPC_0 (0x1U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000100 */
+#define ETH_DMAA4RXACR_RPC_1 (0x2U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000200 */
+#define ETH_DMAA4RXACR_RPC_2 (0x4U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000400 */
+#define ETH_DMAA4RXACR_RPC_3 (0x8U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000800 */
+#define ETH_DMAA4RXACR_RHC_Pos (16U)
+#define ETH_DMAA4RXACR_RHC_Msk (0xFU << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
+#define ETH_DMAA4RXACR_RHC ETH_DMAA4RXACR_RHC_Msk /*!< Receive DMA Header Cache Control */
+#define ETH_DMAA4RXACR_RHC_0 (0x1U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00010000 */
+#define ETH_DMAA4RXACR_RHC_1 (0x2U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00020000 */
+#define ETH_DMAA4RXACR_RHC_2 (0x4U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00040000 */
+#define ETH_DMAA4RXACR_RHC_3 (0x8U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00080000 */
+#define ETH_DMAA4RXACR_RDC_Pos (24U)
+#define ETH_DMAA4RXACR_RDC_Msk (0xFU << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
+#define ETH_DMAA4RXACR_RDC ETH_DMAA4RXACR_RDC_Msk /*!< Receive DMA Buffer Cache Control */
+#define ETH_DMAA4RXACR_RDC_0 (0x1U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x01000000 */
+#define ETH_DMAA4RXACR_RDC_1 (0x2U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x02000000 */
+#define ETH_DMAA4RXACR_RDC_2 (0x4U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x04000000 */
+#define ETH_DMAA4RXACR_RDC_3 (0x8U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x08000000 */
+
+/************* Bit definition for ETH_DMAA4DACR register *************/
+#define ETH_DMAA4DACR_TDWC_Pos (0U)
+#define ETH_DMAA4DACR_TDWC_Msk (0xFU << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
+#define ETH_DMAA4DACR_TDWC ETH_DMAA4DACR_TDWC_Msk /*!< Transmit DMA Write Descriptor Cache control */
+#define ETH_DMAA4DACR_TDWC_0 (0x1U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000001 */
+#define ETH_DMAA4DACR_TDWC_1 (0x2U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000002 */
+#define ETH_DMAA4DACR_TDWC_2 (0x4U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000004 */
+#define ETH_DMAA4DACR_TDWC_3 (0x8U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000008 */
+#define ETH_DMAA4DACR_TDWD_Pos (4U)
+#define ETH_DMAA4DACR_TDWD_Msk (0x3U << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
+#define ETH_DMAA4DACR_TDWD ETH_DMAA4DACR_TDWD_Msk /*!< Transmit DMA Write Descriptor Domain control */
+#define ETH_DMAA4DACR_TDWD_0 (0x1U << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000010 */
+#define ETH_DMAA4DACR_TDWD_1 (0x2U << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000020 */
+#define ETH_DMAA4DACR_RDRC_Pos (8U)
+#define ETH_DMAA4DACR_RDRC_Msk (0xFU << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
+#define ETH_DMAA4DACR_RDRC ETH_DMAA4DACR_RDRC_Msk /*!< Receive DMA Read Descriptor Cache control */
+#define ETH_DMAA4DACR_RDRC_0 (0x1U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000100 */
+#define ETH_DMAA4DACR_RDRC_1 (0x2U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000200 */
+#define ETH_DMAA4DACR_RDRC_2 (0x4U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000400 */
+#define ETH_DMAA4DACR_RDRC_3 (0x8U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000800 */
+
+/************** Bit definition for ETH_DMAC0CR register **************/
+#define ETH_DMAC0CR_MSS_Pos (0U)
+#define ETH_DMAC0CR_MSS_Msk (0x3FFFU << ETH_DMAC0CR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMAC0CR_MSS ETH_DMAC0CR_MSS_Msk /*!< Maximum Segment Size */
+#define ETH_DMAC0CR_MSS_0 (0x1U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0CR_MSS_1 (0x2U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0CR_MSS_2 (0x4U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0CR_MSS_3 (0x8U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0CR_MSS_4 (0x10U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0CR_MSS_5 (0x20U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0CR_MSS_6 (0x40U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0CR_MSS_7 (0x80U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0CR_MSS_8 (0x100U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0CR_MSS_9 (0x200U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0CR_MSS_10 (0x400U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0CR_MSS_11 (0x800U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0CR_MSS_12 (0x1000U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0CR_MSS_13 (0x2000U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0CR_PBLX8_Pos (16U)
+#define ETH_DMAC0CR_PBLX8_Msk (0x1U << ETH_DMAC0CR_PBLX8_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0CR_PBLX8 ETH_DMAC0CR_PBLX8_Msk /*!< 8xPBL mode */
+#define ETH_DMAC0CR_DSL_Pos (18U)
+#define ETH_DMAC0CR_DSL_Msk (0x7U << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */
+#define ETH_DMAC0CR_DSL_0 (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0CR_DSL_1 (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0CR_DSL_2 (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */
+
+/************* Bit definition for ETH_DMAC0TXCR register *************/
+#define ETH_DMAC0TXCR_ST_Pos (0U)
+#define ETH_DMAC0TXCR_ST_Msk (0x1U << ETH_DMAC0TXCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0TXCR_ST ETH_DMAC0TXCR_ST_Msk /*!< Start or Stop Transmission Command */
+#define ETH_DMAC0TXCR_TCW_Pos (1U)
+#define ETH_DMAC0TXCR_TCW_Msk (0x7U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x0000000E */
+#define ETH_DMAC0TXCR_TCW ETH_DMAC0TXCR_TCW_Msk /*!< Transmit Channel Weight */
+#define ETH_DMAC0TXCR_TCW_0 (0x1U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0TXCR_TCW_1 (0x2U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0TXCR_TCW_2 (0x4U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0TXCR_OSF_Pos (4U)
+#define ETH_DMAC0TXCR_OSF_Msk (0x1U << ETH_DMAC0TXCR_OSF_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0TXCR_OSF ETH_DMAC0TXCR_OSF_Msk /*!< Operate on Second Packet */
+#define ETH_DMAC0TXCR_TSE_Pos (12U)
+#define ETH_DMAC0TXCR_TSE_Msk (0x1U << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */
+#define ETH_DMAC0TXCR_TXPBL_Pos (16U)
+#define ETH_DMAC0TXCR_TXPBL_Msk (0x3FU << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */
+#define ETH_DMAC0TXCR_TXPBL_0 (0x1U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0TXCR_TXPBL_1 (0x2U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0TXCR_TXPBL_2 (0x4U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0TXCR_TXPBL_3 (0x8U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0TXCR_TXPBL_4 (0x10U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0TXCR_TXPBL_5 (0x20U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0TXCR_TQOS_Pos (24U)
+#define ETH_DMAC0TXCR_TQOS_Msk (0xFU << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */
+#define ETH_DMAC0TXCR_TQOS_0 (0x1U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0TXCR_TQOS_1 (0x2U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0TXCR_TQOS_2 (0x4U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0TXCR_TQOS_3 (0x8U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x08000000 */
+
+/************* Bit definition for ETH_DMAC0RXCR register *************/
+#define ETH_DMAC0RXCR_SR_Pos (0U)
+#define ETH_DMAC0RXCR_SR_Msk (0x1U << ETH_DMAC0RXCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0RXCR_SR ETH_DMAC0RXCR_SR_Msk /*!< Start or Stop Receive */
+#define ETH_DMAC0RXCR_RBSZ_Pos (1U)
+#define ETH_DMAC0RXCR_RBSZ_Msk (0x3FFFU << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00007FFE */
+#define ETH_DMAC0RXCR_RBSZ ETH_DMAC0RXCR_RBSZ_Msk /*!< Receive Buffer size */
+#define ETH_DMAC0RXCR_RBSZ_0 (0x1U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0RXCR_RBSZ_1 (0x2U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0RXCR_RBSZ_2 (0x4U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0RXCR_RBSZ_3 (0x8U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0RXCR_RBSZ_4 (0x10U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0RXCR_RBSZ_5 (0x20U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0RXCR_RBSZ_6 (0x40U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0RXCR_RBSZ_7 (0x80U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0RXCR_RBSZ_8 (0x100U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0RXCR_RBSZ_9 (0x200U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0RXCR_RBSZ_10 (0x400U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0RXCR_RBSZ_11 (0x800U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0RXCR_RBSZ_12 (0x1000U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0RXCR_RBSZ_13 (0x2000U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0RXCR_RXPBL_Pos (16U)
+#define ETH_DMAC0RXCR_RXPBL_Msk (0x3FU << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */
+#define ETH_DMAC0RXCR_RXPBL_0 (0x1U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0RXCR_RXPBL_1 (0x2U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0RXCR_RXPBL_2 (0x4U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0RXCR_RXPBL_3 (0x8U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0RXCR_RXPBL_4 (0x10U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0RXCR_RXPBL_5 (0x20U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0RXCR_RQOS_Pos (24U)
+#define ETH_DMAC0RXCR_RQOS_Msk (0xFU << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */
+#define ETH_DMAC0RXCR_RQOS_0 (0x1U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0RXCR_RQOS_1 (0x2U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0RXCR_RQOS_2 (0x4U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0RXCR_RQOS_3 (0x8U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0RXCR_RPF_Pos (31U)
+#define ETH_DMAC0RXCR_RPF_Msk (0x1U << ETH_DMAC0RXCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMAC0RXCR_RPF ETH_DMAC0RXCR_RPF_Msk /*!< DMA Rx Channel0 Packet Flush */
+
+/************ Bit definition for ETH_DMAC0TXDLAR register ************/
+#define ETH_DMAC0TXDLAR_TDESLA_Pos (3U)
+#define ETH_DMAC0TXDLAR_TDESLA_Msk (0x1FFFFFFFU << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0xFFFFFFF8 */
+#define ETH_DMAC0TXDLAR_TDESLA ETH_DMAC0TXDLAR_TDESLA_Msk /*!< Start of Transmit List */
+#define ETH_DMAC0TXDLAR_TDESLA_0 (0x1U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0TXDLAR_TDESLA_1 (0x2U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0TXDLAR_TDESLA_2 (0x4U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0TXDLAR_TDESLA_3 (0x8U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0TXDLAR_TDESLA_4 (0x10U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0TXDLAR_TDESLA_5 (0x20U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0TXDLAR_TDESLA_6 (0x40U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0TXDLAR_TDESLA_7 (0x80U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0TXDLAR_TDESLA_8 (0x100U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0TXDLAR_TDESLA_9 (0x200U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0TXDLAR_TDESLA_10 (0x400U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0TXDLAR_TDESLA_11 (0x800U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0TXDLAR_TDESLA_12 (0x1000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0TXDLAR_TDESLA_13 (0x2000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0TXDLAR_TDESLA_14 (0x4000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0TXDLAR_TDESLA_15 (0x8000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0TXDLAR_TDESLA_16 (0x10000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0TXDLAR_TDESLA_17 (0x20000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0TXDLAR_TDESLA_18 (0x40000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0TXDLAR_TDESLA_19 (0x80000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0TXDLAR_TDESLA_20 (0x100000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0TXDLAR_TDESLA_21 (0x200000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0TXDLAR_TDESLA_22 (0x400000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0TXDLAR_TDESLA_23 (0x800000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0TXDLAR_TDESLA_24 (0x1000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0TXDLAR_TDESLA_25 (0x2000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0TXDLAR_TDESLA_26 (0x4000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0TXDLAR_TDESLA_27 (0x8000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0TXDLAR_TDESLA_28 (0x10000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC0RXDLAR register ************/
+#define ETH_DMAC0RXDLAR_RDESLA_Pos (3U)
+#define ETH_DMAC0RXDLAR_RDESLA_Msk (0x1FFFFFFFU << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0xFFFFFFF8 */
+#define ETH_DMAC0RXDLAR_RDESLA ETH_DMAC0RXDLAR_RDESLA_Msk /*!< Start of Receive List */
+#define ETH_DMAC0RXDLAR_RDESLA_0 (0x1U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0RXDLAR_RDESLA_1 (0x2U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0RXDLAR_RDESLA_2 (0x4U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0RXDLAR_RDESLA_3 (0x8U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0RXDLAR_RDESLA_4 (0x10U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0RXDLAR_RDESLA_5 (0x20U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0RXDLAR_RDESLA_6 (0x40U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0RXDLAR_RDESLA_7 (0x80U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0RXDLAR_RDESLA_8 (0x100U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0RXDLAR_RDESLA_9 (0x200U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0RXDLAR_RDESLA_10 (0x400U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0RXDLAR_RDESLA_11 (0x800U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0RXDLAR_RDESLA_12 (0x1000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0RXDLAR_RDESLA_13 (0x2000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0RXDLAR_RDESLA_14 (0x4000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0RXDLAR_RDESLA_15 (0x8000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0RXDLAR_RDESLA_16 (0x10000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0RXDLAR_RDESLA_17 (0x20000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0RXDLAR_RDESLA_18 (0x40000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0RXDLAR_RDESLA_19 (0x80000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0RXDLAR_RDESLA_20 (0x100000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0RXDLAR_RDESLA_21 (0x200000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0RXDLAR_RDESLA_22 (0x400000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0RXDLAR_RDESLA_23 (0x800000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0RXDLAR_RDESLA_24 (0x1000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0RXDLAR_RDESLA_25 (0x2000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0RXDLAR_RDESLA_26 (0x4000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0RXDLAR_RDESLA_27 (0x8000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0RXDLAR_RDESLA_28 (0x10000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC0TXDTPR register ************/
+#define ETH_DMAC0TXDTPR_TDT_Pos (3U)
+#define ETH_DMAC0TXDTPR_TDT_Msk (0x1FFFFFFFU << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0xFFFFFFF8 */
+#define ETH_DMAC0TXDTPR_TDT ETH_DMAC0TXDTPR_TDT_Msk /*!< Transmit Descriptor Tail Pointer */
+#define ETH_DMAC0TXDTPR_TDT_0 (0x1U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0TXDTPR_TDT_1 (0x2U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0TXDTPR_TDT_2 (0x4U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0TXDTPR_TDT_3 (0x8U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0TXDTPR_TDT_4 (0x10U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0TXDTPR_TDT_5 (0x20U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0TXDTPR_TDT_6 (0x40U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0TXDTPR_TDT_7 (0x80U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0TXDTPR_TDT_8 (0x100U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0TXDTPR_TDT_9 (0x200U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0TXDTPR_TDT_10 (0x400U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0TXDTPR_TDT_11 (0x800U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0TXDTPR_TDT_12 (0x1000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0TXDTPR_TDT_13 (0x2000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0TXDTPR_TDT_14 (0x4000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0TXDTPR_TDT_15 (0x8000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0TXDTPR_TDT_16 (0x10000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0TXDTPR_TDT_17 (0x20000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0TXDTPR_TDT_18 (0x40000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0TXDTPR_TDT_19 (0x80000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0TXDTPR_TDT_20 (0x100000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0TXDTPR_TDT_21 (0x200000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0TXDTPR_TDT_22 (0x400000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0TXDTPR_TDT_23 (0x800000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0TXDTPR_TDT_24 (0x1000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0TXDTPR_TDT_25 (0x2000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0TXDTPR_TDT_26 (0x4000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0TXDTPR_TDT_27 (0x8000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0TXDTPR_TDT_28 (0x10000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC0RXDTPR register ************/
+#define ETH_DMAC0RXDTPR_RDT_Pos (3U)
+#define ETH_DMAC0RXDTPR_RDT_Msk (0x1FFFFFFFU << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0xFFFFFFF8 */
+#define ETH_DMAC0RXDTPR_RDT ETH_DMAC0RXDTPR_RDT_Msk /*!< Receive Descriptor Tail Pointer */
+#define ETH_DMAC0RXDTPR_RDT_0 (0x1U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0RXDTPR_RDT_1 (0x2U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0RXDTPR_RDT_2 (0x4U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0RXDTPR_RDT_3 (0x8U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0RXDTPR_RDT_4 (0x10U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0RXDTPR_RDT_5 (0x20U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0RXDTPR_RDT_6 (0x40U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0RXDTPR_RDT_7 (0x80U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0RXDTPR_RDT_8 (0x100U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0RXDTPR_RDT_9 (0x200U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0RXDTPR_RDT_10 (0x400U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0RXDTPR_RDT_11 (0x800U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0RXDTPR_RDT_12 (0x1000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0RXDTPR_RDT_13 (0x2000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0RXDTPR_RDT_14 (0x4000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0RXDTPR_RDT_15 (0x8000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0RXDTPR_RDT_16 (0x10000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0RXDTPR_RDT_17 (0x20000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0RXDTPR_RDT_18 (0x40000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0RXDTPR_RDT_19 (0x80000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0RXDTPR_RDT_20 (0x100000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0RXDTPR_RDT_21 (0x200000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0RXDTPR_RDT_22 (0x400000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0RXDTPR_RDT_23 (0x800000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0RXDTPR_RDT_24 (0x1000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0RXDTPR_RDT_25 (0x2000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0RXDTPR_RDT_26 (0x4000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0RXDTPR_RDT_27 (0x8000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0RXDTPR_RDT_28 (0x10000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC0TXRLR register *************/
+#define ETH_DMAC0TXRLR_TDRL_Pos (0U)
+#define ETH_DMAC0TXRLR_TDRL_Msk (0x3FFU << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMAC0TXRLR_TDRL ETH_DMAC0TXRLR_TDRL_Msk /*!< Transmit Descriptor Ring Length */
+#define ETH_DMAC0TXRLR_TDRL_0 (0x1U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0TXRLR_TDRL_1 (0x2U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0TXRLR_TDRL_2 (0x4U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0TXRLR_TDRL_3 (0x8U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0TXRLR_TDRL_4 (0x10U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0TXRLR_TDRL_5 (0x20U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0TXRLR_TDRL_6 (0x40U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0TXRLR_TDRL_7 (0x80U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0TXRLR_TDRL_8 (0x100U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0TXRLR_TDRL_9 (0x200U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000200 */
+
+/************ Bit definition for ETH_DMAC0RXRLR register *************/
+#define ETH_DMAC0RXRLR_RDRL_Pos (0U)
+#define ETH_DMAC0RXRLR_RDRL_Msk (0x3FFU << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMAC0RXRLR_RDRL ETH_DMAC0RXRLR_RDRL_Msk /*!< Receive Descriptor Ring Length */
+#define ETH_DMAC0RXRLR_RDRL_0 (0x1U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0RXRLR_RDRL_1 (0x2U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0RXRLR_RDRL_2 (0x4U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0RXRLR_RDRL_3 (0x8U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0RXRLR_RDRL_4 (0x10U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0RXRLR_RDRL_5 (0x20U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0RXRLR_RDRL_6 (0x40U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0RXRLR_RDRL_7 (0x80U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0RXRLR_RDRL_8 (0x100U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0RXRLR_RDRL_9 (0x200U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000200 */
+
+/************* Bit definition for ETH_DMAC0IER register **************/
+#define ETH_DMAC0IER_TIE_Pos (0U)
+#define ETH_DMAC0IER_TIE_Msk (0x1U << ETH_DMAC0IER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0IER_TIE ETH_DMAC0IER_TIE_Msk /*!< Transmit Interrupt Enable */
+#define ETH_DMAC0IER_TXSE_Pos (1U)
+#define ETH_DMAC0IER_TXSE_Msk (0x1U << ETH_DMAC0IER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0IER_TXSE ETH_DMAC0IER_TXSE_Msk /*!< Transmit Stopped Enable */
+#define ETH_DMAC0IER_TBUE_Pos (2U)
+#define ETH_DMAC0IER_TBUE_Msk (0x1U << ETH_DMAC0IER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0IER_TBUE ETH_DMAC0IER_TBUE_Msk /*!< Transmit Buffer Unavailable Enable */
+#define ETH_DMAC0IER_RIE_Pos (6U)
+#define ETH_DMAC0IER_RIE_Msk (0x1U << ETH_DMAC0IER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0IER_RIE ETH_DMAC0IER_RIE_Msk /*!< Receive Interrupt Enable */
+#define ETH_DMAC0IER_RBUE_Pos (7U)
+#define ETH_DMAC0IER_RBUE_Msk (0x1U << ETH_DMAC0IER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0IER_RBUE ETH_DMAC0IER_RBUE_Msk /*!< Receive Buffer Unavailable Enable */
+#define ETH_DMAC0IER_RSE_Pos (8U)
+#define ETH_DMAC0IER_RSE_Msk (0x1U << ETH_DMAC0IER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0IER_RSE ETH_DMAC0IER_RSE_Msk /*!< Receive Stopped Enable */
+#define ETH_DMAC0IER_RWTE_Pos (9U)
+#define ETH_DMAC0IER_RWTE_Msk (0x1U << ETH_DMAC0IER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0IER_RWTE ETH_DMAC0IER_RWTE_Msk /*!< Receive Watchdog Timeout Enable */
+#define ETH_DMAC0IER_ETIE_Pos (10U)
+#define ETH_DMAC0IER_ETIE_Msk (0x1U << ETH_DMAC0IER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0IER_ETIE ETH_DMAC0IER_ETIE_Msk /*!< Early Transmit Interrupt Enable */
+#define ETH_DMAC0IER_ERIE_Pos (11U)
+#define ETH_DMAC0IER_ERIE_Msk (0x1U << ETH_DMAC0IER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0IER_ERIE ETH_DMAC0IER_ERIE_Msk /*!< Early Receive Interrupt Enable */
+#define ETH_DMAC0IER_FBEE_Pos (12U)
+#define ETH_DMAC0IER_FBEE_Msk (0x1U << ETH_DMAC0IER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0IER_FBEE ETH_DMAC0IER_FBEE_Msk /*!< Fatal Bus Error Enable */
+#define ETH_DMAC0IER_CDEE_Pos (13U)
+#define ETH_DMAC0IER_CDEE_Msk (0x1U << ETH_DMAC0IER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0IER_CDEE ETH_DMAC0IER_CDEE_Msk /*!< Context Descriptor Error Enable */
+#define ETH_DMAC0IER_AIE_Pos (14U)
+#define ETH_DMAC0IER_AIE_Msk (0x1U << ETH_DMAC0IER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0IER_AIE ETH_DMAC0IER_AIE_Msk /*!< Abnormal Interrupt Summary Enable */
+#define ETH_DMAC0IER_NIE_Pos (15U)
+#define ETH_DMAC0IER_NIE_Msk (0x1U << ETH_DMAC0IER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0IER_NIE ETH_DMAC0IER_NIE_Msk /*!< Normal Interrupt Summary Enable */
+
+/************ Bit definition for ETH_DMAC0RXIWTR register ************/
+#define ETH_DMAC0RXIWTR_RWT_Pos (0U)
+#define ETH_DMAC0RXIWTR_RWT_Msk (0xFFU << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMAC0RXIWTR_RWT ETH_DMAC0RXIWTR_RWT_Msk /*!< Receive Interrupt Watchdog Timer Count */
+#define ETH_DMAC0RXIWTR_RWT_0 (0x1U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0RXIWTR_RWT_1 (0x2U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0RXIWTR_RWT_2 (0x4U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0RXIWTR_RWT_3 (0x8U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0RXIWTR_RWT_4 (0x10U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0RXIWTR_RWT_5 (0x20U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0RXIWTR_RWT_6 (0x40U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0RXIWTR_RWT_7 (0x80U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000080 */
+
+/************ Bit definition for ETH_DMAC0SFCSR register *************/
+#define ETH_DMAC0SFCSR_ESC_Pos (0U)
+#define ETH_DMAC0SFCSR_ESC_Msk (0x1U << ETH_DMAC0SFCSR_ESC_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0SFCSR_ESC ETH_DMAC0SFCSR_ESC_Msk /*!< Enable Slot Comparison */
+#define ETH_DMAC0SFCSR_ASC_Pos (1U)
+#define ETH_DMAC0SFCSR_ASC_Msk (0x1U << ETH_DMAC0SFCSR_ASC_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0SFCSR_ASC ETH_DMAC0SFCSR_ASC_Msk /*!< Advance Slot Check */
+#define ETH_DMAC0SFCSR_RSN_Pos (16U)
+#define ETH_DMAC0SFCSR_RSN_Msk (0xFU << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x000F0000 */
+#define ETH_DMAC0SFCSR_RSN ETH_DMAC0SFCSR_RSN_Msk /*!< Reference Slot Number */
+#define ETH_DMAC0SFCSR_RSN_0 (0x1U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0SFCSR_RSN_1 (0x2U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0SFCSR_RSN_2 (0x4U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0SFCSR_RSN_3 (0x8U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00080000 */
+
+/************ Bit definition for ETH_DMAC0CATXDR register ************/
+#define ETH_DMAC0CATXDR_CURTDESAPTR_Pos (0U)
+#define ETH_DMAC0CATXDR_CURTDESAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMAC0CATXDR_CURTDESAPTR ETH_DMAC0CATXDR_CURTDESAPTR_Msk /*!< Application Transmit Descriptor Address Pointer */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_0 (0x1U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_1 (0x2U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_2 (0x4U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_3 (0x8U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_4 (0x10U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_5 (0x20U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_6 (0x40U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_7 (0x80U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_8 (0x100U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_9 (0x200U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_10 (0x400U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_11 (0x800U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_12 (0x1000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_13 (0x2000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_14 (0x4000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_15 (0x8000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_16 (0x10000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_17 (0x20000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_18 (0x40000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_19 (0x80000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_20 (0x100000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_21 (0x200000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_22 (0x400000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_23 (0x800000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_24 (0x1000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_25 (0x2000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_26 (0x4000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_27 (0x8000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_28 (0x10000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_29 (0x20000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_30 (0x40000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0CATXDR_CURTDESAPTR_31 (0x80000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC0CARXDR register ************/
+#define ETH_DMAC0CARXDR_CURRDESAPTR_Pos (0U)
+#define ETH_DMAC0CARXDR_CURRDESAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMAC0CARXDR_CURRDESAPTR ETH_DMAC0CARXDR_CURRDESAPTR_Msk /*!< Application Receive Descriptor Address Pointer */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_0 (0x1U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_1 (0x2U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_2 (0x4U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_3 (0x8U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_4 (0x10U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_5 (0x20U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_6 (0x40U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_7 (0x80U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_8 (0x100U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_9 (0x200U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_10 (0x400U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_11 (0x800U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_12 (0x1000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_13 (0x2000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_14 (0x4000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_15 (0x8000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_16 (0x10000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_17 (0x20000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_18 (0x40000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_19 (0x80000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_20 (0x100000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_21 (0x200000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_22 (0x400000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_23 (0x800000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_24 (0x1000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_25 (0x2000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_26 (0x4000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_27 (0x8000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_28 (0x10000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_29 (0x20000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_30 (0x40000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0CARXDR_CURRDESAPTR_31 (0x80000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC0CATXBR register ************/
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_Pos (0U)
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR ETH_DMAC0CATXBR_CURTBUFAPTR_Msk /*!< Application Transmit Buffer Address Pointer */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_0 (0x1U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_1 (0x2U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_2 (0x4U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_3 (0x8U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_4 (0x10U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_5 (0x20U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_6 (0x40U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_7 (0x80U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_8 (0x100U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_9 (0x200U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_10 (0x400U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_11 (0x800U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_12 (0x1000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_13 (0x2000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_14 (0x4000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_15 (0x8000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_16 (0x10000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_17 (0x20000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_18 (0x40000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_19 (0x80000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_20 (0x100000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_21 (0x200000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_22 (0x400000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_23 (0x800000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_24 (0x1000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_25 (0x2000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_26 (0x4000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_27 (0x8000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_28 (0x10000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_29 (0x20000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_30 (0x40000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0CATXBR_CURTBUFAPTR_31 (0x80000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC0CARXBR register ************/
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_Pos (0U)
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR ETH_DMAC0CARXBR_CURRBUFAPTR_Msk /*!< Application Receive Buffer Address Pointer */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_0 (0x1U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_1 (0x2U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_2 (0x4U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_3 (0x8U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_4 (0x10U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_5 (0x20U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_6 (0x40U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_7 (0x80U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_8 (0x100U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_9 (0x200U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_10 (0x400U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_11 (0x800U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_12 (0x1000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_13 (0x2000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_14 (0x4000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_15 (0x8000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_16 (0x10000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_17 (0x20000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_18 (0x40000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_19 (0x80000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_20 (0x100000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_21 (0x200000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00200000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_22 (0x400000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00400000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_23 (0x800000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00800000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_24 (0x1000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x01000000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_25 (0x2000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x02000000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_26 (0x4000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x04000000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_27 (0x8000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x08000000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_28 (0x10000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x10000000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_29 (0x20000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x20000000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_30 (0x40000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x40000000 */
+#define ETH_DMAC0CARXBR_CURRBUFAPTR_31 (0x80000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_DMAC0SR register **************/
+#define ETH_DMAC0SR_TI_Pos (0U)
+#define ETH_DMAC0SR_TI_Msk (0x1U << ETH_DMAC0SR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0SR_TI ETH_DMAC0SR_TI_Msk /*!< Transmit Interrupt */
+#define ETH_DMAC0SR_TPS_Pos (1U)
+#define ETH_DMAC0SR_TPS_Msk (0x1U << ETH_DMAC0SR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0SR_TPS ETH_DMAC0SR_TPS_Msk /*!< Transmit Process Stopped */
+#define ETH_DMAC0SR_TBU_Pos (2U)
+#define ETH_DMAC0SR_TBU_Msk (0x1U << ETH_DMAC0SR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0SR_TBU ETH_DMAC0SR_TBU_Msk /*!< Transmit Buffer Unavailable */
+#define ETH_DMAC0SR_RI_Pos (6U)
+#define ETH_DMAC0SR_RI_Msk (0x1U << ETH_DMAC0SR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0SR_RI ETH_DMAC0SR_RI_Msk /*!< Receive Interrupt */
+#define ETH_DMAC0SR_RBU_Pos (7U)
+#define ETH_DMAC0SR_RBU_Msk (0x1U << ETH_DMAC0SR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0SR_RBU ETH_DMAC0SR_RBU_Msk /*!< Receive Buffer Unavailable */
+#define ETH_DMAC0SR_RPS_Pos (8U)
+#define ETH_DMAC0SR_RPS_Msk (0x1U << ETH_DMAC0SR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0SR_RPS ETH_DMAC0SR_RPS_Msk /*!< Receive Process Stopped */
+#define ETH_DMAC0SR_RWT_Pos (9U)
+#define ETH_DMAC0SR_RWT_Msk (0x1U << ETH_DMAC0SR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0SR_RWT ETH_DMAC0SR_RWT_Msk /*!< Receive Watchdog Timeout */
+#define ETH_DMAC0SR_ETI_Pos (10U)
+#define ETH_DMAC0SR_ETI_Msk (0x1U << ETH_DMAC0SR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0SR_ETI ETH_DMAC0SR_ETI_Msk /*!< Early Transmit Interrupt */
+#define ETH_DMAC0SR_ERI_Pos (11U)
+#define ETH_DMAC0SR_ERI_Msk (0x1U << ETH_DMAC0SR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMAC0SR_ERI ETH_DMAC0SR_ERI_Msk /*!< Early Receive Interrupt */
+#define ETH_DMAC0SR_FBE_Pos (12U)
+#define ETH_DMAC0SR_FBE_Msk (0x1U << ETH_DMAC0SR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMAC0SR_FBE ETH_DMAC0SR_FBE_Msk /*!< Fatal Bus Error */
+#define ETH_DMAC0SR_CDE_Pos (13U)
+#define ETH_DMAC0SR_CDE_Msk (0x1U << ETH_DMAC0SR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMAC0SR_CDE ETH_DMAC0SR_CDE_Msk /*!< Context Descriptor Error */
+#define ETH_DMAC0SR_AIS_Pos (14U)
+#define ETH_DMAC0SR_AIS_Msk (0x1U << ETH_DMAC0SR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMAC0SR_AIS ETH_DMAC0SR_AIS_Msk /*!< Abnormal Interrupt Summary */
+#define ETH_DMAC0SR_NIS_Pos (15U)
+#define ETH_DMAC0SR_NIS_Msk (0x1U << ETH_DMAC0SR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0SR_NIS ETH_DMAC0SR_NIS_Msk /*!< Normal Interrupt Summary */
+#define ETH_DMAC0SR_TEB_Pos (16U)
+#define ETH_DMAC0SR_TEB_Msk (0x7U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMAC0SR_TEB ETH_DMAC0SR_TEB_Msk /*!< Tx DMA Error Bits */
+#define ETH_DMAC0SR_TEB_0 (0x1U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00010000 */
+#define ETH_DMAC0SR_TEB_1 (0x2U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00020000 */
+#define ETH_DMAC0SR_TEB_2 (0x4U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00040000 */
+#define ETH_DMAC0SR_REB_Pos (19U)
+#define ETH_DMAC0SR_REB_Msk (0x7U << ETH_DMAC0SR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMAC0SR_REB ETH_DMAC0SR_REB_Msk /*!< Rx DMA Error Bits */
+#define ETH_DMAC0SR_REB_0 (0x1U << ETH_DMAC0SR_REB_Pos) /*!< 0x00080000 */
+#define ETH_DMAC0SR_REB_1 (0x2U << ETH_DMAC0SR_REB_Pos) /*!< 0x00100000 */
+#define ETH_DMAC0SR_REB_2 (0x4U << ETH_DMAC0SR_REB_Pos) /*!< 0x00200000 */
+
+/************* Bit definition for ETH_DMAC0MFCR register *************/
+#define ETH_DMAC0MFCR_MFC_Pos (0U)
+#define ETH_DMAC0MFCR_MFC_Msk (0x7FFU << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMAC0MFCR_MFC ETH_DMAC0MFCR_MFC_Msk /*!< Dropped Packet Counters */
+#define ETH_DMAC0MFCR_MFC_0 (0x1U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000001 */
+#define ETH_DMAC0MFCR_MFC_1 (0x2U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000002 */
+#define ETH_DMAC0MFCR_MFC_2 (0x4U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000004 */
+#define ETH_DMAC0MFCR_MFC_3 (0x8U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000008 */
+#define ETH_DMAC0MFCR_MFC_4 (0x10U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000010 */
+#define ETH_DMAC0MFCR_MFC_5 (0x20U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000020 */
+#define ETH_DMAC0MFCR_MFC_6 (0x40U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000040 */
+#define ETH_DMAC0MFCR_MFC_7 (0x80U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000080 */
+#define ETH_DMAC0MFCR_MFC_8 (0x100U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000100 */
+#define ETH_DMAC0MFCR_MFC_9 (0x200U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000200 */
+#define ETH_DMAC0MFCR_MFC_10 (0x400U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000400 */
+#define ETH_DMAC0MFCR_MFCO_Pos (15U)
+#define ETH_DMAC0MFCR_MFCO_Msk (0x1U << ETH_DMAC0MFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMAC0MFCR_MFCO ETH_DMAC0MFCR_MFCO_Msk /*!< Overflow status of the MFC Counter */
+
+/************** Bit definition for ETH_DMAC1CR register **************/
+#define ETH_DMAC1CR_MSS_Pos (0U)
+#define ETH_DMAC1CR_MSS_Msk (0x3FFFU << ETH_DMAC1CR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMAC1CR_MSS ETH_DMAC1CR_MSS_Msk /*!< Maximum Segment Size */
+#define ETH_DMAC1CR_MSS_0 (0x1U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1CR_MSS_1 (0x2U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1CR_MSS_2 (0x4U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1CR_MSS_3 (0x8U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1CR_MSS_4 (0x10U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1CR_MSS_5 (0x20U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000020 */
+#define ETH_DMAC1CR_MSS_6 (0x40U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1CR_MSS_7 (0x80U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1CR_MSS_8 (0x100U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1CR_MSS_9 (0x200U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1CR_MSS_10 (0x400U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1CR_MSS_11 (0x800U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000800 */
+#define ETH_DMAC1CR_MSS_12 (0x1000U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1CR_MSS_13 (0x2000U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00002000 */
+#define ETH_DMAC1CR_PBLX8_Pos (16U)
+#define ETH_DMAC1CR_PBLX8_Msk (0x1U << ETH_DMAC1CR_PBLX8_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1CR_PBLX8 ETH_DMAC1CR_PBLX8_Msk /*!< 8xPBL mode */
+#define ETH_DMAC1CR_DSL_Pos (18U)
+#define ETH_DMAC1CR_DSL_Msk (0x7U << ETH_DMAC1CR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMAC1CR_DSL ETH_DMAC1CR_DSL_Msk /*!< Descriptor Skip Length */
+#define ETH_DMAC1CR_DSL_0 (0x1U << ETH_DMAC1CR_DSL_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1CR_DSL_1 (0x2U << ETH_DMAC1CR_DSL_Pos) /*!< 0x00080000 */
+#define ETH_DMAC1CR_DSL_2 (0x4U << ETH_DMAC1CR_DSL_Pos) /*!< 0x00100000 */
+
+/************* Bit definition for ETH_DMAC1TXCR register *************/
+#define ETH_DMAC1TXCR_ST_Pos (0U)
+#define ETH_DMAC1TXCR_ST_Msk (0x1U << ETH_DMAC1TXCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1TXCR_ST ETH_DMAC1TXCR_ST_Msk /*!< Start or Stop Transmission Command */
+#define ETH_DMAC1TXCR_TCW_Pos (1U)
+#define ETH_DMAC1TXCR_TCW_Msk (0x7U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x0000000E */
+#define ETH_DMAC1TXCR_TCW ETH_DMAC1TXCR_TCW_Msk /*!< Transmit Channel Weight */
+#define ETH_DMAC1TXCR_TCW_0 (0x1U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1TXCR_TCW_1 (0x2U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1TXCR_TCW_2 (0x4U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1TXCR_OSF_Pos (4U)
+#define ETH_DMAC1TXCR_OSF_Msk (0x1U << ETH_DMAC1TXCR_OSF_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1TXCR_OSF ETH_DMAC1TXCR_OSF_Msk /*!< Operate on Second Packet */
+#define ETH_DMAC1TXCR_TSE_Pos (12U)
+#define ETH_DMAC1TXCR_TSE_Msk (0x1U << ETH_DMAC1TXCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1TXCR_TSE ETH_DMAC1TXCR_TSE_Msk /*!< TCP Segmentation Enabled */
+#define ETH_DMAC1TXCR_TXPBL_Pos (16U)
+#define ETH_DMAC1TXCR_TXPBL_Msk (0x3FU << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMAC1TXCR_TXPBL ETH_DMAC1TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */
+#define ETH_DMAC1TXCR_TXPBL_0 (0x1U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1TXCR_TXPBL_1 (0x2U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00020000 */
+#define ETH_DMAC1TXCR_TXPBL_2 (0x4U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1TXCR_TXPBL_3 (0x8U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00080000 */
+#define ETH_DMAC1TXCR_TXPBL_4 (0x10U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00100000 */
+#define ETH_DMAC1TXCR_TXPBL_5 (0x20U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00200000 */
+#define ETH_DMAC1TXCR_TQOS_Pos (24U)
+#define ETH_DMAC1TXCR_TQOS_Msk (0xFU << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x0F000000 */
+#define ETH_DMAC1TXCR_TQOS ETH_DMAC1TXCR_TQOS_Msk /*!< Transmit QOS. */
+#define ETH_DMAC1TXCR_TQOS_0 (0x1U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x01000000 */
+#define ETH_DMAC1TXCR_TQOS_1 (0x2U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x02000000 */
+#define ETH_DMAC1TXCR_TQOS_2 (0x4U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x04000000 */
+#define ETH_DMAC1TXCR_TQOS_3 (0x8U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x08000000 */
+
+/************ Bit definition for ETH_DMAC1TXDLAR register ************/
+#define ETH_DMAC1TXDLAR_TDESLA_Pos (3U)
+#define ETH_DMAC1TXDLAR_TDESLA_Msk (0x1FFFFFFFU << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0xFFFFFFF8 */
+#define ETH_DMAC1TXDLAR_TDESLA ETH_DMAC1TXDLAR_TDESLA_Msk /*!< Start of Transmit List */
+#define ETH_DMAC1TXDLAR_TDESLA_0 (0x1U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1TXDLAR_TDESLA_1 (0x2U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1TXDLAR_TDESLA_2 (0x4U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000020 */
+#define ETH_DMAC1TXDLAR_TDESLA_3 (0x8U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1TXDLAR_TDESLA_4 (0x10U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1TXDLAR_TDESLA_5 (0x20U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1TXDLAR_TDESLA_6 (0x40U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1TXDLAR_TDESLA_7 (0x80U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1TXDLAR_TDESLA_8 (0x100U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000800 */
+#define ETH_DMAC1TXDLAR_TDESLA_9 (0x200U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1TXDLAR_TDESLA_10 (0x400U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00002000 */
+#define ETH_DMAC1TXDLAR_TDESLA_11 (0x800U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00004000 */
+#define ETH_DMAC1TXDLAR_TDESLA_12 (0x1000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00008000 */
+#define ETH_DMAC1TXDLAR_TDESLA_13 (0x2000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1TXDLAR_TDESLA_14 (0x4000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00020000 */
+#define ETH_DMAC1TXDLAR_TDESLA_15 (0x8000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1TXDLAR_TDESLA_16 (0x10000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00080000 */
+#define ETH_DMAC1TXDLAR_TDESLA_17 (0x20000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00100000 */
+#define ETH_DMAC1TXDLAR_TDESLA_18 (0x40000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00200000 */
+#define ETH_DMAC1TXDLAR_TDESLA_19 (0x80000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00400000 */
+#define ETH_DMAC1TXDLAR_TDESLA_20 (0x100000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00800000 */
+#define ETH_DMAC1TXDLAR_TDESLA_21 (0x200000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x01000000 */
+#define ETH_DMAC1TXDLAR_TDESLA_22 (0x400000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x02000000 */
+#define ETH_DMAC1TXDLAR_TDESLA_23 (0x800000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x04000000 */
+#define ETH_DMAC1TXDLAR_TDESLA_24 (0x1000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x08000000 */
+#define ETH_DMAC1TXDLAR_TDESLA_25 (0x2000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x10000000 */
+#define ETH_DMAC1TXDLAR_TDESLA_26 (0x4000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x20000000 */
+#define ETH_DMAC1TXDLAR_TDESLA_27 (0x8000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x40000000 */
+#define ETH_DMAC1TXDLAR_TDESLA_28 (0x10000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC1TXDTPR register ************/
+#define ETH_DMAC1TXDTPR_TDT_Pos (3U)
+#define ETH_DMAC1TXDTPR_TDT_Msk (0x1FFFFFFFU << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0xFFFFFFF8 */
+#define ETH_DMAC1TXDTPR_TDT ETH_DMAC1TXDTPR_TDT_Msk /*!< Transmit Descriptor Tail Pointer */
+#define ETH_DMAC1TXDTPR_TDT_0 (0x1U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1TXDTPR_TDT_1 (0x2U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1TXDTPR_TDT_2 (0x4U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000020 */
+#define ETH_DMAC1TXDTPR_TDT_3 (0x8U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1TXDTPR_TDT_4 (0x10U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1TXDTPR_TDT_5 (0x20U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1TXDTPR_TDT_6 (0x40U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1TXDTPR_TDT_7 (0x80U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1TXDTPR_TDT_8 (0x100U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000800 */
+#define ETH_DMAC1TXDTPR_TDT_9 (0x200U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1TXDTPR_TDT_10 (0x400U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00002000 */
+#define ETH_DMAC1TXDTPR_TDT_11 (0x800U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00004000 */
+#define ETH_DMAC1TXDTPR_TDT_12 (0x1000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00008000 */
+#define ETH_DMAC1TXDTPR_TDT_13 (0x2000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1TXDTPR_TDT_14 (0x4000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00020000 */
+#define ETH_DMAC1TXDTPR_TDT_15 (0x8000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1TXDTPR_TDT_16 (0x10000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00080000 */
+#define ETH_DMAC1TXDTPR_TDT_17 (0x20000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00100000 */
+#define ETH_DMAC1TXDTPR_TDT_18 (0x40000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00200000 */
+#define ETH_DMAC1TXDTPR_TDT_19 (0x80000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00400000 */
+#define ETH_DMAC1TXDTPR_TDT_20 (0x100000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00800000 */
+#define ETH_DMAC1TXDTPR_TDT_21 (0x200000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x01000000 */
+#define ETH_DMAC1TXDTPR_TDT_22 (0x400000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x02000000 */
+#define ETH_DMAC1TXDTPR_TDT_23 (0x800000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x04000000 */
+#define ETH_DMAC1TXDTPR_TDT_24 (0x1000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x08000000 */
+#define ETH_DMAC1TXDTPR_TDT_25 (0x2000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x10000000 */
+#define ETH_DMAC1TXDTPR_TDT_26 (0x4000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x20000000 */
+#define ETH_DMAC1TXDTPR_TDT_27 (0x8000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x40000000 */
+#define ETH_DMAC1TXDTPR_TDT_28 (0x10000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC1TXRLR register *************/
+#define ETH_DMAC1TXRLR_TDRL_Pos (0U)
+#define ETH_DMAC1TXRLR_TDRL_Msk (0x3FFU << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMAC1TXRLR_TDRL ETH_DMAC1TXRLR_TDRL_Msk /*!< Transmit Descriptor Ring Length */
+#define ETH_DMAC1TXRLR_TDRL_0 (0x1U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1TXRLR_TDRL_1 (0x2U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1TXRLR_TDRL_2 (0x4U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1TXRLR_TDRL_3 (0x8U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1TXRLR_TDRL_4 (0x10U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1TXRLR_TDRL_5 (0x20U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000020 */
+#define ETH_DMAC1TXRLR_TDRL_6 (0x40U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1TXRLR_TDRL_7 (0x80U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1TXRLR_TDRL_8 (0x100U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1TXRLR_TDRL_9 (0x200U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000200 */
+
+/************* Bit definition for ETH_DMAC1IER register **************/
+#define ETH_DMAC1IER_TIE_Pos (0U)
+#define ETH_DMAC1IER_TIE_Msk (0x1U << ETH_DMAC1IER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1IER_TIE ETH_DMAC1IER_TIE_Msk /*!< Transmit Interrupt Enable */
+#define ETH_DMAC1IER_TXSE_Pos (1U)
+#define ETH_DMAC1IER_TXSE_Msk (0x1U << ETH_DMAC1IER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1IER_TXSE ETH_DMAC1IER_TXSE_Msk /*!< Transmit Stopped Enable */
+#define ETH_DMAC1IER_TBUE_Pos (2U)
+#define ETH_DMAC1IER_TBUE_Msk (0x1U << ETH_DMAC1IER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1IER_TBUE ETH_DMAC1IER_TBUE_Msk /*!< Transmit Buffer Unavailable Enable */
+#define ETH_DMAC1IER_RIE_Pos (6U)
+#define ETH_DMAC1IER_RIE_Msk (0x1U << ETH_DMAC1IER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1IER_RIE ETH_DMAC1IER_RIE_Msk /*!< Receive Interrupt Enable */
+#define ETH_DMAC1IER_RBUE_Pos (7U)
+#define ETH_DMAC1IER_RBUE_Msk (0x1U << ETH_DMAC1IER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1IER_RBUE ETH_DMAC1IER_RBUE_Msk /*!< Receive Buffer Unavailable Enable */
+#define ETH_DMAC1IER_RSE_Pos (8U)
+#define ETH_DMAC1IER_RSE_Msk (0x1U << ETH_DMAC1IER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1IER_RSE ETH_DMAC1IER_RSE_Msk /*!< Receive Stopped Enable */
+#define ETH_DMAC1IER_RWTE_Pos (9U)
+#define ETH_DMAC1IER_RWTE_Msk (0x1U << ETH_DMAC1IER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1IER_RWTE ETH_DMAC1IER_RWTE_Msk /*!< Receive Watchdog Timeout Enable */
+#define ETH_DMAC1IER_ETIE_Pos (10U)
+#define ETH_DMAC1IER_ETIE_Msk (0x1U << ETH_DMAC1IER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1IER_ETIE ETH_DMAC1IER_ETIE_Msk /*!< Early Transmit Interrupt Enable */
+#define ETH_DMAC1IER_ERIE_Pos (11U)
+#define ETH_DMAC1IER_ERIE_Msk (0x1U << ETH_DMAC1IER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMAC1IER_ERIE ETH_DMAC1IER_ERIE_Msk /*!< Early Receive Interrupt Enable */
+#define ETH_DMAC1IER_FBEE_Pos (12U)
+#define ETH_DMAC1IER_FBEE_Msk (0x1U << ETH_DMAC1IER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1IER_FBEE ETH_DMAC1IER_FBEE_Msk /*!< Fatal Bus Error Enable */
+#define ETH_DMAC1IER_CDEE_Pos (13U)
+#define ETH_DMAC1IER_CDEE_Msk (0x1U << ETH_DMAC1IER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMAC1IER_CDEE ETH_DMAC1IER_CDEE_Msk /*!< Context Descriptor Error Enable */
+#define ETH_DMAC1IER_AIE_Pos (14U)
+#define ETH_DMAC1IER_AIE_Msk (0x1U << ETH_DMAC1IER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAC1IER_AIE ETH_DMAC1IER_AIE_Msk /*!< Abnormal Interrupt Summary Enable */
+#define ETH_DMAC1IER_NIE_Pos (15U)
+#define ETH_DMAC1IER_NIE_Msk (0x1U << ETH_DMAC1IER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMAC1IER_NIE ETH_DMAC1IER_NIE_Msk /*!< Normal Interrupt Summary Enable */
+
+/************ Bit definition for ETH_DMAC1SFCSR register *************/
+#define ETH_DMAC1SFCSR_ESC_Pos (0U)
+#define ETH_DMAC1SFCSR_ESC_Msk (0x1U << ETH_DMAC1SFCSR_ESC_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1SFCSR_ESC ETH_DMAC1SFCSR_ESC_Msk /*!< Enable Slot Comparison */
+#define ETH_DMAC1SFCSR_ASC_Pos (1U)
+#define ETH_DMAC1SFCSR_ASC_Msk (0x1U << ETH_DMAC1SFCSR_ASC_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1SFCSR_ASC ETH_DMAC1SFCSR_ASC_Msk /*!< Advance Slot Check */
+#define ETH_DMAC1SFCSR_RSN_Pos (16U)
+#define ETH_DMAC1SFCSR_RSN_Msk (0xFU << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x000F0000 */
+#define ETH_DMAC1SFCSR_RSN ETH_DMAC1SFCSR_RSN_Msk /*!< Reference Slot Number */
+#define ETH_DMAC1SFCSR_RSN_0 (0x1U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1SFCSR_RSN_1 (0x2U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00020000 */
+#define ETH_DMAC1SFCSR_RSN_2 (0x4U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1SFCSR_RSN_3 (0x8U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00080000 */
+
+/************ Bit definition for ETH_DMAC1CATXDR register ************/
+#define ETH_DMAC1CATXDR_CURTDESAPTR_Pos (0U)
+#define ETH_DMAC1CATXDR_CURTDESAPTR_Msk (0xFFFFFFFFU << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMAC1CATXDR_CURTDESAPTR ETH_DMAC1CATXDR_CURTDESAPTR_Msk /*!< Application Transmit Descriptor Address Pointer */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_0 (0x1U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_1 (0x2U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_2 (0x4U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_3 (0x8U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_4 (0x10U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_5 (0x20U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000020 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_6 (0x40U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_7 (0x80U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_8 (0x100U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_9 (0x200U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_10 (0x400U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_11 (0x800U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000800 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_12 (0x1000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_13 (0x2000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00002000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_14 (0x4000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00004000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_15 (0x8000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00008000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_16 (0x10000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_17 (0x20000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00020000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_18 (0x40000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_19 (0x80000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00080000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_20 (0x100000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00100000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_21 (0x200000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00200000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_22 (0x400000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00400000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_23 (0x800000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00800000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_24 (0x1000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x01000000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_25 (0x2000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x02000000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_26 (0x4000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x04000000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_27 (0x8000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x08000000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_28 (0x10000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x10000000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_29 (0x20000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x20000000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_30 (0x40000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x40000000 */
+#define ETH_DMAC1CATXDR_CURTDESAPTR_31 (0x80000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x80000000 */
+
+/************ Bit definition for ETH_DMAC1CATXBR register ************/
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_Pos (0U)
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR ETH_DMAC1CATXBR_CURTBUFAPTR_Msk /*!< Application Transmit Buffer Address Pointer */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_0 (0x1U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_1 (0x2U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_2 (0x4U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_3 (0x8U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_4 (0x10U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_5 (0x20U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000020 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_6 (0x40U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_7 (0x80U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_8 (0x100U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_9 (0x200U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_10 (0x400U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_11 (0x800U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000800 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_12 (0x1000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_13 (0x2000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00002000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_14 (0x4000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00004000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_15 (0x8000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00008000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_16 (0x10000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_17 (0x20000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00020000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_18 (0x40000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_19 (0x80000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00080000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_20 (0x100000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00100000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_21 (0x200000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00200000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_22 (0x400000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00400000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_23 (0x800000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00800000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_24 (0x1000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x01000000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_25 (0x2000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x02000000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_26 (0x4000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x04000000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_27 (0x8000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x08000000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_28 (0x10000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x10000000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_29 (0x20000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x20000000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_30 (0x40000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x40000000 */
+#define ETH_DMAC1CATXBR_CURTBUFAPTR_31 (0x80000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x80000000 */
+
+/************** Bit definition for ETH_DMAC1SR register **************/
+#define ETH_DMAC1SR_TI_Pos (0U)
+#define ETH_DMAC1SR_TI_Msk (0x1U << ETH_DMAC1SR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1SR_TI ETH_DMAC1SR_TI_Msk /*!< Transmit Interrupt */
+#define ETH_DMAC1SR_TPS_Pos (1U)
+#define ETH_DMAC1SR_TPS_Msk (0x1U << ETH_DMAC1SR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1SR_TPS ETH_DMAC1SR_TPS_Msk /*!< Transmit Process Stopped */
+#define ETH_DMAC1SR_TBU_Pos (2U)
+#define ETH_DMAC1SR_TBU_Msk (0x1U << ETH_DMAC1SR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1SR_TBU ETH_DMAC1SR_TBU_Msk /*!< Transmit Buffer Unavailable */
+#define ETH_DMAC1SR_RI_Pos (6U)
+#define ETH_DMAC1SR_RI_Msk (0x1U << ETH_DMAC1SR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1SR_RI ETH_DMAC1SR_RI_Msk /*!< Receive Interrupt */
+#define ETH_DMAC1SR_RBU_Pos (7U)
+#define ETH_DMAC1SR_RBU_Msk (0x1U << ETH_DMAC1SR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1SR_RBU ETH_DMAC1SR_RBU_Msk /*!< Receive Buffer Unavailable */
+#define ETH_DMAC1SR_RPS_Pos (8U)
+#define ETH_DMAC1SR_RPS_Msk (0x1U << ETH_DMAC1SR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1SR_RPS ETH_DMAC1SR_RPS_Msk /*!< Receive Process Stopped */
+#define ETH_DMAC1SR_RWT_Pos (9U)
+#define ETH_DMAC1SR_RWT_Msk (0x1U << ETH_DMAC1SR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1SR_RWT ETH_DMAC1SR_RWT_Msk /*!< Receive Watchdog Timeout */
+#define ETH_DMAC1SR_ETI_Pos (10U)
+#define ETH_DMAC1SR_ETI_Msk (0x1U << ETH_DMAC1SR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1SR_ETI ETH_DMAC1SR_ETI_Msk /*!< Early Transmit Interrupt */
+#define ETH_DMAC1SR_ERI_Pos (11U)
+#define ETH_DMAC1SR_ERI_Msk (0x1U << ETH_DMAC1SR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMAC1SR_ERI ETH_DMAC1SR_ERI_Msk /*!< Early Receive Interrupt */
+#define ETH_DMAC1SR_FBE_Pos (12U)
+#define ETH_DMAC1SR_FBE_Msk (0x1U << ETH_DMAC1SR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMAC1SR_FBE ETH_DMAC1SR_FBE_Msk /*!< Fatal Bus Error */
+#define ETH_DMAC1SR_CDE_Pos (13U)
+#define ETH_DMAC1SR_CDE_Msk (0x1U << ETH_DMAC1SR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMAC1SR_CDE ETH_DMAC1SR_CDE_Msk /*!< Context Descriptor Error */
+#define ETH_DMAC1SR_AIS_Pos (14U)
+#define ETH_DMAC1SR_AIS_Msk (0x1U << ETH_DMAC1SR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMAC1SR_AIS ETH_DMAC1SR_AIS_Msk /*!< Abnormal Interrupt Summary */
+#define ETH_DMAC1SR_NIS_Pos (15U)
+#define ETH_DMAC1SR_NIS_Msk (0x1U << ETH_DMAC1SR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMAC1SR_NIS ETH_DMAC1SR_NIS_Msk /*!< Normal Interrupt Summary */
+#define ETH_DMAC1SR_TEB_Pos (16U)
+#define ETH_DMAC1SR_TEB_Msk (0x7U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMAC1SR_TEB ETH_DMAC1SR_TEB_Msk /*!< Tx DMA Error Bits */
+#define ETH_DMAC1SR_TEB_0 (0x1U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00010000 */
+#define ETH_DMAC1SR_TEB_1 (0x2U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00020000 */
+#define ETH_DMAC1SR_TEB_2 (0x4U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00040000 */
+#define ETH_DMAC1SR_REB_Pos (19U)
+#define ETH_DMAC1SR_REB_Msk (0x7U << ETH_DMAC1SR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMAC1SR_REB ETH_DMAC1SR_REB_Msk /*!< Rx DMA Error Bits */
+#define ETH_DMAC1SR_REB_0 (0x1U << ETH_DMAC1SR_REB_Pos) /*!< 0x00080000 */
+#define ETH_DMAC1SR_REB_1 (0x2U << ETH_DMAC1SR_REB_Pos) /*!< 0x00100000 */
+#define ETH_DMAC1SR_REB_2 (0x4U << ETH_DMAC1SR_REB_Pos) /*!< 0x00200000 */
+
+/************* Bit definition for ETH_DMAC1MFCR register *************/
+#define ETH_DMAC1MFCR_MFC_Pos (0U)
+#define ETH_DMAC1MFCR_MFC_Msk (0x7FFU << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMAC1MFCR_MFC ETH_DMAC1MFCR_MFC_Msk /*!< Dropped Packet Counters */
+#define ETH_DMAC1MFCR_MFC_0 (0x1U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000001 */
+#define ETH_DMAC1MFCR_MFC_1 (0x2U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000002 */
+#define ETH_DMAC1MFCR_MFC_2 (0x4U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000004 */
+#define ETH_DMAC1MFCR_MFC_3 (0x8U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000008 */
+#define ETH_DMAC1MFCR_MFC_4 (0x10U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000010 */
+#define ETH_DMAC1MFCR_MFC_5 (0x20U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000020 */
+#define ETH_DMAC1MFCR_MFC_6 (0x40U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000040 */
+#define ETH_DMAC1MFCR_MFC_7 (0x80U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000080 */
+#define ETH_DMAC1MFCR_MFC_8 (0x100U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000100 */
+#define ETH_DMAC1MFCR_MFC_9 (0x200U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000200 */
+#define ETH_DMAC1MFCR_MFC_10 (0x400U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000400 */
+#define ETH_DMAC1MFCR_MFCO_Pos (15U)
+#define ETH_DMAC1MFCR_MFCO_Msk (0x1U << ETH_DMAC1MFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMAC1MFCR_MFCO ETH_DMAC1MFCR_MFCO_Msk /*!< Overflow status of the MFC Counter */
+
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMA_SxCR register *****************/
+#define DMA_SxCR_MBURST_Pos (23U)
+#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
+#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos (21U)
+#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
+#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
+#define DMA_SxCR_ACK_Pos (20U)
+#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
+#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
+#define DMA_SxCR_CT_Pos (19U)
+#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk
+#define DMA_SxCR_DBM_Pos (18U)
+#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
+#define DMA_SxCR_PL_Pos (16U)
+#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk
+#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
+#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos (15U)
+#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
+#define DMA_SxCR_MSIZE_Pos (13U)
+#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
+#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos (11U)
+#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
+#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos (10U)
+#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
+#define DMA_SxCR_PINC_Pos (9U)
+#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
+#define DMA_SxCR_CIRC_Pos (8U)
+#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
+#define DMA_SxCR_DIR_Pos (6U)
+#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
+#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos (5U)
+#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
+#define DMA_SxCR_TCIE_Pos (4U)
+#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
+#define DMA_SxCR_HTIE_Pos (3U)
+#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
+#define DMA_SxCR_TEIE_Pos (2U)
+#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
+#define DMA_SxCR_DMEIE_Pos (1U)
+#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
+#define DMA_SxCR_EN_Pos (0U)
+#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk
+
+/******************** Bits definition for DMA_SxCNDTR register **************/
+#define DMA_SxNDT_Pos (0U)
+#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
+#define DMA_SxNDT DMA_SxNDT_Msk
+#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
+#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
+#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
+#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
+#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
+#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
+#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
+#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
+#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
+#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
+#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
+#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
+#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
+#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
+#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
+#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
+
+/******************** Bits definition for DMA_SxFCR register ****************/
+#define DMA_SxFCR_FEIE_Pos (7U)
+#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
+#define DMA_SxFCR_FS_Pos (3U)
+#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
+#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos (2U)
+#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
+#define DMA_SxFCR_FTH_Pos (0U)
+#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
+#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_SxPAR_PA_Pos (0U)
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_SxM0AR_M0A_Pos (0U)
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
+#define DMA_SxM1AR_M1A_Pos (0U)
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
+
+/******************** Bits definition for DMA_LISR register *****************/
+#define DMA_LISR_TCIF3_Pos (27U)
+#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
+#define DMA_LISR_HTIF3_Pos (26U)
+#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
+#define DMA_LISR_TEIF3_Pos (25U)
+#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
+#define DMA_LISR_DMEIF3_Pos (24U)
+#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
+#define DMA_LISR_FEIF3_Pos (22U)
+#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
+#define DMA_LISR_TCIF2_Pos (21U)
+#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
+#define DMA_LISR_HTIF2_Pos (20U)
+#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
+#define DMA_LISR_TEIF2_Pos (19U)
+#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
+#define DMA_LISR_DMEIF2_Pos (18U)
+#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
+#define DMA_LISR_FEIF2_Pos (16U)
+#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
+#define DMA_LISR_TCIF1_Pos (11U)
+#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
+#define DMA_LISR_HTIF1_Pos (10U)
+#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
+#define DMA_LISR_TEIF1_Pos (9U)
+#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
+#define DMA_LISR_DMEIF1_Pos (8U)
+#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
+#define DMA_LISR_FEIF1_Pos (6U)
+#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
+#define DMA_LISR_TCIF0_Pos (5U)
+#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
+#define DMA_LISR_HTIF0_Pos (4U)
+#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
+#define DMA_LISR_TEIF0_Pos (3U)
+#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
+#define DMA_LISR_DMEIF0_Pos (2U)
+#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
+#define DMA_LISR_FEIF0_Pos (0U)
+#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
+
+/******************** Bits definition for DMA_HISR register *****************/
+#define DMA_HISR_TCIF7_Pos (27U)
+#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
+#define DMA_HISR_HTIF7_Pos (26U)
+#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
+#define DMA_HISR_TEIF7_Pos (25U)
+#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
+#define DMA_HISR_DMEIF7_Pos (24U)
+#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
+#define DMA_HISR_FEIF7_Pos (22U)
+#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
+#define DMA_HISR_TCIF6_Pos (21U)
+#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
+#define DMA_HISR_HTIF6_Pos (20U)
+#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
+#define DMA_HISR_TEIF6_Pos (19U)
+#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
+#define DMA_HISR_DMEIF6_Pos (18U)
+#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
+#define DMA_HISR_FEIF6_Pos (16U)
+#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
+#define DMA_HISR_TCIF5_Pos (11U)
+#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
+#define DMA_HISR_HTIF5_Pos (10U)
+#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
+#define DMA_HISR_TEIF5_Pos (9U)
+#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
+#define DMA_HISR_DMEIF5_Pos (8U)
+#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
+#define DMA_HISR_FEIF5_Pos (6U)
+#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
+#define DMA_HISR_TCIF4_Pos (5U)
+#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
+#define DMA_HISR_HTIF4_Pos (4U)
+#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
+#define DMA_HISR_TEIF4_Pos (3U)
+#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
+#define DMA_HISR_DMEIF4_Pos (2U)
+#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
+#define DMA_HISR_FEIF4_Pos (0U)
+#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
+
+/******************** Bits definition for DMA_LIFCR register ****************/
+#define DMA_LIFCR_CTCIF3_Pos (27U)
+#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
+#define DMA_LIFCR_CHTIF3_Pos (26U)
+#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
+#define DMA_LIFCR_CTEIF3_Pos (25U)
+#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
+#define DMA_LIFCR_CDMEIF3_Pos (24U)
+#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
+#define DMA_LIFCR_CFEIF3_Pos (22U)
+#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
+#define DMA_LIFCR_CTCIF2_Pos (21U)
+#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
+#define DMA_LIFCR_CHTIF2_Pos (20U)
+#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
+#define DMA_LIFCR_CTEIF2_Pos (19U)
+#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
+#define DMA_LIFCR_CDMEIF2_Pos (18U)
+#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
+#define DMA_LIFCR_CFEIF2_Pos (16U)
+#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
+#define DMA_LIFCR_CTCIF1_Pos (11U)
+#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
+#define DMA_LIFCR_CHTIF1_Pos (10U)
+#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
+#define DMA_LIFCR_CTEIF1_Pos (9U)
+#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
+#define DMA_LIFCR_CDMEIF1_Pos (8U)
+#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
+#define DMA_LIFCR_CFEIF1_Pos (6U)
+#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
+#define DMA_LIFCR_CTCIF0_Pos (5U)
+#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
+#define DMA_LIFCR_CHTIF0_Pos (4U)
+#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
+#define DMA_LIFCR_CTEIF0_Pos (3U)
+#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
+#define DMA_LIFCR_CDMEIF0_Pos (2U)
+#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
+#define DMA_LIFCR_CFEIF0_Pos (0U)
+#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
+
+/******************** Bits definition for DMA_HIFCR register ****************/
+#define DMA_HIFCR_CTCIF7_Pos (27U)
+#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
+#define DMA_HIFCR_CHTIF7_Pos (26U)
+#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
+#define DMA_HIFCR_CTEIF7_Pos (25U)
+#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
+#define DMA_HIFCR_CDMEIF7_Pos (24U)
+#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
+#define DMA_HIFCR_CFEIF7_Pos (22U)
+#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
+#define DMA_HIFCR_CTCIF6_Pos (21U)
+#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
+#define DMA_HIFCR_CHTIF6_Pos (20U)
+#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
+#define DMA_HIFCR_CTEIF6_Pos (19U)
+#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
+#define DMA_HIFCR_CDMEIF6_Pos (18U)
+#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
+#define DMA_HIFCR_CFEIF6_Pos (16U)
+#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
+#define DMA_HIFCR_CTCIF5_Pos (11U)
+#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
+#define DMA_HIFCR_CHTIF5_Pos (10U)
+#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
+#define DMA_HIFCR_CTEIF5_Pos (9U)
+#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
+#define DMA_HIFCR_CDMEIF5_Pos (8U)
+#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
+#define DMA_HIFCR_CFEIF5_Pos (6U)
+#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
+#define DMA_HIFCR_CTCIF4_Pos (5U)
+#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
+#define DMA_HIFCR_CHTIF4_Pos (4U)
+#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
+#define DMA_HIFCR_CTEIF4_Pos (3U)
+#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
+#define DMA_HIFCR_CDMEIF4_Pos (2U)
+#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
+#define DMA_HIFCR_CFEIF4_Pos (0U)
+#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
+
+/********************** Bit definition for DMA_HWCFGR2 register ***************/
+#define DMA_HWCFGR2_FIFO_SIZE_Pos (0U)
+#define DMA_HWCFGR2_FIFO_SIZE_Msk (0x3U << DMA_HWCFGR2_FIFO_SIZE_Pos) /*!< 0x00000003 */
+#define DMA_HWCFGR2_FIFO_SIZE DMA_HWCFGR2_FIFO_SIZE_Msk /*!< FIFO size, common to all streams*/
+#define DMA_HWCFGR2_WRITE_BUFFERABLE_Pos (4U)
+#define DMA_HWCFGR2_WRITE_BUFFERABLE_Msk (0x1U << DMA_HWCFGR2_WRITE_BUFFERABLE_Pos) /*!< 0x00000010 */
+#define DMA_HWCFGR2_WRITE_BUFFERABLE DMA_HWCFGR2_WRITE_BUFFERABLE_Msk /*!< Write bufferable*/
+#define DMA_HWCFGR2_CHSEL_WIDTH_Pos (8U)
+#define DMA_HWCFGR2_CHSEL_WIDTH_Msk (0x7U << DMA_HWCFGR2_CHSEL_WIDTH_Pos) /*!< 0x00000700 */
+#define DMA_HWCFGR2_CHSEL_WIDTH DMA_HWCFGR2_CHSEL_WIDTH_Msk /*!< width of the CHSEL field */
+
+/********************** Bit definition for DMA_HWCFGR1 register ***************/
+#define DMA_HWCFGR1_DMA_DEF0_Pos (0U)
+#define DMA_HWCFGR1_DMA_DEF0_Msk (0x3U << DMA_HWCFGR1_DMA_DEF0_Pos) /*!< 0x00000003 */
+#define DMA_HWCFGR1_DMA_DEF0 DMA_HWCFGR1_DMA_DEF0_Msk /*!< Type of the stream 0 */
+#define DMA_HWCFGR1_DMA_DEF1_Pos (4U)
+#define DMA_HWCFGR1_DMA_DEF1_Msk (0x3U << DMA_HWCFGR1_DMA_DEF1_Pos) /*!< 0x00000030 */
+#define DMA_HWCFGR1_DMA_DEF1 DMA_HWCFGR1_DMA_DEF1_Msk /*!< Type of the stream 1 */
+#define DMA_HWCFGR1_DMA_DEF2_Pos (8U)
+#define DMA_HWCFGR1_DMA_DEF2_Msk (0x3U << DMA_HWCFGR1_DMA_DEF2_Pos) /*!< 0x00000300 */
+#define DMA_HWCFGR1_DMA_DEF2 DMA_HWCFGR1_DMA_DEF2_Msk /*!< Type of the stream 2 */
+#define DMA_HWCFGR1_DMA_DEF3_Pos (12U)
+#define DMA_HWCFGR1_DMA_DEF3_Msk (0x3U << DMA_HWCFGR1_DMA_DEF3_Pos) /*!< 0x00003000 */
+#define DMA_HWCFGR1_DMA_DEF3 DMA_HWCFGR1_DMA_DEF3_Msk /*!< Type of the stream 3 */
+#define DMA_HWCFGR1_DMA_DEF4_Pos (16U)
+#define DMA_HWCFGR1_DMA_DEF4_Msk (0x3U << DMA_HWCFGR1_DMA_DEF4_Pos) /*!< 0x00030000 */
+#define DMA_HWCFGR1_DMA_DEF4 DMA_HWCFGR1_DMA_DEF4_Msk /*!< Type of the stream 4 */
+#define DMA_HWCFGR1_DMA_DEF5_Pos (20U)
+#define DMA_HWCFGR1_DMA_DEF5_Msk (0x3U << DMA_HWCFGR1_DMA_DEF5_Pos) /*!< 0x00300000 */
+#define DMA_HWCFGR1_DMA_DEF5 DMA_HWCFGR1_DMA_DEF5_Msk /*!< Type of the stream 5 */
+#define DMA_HWCFGR1_DMA_DEF6_Pos (24U)
+#define DMA_HWCFGR1_DMA_DEF6_Msk (0x3U << DMA_HWCFGR1_DMA_DEF6_Pos) /*!< 0x03000000 */
+#define DMA_HWCFGR1_DMA_DEF6 DMA_HWCFGR1_DMA_DEF6_Msk /*!< Type of the stream 6 */
+#define DMA_HWCFGR1_DMA_DEF7_Pos (28U)
+#define DMA_HWCFGR1_DMA_DEF7_Msk (0x3U << DMA_HWCFGR1_DMA_DEF7_Pos) /*!< 0x30000000 */
+#define DMA_HWCFGR1_DMA_DEF7 DMA_HWCFGR1_DMA_DEF7_Msk /*!< Type of the stream 7 */
+
+/********************** Bit definition for DMA_VERR register *****************/
+#define DMA_VERR_MINREV_Pos (0U)
+#define DMA_VERR_MINREV_Msk (0xFU << DMA_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define DMA_VERR_MINREV DMA_VERR_MINREV_Msk /*!< Minor Revision number */
+#define DMA_VERR_MAJREV_Pos (4U)
+#define DMA_VERR_MAJREV_Msk (0xFU << DMA_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define DMA_VERR_MAJREV DMA_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for DMA_IPIDR register ****************/
+#define DMA_IPIDR_ID_Pos (0U)
+#define DMA_IPIDR_ID_Msk (0xFFFFFFFFU << DMA_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define DMA_IPIDR_ID DMA_IPIDR_ID_Msk /*!< IP Identification */
+
+/********************** Bit definition for DMA_SIDR register *****************/
+#define DMA_SIDR_SID_Pos (0U)
+#define DMA_SIDR_SID_Msk (0xFFFFFFFFU << DMA_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define DMA_SIDR_SID DMA_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* DMAMUX Controller */
+/* */
+/******************************************************************************/
+/******************** Bits definition for DMAMUX_CxCR register **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFU << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
+#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
+#define DMAMUX_CxCR_SOIE_Pos (8U)
+#define DMAMUX_CxCR_SOIE_Msk (0x1U << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
+#define DMAMUX_CxCR_EGE_Pos (9U)
+#define DMAMUX_CxCR_EGE_Msk (0x1U << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
+#define DMAMUX_CxCR_SE_Pos (16U)
+#define DMAMUX_CxCR_SE_Msk (0x1U << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
+#define DMAMUX_CxCR_SPOL_Pos (17U)
+#define DMAMUX_CxCR_SPOL_Msk (0x3U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
+#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos (19U)
+#define DMAMUX_CxCR_NBREQ_Msk (0x1FU << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
+#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FU << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
+#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
+
+/******************** Bits definition for DMAMUX_CSR register **************/
+#define DMAMUX_CSR_SOF0_Pos (0U)
+#define DMAMUX_CSR_SOF0_Msk (0x1U << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
+#define DMAMUX_CSR_SOF1_Pos (1U)
+#define DMAMUX_CSR_SOF1_Msk (0x1U << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
+#define DMAMUX_CSR_SOF2_Pos (2U)
+#define DMAMUX_CSR_SOF2_Msk (0x1U << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
+#define DMAMUX_CSR_SOF3_Pos (3U)
+#define DMAMUX_CSR_SOF3_Msk (0x1U << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
+#define DMAMUX_CSR_SOF4_Pos (4U)
+#define DMAMUX_CSR_SOF4_Msk (0x1U << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
+#define DMAMUX_CSR_SOF5_Pos (5U)
+#define DMAMUX_CSR_SOF5_Msk (0x1U << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
+#define DMAMUX_CSR_SOF6_Pos (6U)
+#define DMAMUX_CSR_SOF6_Msk (0x1U << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
+#define DMAMUX_CSR_SOF7_Pos (7U)
+#define DMAMUX_CSR_SOF7_Msk (0x1U << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
+#define DMAMUX_CSR_SOF8_Pos (8U)
+#define DMAMUX_CSR_SOF8_Msk (0x1U << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
+#define DMAMUX_CSR_SOF9_Pos (9U)
+#define DMAMUX_CSR_SOF9_Msk (0x1U << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
+#define DMAMUX_CSR_SOF10_Pos (10U)
+#define DMAMUX_CSR_SOF10_Msk (0x1U << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
+#define DMAMUX_CSR_SOF11_Pos (11U)
+#define DMAMUX_CSR_SOF11_Msk (0x1U << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
+#define DMAMUX_CSR_SOF12_Pos (12U)
+#define DMAMUX_CSR_SOF12_Msk (0x1U << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
+#define DMAMUX_CSR_SOF13_Pos (13U)
+#define DMAMUX_CSR_SOF13_Msk (0x1U << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
+#define DMAMUX_CSR_SOF14_Pos (14U)
+#define DMAMUX_CSR_SOF14_Msk (0x1U << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
+#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
+#define DMAMUX_CSR_SOF15_Pos (15U)
+#define DMAMUX_CSR_SOF15_Msk (0x1U << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
+#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
+
+/******************** Bits definition for DMAMUX_CFR register **************/
+#define DMAMUX_CFR_CSOF0_Pos (0U)
+#define DMAMUX_CFR_CSOF0_Msk (0x1U << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
+#define DMAMUX_CFR_CSOF1_Pos (1U)
+#define DMAMUX_CFR_CSOF1_Msk (0x1U << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
+#define DMAMUX_CFR_CSOF2_Pos (2U)
+#define DMAMUX_CFR_CSOF2_Msk (0x1U << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
+#define DMAMUX_CFR_CSOF3_Pos (3U)
+#define DMAMUX_CFR_CSOF3_Msk (0x1U << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
+#define DMAMUX_CFR_CSOF4_Pos (4U)
+#define DMAMUX_CFR_CSOF4_Msk (0x1U << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
+#define DMAMUX_CFR_CSOF5_Pos (5U)
+#define DMAMUX_CFR_CSOF5_Msk (0x1U << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
+#define DMAMUX_CFR_CSOF6_Pos (6U)
+#define DMAMUX_CFR_CSOF6_Msk (0x1U << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
+#define DMAMUX_CFR_CSOF7_Pos (7U)
+#define DMAMUX_CFR_CSOF7_Msk (0x1U << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
+#define DMAMUX_CFR_CSOF8_Pos (8U)
+#define DMAMUX_CFR_CSOF8_Msk (0x1U << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
+#define DMAMUX_CFR_CSOF9_Pos (9U)
+#define DMAMUX_CFR_CSOF9_Msk (0x1U << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
+#define DMAMUX_CFR_CSOF10_Pos (10U)
+#define DMAMUX_CFR_CSOF10_Msk (0x1U << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
+#define DMAMUX_CFR_CSOF11_Pos (11U)
+#define DMAMUX_CFR_CSOF11_Msk (0x1U << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
+#define DMAMUX_CFR_CSOF12_Pos (12U)
+#define DMAMUX_CFR_CSOF12_Msk (0x1U << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
+#define DMAMUX_CFR_CSOF13_Pos (13U)
+#define DMAMUX_CFR_CSOF13_Msk (0x1U << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
+#define DMAMUX_CFR_CSOF14_Pos (14U)
+#define DMAMUX_CFR_CSOF14_Msk (0x1U << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
+#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
+#define DMAMUX_CFR_CSOF15_Pos (15U)
+#define DMAMUX_CFR_CSOF15_Msk (0x1U << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
+#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
+
+/******************** Bits definition for DMAMUX_RGxCR register ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FU << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
+#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos (8U)
+#define DMAMUX_RGxCR_OIE_Msk (0x1U << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
+#define DMAMUX_RGxCR_GE_Pos (16U)
+#define DMAMUX_RGxCR_GE_Msk (0x1U << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
+#define DMAMUX_RGxCR_GPOL_Pos (17U)
+#define DMAMUX_RGxCR_GPOL_Msk (0x3U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
+#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FU << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
+#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
+
+/******************** Bits definition for DMAMUX_RGSR register **************/
+#define DMAMUX_RGSR_OF0_Pos (0U)
+#define DMAMUX_RGSR_OF0_Msk (0x1U << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
+#define DMAMUX_RGSR_OF1_Pos (1U)
+#define DMAMUX_RGSR_OF1_Msk (0x1U << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
+#define DMAMUX_RGSR_OF2_Pos (2U)
+#define DMAMUX_RGSR_OF2_Msk (0x1U << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
+#define DMAMUX_RGSR_OF3_Pos (3U)
+#define DMAMUX_RGSR_OF3_Msk (0x1U << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
+#define DMAMUX_RGSR_OF4_Pos (4U)
+#define DMAMUX_RGSR_OF4_Msk (0x1U << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
+#define DMAMUX_RGSR_OF5_Pos (5U)
+#define DMAMUX_RGSR_OF5_Msk (0x1U << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
+#define DMAMUX_RGSR_OF6_Pos (6U)
+#define DMAMUX_RGSR_OF6_Msk (0x1U << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
+#define DMAMUX_RGSR_OF7_Pos (7U)
+#define DMAMUX_RGSR_OF7_Msk (0x1U << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
+#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
+
+/******************** Bits definition for DMAMUX_RGCFR register **************/
+#define DMAMUX_RGCFR_COF0_Pos (0U)
+#define DMAMUX_RGCFR_COF0_Msk (0x1U << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
+#define DMAMUX_RGCFR_COF1_Pos (1U)
+#define DMAMUX_RGCFR_COF1_Msk (0x1U << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
+#define DMAMUX_RGCFR_COF2_Pos (2U)
+#define DMAMUX_RGCFR_COF2_Msk (0x1U << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
+#define DMAMUX_RGCFR_COF3_Pos (3U)
+#define DMAMUX_RGCFR_COF3_Msk (0x1U << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
+#define DMAMUX_RGCFR_COF4_Pos (4U)
+#define DMAMUX_RGCFR_COF4_Msk (0x1U << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
+#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
+#define DMAMUX_RGCFR_COF5_Pos (5U)
+#define DMAMUX_RGCFR_COF5_Msk (0x1U << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
+#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
+#define DMAMUX_RGCFR_COF6_Pos (6U)
+#define DMAMUX_RGCFR_COF6_Msk (0x1U << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
+#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
+#define DMAMUX_RGCFR_COF7_Pos (7U)
+#define DMAMUX_RGCFR_COF7_Msk (0x1U << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
+#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
+
+/********************** Bit definition for DMAMUX_VERR register *****************/
+#define DMAMUX_VERR_MINREV_Pos (0U)
+#define DMAMUX_VERR_MINREV_Msk (0xFU << DMAMUX_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define DMAMUX_VERR_MINREV DMAMUX_VERR_MINREV_Msk /*!< Minor Revision number */
+#define DMAMUX_VERR_MAJREV_Pos (4U)
+#define DMAMUX_VERR_MAJREV_Msk (0xFU << DMAMUX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define DMAMUX_VERR_MAJREV DMAMUX_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for DMAMUX_IPIDR register ****************/
+#define DMAMUX_IPIDR_IPID_Pos (0U)
+#define DMAMUX_IPIDR_IPID_Msk (0xFFFFFFFFU << DMAMUX_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define DMAMUX_IPIDR_IPID DMAMUX_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for DMAMUX_SIDR register *****************/
+#define DMAMUX_SIDR_SID_Pos (0U)
+#define DMAMUX_SIDR_SID_Msk (0xFFFFFFFFU << DMAMUX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define DMAMUX_SIDR_SID DMAMUX_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Display Serial Interface (DSI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DSI_VR register *****************/
+#define DSI_VR ((uint32_t)0x3133312AU) /*!< DSI Host Version */
+
+/******************* Bit definition for DSI_CR register *****************/
+#define DSI_CR_EN ((uint32_t)0x00000001U) /*!< DSI Host power up and reset */
+
+/******************* Bit definition for DSI_CCR register ****************/
+#define DSI_CCR_TXECKDIV ((uint32_t)0x000000FFU) /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0 ((uint32_t)0x00000001U)
+#define DSI_CCR_TXECKDIV1 ((uint32_t)0x00000002U)
+#define DSI_CCR_TXECKDIV2 ((uint32_t)0x00000004U)
+#define DSI_CCR_TXECKDIV3 ((uint32_t)0x00000008U)
+#define DSI_CCR_TXECKDIV4 ((uint32_t)0x00000010U)
+#define DSI_CCR_TXECKDIV5 ((uint32_t)0x00000020U)
+#define DSI_CCR_TXECKDIV6 ((uint32_t)0x00000040U)
+#define DSI_CCR_TXECKDIV7 ((uint32_t)0x00000080U)
+
+#define DSI_CCR_TOCKDIV ((uint32_t)0x0000FF00U) /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0 ((uint32_t)0x00000100U)
+#define DSI_CCR_TOCKDIV1 ((uint32_t)0x00000200U)
+#define DSI_CCR_TOCKDIV2 ((uint32_t)0x00000400U)
+#define DSI_CCR_TOCKDIV3 ((uint32_t)0x00000800U)
+#define DSI_CCR_TOCKDIV4 ((uint32_t)0x00001000U)
+#define DSI_CCR_TOCKDIV5 ((uint32_t)0x00002000U)
+#define DSI_CCR_TOCKDIV6 ((uint32_t)0x00004000U)
+#define DSI_CCR_TOCKDIV7 ((uint32_t)0x00008000U)
+
+/******************* Bit definition for DSI_LVCIDR register *************/
+#define DSI_LVCIDR_VCID ((uint32_t)0x00000003U) /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0 ((uint32_t)0x00000001U)
+#define DSI_LVCIDR_VCID1 ((uint32_t)0x00000002U)
+
+/******************* Bit definition for DSI_LCOLCR register *************/
+#define DSI_LCOLCR_COLC ((uint32_t)0x0000000FU) /*!< Color Coding */
+#define DSI_LCOLCR_COLC0 ((uint32_t)0x00000001U)
+#define DSI_LCOLCR_COLC1 ((uint32_t)0x00000002U)
+#define DSI_LCOLCR_COLC2 ((uint32_t)0x00000004U)
+#define DSI_LCOLCR_COLC3 ((uint32_t)0x00000008U)
+
+#define DSI_LCOLCR_LPE ((uint32_t)0x00000100U) /*!< Loosly Packet Enable */
+
+/******************* Bit definition for DSI_LPCR register ***************/
+#define DSI_LPCR_DEP ((uint32_t)0x00000001U) /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP ((uint32_t)0x00000002U) /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP ((uint32_t)0x00000004U) /*!< HSYNC Polarity */
+
+/******************* Bit definition for DSI_LPMCR register **************/
+#define DSI_LPMCR_VLPSIZE ((uint32_t)0x000000FFU) /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0 ((uint32_t)0x00000001U)
+#define DSI_LPMCR_VLPSIZE1 ((uint32_t)0x00000002U)
+#define DSI_LPMCR_VLPSIZE2 ((uint32_t)0x00000004U)
+#define DSI_LPMCR_VLPSIZE3 ((uint32_t)0x00000008U)
+#define DSI_LPMCR_VLPSIZE4 ((uint32_t)0x00000010U)
+#define DSI_LPMCR_VLPSIZE5 ((uint32_t)0x00000020U)
+#define DSI_LPMCR_VLPSIZE6 ((uint32_t)0x00000040U)
+#define DSI_LPMCR_VLPSIZE7 ((uint32_t)0x00000080U)
+
+#define DSI_LPMCR_LPSIZE ((uint32_t)0x00FF0000U) /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0 ((uint32_t)0x00010000U)
+#define DSI_LPMCR_LPSIZE1 ((uint32_t)0x00020000U)
+#define DSI_LPMCR_LPSIZE2 ((uint32_t)0x00040000U)
+#define DSI_LPMCR_LPSIZE3 ((uint32_t)0x00080000U)
+#define DSI_LPMCR_LPSIZE4 ((uint32_t)0x00100000U)
+#define DSI_LPMCR_LPSIZE5 ((uint32_t)0x00200000U)
+#define DSI_LPMCR_LPSIZE6 ((uint32_t)0x00400000U)
+#define DSI_LPMCR_LPSIZE7 ((uint32_t)0x00800000U)
+
+/******************* Bit definition for DSI_PCR register ****************/
+#define DSI_PCR_ETTXE ((uint32_t)0x00000001U) /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE ((uint32_t)0x00000002U) /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE ((uint32_t)0x00000004U) /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE ((uint32_t)0x00000008U) /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE ((uint32_t)0x00000010U) /*!< CRC Reception Enable */
+
+/******************* Bit definition for DSI_GVCIDR register *************/
+#define DSI_GVCIDR_VCID ((uint32_t)0x00000003U) /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0 ((uint32_t)0x00000001U)
+#define DSI_GVCIDR_VCID1 ((uint32_t)0x00000002U)
+
+/******************* Bit definition for DSI_MCR register ****************/
+#define DSI_MCR_CMDM ((uint32_t)0x00000001U) /*!< Command Mode */
+
+/******************* Bit definition for DSI_VMCR register ***************/
+#define DSI_VMCR_VMT ((uint32_t)0x00000003U) /*!< Video Mode Type */
+#define DSI_VMCR_VMT0 ((uint32_t)0x00000001U)
+#define DSI_VMCR_VMT1 ((uint32_t)0x00000002U)
+
+#define DSI_VMCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE ((uint32_t)0x00001000U) /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE ((uint32_t)0x00002000U) /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE ((uint32_t)0x00004000U) /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE ((uint32_t)0x00008000U) /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE ((uint32_t)0x00010000U) /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM ((uint32_t)0x00100000U) /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO ((uint32_t)0x01000000U) /*!< Pattern Generator Orientation */
+
+/******************* Bit definition for DSI_VPCR register ***************/
+#define DSI_VPCR_VPSIZE ((uint32_t)0x00003FFFU) /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0 ((uint32_t)0x00000001U)
+#define DSI_VPCR_VPSIZE1 ((uint32_t)0x00000002U)
+#define DSI_VPCR_VPSIZE2 ((uint32_t)0x00000004U)
+#define DSI_VPCR_VPSIZE3 ((uint32_t)0x00000008U)
+#define DSI_VPCR_VPSIZE4 ((uint32_t)0x00000010U)
+#define DSI_VPCR_VPSIZE5 ((uint32_t)0x00000020U)
+#define DSI_VPCR_VPSIZE6 ((uint32_t)0x00000040U)
+#define DSI_VPCR_VPSIZE7 ((uint32_t)0x00000080U)
+#define DSI_VPCR_VPSIZE8 ((uint32_t)0x00000100U)
+#define DSI_VPCR_VPSIZE9 ((uint32_t)0x00000200U)
+#define DSI_VPCR_VPSIZE10 ((uint32_t)0x00000400U)
+#define DSI_VPCR_VPSIZE11 ((uint32_t)0x00000800U)
+#define DSI_VPCR_VPSIZE12 ((uint32_t)0x00001000U)
+#define DSI_VPCR_VPSIZE13 ((uint32_t)0x00002000U)
+
+/******************* Bit definition for DSI_VCCR register ***************/
+#define DSI_VCCR_NUMC ((uint32_t)0x00001FFFU) /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0 ((uint32_t)0x00000001U)
+#define DSI_VCCR_NUMC1 ((uint32_t)0x00000002U)
+#define DSI_VCCR_NUMC2 ((uint32_t)0x00000004U)
+#define DSI_VCCR_NUMC3 ((uint32_t)0x00000008U)
+#define DSI_VCCR_NUMC4 ((uint32_t)0x00000010U)
+#define DSI_VCCR_NUMC5 ((uint32_t)0x00000020U)
+#define DSI_VCCR_NUMC6 ((uint32_t)0x00000040U)
+#define DSI_VCCR_NUMC7 ((uint32_t)0x00000080U)
+#define DSI_VCCR_NUMC8 ((uint32_t)0x00000100U)
+#define DSI_VCCR_NUMC9 ((uint32_t)0x00000200U)
+#define DSI_VCCR_NUMC10 ((uint32_t)0x00000400U)
+#define DSI_VCCR_NUMC11 ((uint32_t)0x00000800U)
+#define DSI_VCCR_NUMC12 ((uint32_t)0x00001000U)
+
+/******************* Bit definition for DSI_VNPCR register **************/
+#define DSI_VNPCR_NPSIZE ((uint32_t)0x00001FFFU) /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0 ((uint32_t)0x00000001U)
+#define DSI_VNPCR_NPSIZE1 ((uint32_t)0x00000002U)
+#define DSI_VNPCR_NPSIZE2 ((uint32_t)0x00000004U)
+#define DSI_VNPCR_NPSIZE3 ((uint32_t)0x00000008U)
+#define DSI_VNPCR_NPSIZE4 ((uint32_t)0x00000010U)
+#define DSI_VNPCR_NPSIZE5 ((uint32_t)0x00000020U)
+#define DSI_VNPCR_NPSIZE6 ((uint32_t)0x00000040U)
+#define DSI_VNPCR_NPSIZE7 ((uint32_t)0x00000080U)
+#define DSI_VNPCR_NPSIZE8 ((uint32_t)0x00000100U)
+#define DSI_VNPCR_NPSIZE9 ((uint32_t)0x00000200U)
+#define DSI_VNPCR_NPSIZE10 ((uint32_t)0x00000400U)
+#define DSI_VNPCR_NPSIZE11 ((uint32_t)0x00000800U)
+#define DSI_VNPCR_NPSIZE12 ((uint32_t)0x00001000U)
+
+/******************* Bit definition for DSI_VHSACR register *************/
+#define DSI_VHSACR_HSA ((uint32_t)0x00000FFFU) /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0 ((uint32_t)0x00000001U)
+#define DSI_VHSACR_HSA1 ((uint32_t)0x00000002U)
+#define DSI_VHSACR_HSA2 ((uint32_t)0x00000004U)
+#define DSI_VHSACR_HSA3 ((uint32_t)0x00000008U)
+#define DSI_VHSACR_HSA4 ((uint32_t)0x00000010U)
+#define DSI_VHSACR_HSA5 ((uint32_t)0x00000020U)
+#define DSI_VHSACR_HSA6 ((uint32_t)0x00000040U)
+#define DSI_VHSACR_HSA7 ((uint32_t)0x00000080U)
+#define DSI_VHSACR_HSA8 ((uint32_t)0x00000100U)
+#define DSI_VHSACR_HSA9 ((uint32_t)0x00000200U)
+#define DSI_VHSACR_HSA10 ((uint32_t)0x00000400U)
+#define DSI_VHSACR_HSA11 ((uint32_t)0x00000800U)
+
+/******************* Bit definition for DSI_VHBPCR register *************/
+#define DSI_VHBPCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0 ((uint32_t)0x00000001U)
+#define DSI_VHBPCR_HBP1 ((uint32_t)0x00000002U)
+#define DSI_VHBPCR_HBP2 ((uint32_t)0x00000004U)
+#define DSI_VHBPCR_HBP3 ((uint32_t)0x00000008U)
+#define DSI_VHBPCR_HBP4 ((uint32_t)0x00000010U)
+#define DSI_VHBPCR_HBP5 ((uint32_t)0x00000020U)
+#define DSI_VHBPCR_HBP6 ((uint32_t)0x00000040U)
+#define DSI_VHBPCR_HBP7 ((uint32_t)0x00000080U)
+#define DSI_VHBPCR_HBP8 ((uint32_t)0x00000100U)
+#define DSI_VHBPCR_HBP9 ((uint32_t)0x00000200U)
+#define DSI_VHBPCR_HBP10 ((uint32_t)0x00000400U)
+#define DSI_VHBPCR_HBP11 ((uint32_t)0x00000800U)
+
+/******************* Bit definition for DSI_VLCR register ***************/
+#define DSI_VLCR_HLINE ((uint32_t)0x00007FFFU) /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0 ((uint32_t)0x00000001U)
+#define DSI_VLCR_HLINE1 ((uint32_t)0x00000002U)
+#define DSI_VLCR_HLINE2 ((uint32_t)0x00000004U)
+#define DSI_VLCR_HLINE3 ((uint32_t)0x00000008U)
+#define DSI_VLCR_HLINE4 ((uint32_t)0x00000010U)
+#define DSI_VLCR_HLINE5 ((uint32_t)0x00000020U)
+#define DSI_VLCR_HLINE6 ((uint32_t)0x00000040U)
+#define DSI_VLCR_HLINE7 ((uint32_t)0x00000080U)
+#define DSI_VLCR_HLINE8 ((uint32_t)0x00000100U)
+#define DSI_VLCR_HLINE9 ((uint32_t)0x00000200U)
+#define DSI_VLCR_HLINE10 ((uint32_t)0x00000400U)
+#define DSI_VLCR_HLINE11 ((uint32_t)0x00000800U)
+#define DSI_VLCR_HLINE12 ((uint32_t)0x00001000U)
+#define DSI_VLCR_HLINE13 ((uint32_t)0x00002000U)
+#define DSI_VLCR_HLINE14 ((uint32_t)0x00004000U)
+
+/******************* Bit definition for DSI_VVSACR register *************/
+#define DSI_VVSACR_VSA ((uint32_t)0x000003FFU) /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0 ((uint32_t)0x00000001U)
+#define DSI_VVSACR_VSA1 ((uint32_t)0x00000002U)
+#define DSI_VVSACR_VSA2 ((uint32_t)0x00000004U)
+#define DSI_VVSACR_VSA3 ((uint32_t)0x00000008U)
+#define DSI_VVSACR_VSA4 ((uint32_t)0x00000010U)
+#define DSI_VVSACR_VSA5 ((uint32_t)0x00000020U)
+#define DSI_VVSACR_VSA6 ((uint32_t)0x00000040U)
+#define DSI_VVSACR_VSA7 ((uint32_t)0x00000080U)
+#define DSI_VVSACR_VSA8 ((uint32_t)0x00000100U)
+#define DSI_VVSACR_VSA9 ((uint32_t)0x00000200U)
+
+/******************* Bit definition for DSI_VVBPCR register *************/
+#define DSI_VVBPCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0 ((uint32_t)0x00000001U)
+#define DSI_VVBPCR_VBP1 ((uint32_t)0x00000002U)
+#define DSI_VVBPCR_VBP2 ((uint32_t)0x00000004U)
+#define DSI_VVBPCR_VBP3 ((uint32_t)0x00000008U)
+#define DSI_VVBPCR_VBP4 ((uint32_t)0x00000010U)
+#define DSI_VVBPCR_VBP5 ((uint32_t)0x00000020U)
+#define DSI_VVBPCR_VBP6 ((uint32_t)0x00000040U)
+#define DSI_VVBPCR_VBP7 ((uint32_t)0x00000080U)
+#define DSI_VVBPCR_VBP8 ((uint32_t)0x00000100U)
+#define DSI_VVBPCR_VBP9 ((uint32_t)0x00000200U)
+
+/******************* Bit definition for DSI_VVFPCR register *************/
+#define DSI_VVFPCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0 ((uint32_t)0x00000001U)
+#define DSI_VVFPCR_VFP1 ((uint32_t)0x00000002U)
+#define DSI_VVFPCR_VFP2 ((uint32_t)0x00000004U)
+#define DSI_VVFPCR_VFP3 ((uint32_t)0x00000008U)
+#define DSI_VVFPCR_VFP4 ((uint32_t)0x00000010U)
+#define DSI_VVFPCR_VFP5 ((uint32_t)0x00000020U)
+#define DSI_VVFPCR_VFP6 ((uint32_t)0x00000040U)
+#define DSI_VVFPCR_VFP7 ((uint32_t)0x00000080U)
+#define DSI_VVFPCR_VFP8 ((uint32_t)0x00000100U)
+#define DSI_VVFPCR_VFP9 ((uint32_t)0x00000200U)
+
+/******************* Bit definition for DSI_VVACR register **************/
+#define DSI_VVACR_VA ((uint32_t)0x00003FFFU) /*!< Vertical Active duration */
+#define DSI_VVACR_VA0 ((uint32_t)0x00000001U)
+#define DSI_VVACR_VA1 ((uint32_t)0x00000002U)
+#define DSI_VVACR_VA2 ((uint32_t)0x00000004U)
+#define DSI_VVACR_VA3 ((uint32_t)0x00000008U)
+#define DSI_VVACR_VA4 ((uint32_t)0x00000010U)
+#define DSI_VVACR_VA5 ((uint32_t)0x00000020U)
+#define DSI_VVACR_VA6 ((uint32_t)0x00000040U)
+#define DSI_VVACR_VA7 ((uint32_t)0x00000080U)
+#define DSI_VVACR_VA8 ((uint32_t)0x00000100U)
+#define DSI_VVACR_VA9 ((uint32_t)0x00000200U)
+#define DSI_VVACR_VA10 ((uint32_t)0x00000400U)
+#define DSI_VVACR_VA11 ((uint32_t)0x00000800U)
+#define DSI_VVACR_VA12 ((uint32_t)0x00001000U)
+#define DSI_VVACR_VA13 ((uint32_t)0x00002000U)
+
+/******************* Bit definition for DSI_LCCR register ***************/
+#define DSI_LCCR_CMDSIZE ((uint32_t)0x0000FFFFU) /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0 ((uint32_t)0x00000001U)
+#define DSI_LCCR_CMDSIZE1 ((uint32_t)0x00000002U)
+#define DSI_LCCR_CMDSIZE2 ((uint32_t)0x00000004U)
+#define DSI_LCCR_CMDSIZE3 ((uint32_t)0x00000008U)
+#define DSI_LCCR_CMDSIZE4 ((uint32_t)0x00000010U)
+#define DSI_LCCR_CMDSIZE5 ((uint32_t)0x00000020U)
+#define DSI_LCCR_CMDSIZE6 ((uint32_t)0x00000040U)
+#define DSI_LCCR_CMDSIZE7 ((uint32_t)0x00000080U)
+#define DSI_LCCR_CMDSIZE8 ((uint32_t)0x00000100U)
+#define DSI_LCCR_CMDSIZE9 ((uint32_t)0x00000200U)
+#define DSI_LCCR_CMDSIZE10 ((uint32_t)0x00000400U)
+#define DSI_LCCR_CMDSIZE11 ((uint32_t)0x00000800U)
+#define DSI_LCCR_CMDSIZE12 ((uint32_t)0x00001000U)
+#define DSI_LCCR_CMDSIZE13 ((uint32_t)0x00002000U)
+#define DSI_LCCR_CMDSIZE14 ((uint32_t)0x00004000U)
+#define DSI_LCCR_CMDSIZE15 ((uint32_t)0x00008000U)
+
+/******************* Bit definition for DSI_CMCR register ***************/
+#define DSI_CMCR_TEARE ((uint32_t)0x00000001U) /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE ((uint32_t)0x00000002U) /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX ((uint32_t)0x00000100U) /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX ((uint32_t)0x00000200U) /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX ((uint32_t)0x00000400U) /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX ((uint32_t)0x00000800U) /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX ((uint32_t)0x00001000U) /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX ((uint32_t)0x00002000U) /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX ((uint32_t)0x00004000U) /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX ((uint32_t)0x00010000U) /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX ((uint32_t)0x00020000U) /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX ((uint32_t)0x00040000U) /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX ((uint32_t)0x00080000U) /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS ((uint32_t)0x01000000U) /*!< Maximum Read Packet Size */
+
+/******************* Bit definition for DSI_GHCR register ***************/
+#define DSI_GHCR_DT ((uint32_t)0x0000003FU) /*!< Type */
+#define DSI_GHCR_DT0 ((uint32_t)0x00000001U)
+#define DSI_GHCR_DT1 ((uint32_t)0x00000002U)
+#define DSI_GHCR_DT2 ((uint32_t)0x00000004U)
+#define DSI_GHCR_DT3 ((uint32_t)0x00000008U)
+#define DSI_GHCR_DT4 ((uint32_t)0x00000010U)
+#define DSI_GHCR_DT5 ((uint32_t)0x00000020U)
+
+#define DSI_GHCR_VCID ((uint32_t)0x000000C0U) /*!< Channel */
+#define DSI_GHCR_VCID0 ((uint32_t)0x00000040U)
+#define DSI_GHCR_VCID1 ((uint32_t)0x00000080U)
+
+#define DSI_GHCR_WCLSB ((uint32_t)0x0000FF00U) /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0 ((uint32_t)0x00000100U)
+#define DSI_GHCR_WCLSB1 ((uint32_t)0x00000200U)
+#define DSI_GHCR_WCLSB2 ((uint32_t)0x00000400U)
+#define DSI_GHCR_WCLSB3 ((uint32_t)0x00000800U)
+#define DSI_GHCR_WCLSB4 ((uint32_t)0x00001000U)
+#define DSI_GHCR_WCLSB5 ((uint32_t)0x00002000U)
+#define DSI_GHCR_WCLSB6 ((uint32_t)0x00004000U)
+#define DSI_GHCR_WCLSB7 ((uint32_t)0x00008000U)
+
+#define DSI_GHCR_WCMSB ((uint32_t)0x00FF0000U) /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0 ((uint32_t)0x00010000U)
+#define DSI_GHCR_WCMSB1 ((uint32_t)0x00020000U)
+#define DSI_GHCR_WCMSB2 ((uint32_t)0x00040000U)
+#define DSI_GHCR_WCMSB3 ((uint32_t)0x00080000U)
+#define DSI_GHCR_WCMSB4 ((uint32_t)0x00100000U)
+#define DSI_GHCR_WCMSB5 ((uint32_t)0x00200000U)
+#define DSI_GHCR_WCMSB6 ((uint32_t)0x00400000U)
+#define DSI_GHCR_WCMSB7 ((uint32_t)0x00800000U)
+
+/******************* Bit definition for DSI_GPDR register ***************/
+#define DSI_GPDR_DATA1 ((uint32_t)0x000000FFU) /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0 ((uint32_t)0x00000001U)
+#define DSI_GPDR_DATA1_1 ((uint32_t)0x00000002U)
+#define DSI_GPDR_DATA1_2 ((uint32_t)0x00000004U)
+#define DSI_GPDR_DATA1_3 ((uint32_t)0x00000008U)
+#define DSI_GPDR_DATA1_4 ((uint32_t)0x00000010U)
+#define DSI_GPDR_DATA1_5 ((uint32_t)0x00000020U)
+#define DSI_GPDR_DATA1_6 ((uint32_t)0x00000040U)
+#define DSI_GPDR_DATA1_7 ((uint32_t)0x00000080U)
+
+#define DSI_GPDR_DATA2 ((uint32_t)0x0000FF00U) /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0 ((uint32_t)0x00000100U)
+#define DSI_GPDR_DATA2_1 ((uint32_t)0x00000200U)
+#define DSI_GPDR_DATA2_2 ((uint32_t)0x00000400U)
+#define DSI_GPDR_DATA2_3 ((uint32_t)0x00000800U)
+#define DSI_GPDR_DATA2_4 ((uint32_t)0x00001000U)
+#define DSI_GPDR_DATA2_5 ((uint32_t)0x00002000U)
+#define DSI_GPDR_DATA2_6 ((uint32_t)0x00004000U)
+#define DSI_GPDR_DATA2_7 ((uint32_t)0x00008000U)
+
+#define DSI_GPDR_DATA3 ((uint32_t)0x00FF0000U) /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0 ((uint32_t)0x00010000U)
+#define DSI_GPDR_DATA3_1 ((uint32_t)0x00020000U)
+#define DSI_GPDR_DATA3_2 ((uint32_t)0x00040000U)
+#define DSI_GPDR_DATA3_3 ((uint32_t)0x00080000U)
+#define DSI_GPDR_DATA3_4 ((uint32_t)0x00100000U)
+#define DSI_GPDR_DATA3_5 ((uint32_t)0x00200000U)
+#define DSI_GPDR_DATA3_6 ((uint32_t)0x00400000U)
+#define DSI_GPDR_DATA3_7 ((uint32_t)0x00800000U)
+
+#define DSI_GPDR_DATA4 ((uint32_t)0xFF000000U) /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0 ((uint32_t)0x01000000U)
+#define DSI_GPDR_DATA4_1 ((uint32_t)0x02000000U)
+#define DSI_GPDR_DATA4_2 ((uint32_t)0x04000000U)
+#define DSI_GPDR_DATA4_3 ((uint32_t)0x08000000U)
+#define DSI_GPDR_DATA4_4 ((uint32_t)0x10000000U)
+#define DSI_GPDR_DATA4_5 ((uint32_t)0x20000000U)
+#define DSI_GPDR_DATA4_6 ((uint32_t)0x40000000U)
+#define DSI_GPDR_DATA4_7 ((uint32_t)0x80000000U)
+
+/******************* Bit definition for DSI_GPSR register ***************/
+#define DSI_GPSR_CMDFE ((uint32_t)0x00000001U) /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF ((uint32_t)0x00000002U) /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE ((uint32_t)0x00000004U) /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF ((uint32_t)0x00000008U) /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE ((uint32_t)0x00000010U) /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF ((uint32_t)0x00000020U) /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB ((uint32_t)0x00000040U) /*!< Read Command Busy */
+
+/******************* Bit definition for DSI_TCCR0 register **************/
+#define DSI_TCCR0_LPRX_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0 ((uint32_t)0x00000001U)
+#define DSI_TCCR0_LPRX_TOCNT1 ((uint32_t)0x00000002U)
+#define DSI_TCCR0_LPRX_TOCNT2 ((uint32_t)0x00000004U)
+#define DSI_TCCR0_LPRX_TOCNT3 ((uint32_t)0x00000008U)
+#define DSI_TCCR0_LPRX_TOCNT4 ((uint32_t)0x00000010U)
+#define DSI_TCCR0_LPRX_TOCNT5 ((uint32_t)0x00000020U)
+#define DSI_TCCR0_LPRX_TOCNT6 ((uint32_t)0x00000040U)
+#define DSI_TCCR0_LPRX_TOCNT7 ((uint32_t)0x00000080U)
+#define DSI_TCCR0_LPRX_TOCNT8 ((uint32_t)0x00000100U)
+#define DSI_TCCR0_LPRX_TOCNT9 ((uint32_t)0x00000200U)
+#define DSI_TCCR0_LPRX_TOCNT10 ((uint32_t)0x00000400U)
+#define DSI_TCCR0_LPRX_TOCNT11 ((uint32_t)0x00000800U)
+#define DSI_TCCR0_LPRX_TOCNT12 ((uint32_t)0x00001000U)
+#define DSI_TCCR0_LPRX_TOCNT13 ((uint32_t)0x00002000U)
+#define DSI_TCCR0_LPRX_TOCNT14 ((uint32_t)0x00004000U)
+#define DSI_TCCR0_LPRX_TOCNT15 ((uint32_t)0x00008000U)
+
+#define DSI_TCCR0_HSTX_TOCNT ((uint32_t)0xFFFF0000U) /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0 ((uint32_t)0x00010000U)
+#define DSI_TCCR0_HSTX_TOCNT1 ((uint32_t)0x00020000U)
+#define DSI_TCCR0_HSTX_TOCNT2 ((uint32_t)0x00040000U)
+#define DSI_TCCR0_HSTX_TOCNT3 ((uint32_t)0x00080000U)
+#define DSI_TCCR0_HSTX_TOCNT4 ((uint32_t)0x00100000U)
+#define DSI_TCCR0_HSTX_TOCNT5 ((uint32_t)0x00200000U)
+#define DSI_TCCR0_HSTX_TOCNT6 ((uint32_t)0x00400000U)
+#define DSI_TCCR0_HSTX_TOCNT7 ((uint32_t)0x00800000U)
+#define DSI_TCCR0_HSTX_TOCNT8 ((uint32_t)0x01000000U)
+#define DSI_TCCR0_HSTX_TOCNT9 ((uint32_t)0x02000000U)
+#define DSI_TCCR0_HSTX_TOCNT10 ((uint32_t)0x04000000U)
+#define DSI_TCCR0_HSTX_TOCNT11 ((uint32_t)0x08000000U)
+#define DSI_TCCR0_HSTX_TOCNT12 ((uint32_t)0x10000000U)
+#define DSI_TCCR0_HSTX_TOCNT13 ((uint32_t)0x20000000U)
+#define DSI_TCCR0_HSTX_TOCNT14 ((uint32_t)0x40000000U)
+#define DSI_TCCR0_HSTX_TOCNT15 ((uint32_t)0x80000000U)
+
+/******************* Bit definition for DSI_TCCR1 register **************/
+#define DSI_TCCR1_HSRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0 ((uint32_t)0x00000001U)
+#define DSI_TCCR1_HSRD_TOCNT1 ((uint32_t)0x00000002U)
+#define DSI_TCCR1_HSRD_TOCNT2 ((uint32_t)0x00000004U)
+#define DSI_TCCR1_HSRD_TOCNT3 ((uint32_t)0x00000008U)
+#define DSI_TCCR1_HSRD_TOCNT4 ((uint32_t)0x00000010U)
+#define DSI_TCCR1_HSRD_TOCNT5 ((uint32_t)0x00000020U)
+#define DSI_TCCR1_HSRD_TOCNT6 ((uint32_t)0x00000040U)
+#define DSI_TCCR1_HSRD_TOCNT7 ((uint32_t)0x00000080U)
+#define DSI_TCCR1_HSRD_TOCNT8 ((uint32_t)0x00000100U)
+#define DSI_TCCR1_HSRD_TOCNT9 ((uint32_t)0x00000200U)
+#define DSI_TCCR1_HSRD_TOCNT10 ((uint32_t)0x00000400U)
+#define DSI_TCCR1_HSRD_TOCNT11 ((uint32_t)0x00000800U)
+#define DSI_TCCR1_HSRD_TOCNT12 ((uint32_t)0x00001000U)
+#define DSI_TCCR1_HSRD_TOCNT13 ((uint32_t)0x00002000U)
+#define DSI_TCCR1_HSRD_TOCNT14 ((uint32_t)0x00004000U)
+#define DSI_TCCR1_HSRD_TOCNT15 ((uint32_t)0x00008000U)
+
+/******************* Bit definition for DSI_TCCR2 register **************/
+#define DSI_TCCR2_LPRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0 ((uint32_t)0x00000001U)
+#define DSI_TCCR2_LPRD_TOCNT1 ((uint32_t)0x00000002U)
+#define DSI_TCCR2_LPRD_TOCNT2 ((uint32_t)0x00000004U)
+#define DSI_TCCR2_LPRD_TOCNT3 ((uint32_t)0x00000008U)
+#define DSI_TCCR2_LPRD_TOCNT4 ((uint32_t)0x00000010U)
+#define DSI_TCCR2_LPRD_TOCNT5 ((uint32_t)0x00000020U)
+#define DSI_TCCR2_LPRD_TOCNT6 ((uint32_t)0x00000040U)
+#define DSI_TCCR2_LPRD_TOCNT7 ((uint32_t)0x00000080U)
+#define DSI_TCCR2_LPRD_TOCNT8 ((uint32_t)0x00000100U)
+#define DSI_TCCR2_LPRD_TOCNT9 ((uint32_t)0x00000200U)
+#define DSI_TCCR2_LPRD_TOCNT10 ((uint32_t)0x00000400U)
+#define DSI_TCCR2_LPRD_TOCNT11 ((uint32_t)0x00000800U)
+#define DSI_TCCR2_LPRD_TOCNT12 ((uint32_t)0x00001000U)
+#define DSI_TCCR2_LPRD_TOCNT13 ((uint32_t)0x00002000U)
+#define DSI_TCCR2_LPRD_TOCNT14 ((uint32_t)0x00004000U)
+#define DSI_TCCR2_LPRD_TOCNT15 ((uint32_t)0x00008000U)
+
+/******************* Bit definition for DSI_TCCR3 register **************/
+#define DSI_TCCR3_HSWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0 ((uint32_t)0x00000001U)
+#define DSI_TCCR3_HSWR_TOCNT1 ((uint32_t)0x00000002U)
+#define DSI_TCCR3_HSWR_TOCNT2 ((uint32_t)0x00000004U)
+#define DSI_TCCR3_HSWR_TOCNT3 ((uint32_t)0x00000008U)
+#define DSI_TCCR3_HSWR_TOCNT4 ((uint32_t)0x00000010U)
+#define DSI_TCCR3_HSWR_TOCNT5 ((uint32_t)0x00000020U)
+#define DSI_TCCR3_HSWR_TOCNT6 ((uint32_t)0x00000040U)
+#define DSI_TCCR3_HSWR_TOCNT7 ((uint32_t)0x00000080U)
+#define DSI_TCCR3_HSWR_TOCNT8 ((uint32_t)0x00000100U)
+#define DSI_TCCR3_HSWR_TOCNT9 ((uint32_t)0x00000200U)
+#define DSI_TCCR3_HSWR_TOCNT10 ((uint32_t)0x00000400U)
+#define DSI_TCCR3_HSWR_TOCNT11 ((uint32_t)0x00000800U)
+#define DSI_TCCR3_HSWR_TOCNT12 ((uint32_t)0x00001000U)
+#define DSI_TCCR3_HSWR_TOCNT13 ((uint32_t)0x00002000U)
+#define DSI_TCCR3_HSWR_TOCNT14 ((uint32_t)0x00004000U)
+#define DSI_TCCR3_HSWR_TOCNT15 ((uint32_t)0x00008000U)
+
+#define DSI_TCCR3_PM ((uint32_t)0x01000000U) /*!< Presp Mode */
+
+/******************* Bit definition for DSI_TCCR4 register **************/
+#define DSI_TCCR4_LPWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0 ((uint32_t)0x00000001U)
+#define DSI_TCCR4_LPWR_TOCNT1 ((uint32_t)0x00000002U)
+#define DSI_TCCR4_LPWR_TOCNT2 ((uint32_t)0x00000004U)
+#define DSI_TCCR4_LPWR_TOCNT3 ((uint32_t)0x00000008U)
+#define DSI_TCCR4_LPWR_TOCNT4 ((uint32_t)0x00000010U)
+#define DSI_TCCR4_LPWR_TOCNT5 ((uint32_t)0x00000020U)
+#define DSI_TCCR4_LPWR_TOCNT6 ((uint32_t)0x00000040U)
+#define DSI_TCCR4_LPWR_TOCNT7 ((uint32_t)0x00000080U)
+#define DSI_TCCR4_LPWR_TOCNT8 ((uint32_t)0x00000100U)
+#define DSI_TCCR4_LPWR_TOCNT9 ((uint32_t)0x00000200U)
+#define DSI_TCCR4_LPWR_TOCNT10 ((uint32_t)0x00000400U)
+#define DSI_TCCR4_LPWR_TOCNT11 ((uint32_t)0x00000800U)
+#define DSI_TCCR4_LPWR_TOCNT12 ((uint32_t)0x00001000U)
+#define DSI_TCCR4_LPWR_TOCNT13 ((uint32_t)0x00002000U)
+#define DSI_TCCR4_LPWR_TOCNT14 ((uint32_t)0x00004000U)
+#define DSI_TCCR4_LPWR_TOCNT15 ((uint32_t)0x00008000U)
+
+/******************* Bit definition for DSI_TCCR5 register **************/
+#define DSI_TCCR5_BTA_TOCNT ((uint32_t)0x0000FFFFU) /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0 ((uint32_t)0x00000001U)
+#define DSI_TCCR5_BTA_TOCNT1 ((uint32_t)0x00000002U)
+#define DSI_TCCR5_BTA_TOCNT2 ((uint32_t)0x00000004U)
+#define DSI_TCCR5_BTA_TOCNT3 ((uint32_t)0x00000008U)
+#define DSI_TCCR5_BTA_TOCNT4 ((uint32_t)0x00000010U)
+#define DSI_TCCR5_BTA_TOCNT5 ((uint32_t)0x00000020U)
+#define DSI_TCCR5_BTA_TOCNT6 ((uint32_t)0x00000040U)
+#define DSI_TCCR5_BTA_TOCNT7 ((uint32_t)0x00000080U)
+#define DSI_TCCR5_BTA_TOCNT8 ((uint32_t)0x00000100U)
+#define DSI_TCCR5_BTA_TOCNT9 ((uint32_t)0x00000200U)
+#define DSI_TCCR5_BTA_TOCNT10 ((uint32_t)0x00000400U)
+#define DSI_TCCR5_BTA_TOCNT11 ((uint32_t)0x00000800U)
+#define DSI_TCCR5_BTA_TOCNT12 ((uint32_t)0x00001000U)
+#define DSI_TCCR5_BTA_TOCNT13 ((uint32_t)0x00002000U)
+#define DSI_TCCR5_BTA_TOCNT14 ((uint32_t)0x00004000U)
+#define DSI_TCCR5_BTA_TOCNT15 ((uint32_t)0x00008000U)
+
+/******************* Bit definition for DSI_TDCR register ***************/
+#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
+#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U)
+#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U)
+
+#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
+#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U)
+#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U)
+
+#define DSI_TDCR_SVS ((uint32_t)0x00000010U) /*!< Second VSYNC */
+#define DSI_TDCR_RF ((uint32_t)0x00000020U) /*!< Right First */
+#define DSI_TDCR_S3DC ((uint32_t)0x00010000U) /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_CLCR register ***************/
+#define DSI_CLCR_DPCC ((uint32_t)0x00000001U) /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR ((uint32_t)0x00000002U) /*!< Automatic Clocklane Control */
+
+/******************* Bit definition for DSI_CLTCR register **************/
+#define DSI_CLTCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0 ((uint32_t)0x00000001U)
+#define DSI_CLTCR_LP2HS_TIME1 ((uint32_t)0x00000002U)
+#define DSI_CLTCR_LP2HS_TIME2 ((uint32_t)0x00000004U)
+#define DSI_CLTCR_LP2HS_TIME3 ((uint32_t)0x00000008U)
+#define DSI_CLTCR_LP2HS_TIME4 ((uint32_t)0x00000010U)
+#define DSI_CLTCR_LP2HS_TIME5 ((uint32_t)0x00000020U)
+#define DSI_CLTCR_LP2HS_TIME6 ((uint32_t)0x00000040U)
+#define DSI_CLTCR_LP2HS_TIME7 ((uint32_t)0x00000080U)
+#define DSI_CLTCR_LP2HS_TIME8 ((uint32_t)0x00000100U)
+#define DSI_CLTCR_LP2HS_TIME9 ((uint32_t)0x00000200U)
+
+#define DSI_CLTCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0 ((uint32_t)0x00010000U)
+#define DSI_CLTCR_HS2LP_TIME1 ((uint32_t)0x00020000U)
+#define DSI_CLTCR_HS2LP_TIME2 ((uint32_t)0x00040000U)
+#define DSI_CLTCR_HS2LP_TIME3 ((uint32_t)0x00080000U)
+#define DSI_CLTCR_HS2LP_TIME4 ((uint32_t)0x00100000U)
+#define DSI_CLTCR_HS2LP_TIME5 ((uint32_t)0x00200000U)
+#define DSI_CLTCR_HS2LP_TIME6 ((uint32_t)0x00400000U)
+#define DSI_CLTCR_HS2LP_TIME7 ((uint32_t)0x00800000U)
+#define DSI_CLTCR_HS2LP_TIME8 ((uint32_t)0x01000000U)
+#define DSI_CLTCR_HS2LP_TIME9 ((uint32_t)0x02000000U)
+
+/******************* Bit definition for DSI_DLTCR register **************/
+#define DSI_DLTCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0 ((uint32_t)0x00000001U)
+#define DSI_DLTCR_LP2HS_TIME1 ((uint32_t)0x00000002U)
+#define DSI_DLTCR_LP2HS_TIME2 ((uint32_t)0x00000004U)
+#define DSI_DLTCR_LP2HS_TIME3 ((uint32_t)0x00000008U)
+#define DSI_DLTCR_LP2HS_TIME4 ((uint32_t)0x00000010U)
+#define DSI_DLTCR_LP2HS_TIME5 ((uint32_t)0x00000020U)
+#define DSI_DLTCR_LP2HS_TIME6 ((uint32_t)0x00000040U)
+#define DSI_DLTCR_LP2HS_TIME7 ((uint32_t)0x00000080U)
+#define DSI_DLTCR_LP2HS_TIME8 ((uint32_t)0x00000100U)
+#define DSI_DLTCR_LP2HS_TIME9 ((uint32_t)0x00000200U)
+
+#define DSI_DLTCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0 ((uint32_t)0x00010000U)
+#define DSI_DLTCR_HS2LP_TIME1 ((uint32_t)0x00020000U)
+#define DSI_DLTCR_HS2LP_TIME2 ((uint32_t)0x00040000U)
+#define DSI_DLTCR_HS2LP_TIME3 ((uint32_t)0x00080000U)
+#define DSI_DLTCR_HS2LP_TIME4 ((uint32_t)0x00100000U)
+#define DSI_DLTCR_HS2LP_TIME5 ((uint32_t)0x00200000U)
+#define DSI_DLTCR_HS2LP_TIME6 ((uint32_t)0x00400000U)
+#define DSI_DLTCR_HS2LP_TIME7 ((uint32_t)0x00800000U)
+#define DSI_DLTCR_HS2LP_TIME8 ((uint32_t)0x01000000U)
+#define DSI_DLTCR_HS2LP_TIME9 ((uint32_t)0x02000000U)
+
+/******************* Bit definition for DSI_PCTLR register **************/
+#define DSI_PCTLR_DEN ((uint32_t)0x00000002U) /*!< Digital Enable */
+#define DSI_PCTLR_CKE ((uint32_t)0x00000004U) /*!< Clock Enable */
+
+/******************* Bit definition for DSI_PCONFR register *************/
+#define DSI_PCONFR_NL ((uint32_t)0x00000003U) /*!< Number of Lanes */
+#define DSI_PCONFR_NL0 ((uint32_t)0x00000001U)
+#define DSI_PCONFR_NL1 ((uint32_t)0x00000002U)
+
+#define DSI_PCONFR_SW_TIME ((uint32_t)0x0000FF00U) /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0 ((uint32_t)0x00000100U)
+#define DSI_PCONFR_SW_TIME1 ((uint32_t)0x00000200U)
+#define DSI_PCONFR_SW_TIME2 ((uint32_t)0x00000400U)
+#define DSI_PCONFR_SW_TIME3 ((uint32_t)0x00000800U)
+#define DSI_PCONFR_SW_TIME4 ((uint32_t)0x00001000U)
+#define DSI_PCONFR_SW_TIME5 ((uint32_t)0x00002000U)
+#define DSI_PCONFR_SW_TIME6 ((uint32_t)0x00004000U)
+#define DSI_PCONFR_SW_TIME7 ((uint32_t)0x00008000U)
+
+/******************* Bit definition for DSI_PUCR register ***************/
+#define DSI_PUCR_URCL ((uint32_t)0x00000001U) /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL ((uint32_t)0x00000002U) /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL ((uint32_t)0x00000004U) /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL ((uint32_t)0x00000008U) /*!< ULPS Exit on Data Lane */
+
+/******************* Bit definition for DSI_PTTCR register **************/
+#define DSI_PTTCR_TX_TRIG ((uint32_t)0x0000000FU) /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0 ((uint32_t)0x00000001U)
+#define DSI_PTTCR_TX_TRIG1 ((uint32_t)0x00000002U)
+#define DSI_PTTCR_TX_TRIG2 ((uint32_t)0x00000004U)
+#define DSI_PTTCR_TX_TRIG3 ((uint32_t)0x00000008U)
+
+/******************* Bit definition for DSI_PSR register ****************/
+#define DSI_PSR_PD ((uint32_t)0x00000002U) /*!< PHY Direction */
+#define DSI_PSR_PSSC ((uint32_t)0x00000004U) /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC ((uint32_t)0x00000008U) /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0 ((uint32_t)0x00000010U) /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0 ((uint32_t)0x00000020U) /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0 ((uint32_t)0x00000040U) /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1 ((uint32_t)0x00000080U) /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1 ((uint32_t)0x00000100U) /*!< ULPS Active Not lane 1 */
+
+/******************* Bit definition for DSI_ISR0 register ***************/
+#define DSI_ISR0_AE0 ((uint32_t)0x00000001U) /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1 ((uint32_t)0x00000002U) /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2 ((uint32_t)0x00000004U) /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3 ((uint32_t)0x00000008U) /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4 ((uint32_t)0x00000010U) /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5 ((uint32_t)0x00000020U) /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6 ((uint32_t)0x00000040U) /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7 ((uint32_t)0x00000080U) /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8 ((uint32_t)0x00000100U) /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9 ((uint32_t)0x00000200U) /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10 ((uint32_t)0x00000400U) /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11 ((uint32_t)0x00000800U) /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12 ((uint32_t)0x00001000U) /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13 ((uint32_t)0x00002000U) /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14 ((uint32_t)0x00004000U) /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15 ((uint32_t)0x00008000U) /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0 ((uint32_t)0x00010000U) /*!< PHY Error 0 */
+#define DSI_ISR0_PE1 ((uint32_t)0x00020000U) /*!< PHY Error 1 */
+#define DSI_ISR0_PE2 ((uint32_t)0x00040000U) /*!< PHY Error 2 */
+#define DSI_ISR0_PE3 ((uint32_t)0x00080000U) /*!< PHY Error 3 */
+#define DSI_ISR0_PE4 ((uint32_t)0x00100000U) /*!< PHY Error 4 */
+
+/******************* Bit definition for DSI_ISR1 register ***************/
+#define DSI_ISR1_TOHSTX ((uint32_t)0x00000001U) /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX ((uint32_t)0x00000002U) /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE ((uint32_t)0x00000004U) /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME ((uint32_t)0x00000008U) /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE ((uint32_t)0x00000010U) /*!< CRC Error */
+#define DSI_ISR1_PSE ((uint32_t)0x00000020U) /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE ((uint32_t)0x00000040U) /*!< EoTp Error */
+#define DSI_ISR1_LPWRE ((uint32_t)0x00000080U) /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE ((uint32_t)0x00000100U) /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE ((uint32_t)0x00000200U) /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE ((uint32_t)0x00000400U) /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE ((uint32_t)0x00000800U) /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE ((uint32_t)0x00001000U) /*!< Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_IER0 register ***************/
+#define DSI_IER0_AE0IE ((uint32_t)0x00000001U) /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE ((uint32_t)0x00000002U) /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE ((uint32_t)0x00000004U) /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE ((uint32_t)0x00000008U) /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE ((uint32_t)0x00000010U) /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE ((uint32_t)0x00000020U) /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE ((uint32_t)0x00000040U) /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE ((uint32_t)0x00000080U) /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE ((uint32_t)0x00000100U) /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE ((uint32_t)0x00000200U) /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE ((uint32_t)0x00000400U) /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE ((uint32_t)0x00000800U) /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE ((uint32_t)0x00001000U) /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE ((uint32_t)0x00002000U) /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE ((uint32_t)0x00004000U) /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE ((uint32_t)0x00008000U) /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE ((uint32_t)0x00010000U) /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE ((uint32_t)0x00020000U) /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE ((uint32_t)0x00040000U) /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE ((uint32_t)0x00080000U) /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE ((uint32_t)0x00100000U) /*!< PHY Error 4 Interrupt Enable */
+
+/******************* Bit definition for DSI_IER1 register ***************/
+#define DSI_IER1_TOHSTXIE ((uint32_t)0x00000001U) /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE ((uint32_t)0x00000002U) /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE ((uint32_t)0x00000004U) /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE ((uint32_t)0x00000008U) /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE ((uint32_t)0x00000010U) /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE ((uint32_t)0x00000020U) /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE ((uint32_t)0x00000040U) /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE ((uint32_t)0x00000080U) /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE ((uint32_t)0x00000100U) /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE ((uint32_t)0x00000200U) /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE ((uint32_t)0x00000400U) /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE ((uint32_t)0x00000800U) /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE ((uint32_t)0x00001000U) /*!< Generic Payload Receive Error Interrupt Enable */
+
+/******************* Bit definition for DSI_FIR0 register ***************/
+#define DSI_FIR0_FAE0 ((uint32_t)0x00000001U) /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1 ((uint32_t)0x00000002U) /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2 ((uint32_t)0x00000004U) /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3 ((uint32_t)0x00000008U) /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4 ((uint32_t)0x00000010U) /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5 ((uint32_t)0x00000020U) /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6 ((uint32_t)0x00000040U) /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7 ((uint32_t)0x00000080U) /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8 ((uint32_t)0x00000100U) /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9 ((uint32_t)0x00000200U) /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10 ((uint32_t)0x00000400U) /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11 ((uint32_t)0x00000800U) /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12 ((uint32_t)0x00001000U) /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13 ((uint32_t)0x00002000U) /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14 ((uint32_t)0x00004000U) /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15 ((uint32_t)0x00008000U) /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0 ((uint32_t)0x00010000U) /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1 ((uint32_t)0x00020000U) /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2 ((uint32_t)0x00040000U) /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3 ((uint32_t)0x00080000U) /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4 ((uint32_t)0x00100000U) /*!< Force PHY Error 4 */
+
+/******************* Bit definition for DSI_FIR1 register ***************/
+#define DSI_FIR1_FTOHSTX ((uint32_t)0x00000001U) /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX ((uint32_t)0x00000002U) /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE ((uint32_t)0x00000004U) /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME ((uint32_t)0x00000008U) /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE ((uint32_t)0x00000010U) /*!< Force CRC Error */
+#define DSI_FIR1_FPSE ((uint32_t)0x00000020U) /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE ((uint32_t)0x00000040U) /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE ((uint32_t)0x00000080U) /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE ((uint32_t)0x00000100U) /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE ((uint32_t)0x00000200U) /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE ((uint32_t)0x00000400U) /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE ((uint32_t)0x00000800U) /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE ((uint32_t)0x00001000U) /*!< Force Generic Payload Receive Error */
+
+/******************* Bit definition for DSI_DLTRCR register *************/
+#define DSI_DLTRCR_MRD_TIME ((uint32_t)0x00007FFFU) /*!< Maximum Read Time */
+#define DSI_DLTRCR_MRD_TIME0 ((uint32_t)0x00000001U)
+#define DSI_DLTRCR_MRD_TIME1 ((uint32_t)0x00000002U)
+#define DSI_DLTRCR_MRD_TIME2 ((uint32_t)0x00000004U)
+#define DSI_DLTRCR_MRD_TIME3 ((uint32_t)0x00000008U)
+#define DSI_DLTRCR_MRD_TIME4 ((uint32_t)0x00000010U)
+#define DSI_DLTRCR_MRD_TIME5 ((uint32_t)0x00000020U)
+#define DSI_DLTRCR_MRD_TIME6 ((uint32_t)0x00000040U)
+#define DSI_DLTRCR_MRD_TIME7 ((uint32_t)0x00000080U)
+#define DSI_DLTRCR_MRD_TIME8 ((uint32_t)0x00000100U)
+#define DSI_DLTRCR_MRD_TIME9 ((uint32_t)0x00000200U)
+#define DSI_DLTRCR_MRD_TIME10 ((uint32_t)0x00000400U)
+#define DSI_DLTRCR_MRD_TIME11 ((uint32_t)0x00000800U)
+#define DSI_DLTRCR_MRD_TIME12 ((uint32_t)0x00001000U)
+#define DSI_DLTRCR_MRD_TIME13 ((uint32_t)0x00002000U)
+#define DSI_DLTRCR_MRD_TIME14 ((uint32_t)0x00004000U)
+
+/******************* Bit definition for DSI_VSCR register ***************/
+#define DSI_VSCR_EN ((uint32_t)0x00000001U) /*!< Enable */
+#define DSI_VSCR_UR ((uint32_t)0x00000100U) /*!< Update Register */
+
+/******************* Bit definition for DSI_LCVCIDR register ************/
+#define DSI_LCVCIDR_VCID ((uint32_t)0x00000003U) /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0 ((uint32_t)0x00000001U)
+#define DSI_LCVCIDR_VCID1 ((uint32_t)0x00000002U)
+
+/******************* Bit definition for DSI_LCCCR register **************/
+#define DSI_LCCCR_COLC ((uint32_t)0x0000000FU) /*!< Color Coding */
+#define DSI_LCCCR_COLC0 ((uint32_t)0x00000001U)
+#define DSI_LCCCR_COLC1 ((uint32_t)0x00000002U)
+#define DSI_LCCCR_COLC2 ((uint32_t)0x00000004U)
+#define DSI_LCCCR_COLC3 ((uint32_t)0x00000008U)
+
+#define DSI_LCCCR_LPE ((uint32_t)0x00000100U) /*!< Loosely Packed Enable */
+
+/******************* Bit definition for DSI_LPMCCR register *************/
+#define DSI_LPMCCR_VLPSIZE ((uint32_t)0x000000FFU) /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0 ((uint32_t)0x00000001U)
+#define DSI_LPMCCR_VLPSIZE1 ((uint32_t)0x00000002U)
+#define DSI_LPMCCR_VLPSIZE2 ((uint32_t)0x00000004U)
+#define DSI_LPMCCR_VLPSIZE3 ((uint32_t)0x00000008U)
+#define DSI_LPMCCR_VLPSIZE4 ((uint32_t)0x00000010U)
+#define DSI_LPMCCR_VLPSIZE5 ((uint32_t)0x00000020U)
+#define DSI_LPMCCR_VLPSIZE6 ((uint32_t)0x00000040U)
+#define DSI_LPMCCR_VLPSIZE7 ((uint32_t)0x00000080U)
+
+#define DSI_LPMCCR_LPSIZE ((uint32_t)0x00FF0000U) /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0 ((uint32_t)0x00010000U)
+#define DSI_LPMCCR_LPSIZE1 ((uint32_t)0x00020000U)
+#define DSI_LPMCCR_LPSIZE2 ((uint32_t)0x00040000U)
+#define DSI_LPMCCR_LPSIZE3 ((uint32_t)0x00080000U)
+#define DSI_LPMCCR_LPSIZE4 ((uint32_t)0x00100000U)
+#define DSI_LPMCCR_LPSIZE5 ((uint32_t)0x00200000U)
+#define DSI_LPMCCR_LPSIZE6 ((uint32_t)0x00400000U)
+#define DSI_LPMCCR_LPSIZE7 ((uint32_t)0x00800000U)
+
+/******************* Bit definition for DSI_VMCCR register **************/
+#define DSI_VMCCR_VMT ((uint32_t)0x00000003U) /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0 ((uint32_t)0x00000001U)
+#define DSI_VMCCR_VMT1 ((uint32_t)0x00000002U)
+
+#define DSI_VMCCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE ((uint32_t)0x00001000U) /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE ((uint32_t)0x00002000U) /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE ((uint32_t)0x00004000U) /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE ((uint32_t)0x00008000U) /*!< Low-power Command Enable */
+
+/******************* Bit definition for DSI_VPCCR register **************/
+#define DSI_VPCCR_VPSIZE ((uint32_t)0x00003FFFU) /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0 ((uint32_t)0x00000001U)
+#define DSI_VPCCR_VPSIZE1 ((uint32_t)0x00000002U)
+#define DSI_VPCCR_VPSIZE2 ((uint32_t)0x00000004U)
+#define DSI_VPCCR_VPSIZE3 ((uint32_t)0x00000008U)
+#define DSI_VPCCR_VPSIZE4 ((uint32_t)0x00000010U)
+#define DSI_VPCCR_VPSIZE5 ((uint32_t)0x00000020U)
+#define DSI_VPCCR_VPSIZE6 ((uint32_t)0x00000040U)
+#define DSI_VPCCR_VPSIZE7 ((uint32_t)0x00000080U)
+#define DSI_VPCCR_VPSIZE8 ((uint32_t)0x00000100U)
+#define DSI_VPCCR_VPSIZE9 ((uint32_t)0x00000200U)
+#define DSI_VPCCR_VPSIZE10 ((uint32_t)0x00000400U)
+#define DSI_VPCCR_VPSIZE11 ((uint32_t)0x00000800U)
+#define DSI_VPCCR_VPSIZE12 ((uint32_t)0x00001000U)
+#define DSI_VPCCR_VPSIZE13 ((uint32_t)0x00002000U)
+
+/******************* Bit definition for DSI_VCCCR register **************/
+#define DSI_VCCCR_NUMC ((uint32_t)0x00001FFFU) /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0 ((uint32_t)0x00000001U)
+#define DSI_VCCCR_NUMC1 ((uint32_t)0x00000002U)
+#define DSI_VCCCR_NUMC2 ((uint32_t)0x00000004U)
+#define DSI_VCCCR_NUMC3 ((uint32_t)0x00000008U)
+#define DSI_VCCCR_NUMC4 ((uint32_t)0x00000010U)
+#define DSI_VCCCR_NUMC5 ((uint32_t)0x00000020U)
+#define DSI_VCCCR_NUMC6 ((uint32_t)0x00000040U)
+#define DSI_VCCCR_NUMC7 ((uint32_t)0x00000080U)
+#define DSI_VCCCR_NUMC8 ((uint32_t)0x00000100U)
+#define DSI_VCCCR_NUMC9 ((uint32_t)0x00000200U)
+#define DSI_VCCCR_NUMC10 ((uint32_t)0x00000400U)
+#define DSI_VCCCR_NUMC11 ((uint32_t)0x00000800U)
+#define DSI_VCCCR_NUMC12 ((uint32_t)0x00001000U)
+
+/******************* Bit definition for DSI_VNPCCR register *************/
+#define DSI_VNPCCR_NPSIZE ((uint32_t)0x00001FFFU) /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0 ((uint32_t)0x00000001U)
+#define DSI_VNPCCR_NPSIZE1 ((uint32_t)0x00000002U)
+#define DSI_VNPCCR_NPSIZE2 ((uint32_t)0x00000004U)
+#define DSI_VNPCCR_NPSIZE3 ((uint32_t)0x00000008U)
+#define DSI_VNPCCR_NPSIZE4 ((uint32_t)0x00000010U)
+#define DSI_VNPCCR_NPSIZE5 ((uint32_t)0x00000020U)
+#define DSI_VNPCCR_NPSIZE6 ((uint32_t)0x00000040U)
+#define DSI_VNPCCR_NPSIZE7 ((uint32_t)0x00000080U)
+#define DSI_VNPCCR_NPSIZE8 ((uint32_t)0x00000100U)
+#define DSI_VNPCCR_NPSIZE9 ((uint32_t)0x00000200U)
+#define DSI_VNPCCR_NPSIZE10 ((uint32_t)0x00000400U)
+#define DSI_VNPCCR_NPSIZE11 ((uint32_t)0x00000800U)
+#define DSI_VNPCCR_NPSIZE12 ((uint32_t)0x00001000U)
+
+/******************* Bit definition for DSI_VHSACCR register ************/
+#define DSI_VHSACCR_HSA ((uint32_t)0x00000FFFU) /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0 ((uint32_t)0x00000001U)
+#define DSI_VHSACCR_HSA1 ((uint32_t)0x00000002U)
+#define DSI_VHSACCR_HSA2 ((uint32_t)0x00000004U)
+#define DSI_VHSACCR_HSA3 ((uint32_t)0x00000008U)
+#define DSI_VHSACCR_HSA4 ((uint32_t)0x00000010U)
+#define DSI_VHSACCR_HSA5 ((uint32_t)0x00000020U)
+#define DSI_VHSACCR_HSA6 ((uint32_t)0x00000040U)
+#define DSI_VHSACCR_HSA7 ((uint32_t)0x00000080U)
+#define DSI_VHSACCR_HSA8 ((uint32_t)0x00000100U)
+#define DSI_VHSACCR_HSA9 ((uint32_t)0x00000200U)
+#define DSI_VHSACCR_HSA10 ((uint32_t)0x00000400U)
+#define DSI_VHSACCR_HSA11 ((uint32_t)0x00000800U)
+
+/******************* Bit definition for DSI_VHBPCCR register ************/
+#define DSI_VHBPCCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0 ((uint32_t)0x00000001U)
+#define DSI_VHBPCCR_HBP1 ((uint32_t)0x00000002U)
+#define DSI_VHBPCCR_HBP2 ((uint32_t)0x00000004U)
+#define DSI_VHBPCCR_HBP3 ((uint32_t)0x00000008U)
+#define DSI_VHBPCCR_HBP4 ((uint32_t)0x00000010U)
+#define DSI_VHBPCCR_HBP5 ((uint32_t)0x00000020U)
+#define DSI_VHBPCCR_HBP6 ((uint32_t)0x00000040U)
+#define DSI_VHBPCCR_HBP7 ((uint32_t)0x00000080U)
+#define DSI_VHBPCCR_HBP8 ((uint32_t)0x00000100U)
+#define DSI_VHBPCCR_HBP9 ((uint32_t)0x00000200U)
+#define DSI_VHBPCCR_HBP10 ((uint32_t)0x00000400U)
+#define DSI_VHBPCCR_HBP11 ((uint32_t)0x00000800U)
+
+/******************* Bit definition for DSI_VLCCR register **************/
+#define DSI_VLCCR_HLINE ((uint32_t)0x00007FFFU) /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0 ((uint32_t)0x00000001U)
+#define DSI_VLCCR_HLINE1 ((uint32_t)0x00000002U)
+#define DSI_VLCCR_HLINE2 ((uint32_t)0x00000004U)
+#define DSI_VLCCR_HLINE3 ((uint32_t)0x00000008U)
+#define DSI_VLCCR_HLINE4 ((uint32_t)0x00000010U)
+#define DSI_VLCCR_HLINE5 ((uint32_t)0x00000020U)
+#define DSI_VLCCR_HLINE6 ((uint32_t)0x00000040U)
+#define DSI_VLCCR_HLINE7 ((uint32_t)0x00000080U)
+#define DSI_VLCCR_HLINE8 ((uint32_t)0x00000100U)
+#define DSI_VLCCR_HLINE9 ((uint32_t)0x00000200U)
+#define DSI_VLCCR_HLINE10 ((uint32_t)0x00000400U)
+#define DSI_VLCCR_HLINE11 ((uint32_t)0x00000800U)
+#define DSI_VLCCR_HLINE12 ((uint32_t)0x00001000U)
+#define DSI_VLCCR_HLINE13 ((uint32_t)0x00002000U)
+#define DSI_VLCCR_HLINE14 ((uint32_t)0x00004000U)
+
+/******************* Bit definition for DSI_VVSACCR register ***************/
+#define DSI_VVSACCR_VSA ((uint32_t)0x000003FFU) /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0 ((uint32_t)0x00000001U)
+#define DSI_VVSACCR_VSA1 ((uint32_t)0x00000002U)
+#define DSI_VVSACCR_VSA2 ((uint32_t)0x00000004U)
+#define DSI_VVSACCR_VSA3 ((uint32_t)0x00000008U)
+#define DSI_VVSACCR_VSA4 ((uint32_t)0x00000010U)
+#define DSI_VVSACCR_VSA5 ((uint32_t)0x00000020U)
+#define DSI_VVSACCR_VSA6 ((uint32_t)0x00000040U)
+#define DSI_VVSACCR_VSA7 ((uint32_t)0x00000080U)
+#define DSI_VVSACCR_VSA8 ((uint32_t)0x00000100U)
+#define DSI_VVSACCR_VSA9 ((uint32_t)0x00000200U)
+
+/******************* Bit definition for DSI_VVBPCCR register ************/
+#define DSI_VVBPCCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0 ((uint32_t)0x00000001U)
+#define DSI_VVBPCCR_VBP1 ((uint32_t)0x00000002U)
+#define DSI_VVBPCCR_VBP2 ((uint32_t)0x00000004U)
+#define DSI_VVBPCCR_VBP3 ((uint32_t)0x00000008U)
+#define DSI_VVBPCCR_VBP4 ((uint32_t)0x00000010U)
+#define DSI_VVBPCCR_VBP5 ((uint32_t)0x00000020U)
+#define DSI_VVBPCCR_VBP6 ((uint32_t)0x00000040U)
+#define DSI_VVBPCCR_VBP7 ((uint32_t)0x00000080U)
+#define DSI_VVBPCCR_VBP8 ((uint32_t)0x00000100U)
+#define DSI_VVBPCCR_VBP9 ((uint32_t)0x00000200U)
+
+/******************* Bit definition for DSI_VVFPCCR register ************/
+#define DSI_VVFPCCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0 ((uint32_t)0x00000001U)
+#define DSI_VVFPCCR_VFP1 ((uint32_t)0x00000002U)
+#define DSI_VVFPCCR_VFP2 ((uint32_t)0x00000004U)
+#define DSI_VVFPCCR_VFP3 ((uint32_t)0x00000008U)
+#define DSI_VVFPCCR_VFP4 ((uint32_t)0x00000010U)
+#define DSI_VVFPCCR_VFP5 ((uint32_t)0x00000020U)
+#define DSI_VVFPCCR_VFP6 ((uint32_t)0x00000040U)
+#define DSI_VVFPCCR_VFP7 ((uint32_t)0x00000080U)
+#define DSI_VVFPCCR_VFP8 ((uint32_t)0x00000100U)
+#define DSI_VVFPCCR_VFP9 ((uint32_t)0x00000200U)
+
+/******************* Bit definition for DSI_VVACCR register *************/
+#define DSI_VVACCR_VA ((uint32_t)0x00003FFFU) /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0 ((uint32_t)0x00000001U)
+#define DSI_VVACCR_VA1 ((uint32_t)0x00000002U)
+#define DSI_VVACCR_VA2 ((uint32_t)0x00000004U)
+#define DSI_VVACCR_VA3 ((uint32_t)0x00000008U)
+#define DSI_VVACCR_VA4 ((uint32_t)0x00000010U)
+#define DSI_VVACCR_VA5 ((uint32_t)0x00000020U)
+#define DSI_VVACCR_VA6 ((uint32_t)0x00000040U)
+#define DSI_VVACCR_VA7 ((uint32_t)0x00000080U)
+#define DSI_VVACCR_VA8 ((uint32_t)0x00000100U)
+#define DSI_VVACCR_VA9 ((uint32_t)0x00000200U)
+#define DSI_VVACCR_VA10 ((uint32_t)0x00000400U)
+#define DSI_VVACCR_VA11 ((uint32_t)0x00000800U)
+#define DSI_VVACCR_VA12 ((uint32_t)0x00001000U)
+#define DSI_VVACCR_VA13 ((uint32_t)0x00002000U)
+
+/******************* Bit definition for DSI_TDCCR register **************/
+#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
+#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U)
+#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U)
+
+#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
+#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U)
+#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U)
+
+#define DSI_TDCCR_SVS ((uint32_t)0x00000010U) /*!< Second VSYNC */
+#define DSI_TDCCR_RF ((uint32_t)0x00000020U) /*!< Right First */
+#define DSI_TDCCR_S3DC ((uint32_t)0x00010000U) /*!< Send 3D Control */
+
+/******************* Bit definition for DSI_WCFGR register ***************/
+#define DSI_WCFGR_DSIM ((uint32_t)0x00000001U) /*!< DSI Mode */
+
+#define DSI_WCFGR_COLMUX ((uint32_t)0x0000000EU) /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0 ((uint32_t)0x00000002U)
+#define DSI_WCFGR_COLMUX1 ((uint32_t)0x00000004U)
+#define DSI_WCFGR_COLMUX2 ((uint32_t)0x00000008U)
+
+#define DSI_WCFGR_TESRC ((uint32_t)0x00000010U) /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL ((uint32_t)0x00000020U) /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR ((uint32_t)0x00000040U) /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL ((uint32_t)0x00000080U) /*!< VSync Polarity */
+
+/******************* Bit definition for DSI_WCR register *****************/
+#define DSI_WCR_COLM ((uint32_t)0x00000001U) /*!< Color Mode */
+#define DSI_WCR_SHTDN ((uint32_t)0x00000002U) /*!< Shutdown */
+#define DSI_WCR_LTDCEN ((uint32_t)0x00000004U) /*!< LTDC Enable */
+#define DSI_WCR_DSIEN ((uint32_t)0x00000008U) /*!< DSI Enable */
+
+/******************* Bit definition for DSI_WIER register ****************/
+#define DSI_WIER_TEIE ((uint32_t)0x00000001U) /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE ((uint32_t)0x00000002U) /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE ((uint32_t)0x00000200U) /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE ((uint32_t)0x00000400U) /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE ((uint32_t)0x00002000U) /*!< Regulator Ready Interrupt Enable */
+
+/******************* Bit definition for DSI_WISR register ****************/
+#define DSI_WISR_TEIF ((uint32_t)0x00000001U) /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF ((uint32_t)0x00000002U) /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY ((uint32_t)0x00000004U) /*!< Busy Flag */
+#define DSI_WISR_PLLLS ((uint32_t)0x00000100U) /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF ((uint32_t)0x00000200U) /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF ((uint32_t)0x00000400U) /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS ((uint32_t)0x00001000U) /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF ((uint32_t)0x00002000U) /*!< Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WIFCR register ***************/
+#define DSI_WIFCR_CTEIF ((uint32_t)0x00000001U) /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF ((uint32_t)0x00000002U) /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF ((uint32_t)0x00000200U) /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF ((uint32_t)0x00000400U) /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF ((uint32_t)0x00002000U) /*!< Clear Regulator Ready Interrupt Flag */
+
+/******************* Bit definition for DSI_WPCR0 register ***************/
+#define DSI_WPCR0_UIX4 ((uint32_t)0x0000003FU) /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0 ((uint32_t)0x00000001U)
+#define DSI_WPCR0_UIX4_1 ((uint32_t)0x00000002U)
+#define DSI_WPCR0_UIX4_2 ((uint32_t)0x00000004U)
+#define DSI_WPCR0_UIX4_3 ((uint32_t)0x00000008U)
+#define DSI_WPCR0_UIX4_4 ((uint32_t)0x00000010U)
+#define DSI_WPCR0_UIX4_5 ((uint32_t)0x00000020U)
+
+#define DSI_WPCR0_SWCL ((uint32_t)0x00000040U) /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0 ((uint32_t)0x00000080U) /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1 ((uint32_t)0x00000100U) /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL ((uint32_t)0x00000200U) /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0 ((uint32_t)0x00000400U) /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1 ((uint32_t)0x00000800U) /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL ((uint32_t)0x00001000U) /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL ((uint32_t)0x00002000U) /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL ((uint32_t)0x00004000U) /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL ((uint32_t)0x00010000U) /*!< Turn Disable Data Lanes */
+
+/******************* Bit definition for DSI_WPCR1 register ***************/
+#define DSI_WPCR1_SKEWCL ((uint32_t)0x00000003U) /*!< Skew on Clock Lanes */
+#define DSI_WPCR1_SKEWCL0 ((uint32_t)0x00000001U)
+#define DSI_WPCR1_SKEWCL1 ((uint32_t)0x00000002U)
+
+#define DSI_WPCR1_SKEWDL ((uint32_t)0x0000000CU) /*!< Skew on Data Lanes */
+#define DSI_WPCR1_SKEWDL0 ((uint32_t)0x00000004U)
+#define DSI_WPCR1_SKEWDL1 ((uint32_t)0x00000008U)
+
+#define DSI_WPCR1_LPTXSRCL ((uint32_t)0x000000C0U) /*!< Low-Power TX Slew Rate on Clock Lanes */
+#define DSI_WPCR1_LPTXSRCL0 ((uint32_t)0x00000040U)
+#define DSI_WPCR1_LPTXSRCL1 ((uint32_t)0x00000080U)
+
+#define DSI_WPCR1_LPTXSRDL ((uint32_t)0x00000300U) /*!< Low-Power TX Slew Rate on Data Lanes */
+#define DSI_WPCR1_LPTXSRDL0 ((uint32_t)0x00000100U)
+#define DSI_WPCR1_LPTXSRDL1 ((uint32_t)0x00000200U)
+
+#define DSI_WPCR1_SDDCCL ((uint32_t)0x00001000U) /*!< SDD Control Clock Lane */
+#define DSI_WPCR1_SDDCDL ((uint32_t)0x00002000U) /*!< SDD Control Data Lanes */
+#define DSI_WPCR1_HSTXSRUCL ((uint32_t)0x00010000U) /*!< High-Speed TX Slew-Rate Up Clock Lane */
+#define DSI_WPCR1_HSTXSRDCL ((uint32_t)0x00020000U) /*!< High-Speed TX Slew-Rate Down Clock Lane */
+#define DSI_WPCR1_HSTXSRUDL ((uint32_t)0x00040000U) /*!< High-Speed TX Slew-Rate Up Data Lane */
+#define DSI_WPCR1_HSTXSRDDL ((uint32_t)0x00080000U) /*!< High-Speed TX Slew-Rate Down Data Lane */
+
+/******************* Bit definition for DSI_WRPCR register ***************/
+#define DSI_WRPCR_PLLEN ((uint32_t)0x00000001U) /*!< PLL Enable */
+
+#define DSI_WRPCR_PLL_NDIV ((uint32_t)0x000001FCU) /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0 ((uint32_t)0x00000004U)
+#define DSI_WRPCR_PLL_NDIV1 ((uint32_t)0x00000008U)
+#define DSI_WRPCR_PLL_NDIV2 ((uint32_t)0x00000010U)
+#define DSI_WRPCR_PLL_NDIV3 ((uint32_t)0x00000020U)
+#define DSI_WRPCR_PLL_NDIV4 ((uint32_t)0x00000040U)
+#define DSI_WRPCR_PLL_NDIV5 ((uint32_t)0x00000080U)
+#define DSI_WRPCR_PLL_NDIV6 ((uint32_t)0x00000100U)
+
+#define DSI_WRPCR_PLL_IDF ((uint32_t)0x00007800U) /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0 ((uint32_t)0x00000800U)
+#define DSI_WRPCR_PLL_IDF1 ((uint32_t)0x00001000U)
+#define DSI_WRPCR_PLL_IDF2 ((uint32_t)0x00002000U)
+#define DSI_WRPCR_PLL_IDF3 ((uint32_t)0x00004000U)
+
+#define DSI_WRPCR_PLL_ODF ((uint32_t)0x00030000U) /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0 ((uint32_t)0x00010000U)
+#define DSI_WRPCR_PLL_ODF1 ((uint32_t)0x00020000U)
+
+#define DSI_WRPCR_REGEN ((uint32_t)0x01000000U) /*!< Regulator Enable */
+
+#define DSI_WRPCR_BGREN ((uint32_t)0x10000000U) /*!< Bandgap Enable */
+
+/********************** Bit definition for DSI_HWCFGR register ***************/
+#define DSI_HWCFGR_TECHNO_Pos (0U)
+#define DSI_HWCFGR_TECHNO_Msk (0xFU << DSI_HWCFGR_TECHNO_Pos) /*!< 0x0000000F */
+#define DSI_HWCFGR_TECHNO DSI_HWCFGR_TECHNO_Msk /*!< Size of the payload FIFO */
+#define DSI_HWCFGR_FIFOSIZE_Pos (4U)
+#define DSI_HWCFGR_FIFOSIZE_Msk (0xFFFU << DSI_HWCFGR_FIFOSIZE_Pos) /*!< 0x0000FFF0 */
+#define DSI_HWCFGR_FIFOSIZE DSI_HWCFGR_FIFOSIZE_Msk /*!< Technology used. */
+
+
+/********************** Bit definition for DSI_VERR register *****************/
+#define DSI_VERR_MINREV_Pos (0U)
+#define DSI_VERR_MINREV_Msk (0xFU << DSI_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define DSI_VERR_MINREV DSI_VERR_MINREV_Msk /*!< Minor Revision number */
+#define DSI_VERR_MAJREV_Pos (4U)
+#define DSI_VERR_MAJREV_Msk (0xFU << DSI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define DSI_VERR_MAJREV DSI_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for DSI_IPIDR register ****************/
+#define DSI_IPIDR_IPID_Pos (0U)
+#define DSI_IPIDR_IPID_Msk (0xFFFFFFFFU << DSI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define DSI_IPIDR_IPID DSI_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for DSI_SIDR register *****************/
+#define DSI_SIDR_SID_Pos (0U)
+#define DSI_SIDR_SID_Msk (0xFFFFFFFFU << DSI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define DSI_SIDR_SID DSI_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR1 register *******************/
+#define EXTI_IMR1_IM0_Pos (0U)
+#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos (1U)
+#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos (2U)
+#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos (3U)
+#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos (4U)
+#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos (5U)
+#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos (6U)
+#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos (7U)
+#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos (8U)
+#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos (9U)
+#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos (10U)
+#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos (11U)
+#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos (12U)
+#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos (13U)
+#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos (14U)
+#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos (15U)
+#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos (16U)
+#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos (17U)
+#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos (18U)
+#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos (19U)
+#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos (20U)
+#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos (21U)
+#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos (22U)
+#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos (23U)
+#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos (24U)
+#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
+#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos (25U)
+#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos (26U)
+#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos (27U)
+#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
+#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos (28U)
+#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos (29U)
+#define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos (30U)
+#define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
+#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos (31U)
+#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
+#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
+/******************* Bit definition for EXTI_IMR2 register *******************/
+#define EXTI_IMR2_IM32_Pos (0U)
+#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
+#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos (1U)
+#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
+#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos (2U)
+#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
+#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos (3U)
+#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
+#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos (4U)
+#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
+#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos (5U)
+#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
+#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos (6U)
+#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
+#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos (7U)
+#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
+#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos (8U)
+#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
+#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos (9U)
+#define EXTI_IMR2_IM41_Msk (0x1U << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
+#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos (10U)
+#define EXTI_IMR2_IM42_Msk (0x1U << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
+#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos (11U)
+#define EXTI_IMR2_IM43_Msk (0x1U << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
+#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos (12U)
+#define EXTI_IMR2_IM44_Msk (0x1U << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
+#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM45_Pos (13U)
+#define EXTI_IMR2_IM45_Msk (0x1U << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
+#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */
+#define EXTI_IMR2_IM46_Pos (14U)
+#define EXTI_IMR2_IM46_Msk (0x1U << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
+#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos (15U)
+#define EXTI_IMR2_IM47_Msk (0x1U << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
+#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos (16U)
+#define EXTI_IMR2_IM48_Msk (0x1U << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
+#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos (17U)
+#define EXTI_IMR2_IM49_Msk (0x1U << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
+#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos (18U)
+#define EXTI_IMR2_IM50_Msk (0x1U << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
+#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos (19U)
+#define EXTI_IMR2_IM51_Msk (0x1U << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
+#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos (20U)
+#define EXTI_IMR2_IM52_Msk (0x1U << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
+#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos (21U)
+#define EXTI_IMR2_IM53_Msk (0x1U << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
+#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos (22U)
+#define EXTI_IMR2_IM54_Msk (0x1U << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
+#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos (23U)
+#define EXTI_IMR2_IM55_Msk (0x1U << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
+#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos (24U)
+#define EXTI_IMR2_IM56_Msk (0x1U << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
+#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos (25U)
+#define EXTI_IMR2_IM57_Msk (0x1U << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
+#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos (26U)
+#define EXTI_IMR2_IM58_Msk (0x1U << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
+#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM59_Pos (27U)
+#define EXTI_IMR2_IM59_Msk (0x1U << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
+#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
+#define EXTI_IMR2_IM60_Pos (28U)
+#define EXTI_IMR2_IM60_Msk (0x1U << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
+#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos (29U)
+#define EXTI_IMR2_IM61_Msk (0x1U << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
+#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos (30U)
+#define EXTI_IMR2_IM62_Msk (0x1U << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
+#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos (31U)
+#define EXTI_IMR2_IM63_Msk (0x1U << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
+#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
+/******************* Bit definition for EXTI_IMR3 register *******************/
+#define EXTI_IMR3_IM64_Pos (0U)
+#define EXTI_IMR3_IM64_Msk (0x1U << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
+#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos (1U)
+#define EXTI_IMR3_IM65_Msk (0x1U << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
+#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos (2U)
+#define EXTI_IMR3_IM66_Msk (0x1U << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
+#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
+#define EXTI_IMR3_IM67_Pos (3U)
+#define EXTI_IMR3_IM67_Msk (0x1U << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
+#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
+#define EXTI_IMR3_IM68_Pos (4U)
+#define EXTI_IMR3_IM68_Msk (0x1U << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
+#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos (5U)
+#define EXTI_IMR3_IM69_Msk (0x1U << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
+#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos (6U)
+#define EXTI_IMR3_IM70_Msk (0x1U << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
+#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos (7U)
+#define EXTI_IMR3_IM71_Msk (0x1U << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
+#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos (8U)
+#define EXTI_IMR3_IM72_Msk (0x1U << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
+#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos (9U)
+#define EXTI_IMR3_IM73_Msk (0x1U << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
+#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos (10U)
+#define EXTI_IMR3_IM74_Msk (0x1U << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
+#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM75_Pos (11U)
+#define EXTI_IMR3_IM75_Msk (0x1U << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
+#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
+#define EXTI_IMR3_IM76_Pos (12U)
+#define EXTI_IMR3_IM76_Msk (0x1U << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
+#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
+#define EXTI_IMR3_IM77_Pos (13U)
+#define EXTI_IMR3_IM77_Msk (0x1U << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
+#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM78_Pos (14U)
+#define EXTI_IMR3_IM78_Msk (0x1U << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
+#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
+#define EXTI_IMR3_IM79_Pos (15U)
+#define EXTI_IMR3_IM79_Msk (0x1U << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
+#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
+#define EXTI_IMR3_IM80_Pos (16U)
+#define EXTI_IMR3_IM80_Msk (0x1U << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
+#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
+#define EXTI_IMR3_IM81_Pos (17U)
+#define EXTI_IMR3_IM81_Msk (0x1U << EXTI_IMR3_IM81_Pos) /*!< 0x00020000 */
+#define EXTI_IMR3_IM81 EXTI_IMR3_IM81_Msk /*!< Interrupt Mask on line 81 */
+#define EXTI_IMR3_IM82_Pos (18U)
+#define EXTI_IMR3_IM82_Msk (0x1U << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
+#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
+#define EXTI_IMR3_IM84_Pos (20U)
+#define EXTI_IMR3_IM84_Msk (0x1U << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
+#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
+#define EXTI_IMR3_IM85_Pos (21U)
+#define EXTI_IMR3_IM85_Msk (0x1U << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
+#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
+#define EXTI_IMR3_IM86_Pos (22U)
+#define EXTI_IMR3_IM86_Msk (0x1U << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
+#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
+#define EXTI_IMR3_IM87_Pos (23U)
+#define EXTI_IMR3_IM87_Msk (0x1U << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
+#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
+#define EXTI_IMR3_IM88_Pos (24U)
+#define EXTI_IMR3_IM88_Msk (0x1U << EXTI_IMR3_IM88_Pos) /*!< 0x01000000 */
+#define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk /*!< Interrupt Mask on line 88 */
+/******************* Bit definition for EXTI_EMR1 register *******************/
+#define EXTI_EMR1_EM0_Pos (0U)
+#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos (1U)
+#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos (2U)
+#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos (3U)
+#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos (4U)
+#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos (5U)
+#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos (6U)
+#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos (7U)
+#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos (8U)
+#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos (9U)
+#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos (10U)
+#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos (11U)
+#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos (12U)
+#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos (13U)
+#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos (14U)
+#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos (15U)
+#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos (16U)
+#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos (17U)
+#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos (18U)
+#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM20_Pos (20U)
+#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos (21U)
+#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos (22U)
+#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos (23U)
+#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos (24U)
+#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
+#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos (25U)
+#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos (26U)
+#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos (27U)
+#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
+#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos (28U)
+#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos (29U)
+#define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos (30U)
+#define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
+#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos (31U)
+#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
+#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
+/******************* Bit definition for EXTI_EMR2 register *******************/
+#define EXTI_EMR2_EM32_Pos (0U)
+#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
+#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
+#define EXTI_EMR2_EM33_Pos (1U)
+#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
+#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
+#define EXTI_EMR2_EM34_Pos (2U)
+#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
+#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
+#define EXTI_EMR2_EM35_Pos (3U)
+#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
+#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
+#define EXTI_EMR2_EM36_Pos (4U)
+#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
+#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
+#define EXTI_EMR2_EM37_Pos (5U)
+#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
+#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
+#define EXTI_EMR2_EM38_Pos (6U)
+#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
+#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
+#define EXTI_EMR2_EM39_Pos (7U)
+#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
+#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
+#define EXTI_EMR2_EM40_Pos (8U)
+#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
+#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
+#define EXTI_EMR2_EM41_Pos (9U)
+#define EXTI_EMR2_EM41_Msk (0x1U << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
+#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
+#define EXTI_EMR2_EM42_Pos (10U)
+#define EXTI_EMR2_EM42_Msk (0x1U << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
+#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos (11U)
+#define EXTI_EMR2_EM43_Msk (0x1U << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
+#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos (12U)
+#define EXTI_EMR2_EM44_Msk (0x1U << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
+#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM45_Pos (13U)
+#define EXTI_EMR2_EM45_Msk (0x1U << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */
+#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */
+#define EXTI_EMR2_EM46_Pos (14U)
+#define EXTI_EMR2_EM46_Msk (0x1U << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
+#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos (15U)
+#define EXTI_EMR2_EM47_Msk (0x1U << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
+#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos (16U)
+#define EXTI_EMR2_EM48_Msk (0x1U << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
+#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos (17U)
+#define EXTI_EMR2_EM49_Msk (0x1U << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
+#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos (18U)
+#define EXTI_EMR2_EM50_Msk (0x1U << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
+#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos (19U)
+#define EXTI_EMR2_EM51_Msk (0x1U << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
+#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos (20U)
+#define EXTI_EMR2_EM52_Msk (0x1U << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
+#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos (21U)
+#define EXTI_EMR2_EM53_Msk (0x1U << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
+#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos (22U)
+#define EXTI_EMR2_EM54_Msk (0x1U << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
+#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos (23U)
+#define EXTI_EMR2_EM55_Msk (0x1U << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
+#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos (24U)
+#define EXTI_EMR2_EM56_Msk (0x1U << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
+#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos (25U)
+#define EXTI_EMR2_EM57_Msk (0x1U << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
+#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos (26U)
+#define EXTI_EMR2_EM58_Msk (0x1U << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
+#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM59_Pos (27U)
+#define EXTI_EMR2_EM59_Msk (0x1U << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
+#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
+#define EXTI_EMR2_EM60_Pos (28U)
+#define EXTI_EMR2_EM60_Msk (0x1U << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
+#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos (29U)
+#define EXTI_EMR2_EM61_Msk (0x1U << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
+#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos (30U)
+#define EXTI_EMR2_EM62_Msk (0x1U << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
+#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos (31U)
+#define EXTI_EMR2_EM63_Msk (0x1U << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
+#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
+/******************* Bit definition for EXTI_EMR3 register *******************/
+#define EXTI_EMR3_EM64_Pos (0U)
+#define EXTI_EMR3_EM64_Msk (0x1U << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
+#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
+#define EXTI_EMR3_EM65_Pos (1U)
+#define EXTI_EMR3_EM65_Msk (0x1U << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
+#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
+#define EXTI_EMR3_EM66_Pos (2U)
+#define EXTI_EMR3_EM66_Msk (0x1U << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
+#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
+#define EXTI_EMR3_EM67_Pos (3U)
+#define EXTI_EMR3_EM67_Msk (0x1U << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
+#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
+#define EXTI_EMR3_EM68_Pos (4U)
+#define EXTI_EMR3_EM68_Msk (0x1U << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
+#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
+#define EXTI_EMR3_EM69_Pos (5U)
+#define EXTI_EMR3_EM69_Msk (0x1U << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
+#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
+#define EXTI_EMR3_EM70_Pos (6U)
+#define EXTI_EMR3_EM70_Msk (0x1U << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
+#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
+#define EXTI_EMR3_EM71_Pos (7U)
+#define EXTI_EMR3_EM71_Msk (0x1U << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
+#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
+#define EXTI_EMR3_EM72_Pos (8U)
+#define EXTI_EMR3_EM72_Msk (0x1U << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
+#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
+#define EXTI_EMR3_EM73_Pos (9U)
+#define EXTI_EMR3_EM73_Msk (0x1U << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
+#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
+#define EXTI_EMR3_EM74_Pos (10U)
+#define EXTI_EMR3_EM74_Msk (0x1U << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
+#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM75_Pos (11U)
+#define EXTI_EMR3_EM75_Msk (0x1U << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
+#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
+#define EXTI_EMR3_EM76_Pos (12U)
+#define EXTI_EMR3_EM76_Msk (0x1U << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
+#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
+#define EXTI_EMR3_EM77_Pos (13U)
+#define EXTI_EMR3_EM77_Msk (0x1U << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
+#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM78_Pos (14U)
+#define EXTI_EMR3_EM78_Msk (0x1U << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
+#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
+#define EXTI_EMR3_EM79_Pos (15U)
+#define EXTI_EMR3_EM79_Msk (0x1U << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
+#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
+#define EXTI_EMR3_EM80_Pos (16U)
+#define EXTI_EMR3_EM80_Msk (0x1U << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
+#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
+#define EXTI_EMR3_EM81_Pos (17U)
+#define EXTI_EMR3_EM81_Msk (0x1U << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
+#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
+#define EXTI_EMR3_EM82_Pos (18U)
+#define EXTI_EMR3_EM82_Msk (0x1U << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
+#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
+#define EXTI_EMR3_EM84_Pos (20U)
+#define EXTI_EMR3_EM84_Msk (0x1U << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
+#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
+#define EXTI_EMR3_EM85_Pos (21U)
+#define EXTI_EMR3_EM85_Msk (0x1U << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
+#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
+#define EXTI_EMR3_EM86_Pos (22U)
+#define EXTI_EMR3_EM86_Msk (0x1U << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
+#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
+#define EXTI_EMR3_EM87_Pos (23U)
+#define EXTI_EMR3_EM87_Msk (0x1U << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
+#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
+#define EXTI_EMR3_EM88_Pos (24U)
+#define EXTI_EMR3_EM88_Msk (0x1U << EXTI_EMR3_EM88_Pos) /*!< 0x01000000 */
+#define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk /*!< Event Mask on line 88 */
+/****************** Bit definition for EXTI_RTSR1 register *******************/
+#define EXTI_RTSR1_TR0_Pos (0U)
+#define EXTI_RTSR1_TR0_Msk (0x1U << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_TR1_Pos (1U)
+#define EXTI_RTSR1_TR1_Msk (0x1U << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_TR2_Pos (2U)
+#define EXTI_RTSR1_TR2_Msk (0x1U << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_TR3_Pos (3U)
+#define EXTI_RTSR1_TR3_Msk (0x1U << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_TR4_Pos (4U)
+#define EXTI_RTSR1_TR4_Msk (0x1U << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_TR5_Pos (5U)
+#define EXTI_RTSR1_TR5_Msk (0x1U << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_TR6_Pos (6U)
+#define EXTI_RTSR1_TR6_Msk (0x1U << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_TR7_Pos (7U)
+#define EXTI_RTSR1_TR7_Msk (0x1U << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_TR8_Pos (8U)
+#define EXTI_RTSR1_TR8_Msk (0x1U << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_TR9_Pos (9U)
+#define EXTI_RTSR1_TR9_Msk (0x1U << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_TR10_Pos (10U)
+#define EXTI_RTSR1_TR10_Msk (0x1U << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_TR11_Pos (11U)
+#define EXTI_RTSR1_TR11_Msk (0x1U << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_TR12_Pos (12U)
+#define EXTI_RTSR1_TR12_Msk (0x1U << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_TR13_Pos (13U)
+#define EXTI_RTSR1_TR13_Msk (0x1U << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_TR14_Pos (14U)
+#define EXTI_RTSR1_TR14_Msk (0x1U << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_TR15_Pos (15U)
+#define EXTI_RTSR1_TR15_Msk (0x1U << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_TR16_Pos (16U)
+#define EXTI_RTSR1_TR16_Msk (0x1U << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_TR17_Pos (17U)
+#define EXTI_RTSR1_TR17_Msk (0x1U << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_TR18_Pos (18U)
+#define EXTI_RTSR1_TR18_Msk (0x1U << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_TR19_Pos (19U)
+#define EXTI_RTSR1_TR19_Msk (0x1U << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_TR20_Pos (20U)
+#define EXTI_RTSR1_TR20_Msk (0x1U << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_TR21_Pos (21U)
+#define EXTI_RTSR1_TR21_Msk (0x1U << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
+/****************** Bit definition for EXTI_RTSR2 register *******************/
+#define EXTI_RTSR2_TR49_Pos (17U)
+#define EXTI_RTSR2_TR49_Msk (0x1U << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
+#define EXTI_RTSR2_TR51_Pos (19U)
+#define EXTI_RTSR2_TR51_Msk (0x1U << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
+/****************** Bit definition for EXTI_RTSR3 register *******************/
+#define EXTI_RTSR3_TR85_Pos (21U)
+#define EXTI_RTSR3_TR85_Msk (0x1U << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
+#define EXTI_RTSR3_TR86_Pos (22U)
+#define EXTI_RTSR3_TR86_Msk (0x1U << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
+
+/****************** Bit definition for EXTI_FTSR1 register *******************/
+#define EXTI_FTSR1_TR0_Pos (0U)
+#define EXTI_FTSR1_TR0_Msk (0x1U << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_TR1_Pos (1U)
+#define EXTI_FTSR1_TR1_Msk (0x1U << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_TR2_Pos (2U)
+#define EXTI_FTSR1_TR2_Msk (0x1U << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_TR3_Pos (3U)
+#define EXTI_FTSR1_TR3_Msk (0x1U << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_TR4_Pos (4U)
+#define EXTI_FTSR1_TR4_Msk (0x1U << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_TR5_Pos (5U)
+#define EXTI_FTSR1_TR5_Msk (0x1U << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_TR6_Pos (6U)
+#define EXTI_FTSR1_TR6_Msk (0x1U << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_TR7_Pos (7U)
+#define EXTI_FTSR1_TR7_Msk (0x1U << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_TR8_Pos (8U)
+#define EXTI_FTSR1_TR8_Msk (0x1U << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_TR9_Pos (9U)
+#define EXTI_FTSR1_TR9_Msk (0x1U << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_TR10_Pos (10U)
+#define EXTI_FTSR1_TR10_Msk (0x1U << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_TR11_Pos (11U)
+#define EXTI_FTSR1_TR11_Msk (0x1U << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_TR12_Pos (12U)
+#define EXTI_FTSR1_TR12_Msk (0x1U << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_TR13_Pos (13U)
+#define EXTI_FTSR1_TR13_Msk (0x1U << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_TR14_Pos (14U)
+#define EXTI_FTSR1_TR14_Msk (0x1U << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_TR15_Pos (15U)
+#define EXTI_FTSR1_TR15_Msk (0x1U << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_TR16_Pos (16U)
+#define EXTI_FTSR1_TR16_Msk (0x1U << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_TR17_Pos (17U)
+#define EXTI_FTSR1_TR17_Msk (0x1U << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_TR18_Pos (18U)
+#define EXTI_FTSR1_TR18_Msk (0x1U << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
+#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_TR19_Pos (19U)
+#define EXTI_FTSR1_TR19_Msk (0x1U << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_TR20_Pos (20U)
+#define EXTI_FTSR1_TR20_Msk (0x1U << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_TR21_Pos (21U)
+#define EXTI_FTSR1_TR21_Msk (0x1U << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
+/****************** Bit definition for EXTI_FTSR2 register *******************/
+#define EXTI_FTSR2_TR49_Pos (17U)
+#define EXTI_FTSR2_TR49_Msk (0x1U << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
+#define EXTI_FTSR2_TR51_Pos (19U)
+#define EXTI_FTSR2_TR51_Msk (0x1U << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
+
+/****************** Bit definition for EXTI_FTSR3 register *******************/
+#define EXTI_FTSR3_TR85_Pos (21U)
+#define EXTI_FTSR3_TR85_Msk (0x1U << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
+#define EXTI_FTSR3_TR86_Pos (22U)
+#define EXTI_FTSR3_TR86_Msk (0x1U << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
+/****************** Bit definition for EXTI_SWIER1 register ******************/
+#define EXTI_SWIER1_SWIER0_Pos (0U)
+#define EXTI_SWIER1_SWIER0_Msk (0x1U << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWIER1_Pos (1U)
+#define EXTI_SWIER1_SWIER1_Msk (0x1U << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWIER2_Pos (2U)
+#define EXTI_SWIER1_SWIER2_Msk (0x1U << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWIER3_Pos (3U)
+#define EXTI_SWIER1_SWIER3_Msk (0x1U << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWIER4_Pos (4U)
+#define EXTI_SWIER1_SWIER4_Msk (0x1U << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWIER5_Pos (5U)
+#define EXTI_SWIER1_SWIER5_Msk (0x1U << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWIER6_Pos (6U)
+#define EXTI_SWIER1_SWIER6_Msk (0x1U << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWIER7_Pos (7U)
+#define EXTI_SWIER1_SWIER7_Msk (0x1U << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWIER8_Pos (8U)
+#define EXTI_SWIER1_SWIER8_Msk (0x1U << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWIER9_Pos (9U)
+#define EXTI_SWIER1_SWIER9_Msk (0x1U << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWIER10_Pos (10U)
+#define EXTI_SWIER1_SWIER10_Msk (0x1U << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWIER11_Pos (11U)
+#define EXTI_SWIER1_SWIER11_Msk (0x1U << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWIER12_Pos (12U)
+#define EXTI_SWIER1_SWIER12_Msk (0x1U << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWIER13_Pos (13U)
+#define EXTI_SWIER1_SWIER13_Msk (0x1U << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWIER14_Pos (14U)
+#define EXTI_SWIER1_SWIER14_Msk (0x1U << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWIER15_Pos (15U)
+#define EXTI_SWIER1_SWIER15_Msk (0x1U << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWIER16_Pos (16U)
+#define EXTI_SWIER1_SWIER16_Msk (0x1U << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWIER17_Pos (17U)
+#define EXTI_SWIER1_SWIER17_Msk (0x1U << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWIER18_Pos (18U)
+#define EXTI_SWIER1_SWIER18_Msk (0x1U << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
+#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWIER19_Pos (19U)
+#define EXTI_SWIER1_SWIER19_Msk (0x1U << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWIER20_Pos (20U)
+#define EXTI_SWIER1_SWIER20_Msk (0x1U << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWIER21_Pos (21U)
+#define EXTI_SWIER1_SWIER21_Msk (0x1U << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
+
+/****************** Bit definition for EXTI_SWIER2 register ******************/
+#define EXTI_SWIER2_SWIER49_Pos (17U)
+#define EXTI_SWIER2_SWIER49_Msk (0x1U << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
+#define EXTI_SWIER2_SWIER51_Pos (19U)
+#define EXTI_SWIER2_SWIER51_Msk (0x1U << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
+
+/****************** Bit definition for EXTI_SWIER3 register ******************/
+#define EXTI_SWIER3_SWIER85_Pos (21U)
+#define EXTI_SWIER3_SWIER85_Msk (0x1U << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
+#define EXTI_SWIER3_SWIER86_Pos (22U)
+#define EXTI_SWIER3_SWIER86_Msk (0x1U << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
+
+/******************* Bit definition for EXTI_PR1 register ********************/
+#define EXTI_PR1_PR0_Pos (0U)
+#define EXTI_PR1_PR0_Msk (0x1U << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
+#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
+#define EXTI_PR1_PR1_Pos (1U)
+#define EXTI_PR1_PR1_Msk (0x1U << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
+#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
+#define EXTI_PR1_PR2_Pos (2U)
+#define EXTI_PR1_PR2_Msk (0x1U << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
+#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
+#define EXTI_PR1_PR3_Pos (3U)
+#define EXTI_PR1_PR3_Msk (0x1U << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
+#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
+#define EXTI_PR1_PR4_Pos (4U)
+#define EXTI_PR1_PR4_Msk (0x1U << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
+#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
+#define EXTI_PR1_PR5_Pos (5U)
+#define EXTI_PR1_PR5_Msk (0x1U << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
+#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
+#define EXTI_PR1_PR6_Pos (6U)
+#define EXTI_PR1_PR6_Msk (0x1U << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
+#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
+#define EXTI_PR1_PR7_Pos (7U)
+#define EXTI_PR1_PR7_Msk (0x1U << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
+#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
+#define EXTI_PR1_PR8_Pos (8U)
+#define EXTI_PR1_PR8_Msk (0x1U << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
+#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
+#define EXTI_PR1_PR9_Pos (9U)
+#define EXTI_PR1_PR9_Msk (0x1U << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
+#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
+#define EXTI_PR1_PR10_Pos (10U)
+#define EXTI_PR1_PR10_Msk (0x1U << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
+#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
+#define EXTI_PR1_PR11_Pos (11U)
+#define EXTI_PR1_PR11_Msk (0x1U << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
+#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
+#define EXTI_PR1_PR12_Pos (12U)
+#define EXTI_PR1_PR12_Msk (0x1U << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
+#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
+#define EXTI_PR1_PR13_Pos (13U)
+#define EXTI_PR1_PR13_Msk (0x1U << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
+#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
+#define EXTI_PR1_PR14_Pos (14U)
+#define EXTI_PR1_PR14_Msk (0x1U << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
+#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
+#define EXTI_PR1_PR15_Pos (15U)
+#define EXTI_PR1_PR15_Msk (0x1U << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
+#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
+#define EXTI_PR1_PR16_Pos (16U)
+#define EXTI_PR1_PR16_Msk (0x1U << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
+#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
+
+/******************* Bit definition for EXTI_PR3 register ********************/
+#define EXTI_PR3_PR65_Pos (1U)
+#define EXTI_PR3_PR65_Msk (0x1U << EXTI_PR3_PR65_Pos) /*!< 0x00000002 */
+#define EXTI_PR3_PR65 EXTI_PR3_PR65_Msk /*!< Pending bit for line 65 */
+#define EXTI_PR3_PR66_Pos (2U)
+#define EXTI_PR3_PR66_Msk (0x1U << EXTI_PR3_PR66_Pos) /*!< 0x00000004 */
+#define EXTI_PR3_PR66 EXTI_PR3_PR66_Msk /*!< Pending bit for line 66 */
+#define EXTI_PR3_PR68_Pos (4U)
+#define EXTI_PR3_PR68_Msk (0x1U << EXTI_PR3_PR68_Pos) /*!< 0x00000010 */
+#define EXTI_PR3_PR68 EXTI_PR3_PR68_Msk /*!< Pending bit for line 68 */
+#define EXTI_PR3_PR73_Pos (9U)
+#define EXTI_PR3_PR73_Msk (0x1U << EXTI_PR3_PR73_Pos) /*!< 0x00000200 */
+#define EXTI_PR3_PR73 EXTI_PR3_PR73_Msk /*!< Pending bit for line 73 */
+#define EXTI_PR3_PR74_Pos (10U)
+#define EXTI_PR3_PR74_Msk (0x1U << EXTI_PR3_PR74_Pos) /*!< 0x00000400 */
+#define EXTI_PR3_PR74 EXTI_PR3_PR74_Msk /*!< Pending bit for line 74 */
+
+/***************** Bit definition for EXTI_EXTICR1 register ***************/
+#define EXTI_EXTICR1_EXTI0_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_Msk (0x0FU << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
+#define EXTI_EXTICR1_EXTI1_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_Msk (0x0FU << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000F00 */
+#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
+#define EXTI_EXTICR1_EXTI2_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_Msk (0x0FU << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x000F0000 */
+#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
+#define EXTI_EXTICR1_EXTI3_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_Msk (0x0FU << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x0F000000 */
+#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
+/**
+ * @brief EXTI0 configuration
+ */
+#define EXTI_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
+#define EXTI_EXTICR1_EXTI0_PB_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_PB_Msk (0x1U << EXTI_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR1_EXTI0_PB EXTI_EXTICR1_EXTI0_PB_Msk /*!<PB[0] pin */
+#define EXTI_EXTICR1_EXTI0_PC_Pos (1U)
+#define EXTI_EXTICR1_EXTI0_PC_Msk (0x1U << EXTI_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR1_EXTI0_PC EXTI_EXTICR1_EXTI0_PC_Msk /*!<PC[0] pin */
+#define EXTI_EXTICR1_EXTI0_PD_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_PD_Msk (0x3U << EXTI_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
+#define EXTI_EXTICR1_EXTI0_PD EXTI_EXTICR1_EXTI0_PD_Msk /*!<PD[0] pin */
+#define EXTI_EXTICR1_EXTI0_PE_Pos (2U)
+#define EXTI_EXTICR1_EXTI0_PE_Msk (0x1U << EXTI_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR1_EXTI0_PE EXTI_EXTICR1_EXTI0_PE_Msk /*!<PE[0] pin */
+#define EXTI_EXTICR1_EXTI0_PF_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_PF_Msk (0x5U << EXTI_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
+#define EXTI_EXTICR1_EXTI0_PF EXTI_EXTICR1_EXTI0_PF_Msk /*!<PF[0] pin */
+#define EXTI_EXTICR1_EXTI0_PG_Pos (1U)
+#define EXTI_EXTICR1_EXTI0_PG_Msk (0x3U << EXTI_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
+#define EXTI_EXTICR1_EXTI0_PG EXTI_EXTICR1_EXTI0_PG_Msk /*!<PG[0] pin */
+#define EXTI_EXTICR1_EXTI0_PH_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_PH_Msk (0x7U << EXTI_EXTICR1_EXTI0_PH_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR1_EXTI0_PH EXTI_EXTICR1_EXTI0_PH_Msk /*!<PH[0] pin */
+#define EXTI_EXTICR1_EXTI0_PI_Pos (3U)
+#define EXTI_EXTICR1_EXTI0_PI_Msk (0x1U << EXTI_EXTICR1_EXTI0_PI_Pos) /*!< 0x00000008 */
+#define EXTI_EXTICR1_EXTI0_PI EXTI_EXTICR1_EXTI0_PI_Msk /*!<PI[0] pin */
+#define EXTI_EXTICR1_EXTI0_PJ_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI0_PJ_Pos) /*!< 0x00000009 */
+#define EXTI_EXTICR1_EXTI0_PJ EXTI_EXTICR1_EXTI0_PJ_Msk /*!<PJ[0] pin */
+#define EXTI_EXTICR1_EXTI0_PK_Pos (1U)
+#define EXTI_EXTICR1_EXTI0_PK_Msk (0x5U << EXTI_EXTICR1_EXTI0_PK_Pos) /*!< 0x0000000A */
+#define EXTI_EXTICR1_EXTI0_PK EXTI_EXTICR1_EXTI0_PK_Msk /*!<PK[0] pin */
+#define EXTI_EXTICR1_EXTI0_PZ_Pos (0U)
+#define EXTI_EXTICR1_EXTI0_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI0_PZ_Pos) /*!< 0x0000000B */
+#define EXTI_EXTICR1_EXTI0_PZ EXTI_EXTICR1_EXTI0_PZ_Msk /*!<PZ[0] pin */
+
+
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define EXTI_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
+#define EXTI_EXTICR1_EXTI1_PB_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_PB_Msk (0x1U << EXTI_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR1_EXTI1_PB EXTI_EXTICR1_EXTI1_PB_Msk /*!<PB[1] pin */
+#define EXTI_EXTICR1_EXTI1_PC_Pos (9U)
+#define EXTI_EXTICR1_EXTI1_PC_Msk (0x1U << EXTI_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR1_EXTI1_PC EXTI_EXTICR1_EXTI1_PC_Msk /*!<PC[1] pin */
+#define EXTI_EXTICR1_EXTI1_PD_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_PD_Msk (0x3U << EXTI_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000300 */
+#define EXTI_EXTICR1_EXTI1_PD EXTI_EXTICR1_EXTI1_PD_Msk /*!<PD[1] pin */
+#define EXTI_EXTICR1_EXTI1_PE_Pos (10U)
+#define EXTI_EXTICR1_EXTI1_PE_Msk (0x1U << EXTI_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR1_EXTI1_PE EXTI_EXTICR1_EXTI1_PE_Msk /*!<PE[1] pin */
+#define EXTI_EXTICR1_EXTI1_PF_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_PF_Msk (0x5U << EXTI_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000500 */
+#define EXTI_EXTICR1_EXTI1_PF EXTI_EXTICR1_EXTI1_PF_Msk /*!<PF[1] pin */
+#define EXTI_EXTICR1_EXTI1_PG_Pos (9U)
+#define EXTI_EXTICR1_EXTI1_PG_Msk (0x3U << EXTI_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000600 */
+#define EXTI_EXTICR1_EXTI1_PG EXTI_EXTICR1_EXTI1_PG_Msk /*!<PG[1] pin */
+#define EXTI_EXTICR1_EXTI1_PH_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_PH_Msk (0x7U << EXTI_EXTICR1_EXTI1_PH_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR1_EXTI1_PH EXTI_EXTICR1_EXTI1_PH_Msk /*!<PH[1] pin */
+#define EXTI_EXTICR1_EXTI1_PI_Pos (11U)
+#define EXTI_EXTICR1_EXTI1_PI_Msk (0x1U << EXTI_EXTICR1_EXTI1_PI_Pos) /*!< 0x00000800 */
+#define EXTI_EXTICR1_EXTI1_PI EXTI_EXTICR1_EXTI1_PI_Msk /*!<PI[1] pin */
+#define EXTI_EXTICR1_EXTI1_PJ_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI1_PJ_Pos) /*!< 0x00000900 */
+#define EXTI_EXTICR1_EXTI1_PJ EXTI_EXTICR1_EXTI1_PJ_Msk /*!<PJ[1] pin */
+#define EXTI_EXTICR1_EXTI1_PK_Pos (9U)
+#define EXTI_EXTICR1_EXTI1_PK_Msk (0x5U << EXTI_EXTICR1_EXTI1_PK_Pos) /*!< 0x00000A00 */
+#define EXTI_EXTICR1_EXTI1_PK EXTI_EXTICR1_EXTI1_PK_Msk /*!<PK[1] pin */
+#define EXTI_EXTICR1_EXTI1_PZ_Pos (8U)
+#define EXTI_EXTICR1_EXTI1_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI1_PZ_Pos) /*!< 0x00000B00 */
+#define EXTI_EXTICR1_EXTI1_PZ EXTI_EXTICR1_EXTI1_PZ_Msk /*!<PZ[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define EXTI_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
+#define EXTI_EXTICR1_EXTI2_PB_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_PB_Msk (0x1U << EXTI_EXTICR1_EXTI2_PB_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR1_EXTI2_PB EXTI_EXTICR1_EXTI2_PB_Msk /*!<PB[2] pin */
+#define EXTI_EXTICR1_EXTI2_PC_Pos (17U)
+#define EXTI_EXTICR1_EXTI2_PC_Msk (0x1U << EXTI_EXTICR1_EXTI2_PC_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR1_EXTI2_PC EXTI_EXTICR1_EXTI2_PC_Msk /*!<PC[2] pin */
+#define EXTI_EXTICR1_EXTI2_PD_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_PD_Msk (0x3U << EXTI_EXTICR1_EXTI2_PD_Pos) /*!< 0x00030000 */
+#define EXTI_EXTICR1_EXTI2_PD EXTI_EXTICR1_EXTI2_PD_Msk /*!<PD[2] pin */
+#define EXTI_EXTICR1_EXTI2_PE_Pos (18U)
+#define EXTI_EXTICR1_EXTI2_PE_Msk (0x1U << EXTI_EXTICR1_EXTI2_PE_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR1_EXTI2_PE EXTI_EXTICR1_EXTI2_PE_Msk /*!<PE[2] pin */
+#define EXTI_EXTICR1_EXTI2_PF_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_PF_Msk (0x5U << EXTI_EXTICR1_EXTI2_PF_Pos) /*!< 0x00050000 */
+#define EXTI_EXTICR1_EXTI2_PF EXTI_EXTICR1_EXTI2_PF_Msk /*!<PF[2] pin */
+#define EXTI_EXTICR1_EXTI2_PG_Pos (17U)
+#define EXTI_EXTICR1_EXTI2_PG_Msk (0x3U << EXTI_EXTICR1_EXTI2_PG_Pos) /*!< 0x00060000 */
+#define EXTI_EXTICR1_EXTI2_PG EXTI_EXTICR1_EXTI2_PG_Msk /*!<PG[2] pin */
+#define EXTI_EXTICR1_EXTI2_PH_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_PH_Msk (0x7U << EXTI_EXTICR1_EXTI2_PH_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR1_EXTI2_PH EXTI_EXTICR1_EXTI2_PH_Msk /*!<PH[2] pin */
+#define EXTI_EXTICR1_EXTI2_PI_Pos (19U)
+#define EXTI_EXTICR1_EXTI2_PI_Msk (0x1U << EXTI_EXTICR1_EXTI2_PI_Pos) /*!< 0x00080000 */
+#define EXTI_EXTICR1_EXTI2_PI EXTI_EXTICR1_EXTI2_PI_Msk /*!<PI[2] pin */
+#define EXTI_EXTICR1_EXTI2_PJ_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI2_PJ_Pos) /*!< 0x00090000 */
+#define EXTI_EXTICR1_EXTI2_PJ EXTI_EXTICR1_EXTI2_PJ_Msk /*!<PJ[2] pin */
+#define EXTI_EXTICR1_EXTI2_PK_Pos (17U)
+#define EXTI_EXTICR1_EXTI2_PK_Msk (0x5U << EXTI_EXTICR1_EXTI2_PK_Pos) /*!< 0x000A0000 */
+#define EXTI_EXTICR1_EXTI2_PK EXTI_EXTICR1_EXTI2_PK_Msk /*!<PK[2] pin */
+#define EXTI_EXTICR1_EXTI2_PZ_Pos (16U)
+#define EXTI_EXTICR1_EXTI2_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI2_PZ_Pos) /*!< 0x000B0000 */
+#define EXTI_EXTICR1_EXTI2_PZ EXTI_EXTICR1_EXTI2_PZ_Msk /*!<PZ[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define EXTI_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
+#define EXTI_EXTICR1_EXTI3_PB_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_PB_Msk (0x1U << EXTI_EXTICR1_EXTI3_PB_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR1_EXTI3_PB EXTI_EXTICR1_EXTI3_PB_Msk /*!<PB[3] pin */
+#define EXTI_EXTICR1_EXTI3_PC_Pos (25U)
+#define EXTI_EXTICR1_EXTI3_PC_Msk (0x1U << EXTI_EXTICR1_EXTI3_PC_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR1_EXTI3_PC EXTI_EXTICR1_EXTI3_PC_Msk /*!<PC[3] pin */
+#define EXTI_EXTICR1_EXTI3_PD_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_PD_Msk (0x3U << EXTI_EXTICR1_EXTI3_PD_Pos) /*!< 0x03000000 */
+#define EXTI_EXTICR1_EXTI3_PD EXTI_EXTICR1_EXTI3_PD_Msk /*!<PD[3] pin */
+#define EXTI_EXTICR1_EXTI3_PE_Pos (26U)
+#define EXTI_EXTICR1_EXTI3_PE_Msk (0x1U << EXTI_EXTICR1_EXTI3_PE_Pos) /*!< 0x04000000 */
+#define EXTI_EXTICR1_EXTI3_PE EXTI_EXTICR1_EXTI3_PE_Msk /*!<PE[3] pin */
+#define EXTI_EXTICR1_EXTI3_PF_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_PF_Msk (0x5U << EXTI_EXTICR1_EXTI3_PF_Pos) /*!< 0x05000000 */
+#define EXTI_EXTICR1_EXTI3_PF EXTI_EXTICR1_EXTI3_PF_Msk /*!<PF[3] pin */
+#define EXTI_EXTICR1_EXTI3_PG_Pos (25U)
+#define EXTI_EXTICR1_EXTI3_PG_Msk (0x3U << EXTI_EXTICR1_EXTI3_PG_Pos) /*!< 0x06000000 */
+#define EXTI_EXTICR1_EXTI3_PG EXTI_EXTICR1_EXTI3_PG_Msk /*!<PG[3] pin */
+#define EXTI_EXTICR1_EXTI3_PH_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_PH_Msk (0x7U << EXTI_EXTICR1_EXTI3_PH_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR1_EXTI3_PH EXTI_EXTICR1_EXTI3_PH_Msk /*!<PH[3] pin */
+#define EXTI_EXTICR1_EXTI3_PI_Pos (27U)
+#define EXTI_EXTICR1_EXTI3_PI_Msk (0x1U << EXTI_EXTICR1_EXTI3_PI_Pos) /*!< 0x08000000 */
+#define EXTI_EXTICR1_EXTI3_PI EXTI_EXTICR1_EXTI3_PI_Msk /*!<PI[3] pin */
+#define EXTI_EXTICR1_EXTI3_PJ_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI3_PJ_Pos) /*!< 0x09000000 */
+#define EXTI_EXTICR1_EXTI3_PJ EXTI_EXTICR1_EXTI3_PJ_Msk /*!<PJ[3] pin */
+#define EXTI_EXTICR1_EXTI3_PK_Pos (25U)
+#define EXTI_EXTICR1_EXTI3_PK_Msk (0x5U << EXTI_EXTICR1_EXTI3_PK_Pos) /*!< 0x0A000000 */
+#define EXTI_EXTICR1_EXTI3_PK EXTI_EXTICR1_EXTI3_PK_Msk /*!<PK[3] pin */
+#define EXTI_EXTICR1_EXTI3_PZ_Pos (24U)
+#define EXTI_EXTICR1_EXTI3_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI3_PZ_Pos) /*!< 0x0B000000 */
+#define EXTI_EXTICR1_EXTI3_PZ EXTI_EXTICR1_EXTI3_PZ_Msk /*!<PZ[3] pin */
+
+
+/***************** Bit definition for EXTI_EXTICR2 register ***************/
+#define EXTI_EXTICR2_EXTI4_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_Msk (0x0FU << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000F */
+#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
+#define EXTI_EXTICR2_EXTI5_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_Msk (0x0FU << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000F00 */
+#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
+#define EXTI_EXTICR2_EXTI6_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_Msk (0x0FU << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x000F0000 */
+#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
+#define EXTI_EXTICR2_EXTI7_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_Msk (0x0FU << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x0F000000 */
+#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define EXTI_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
+#define EXTI_EXTICR2_EXTI4_PB_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_PB_Msk (0x1U << EXTI_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR2_EXTI4_PB EXTI_EXTICR2_EXTI4_PB_Msk /*!<PB[4] pin */
+#define EXTI_EXTICR2_EXTI4_PC_Pos (1U)
+#define EXTI_EXTICR2_EXTI4_PC_Msk (0x1U << EXTI_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR2_EXTI4_PC EXTI_EXTICR2_EXTI4_PC_Msk /*!<PC[4] pin */
+#define EXTI_EXTICR2_EXTI4_PD_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_PD_Msk (0x3U << EXTI_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
+#define EXTI_EXTICR2_EXTI4_PD EXTI_EXTICR2_EXTI4_PD_Msk /*!<PD[4] pin */
+#define EXTI_EXTICR2_EXTI4_PE_Pos (2U)
+#define EXTI_EXTICR2_EXTI4_PE_Msk (0x1U << EXTI_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR2_EXTI4_PE EXTI_EXTICR2_EXTI4_PE_Msk /*!<PE[4] pin */
+#define EXTI_EXTICR2_EXTI4_PF_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_PF_Msk (0x5U << EXTI_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
+#define EXTI_EXTICR2_EXTI4_PF EXTI_EXTICR2_EXTI4_PF_Msk /*!<PF[4] pin */
+#define EXTI_EXTICR2_EXTI4_PG_Pos (1U)
+#define EXTI_EXTICR2_EXTI4_PG_Msk (0x3U << EXTI_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
+#define EXTI_EXTICR2_EXTI4_PG EXTI_EXTICR2_EXTI4_PG_Msk /*!<PG[4] pin */
+#define EXTI_EXTICR2_EXTI4_PH_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_PH_Msk (0x7U << EXTI_EXTICR2_EXTI4_PH_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR2_EXTI4_PH EXTI_EXTICR2_EXTI4_PH_Msk /*!<PH[4] pin */
+#define EXTI_EXTICR2_EXTI4_PI_Pos (3U)
+#define EXTI_EXTICR2_EXTI4_PI_Msk (0x1U << EXTI_EXTICR2_EXTI4_PI_Pos) /*!< 0x00000008 */
+#define EXTI_EXTICR2_EXTI4_PI EXTI_EXTICR2_EXTI4_PI_Msk /*!<PI[4] pin */
+#define EXTI_EXTICR2_EXTI4_PJ_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI4_PJ_Pos) /*!< 0x00000009 */
+#define EXTI_EXTICR2_EXTI4_PJ EXTI_EXTICR2_EXTI4_PJ_Msk /*!<PJ[4] pin */
+#define EXTI_EXTICR2_EXTI4_PK_Pos (1U)
+#define EXTI_EXTICR2_EXTI4_PK_Msk (0x5U << EXTI_EXTICR2_EXTI4_PK_Pos) /*!< 0x0000000A */
+#define EXTI_EXTICR2_EXTI4_PK EXTI_EXTICR2_EXTI4_PK_Msk /*!<PK[4] pin */
+#define EXTI_EXTICR2_EXTI4_PZ_Pos (0U)
+#define EXTI_EXTICR2_EXTI4_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI4_PZ_Pos) /*!< 0x0000000B */
+#define EXTI_EXTICR2_EXTI4_PZ EXTI_EXTICR2_EXTI4_PZ_Msk /*!<PZ[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define EXTI_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
+#define EXTI_EXTICR2_EXTI5_PB_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_PB_Msk (0x1U << EXTI_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR2_EXTI5_PB EXTI_EXTICR2_EXTI5_PB_Msk /*!<PB[5] pin */
+#define EXTI_EXTICR2_EXTI5_PC_Pos (9U)
+#define EXTI_EXTICR2_EXTI5_PC_Msk (0x1U << EXTI_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR2_EXTI5_PC EXTI_EXTICR2_EXTI5_PC_Msk /*!<PC[5] pin */
+#define EXTI_EXTICR2_EXTI5_PD_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_PD_Msk (0x3U << EXTI_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000300 */
+#define EXTI_EXTICR2_EXTI5_PD EXTI_EXTICR2_EXTI5_PD_Msk /*!<PD[5] pin */
+#define EXTI_EXTICR2_EXTI5_PE_Pos (10U)
+#define EXTI_EXTICR2_EXTI5_PE_Msk (0x1U << EXTI_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR2_EXTI5_PE EXTI_EXTICR2_EXTI5_PE_Msk /*!<PE[5] pin */
+#define EXTI_EXTICR2_EXTI5_PF_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_PF_Msk (0x5U << EXTI_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000500 */
+#define EXTI_EXTICR2_EXTI5_PF EXTI_EXTICR2_EXTI5_PF_Msk /*!<PF[5] pin */
+#define EXTI_EXTICR2_EXTI5_PG_Pos (9U)
+#define EXTI_EXTICR2_EXTI5_PG_Msk (0x3U << EXTI_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000600 */
+#define EXTI_EXTICR2_EXTI5_PG EXTI_EXTICR2_EXTI5_PG_Msk /*!<PG[5] pin */
+#define EXTI_EXTICR2_EXTI5_PH_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_PH_Msk (0x7U << EXTI_EXTICR2_EXTI5_PH_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR2_EXTI5_PH EXTI_EXTICR2_EXTI5_PH_Msk /*!<PH[5] pin */
+#define EXTI_EXTICR2_EXTI5_PI_Pos (11U)
+#define EXTI_EXTICR2_EXTI5_PI_Msk (0x1U << EXTI_EXTICR2_EXTI5_PI_Pos) /*!< 0x00000800 */
+#define EXTI_EXTICR2_EXTI5_PI EXTI_EXTICR2_EXTI5_PI_Msk /*!<PI[5] pin */
+#define EXTI_EXTICR2_EXTI5_PJ_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI5_PJ_Pos) /*!< 0x00000900 */
+#define EXTI_EXTICR2_EXTI5_PJ EXTI_EXTICR2_EXTI5_PJ_Msk /*!<PJ[5] pin */
+#define EXTI_EXTICR2_EXTI5_PK_Pos (9U)
+#define EXTI_EXTICR2_EXTI5_PK_Msk (0x5U << EXTI_EXTICR2_EXTI5_PK_Pos) /*!< 0x00000A00 */
+#define EXTI_EXTICR2_EXTI5_PK EXTI_EXTICR2_EXTI5_PK_Msk /*!<PK[5] pin */
+#define EXTI_EXTICR2_EXTI5_PZ_Pos (8U)
+#define EXTI_EXTICR2_EXTI5_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI5_PZ_Pos) /*!< 0x00000B00 */
+#define EXTI_EXTICR2_EXTI5_PZ EXTI_EXTICR2_EXTI5_PZ_Msk /*!<PZ[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define EXTI_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
+#define EXTI_EXTICR2_EXTI6_PB_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_PB_Msk (0x1U << EXTI_EXTICR2_EXTI6_PB_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR2_EXTI6_PB EXTI_EXTICR2_EXTI6_PB_Msk /*!<PB[6] pin */
+#define EXTI_EXTICR2_EXTI6_PC_Pos (17U)
+#define EXTI_EXTICR2_EXTI6_PC_Msk (0x1U << EXTI_EXTICR2_EXTI6_PC_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR2_EXTI6_PC EXTI_EXTICR2_EXTI6_PC_Msk /*!<PC[6] pin */
+#define EXTI_EXTICR2_EXTI6_PD_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_PD_Msk (0x3U << EXTI_EXTICR2_EXTI6_PD_Pos) /*!< 0x00030000 */
+#define EXTI_EXTICR2_EXTI6_PD EXTI_EXTICR2_EXTI6_PD_Msk /*!<PD[6] pin */
+#define EXTI_EXTICR2_EXTI6_PE_Pos (18U)
+#define EXTI_EXTICR2_EXTI6_PE_Msk (0x1U << EXTI_EXTICR2_EXTI6_PE_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR2_EXTI6_PE EXTI_EXTICR2_EXTI6_PE_Msk /*!<PE[6] pin */
+#define EXTI_EXTICR2_EXTI6_PF_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_PF_Msk (0x5U << EXTI_EXTICR2_EXTI6_PF_Pos) /*!< 0x00050000 */
+#define EXTI_EXTICR2_EXTI6_PF EXTI_EXTICR2_EXTI6_PF_Msk /*!<PF[6] pin */
+#define EXTI_EXTICR2_EXTI6_PG_Pos (17U)
+#define EXTI_EXTICR2_EXTI6_PG_Msk (0x3U << EXTI_EXTICR2_EXTI6_PG_Pos) /*!< 0x00060000 */
+#define EXTI_EXTICR2_EXTI6_PG EXTI_EXTICR2_EXTI6_PG_Msk /*!<PG[6] pin */
+#define EXTI_EXTICR2_EXTI6_PH_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_PH_Msk (0x7U << EXTI_EXTICR2_EXTI6_PH_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR2_EXTI6_PH EXTI_EXTICR2_EXTI6_PH_Msk /*!<PH[6] pin */
+#define EXTI_EXTICR2_EXTI6_PI_Pos (19U)
+#define EXTI_EXTICR2_EXTI6_PI_Msk (0x1U << EXTI_EXTICR2_EXTI6_PI_Pos) /*!< 0x00080000 */
+#define EXTI_EXTICR2_EXTI6_PI EXTI_EXTICR2_EXTI6_PI_Msk /*!<PI[6] pin */
+#define EXTI_EXTICR2_EXTI6_PJ_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI6_PJ_Pos) /*!< 0x00090000 */
+#define EXTI_EXTICR2_EXTI6_PJ EXTI_EXTICR2_EXTI6_PJ_Msk /*!<PJ[6] pin */
+#define EXTI_EXTICR2_EXTI6_PK_Pos (17U)
+#define EXTI_EXTICR2_EXTI6_PK_Msk (0x5U << EXTI_EXTICR2_EXTI6_PK_Pos) /*!< 0x000A0000 */
+#define EXTI_EXTICR2_EXTI6_PK EXTI_EXTICR2_EXTI6_PK_Msk /*!<PK[6] pin */
+#define EXTI_EXTICR2_EXTI6_PZ_Pos (16U)
+#define EXTI_EXTICR2_EXTI6_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI6_PZ_Pos) /*!< 0x000B0000 */
+#define EXTI_EXTICR2_EXTI6_PZ EXTI_EXTICR2_EXTI6_PZ_Msk /*!<PZ[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define EXTI_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
+#define EXTI_EXTICR2_EXTI7_PB_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_PB_Msk (0x1U << EXTI_EXTICR2_EXTI7_PB_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR2_EXTI7_PB EXTI_EXTICR2_EXTI7_PB_Msk /*!<PB[7] pin */
+#define EXTI_EXTICR2_EXTI7_PC_Pos (25U)
+#define EXTI_EXTICR2_EXTI7_PC_Msk (0x1U << EXTI_EXTICR2_EXTI7_PC_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR2_EXTI7_PC EXTI_EXTICR2_EXTI7_PC_Msk /*!<PC[7] pin */
+#define EXTI_EXTICR2_EXTI7_PD_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_PD_Msk (0x3U << EXTI_EXTICR2_EXTI7_PD_Pos) /*!< 0x03000000 */
+#define EXTI_EXTICR2_EXTI7_PD EXTI_EXTICR2_EXTI7_PD_Msk /*!<PD[7] pin */
+#define EXTI_EXTICR2_EXTI7_PE_Pos (26U)
+#define EXTI_EXTICR2_EXTI7_PE_Msk (0x1U << EXTI_EXTICR2_EXTI7_PE_Pos) /*!< 0x04000000 */
+#define EXTI_EXTICR2_EXTI7_PE EXTI_EXTICR2_EXTI7_PE_Msk /*!<PE[7] pin */
+#define EXTI_EXTICR2_EXTI7_PF_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_PF_Msk (0x5U << EXTI_EXTICR2_EXTI7_PF_Pos) /*!< 0x05000000 */
+#define EXTI_EXTICR2_EXTI7_PF EXTI_EXTICR2_EXTI7_PF_Msk /*!<PF[7] pin */
+#define EXTI_EXTICR2_EXTI7_PG_Pos (25U)
+#define EXTI_EXTICR2_EXTI7_PG_Msk (0x3U << EXTI_EXTICR2_EXTI7_PG_Pos) /*!< 0x06000000 */
+#define EXTI_EXTICR2_EXTI7_PG EXTI_EXTICR2_EXTI7_PG_Msk /*!<PG[7] pin */
+#define EXTI_EXTICR2_EXTI7_PH_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_PH_Msk (0x7U << EXTI_EXTICR2_EXTI7_PH_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR2_EXTI7_PH EXTI_EXTICR2_EXTI7_PH_Msk /*!<PH[7] pin */
+#define EXTI_EXTICR2_EXTI7_PI_Pos (27U)
+#define EXTI_EXTICR2_EXTI7_PI_Msk (0x1U << EXTI_EXTICR2_EXTI7_PI_Pos) /*!< 0x08000000 */
+#define EXTI_EXTICR2_EXTI7_PI EXTI_EXTICR2_EXTI7_PI_Msk /*!<PI[7] pin */
+#define EXTI_EXTICR2_EXTI7_PJ_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI7_PJ_Pos) /*!< 0x09000000 */
+#define EXTI_EXTICR2_EXTI7_PJ EXTI_EXTICR2_EXTI7_PJ_Msk /*!<PJ[7] pin */
+#define EXTI_EXTICR2_EXTI7_PK_Pos (25U)
+#define EXTI_EXTICR2_EXTI7_PK_Msk (0x5U << EXTI_EXTICR2_EXTI7_PK_Pos) /*!< 0x0A000000 */
+#define EXTI_EXTICR2_EXTI7_PK EXTI_EXTICR2_EXTI7_PK_Msk /*!<PK[7] pin */
+#define EXTI_EXTICR2_EXTI7_PZ_Pos (24U)
+#define EXTI_EXTICR2_EXTI7_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI7_PZ_Pos) /*!< 0x0B000000 */
+#define EXTI_EXTICR2_EXTI7_PZ EXTI_EXTICR2_EXTI7_PZ_Msk /*!<PZ[7] pin */
+
+
+/***************** Bit definition for EXTI_EXTICR3 register ***************/
+#define EXTI_EXTICR3_EXTI8_Pos (0U)
+#define EXTI_EXTICR3_EXTI8_Msk (0x0FU << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
+#define EXTI_EXTICR3_EXTI9_Pos (8U)
+#define EXTI_EXTICR3_EXTI9_Msk (0x0FU << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000F00 */
+#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
+#define EXTI_EXTICR3_EXTI10_Pos (16U)
+#define EXTI_EXTICR3_EXTI10_Msk (0x0FU << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x000F0000 */
+#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
+#define EXTI_EXTICR3_EXTI11_Pos (24U)
+#define EXTI_EXTICR3_EXTI11_Msk (0x0FU << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x0F000000 */
+#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define EXTI_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
+#define EXTI_EXTICR3_EXTI8_PB_Pos (0U)
+#define EXTI_EXTICR3_EXTI8_PB_Msk (0x1U << EXTI_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR3_EXTI8_PB EXTI_EXTICR3_EXTI8_PB_Msk /*!<PB[8] pin */
+#define EXTI_EXTICR3_EXTI8_PC_Pos (1U)
+#define EXTI_EXTICR3_EXTI8_PC_Msk (0x1U << EXTI_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR3_EXTI8_PC EXTI_EXTICR3_EXTI8_PC_Msk /*!<PC[8] pin */
+#define EXTI_EXTICR3_EXTI8_PD_Pos (0U)
+#define EXTI_EXTICR3_EXTI8_PD_Msk (0x3U << EXTI_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
+#define EXTI_EXTICR3_EXTI8_PD EXTI_EXTICR3_EXTI8_PD_Msk /*!<PD[8] pin */
+#define EXTI_EXTICR3_EXTI8_PE_Pos (2U)
+#define EXTI_EXTICR3_EXTI8_PE_Msk (0x1U << EXTI_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR3_EXTI8_PE EXTI_EXTICR3_EXTI8_PE_Msk /*!<PE[8] pin */
+#define EXTI_EXTICR3_EXTI8_PF_Pos (0U)
+#define EXTI_EXTICR3_EXTI8_PF_Msk (0x5U << EXTI_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
+#define EXTI_EXTICR3_EXTI8_PF EXTI_EXTICR3_EXTI8_PF_Msk /*!<PF[8] pin */
+#define EXTI_EXTICR3_EXTI8_PG_Pos (1U)
+#define EXTI_EXTICR3_EXTI8_PG_Msk (0x3U << EXTI_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
+#define EXTI_EXTICR3_EXTI8_PG EXTI_EXTICR3_EXTI8_PG_Msk /*!<PG[8] pin */
+#define EXTI_EXTICR3_EXTI8_PH_Pos (0U)
+#define EXTI_EXTICR3_EXTI8_PH_Msk (0x7U << EXTI_EXTICR3_EXTI8_PH_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR3_EXTI8_PH EXTI_EXTICR3_EXTI8_PH_Msk /*!<PH[8] pin */
+#define EXTI_EXTICR3_EXTI8_PI_Pos (3U)
+#define EXTI_EXTICR3_EXTI8_PI_Msk (0x1U << EXTI_EXTICR3_EXTI8_PI_Pos) /*!< 0x00000008 */
+#define EXTI_EXTICR3_EXTI8_PI EXTI_EXTICR3_EXTI8_PI_Msk /*!<PI[8] pin */
+#define EXTI_EXTICR3_EXTI8_PJ_Pos (0U)
+#define EXTI_EXTICR3_EXTI8_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI8_PJ_Pos) /*!< 0x00000009 */
+#define EXTI_EXTICR3_EXTI8_PJ EXTI_EXTICR3_EXTI8_PJ_Msk /*!<PJ[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define EXTI_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
+#define EXTI_EXTICR3_EXTI9_PB_Pos (8U)
+#define EXTI_EXTICR3_EXTI9_PB_Msk (0x1U << EXTI_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR3_EXTI9_PB EXTI_EXTICR3_EXTI9_PB_Msk /*!<PB[9] pin */
+#define EXTI_EXTICR3_EXTI9_PC_Pos (9U)
+#define EXTI_EXTICR3_EXTI9_PC_Msk (0x1U << EXTI_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR3_EXTI9_PC EXTI_EXTICR3_EXTI9_PC_Msk /*!<PC[9] pin */
+#define EXTI_EXTICR3_EXTI9_PD_Pos (8U)
+#define EXTI_EXTICR3_EXTI9_PD_Msk (0x3U << EXTI_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000300 */
+#define EXTI_EXTICR3_EXTI9_PD EXTI_EXTICR3_EXTI9_PD_Msk /*!<PD[9] pin */
+#define EXTI_EXTICR3_EXTI9_PE_Pos (10U)
+#define EXTI_EXTICR3_EXTI9_PE_Msk (0x1U << EXTI_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR3_EXTI9_PE EXTI_EXTICR3_EXTI9_PE_Msk /*!<PE[9] pin */
+#define EXTI_EXTICR3_EXTI9_PF_Pos (8U)
+#define EXTI_EXTICR3_EXTI9_PF_Msk (0x5U << EXTI_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000500 */
+#define EXTI_EXTICR3_EXTI9_PF EXTI_EXTICR3_EXTI9_PF_Msk /*!<PF[9] pin */
+#define EXTI_EXTICR3_EXTI9_PG_Pos (9U)
+#define EXTI_EXTICR3_EXTI9_PG_Msk (0x3U << EXTI_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000600 */
+#define EXTI_EXTICR3_EXTI9_PG EXTI_EXTICR3_EXTI9_PG_Msk /*!<PG[9] pin */
+#define EXTI_EXTICR3_EXTI9_PH_Pos (8U)
+#define EXTI_EXTICR3_EXTI9_PH_Msk (0x7U << EXTI_EXTICR3_EXTI9_PH_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR3_EXTI9_PH EXTI_EXTICR3_EXTI9_PH_Msk /*!<PH[9] pin */
+#define EXTI_EXTICR3_EXTI9_PI_Pos (11U)
+#define EXTI_EXTICR3_EXTI9_PI_Msk (0x1U << EXTI_EXTICR3_EXTI9_PI_Pos) /*!< 0x00000800 */
+#define EXTI_EXTICR3_EXTI9_PI EXTI_EXTICR3_EXTI9_PI_Msk /*!<PI[9] pin */
+#define EXTI_EXTICR3_EXTI9_PJ_Pos (8U)
+#define EXTI_EXTICR3_EXTI9_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI9_PJ_Pos) /*!< 0x00000900 */
+#define EXTI_EXTICR3_EXTI9_PJ EXTI_EXTICR3_EXTI9_PJ_Msk /*!<PJ[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define EXTI_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
+#define EXTI_EXTICR3_EXTI10_PB_Pos (16U)
+#define EXTI_EXTICR3_EXTI10_PB_Msk (0x1U << EXTI_EXTICR3_EXTI10_PB_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR3_EXTI10_PB EXTI_EXTICR3_EXTI10_PB_Msk /*!<PB[10] pin */
+#define EXTI_EXTICR3_EXTI10_PC_Pos (17U)
+#define EXTI_EXTICR3_EXTI10_PC_Msk (0x1U << EXTI_EXTICR3_EXTI10_PC_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR3_EXTI10_PC EXTI_EXTICR3_EXTI10_PC_Msk /*!<PC[10] pin */
+#define EXTI_EXTICR3_EXTI10_PD_Pos (16U)
+#define EXTI_EXTICR3_EXTI10_PD_Msk (0x3U << EXTI_EXTICR3_EXTI10_PD_Pos) /*!< 0x00030000 */
+#define EXTI_EXTICR3_EXTI10_PD EXTI_EXTICR3_EXTI10_PD_Msk /*!<PD[10] pin */
+#define EXTI_EXTICR3_EXTI10_PE_Pos (18U)
+#define EXTI_EXTICR3_EXTI10_PE_Msk (0x1U << EXTI_EXTICR3_EXTI10_PE_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR3_EXTI10_PE EXTI_EXTICR3_EXTI10_PE_Msk /*!<PE[10] pin */
+#define EXTI_EXTICR3_EXTI10_PF_Pos (16U)
+#define EXTI_EXTICR3_EXTI10_PF_Msk (0x5U << EXTI_EXTICR3_EXTI10_PF_Pos) /*!< 0x00050000 */
+#define EXTI_EXTICR3_EXTI10_PF EXTI_EXTICR3_EXTI10_PF_Msk /*!<PF[10] pin */
+#define EXTI_EXTICR3_EXTI10_PG_Pos (17U)
+#define EXTI_EXTICR3_EXTI10_PG_Msk (0x3U << EXTI_EXTICR3_EXTI10_PG_Pos) /*!< 0x00060000 */
+#define EXTI_EXTICR3_EXTI10_PG EXTI_EXTICR3_EXTI10_PG_Msk /*!<PG[10] pin */
+#define EXTI_EXTICR3_EXTI10_PH_Pos (16U)
+#define EXTI_EXTICR3_EXTI10_PH_Msk (0x7U << EXTI_EXTICR3_EXTI10_PH_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR3_EXTI10_PH EXTI_EXTICR3_EXTI10_PH_Msk /*!<PH[10] pin */
+#define EXTI_EXTICR3_EXTI10_PI_Pos (19U)
+#define EXTI_EXTICR3_EXTI10_PI_Msk (0x1U << EXTI_EXTICR3_EXTI10_PI_Pos) /*!< 0x00080000 */
+#define EXTI_EXTICR3_EXTI10_PI EXTI_EXTICR3_EXTI10_PI_Msk /*!<PI[10] pin */
+#define EXTI_EXTICR3_EXTI10_PJ_Pos (16U)
+#define EXTI_EXTICR3_EXTI10_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI10_PJ_Pos) /*!< 0x00090000 */
+#define EXTI_EXTICR3_EXTI10_PJ EXTI_EXTICR3_EXTI10_PJ_Msk /*!<PJ[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define EXTI_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
+#define EXTI_EXTICR3_EXTI11_PB_Pos (24U)
+#define EXTI_EXTICR3_EXTI11_PB_Msk (0x1U << EXTI_EXTICR3_EXTI11_PB_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR3_EXTI11_PB EXTI_EXTICR3_EXTI11_PB_Msk /*!<PB[11] pin */
+#define EXTI_EXTICR3_EXTI11_PC_Pos (25U)
+#define EXTI_EXTICR3_EXTI11_PC_Msk (0x1U << EXTI_EXTICR3_EXTI11_PC_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR3_EXTI11_PC EXTI_EXTICR3_EXTI11_PC_Msk /*!<PC[11] pin */
+#define EXTI_EXTICR3_EXTI11_PD_Pos (24U)
+#define EXTI_EXTICR3_EXTI11_PD_Msk (0x3U << EXTI_EXTICR3_EXTI11_PD_Pos) /*!< 0x03000000 */
+#define EXTI_EXTICR3_EXTI11_PD EXTI_EXTICR3_EXTI11_PD_Msk /*!<PD[11] pin */
+#define EXTI_EXTICR3_EXTI11_PE_Pos (26U)
+#define EXTI_EXTICR3_EXTI11_PE_Msk (0x1U << EXTI_EXTICR3_EXTI11_PE_Pos) /*!< 0x04000000 */
+#define EXTI_EXTICR3_EXTI11_PE EXTI_EXTICR3_EXTI11_PE_Msk /*!<PE[11] pin */
+#define EXTI_EXTICR3_EXTI11_PF_Pos (24U)
+#define EXTI_EXTICR3_EXTI11_PF_Msk (0x5U << EXTI_EXTICR3_EXTI11_PF_Pos) /*!< 0x05000000 */
+#define EXTI_EXTICR3_EXTI11_PF EXTI_EXTICR3_EXTI11_PF_Msk /*!<PF[11] pin */
+#define EXTI_EXTICR3_EXTI11_PG_Pos (25U)
+#define EXTI_EXTICR3_EXTI11_PG_Msk (0x3U << EXTI_EXTICR3_EXTI11_PG_Pos) /*!< 0x06000000 */
+#define EXTI_EXTICR3_EXTI11_PG EXTI_EXTICR3_EXTI11_PG_Msk /*!<PG[11] pin */
+#define EXTI_EXTICR3_EXTI11_PH_Pos (24U)
+#define EXTI_EXTICR3_EXTI11_PH_Msk (0x7U << EXTI_EXTICR3_EXTI11_PH_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR3_EXTI11_PH EXTI_EXTICR3_EXTI11_PH_Msk /*!<PH[11] pin */
+#define EXTI_EXTICR3_EXTI11_PI_Pos (27U)
+#define EXTI_EXTICR3_EXTI11_PI_Msk (0x1U << EXTI_EXTICR3_EXTI11_PI_Pos) /*!< 0x08000000 */
+#define EXTI_EXTICR3_EXTI11_PI EXTI_EXTICR3_EXTI11_PI_Msk /*!<PI[11] pin */
+#define EXTI_EXTICR3_EXTI11_PJ_Pos (24U)
+#define EXTI_EXTICR3_EXTI11_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI11_PJ_Pos) /*!< 0x09000000 */
+#define EXTI_EXTICR3_EXTI11_PJ EXTI_EXTICR3_EXTI11_PJ_Msk /*!<PJ[11] pin */
+
+
+/***************** Bit definition for EXTI_EXTICR4 register ***************/
+#define EXTI_EXTICR4_EXTI12_Pos (0U)
+#define EXTI_EXTICR4_EXTI12_Msk (0x0FU << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
+#define EXTI_EXTICR4_EXTI13_Pos (8U)
+#define EXTI_EXTICR4_EXTI13_Msk (0x0FU << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000F00 */
+#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
+#define EXTI_EXTICR4_EXTI14_Pos (16U)
+#define EXTI_EXTICR4_EXTI14_Msk (0x0FU << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x000F0000 */
+#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
+#define EXTI_EXTICR4_EXTI15_Pos (24U)
+#define EXTI_EXTICR4_EXTI15_Msk (0x0FU << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x0F000000 */
+#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define EXTI_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
+#define EXTI_EXTICR4_EXTI12_PB_Pos (0U)
+#define EXTI_EXTICR4_EXTI12_PB_Msk (0x1U << EXTI_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
+#define EXTI_EXTICR4_EXTI12_PB EXTI_EXTICR4_EXTI12_PB_Msk /*!<PB[12] pin */
+#define EXTI_EXTICR4_EXTI12_PC_Pos (1U)
+#define EXTI_EXTICR4_EXTI12_PC_Msk (0x1U << EXTI_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
+#define EXTI_EXTICR4_EXTI12_PC EXTI_EXTICR4_EXTI12_PC_Msk /*!<PC[12] pin */
+#define EXTI_EXTICR4_EXTI12_PD_Pos (0U)
+#define EXTI_EXTICR4_EXTI12_PD_Msk (0x3U << EXTI_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
+#define EXTI_EXTICR4_EXTI12_PD EXTI_EXTICR4_EXTI12_PD_Msk /*!<PD[12] pin */
+#define EXTI_EXTICR4_EXTI12_PE_Pos (2U)
+#define EXTI_EXTICR4_EXTI12_PE_Msk (0x1U << EXTI_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
+#define EXTI_EXTICR4_EXTI12_PE EXTI_EXTICR4_EXTI12_PE_Msk /*!<PE[12] pin */
+#define EXTI_EXTICR4_EXTI12_PF_Pos (0U)
+#define EXTI_EXTICR4_EXTI12_PF_Msk (0x5U << EXTI_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
+#define EXTI_EXTICR4_EXTI12_PF EXTI_EXTICR4_EXTI12_PF_Msk /*!<PF[12] pin */
+#define EXTI_EXTICR4_EXTI12_PG_Pos (1U)
+#define EXTI_EXTICR4_EXTI12_PG_Msk (0x3U << EXTI_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
+#define EXTI_EXTICR4_EXTI12_PG EXTI_EXTICR4_EXTI12_PG_Msk /*!<PG[12] pin */
+#define EXTI_EXTICR4_EXTI12_PH_Pos (0U)
+#define EXTI_EXTICR4_EXTI12_PH_Msk (0x7U << EXTI_EXTICR4_EXTI12_PH_Pos) /*!< 0x00000007 */
+#define EXTI_EXTICR4_EXTI12_PH EXTI_EXTICR4_EXTI12_PH_Msk /*!<PH[12] pin */
+#define EXTI_EXTICR4_EXTI12_PI_Pos (3U)
+#define EXTI_EXTICR4_EXTI12_PI_Msk (0x1U << EXTI_EXTICR4_EXTI12_PI_Pos) /*!< 0x00000008 */
+#define EXTI_EXTICR4_EXTI12_PI EXTI_EXTICR4_EXTI12_PI_Msk /*!<PI[12] pin */
+#define EXTI_EXTICR4_EXTI12_PJ_Pos (0U)
+#define EXTI_EXTICR4_EXTI12_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI12_PJ_Pos) /*!< 0x00000009 */
+#define EXTI_EXTICR4_EXTI12_PJ EXTI_EXTICR4_EXTI12_PJ_Msk /*!<PJ[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define EXTI_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
+#define EXTI_EXTICR4_EXTI13_PB_Pos (8U)
+#define EXTI_EXTICR4_EXTI13_PB_Msk (0x1U << EXTI_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000100 */
+#define EXTI_EXTICR4_EXTI13_PB EXTI_EXTICR4_EXTI13_PB_Msk /*!<PB[13] pin */
+#define EXTI_EXTICR4_EXTI13_PC_Pos (9U)
+#define EXTI_EXTICR4_EXTI13_PC_Msk (0x1U << EXTI_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000200 */
+#define EXTI_EXTICR4_EXTI13_PC EXTI_EXTICR4_EXTI13_PC_Msk /*!<PC[13] pin */
+#define EXTI_EXTICR4_EXTI13_PD_Pos (8U)
+#define EXTI_EXTICR4_EXTI13_PD_Msk (0x3U << EXTI_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000300 */
+#define EXTI_EXTICR4_EXTI13_PD EXTI_EXTICR4_EXTI13_PD_Msk /*!<PD[13] pin */
+#define EXTI_EXTICR4_EXTI13_PE_Pos (10U)
+#define EXTI_EXTICR4_EXTI13_PE_Msk (0x1U << EXTI_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000400 */
+#define EXTI_EXTICR4_EXTI13_PE EXTI_EXTICR4_EXTI13_PE_Msk /*!<PE[13] pin */
+#define EXTI_EXTICR4_EXTI13_PF_Pos (8U)
+#define EXTI_EXTICR4_EXTI13_PF_Msk (0x5U << EXTI_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000500 */
+#define EXTI_EXTICR4_EXTI13_PF EXTI_EXTICR4_EXTI13_PF_Msk /*!<PF[13] pin */
+#define EXTI_EXTICR4_EXTI13_PG_Pos (9U)
+#define EXTI_EXTICR4_EXTI13_PG_Msk (0x3U << EXTI_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000600 */
+#define EXTI_EXTICR4_EXTI13_PG EXTI_EXTICR4_EXTI13_PG_Msk /*!<PG[13] pin */
+#define EXTI_EXTICR4_EXTI13_PH_Pos (8U)
+#define EXTI_EXTICR4_EXTI13_PH_Msk (0x7U << EXTI_EXTICR4_EXTI13_PH_Pos) /*!< 0x00000700 */
+#define EXTI_EXTICR4_EXTI13_PH EXTI_EXTICR4_EXTI13_PH_Msk /*!<PH[13] pin */
+#define EXTI_EXTICR4_EXTI13_PI_Pos (11U)
+#define EXTI_EXTICR4_EXTI13_PI_Msk (0x1U << EXTI_EXTICR4_EXTI13_PI_Pos) /*!< 0x00000800 */
+#define EXTI_EXTICR4_EXTI13_PI EXTI_EXTICR4_EXTI13_PI_Msk /*!<PI[13] pin */
+#define EXTI_EXTICR4_EXTI13_PJ_Pos (8U)
+#define EXTI_EXTICR4_EXTI13_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI13_PJ_Pos) /*!< 0x00000900 */
+#define EXTI_EXTICR4_EXTI13_PJ EXTI_EXTICR4_EXTI13_PJ_Msk /*!<PJ[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define EXTI_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
+#define EXTI_EXTICR4_EXTI14_PB_Pos (16U)
+#define EXTI_EXTICR4_EXTI14_PB_Msk (0x1U << EXTI_EXTICR4_EXTI14_PB_Pos) /*!< 0x00010000 */
+#define EXTI_EXTICR4_EXTI14_PB EXTI_EXTICR4_EXTI14_PB_Msk /*!<PB[14] pin */
+#define EXTI_EXTICR4_EXTI14_PC_Pos (17U)
+#define EXTI_EXTICR4_EXTI14_PC_Msk (0x1U << EXTI_EXTICR4_EXTI14_PC_Pos) /*!< 0x00020000 */
+#define EXTI_EXTICR4_EXTI14_PC EXTI_EXTICR4_EXTI14_PC_Msk /*!<PC[14] pin */
+#define EXTI_EXTICR4_EXTI14_PD_Pos (16U)
+#define EXTI_EXTICR4_EXTI14_PD_Msk (0x3U << EXTI_EXTICR4_EXTI14_PD_Pos) /*!< 0x00030000 */
+#define EXTI_EXTICR4_EXTI14_PD EXTI_EXTICR4_EXTI14_PD_Msk /*!<PD[14] pin */
+#define EXTI_EXTICR4_EXTI14_PE_Pos (18U)
+#define EXTI_EXTICR4_EXTI14_PE_Msk (0x1U << EXTI_EXTICR4_EXTI14_PE_Pos) /*!< 0x00040000 */
+#define EXTI_EXTICR4_EXTI14_PE EXTI_EXTICR4_EXTI14_PE_Msk /*!<PE[14] pin */
+#define EXTI_EXTICR4_EXTI14_PF_Pos (16U)
+#define EXTI_EXTICR4_EXTI14_PF_Msk (0x5U << EXTI_EXTICR4_EXTI14_PF_Pos) /*!< 0x00050000 */
+#define EXTI_EXTICR4_EXTI14_PF EXTI_EXTICR4_EXTI14_PF_Msk /*!<PF[14] pin */
+#define EXTI_EXTICR4_EXTI14_PG_Pos (17U)
+#define EXTI_EXTICR4_EXTI14_PG_Msk (0x3U << EXTI_EXTICR4_EXTI14_PG_Pos) /*!< 0x00060000 */
+#define EXTI_EXTICR4_EXTI14_PG EXTI_EXTICR4_EXTI14_PG_Msk /*!<PG[14] pin */
+#define EXTI_EXTICR4_EXTI14_PH_Pos (16U)
+#define EXTI_EXTICR4_EXTI14_PH_Msk (0x7U << EXTI_EXTICR4_EXTI14_PH_Pos) /*!< 0x00070000 */
+#define EXTI_EXTICR4_EXTI14_PH EXTI_EXTICR4_EXTI14_PH_Msk /*!<PH[14] pin */
+#define EXTI_EXTICR4_EXTI14_PI_Pos (19U)
+#define EXTI_EXTICR4_EXTI14_PI_Msk (0x1U << EXTI_EXTICR4_EXTI14_PI_Pos) /*!< 0x00080000 */
+#define EXTI_EXTICR4_EXTI14_PI EXTI_EXTICR4_EXTI14_PI_Msk /*!<PI[14] pin */
+#define EXTI_EXTICR4_EXTI14_PJ_Pos (16U)
+#define EXTI_EXTICR4_EXTI14_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI14_PJ_Pos) /*!< 0x00090000 */
+#define EXTI_EXTICR4_EXTI14_PJ EXTI_EXTICR4_EXTI14_PJ_Msk /*!<PJ[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define EXTI_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
+#define EXTI_EXTICR4_EXTI15_PB_Pos (24U)
+#define EXTI_EXTICR4_EXTI15_PB_Msk (0x1U << EXTI_EXTICR4_EXTI15_PB_Pos) /*!< 0x01000000 */
+#define EXTI_EXTICR4_EXTI15_PB EXTI_EXTICR4_EXTI15_PB_Msk /*!<PB[15] pin */
+#define EXTI_EXTICR4_EXTI15_PC_Pos (25U)
+#define EXTI_EXTICR4_EXTI15_PC_Msk (0x1U << EXTI_EXTICR4_EXTI15_PC_Pos) /*!< 0x02000000 */
+#define EXTI_EXTICR4_EXTI15_PC EXTI_EXTICR4_EXTI15_PC_Msk /*!<PC[15] pin */
+#define EXTI_EXTICR4_EXTI15_PD_Pos (24U)
+#define EXTI_EXTICR4_EXTI15_PD_Msk (0x3U << EXTI_EXTICR4_EXTI15_PD_Pos) /*!< 0x03000000 */
+#define EXTI_EXTICR4_EXTI15_PD EXTI_EXTICR4_EXTI15_PD_Msk /*!<PD[15] pin */
+#define EXTI_EXTICR4_EXTI15_PE_Pos (26U)
+#define EXTI_EXTICR4_EXTI15_PE_Msk (0x1U << EXTI_EXTICR4_EXTI15_PE_Pos) /*!< 0x04000000 */
+#define EXTI_EXTICR4_EXTI15_PE EXTI_EXTICR4_EXTI15_PE_Msk /*!<PE[15] pin */
+#define EXTI_EXTICR4_EXTI15_PF_Pos (24U)
+#define EXTI_EXTICR4_EXTI15_PF_Msk (0x5U << EXTI_EXTICR4_EXTI15_PF_Pos) /*!< 0x05000000 */
+#define EXTI_EXTICR4_EXTI15_PF EXTI_EXTICR4_EXTI15_PF_Msk /*!<PF[15] pin */
+#define EXTI_EXTICR4_EXTI15_PG_Pos (25U)
+#define EXTI_EXTICR4_EXTI15_PG_Msk (0x3U << EXTI_EXTICR4_EXTI15_PG_Pos) /*!< 0x06000000 */
+#define EXTI_EXTICR4_EXTI15_PG EXTI_EXTICR4_EXTI15_PG_Msk /*!<PG[15] pin */
+#define EXTI_EXTICR4_EXTI15_PH_Pos (24U)
+#define EXTI_EXTICR4_EXTI15_PH_Msk (0x7U << EXTI_EXTICR4_EXTI15_PH_Pos) /*!< 0x07000000 */
+#define EXTI_EXTICR4_EXTI15_PH EXTI_EXTICR4_EXTI15_PH_Msk /*!<PH[15] pin */
+#define EXTI_EXTICR4_EXTI15_PI_Pos (27U)
+#define EXTI_EXTICR4_EXTI15_PI_Msk (0x1U << EXTI_EXTICR4_EXTI15_PI_Pos) /*!< 0x08000000 */
+#define EXTI_EXTICR4_EXTI15_PI EXTI_EXTICR4_EXTI15_PI_Msk /*!<PI[15] pin */
+#define EXTI_EXTICR4_EXTI15_PJ_Pos (24U)
+#define EXTI_EXTICR4_EXTI15_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI15_PJ_Pos) /*!< 0x09000000 */
+#define EXTI_EXTICR4_EXTI15_PJ EXTI_EXTICR4_EXTI15_PJ_Msk /*!<PJ[15] pin */
+
+/********************** Bit definition for EXTI_HWCFGR1 register ***************/
+#define EXTI_HWCFGR1_NBEVENTS_Pos (0U)
+#define EXTI_HWCFGR1_NBEVENTS_Msk (0xFFU << EXTI_HWCFGR1_NBEVENTS_Pos) /*!< 0x000000FF */
+#define EXTI_HWCFGR1_NBEVENTS EXTI_HWCFGR1_NBEVENTS_Msk /*!< Number of EVENT */
+#define EXTI_HWCFGR1_NBCPUS_Pos (8U)
+#define EXTI_HWCFGR1_NBCPUS_Msk (0xFU << EXTI_HWCFGR1_NBCPUS_Pos) /*!< 0x00000F00 */
+#define EXTI_HWCFGR1_NBCPUS EXTI_HWCFGR1_NBCPUS_Msk /*!< Number of CPUs */
+#define EXTI_HWCFGR1_CPUEVTEN_Pos (12U)
+#define EXTI_HWCFGR1_CPUEVTEN_Msk (0xFU << EXTI_HWCFGR1_CPUEVTEN_Pos) /*!< 0x0000F000 */
+#define EXTI_HWCFGR1_CPUEVTEN EXTI_HWCFGR1_CPUEVTEN_Msk /*!< CPU(m) event output enable */
+#define EXTI_HWCFGR1_NBIOPORT_Pos (16U)
+#define EXTI_HWCFGR1_NBIOPORT_Msk (0xFFU << EXTI_HWCFGR1_NBIOPORT_Pos) /*!< 0x00FF0000 */
+#define EXTI_HWCFGR1_NBIOPORT EXTI_HWCFGR1_NBIOPORT_Msk /*!< Number of IO ports on EXTI */
+
+/********************** Bit definition for EXTI_VERR register *****************/
+#define EXTI_VERR_MINREV_Pos (0U)
+#define EXTI_VERR_MINREV_Msk (0xFU << EXTI_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define EXTI_VERR_MINREV EXTI_VERR_MINREV_Msk /*!< Minor Revision number */
+#define EXTI_VERR_MAJREV_Pos (4U)
+#define EXTI_VERR_MAJREV_Msk (0xFU << EXTI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define EXTI_VERR_MAJREV EXTI_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for EXTI_IPIDR register ****************/
+#define EXTI_IPIDR_IPID_Pos (0U)
+#define EXTI_IPIDR_IPID_Msk (0xFFFFFFFFU << EXTI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define EXTI_IPIDR_IPID EXTI_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for EXTI_SIDR register *****************/
+#define EXTI_SIDR_SID_Pos (0U)
+#define EXTI_SIDR_SID_Msk (0xFFFFFFFFU << EXTI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define EXTI_SIDR_SID EXTI_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* FDCAN Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FDCAN_CCCR register *****************/
+#define FDCAN_CCCR_INIT_Pos (0U)
+#define FDCAN_CCCR_INIT_Msk (0x1U << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!< Initialization bit */
+#define FDCAN_CCCR_CCCE_Pos (1U)
+#define FDCAN_CCCR_CCCE_Msk (0x1U << FDCAN_CCCR_CCCE_Pos) /*!< 0x00000002 */
+#define FDCAN_CCCR_CCCE FDCAN_CCCR_CCCE_Msk /*!< Configuration Change Enable bit */
+
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN_Pos (0U)
+#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN_Pos (1U)
+#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP_Pos (2U)
+#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos (4U)
+#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos (6U)
+#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN_Pos (8U)
+#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL_Pos (9U)
+#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD_Pos (10U)
+#define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG_Pos (11U)
+#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR1_WREN_Pos (12U)
+#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR1_WAITEN_Pos (13U)
+#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD_Pos (14U)
+#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
+
+#define FMC_BCR1_CPSIZE_Pos (16U)
+#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
+
+#define FMC_BCR1_CBURSTRW_Pos (19U)
+#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN_Pos (20U)
+#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+
+#define FMC_BCR1_NBLSET_Pos (22U)
+#define FMC_BCR1_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
+#define FMC_BCR1_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
+#define FMC_BCR1_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
+#define FMC_BCR1_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
+
+#define FMC_BCR1_FMCEN_Pos (31U)
+#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
+#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller enable*/
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN_Pos (0U)
+#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN_Pos (1U)
+#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP_Pos (2U)
+#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos (4U)
+#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos (6U)
+#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN_Pos (8U)
+#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL_Pos (9U)
+#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD_Pos (10U)
+#define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG_Pos (11U)
+#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR2_WREN_Pos (12U)
+#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR2_WAITEN_Pos (13U)
+#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD_Pos (14U)
+#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT_Pos (15U)
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
+
+#define FMC_BCR2_PSIZE_Pos (16U)
+#define FMC_BCR2_PSIZE_Msk (0x7U << FMC_BCR2_PSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR2_PSIZE FMC_BCR2_PSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCR2_PSIZE_0 (0x1U << FMC_BCR2_PSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR2_PSIZE_1 (0x2U << FMC_BCR2_PSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR2_PSIZE_2 (0x4U << FMC_BCR2_PSIZE_Pos) /*!< 0x00040000 */
+
+#define FMC_BCR2_CBURSTRW_Pos (19U)
+#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
+
+#define FMC_BCR2_NBLSET_Pos (22U)
+#define FMC_BCR2_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
+#define FMC_BCR2_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
+#define FMC_BCR2_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
+#define FMC_BCR2_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN_Pos (0U)
+#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN_Pos (1U)
+#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP_Pos (2U)
+#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos (4U)
+#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos (6U)
+#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN_Pos (8U)
+#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL_Pos (9U)
+#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD_Pos (10U)
+#define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG_Pos (11U)
+#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR3_WREN_Pos (12U)
+#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR3_WAITEN_Pos (13U)
+#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD_Pos (14U)
+#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT_Pos (15U)
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
+
+#define FMC_BCR3_PSIZE_Pos (16U)
+#define FMC_BCR3_PSIZE_Msk (0x7U << FMC_BCR3_PSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR3_PSIZE FMC_BCR3_PSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCR3_PSIZE_0 (0x1U << FMC_BCR3_PSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR3_PSIZE_1 (0x2U << FMC_BCR3_PSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR3_PSIZE_2 (0x4U << FMC_BCR3_PSIZE_Pos) /*!< 0x00040000 */
+
+#define FMC_BCR3_CBURSTRW_Pos (19U)
+#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
+
+#define FMC_BCR3_NBLSET_Pos (22U)
+#define FMC_BCR3_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
+#define FMC_BCR3_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
+#define FMC_BCR3_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
+#define FMC_BCR3_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN_Pos (0U)
+#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN_Pos (1U)
+#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP_Pos (2U)
+#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos (4U)
+#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos (6U)
+#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN_Pos (8U)
+#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL_Pos (9U)
+#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD_Pos (10U)
+#define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
+#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG_Pos (11U)
+#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
+#define FMC_BCR4_WREN_Pos (12U)
+#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
+#define FMC_BCR4_WAITEN_Pos (13U)
+#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD_Pos (14U)
+#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT_Pos (15U)
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
+
+#define FMC_BCR4_PSIZE_Pos (16U)
+#define FMC_BCR4_PSIZE_Msk (0x7U << FMC_BCR4_PSIZE_Pos) /*!< 0x00070000 */
+#define FMC_BCR4_PSIZE FMC_BCR4_PSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCR4_PSIZE_0 (0x1U << FMC_BCR4_PSIZE_Pos) /*!< 0x00010000 */
+#define FMC_BCR4_PSIZE_1 (0x2U << FMC_BCR4_PSIZE_Pos) /*!< 0x00020000 */
+#define FMC_BCR4_PSIZE_2 (0x4U << FMC_BCR4_PSIZE_Pos) /*!< 0x00040000 */
+
+#define FMC_BCR4_CBURSTRW_Pos (19U)
+#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
+
+#define FMC_BCR4_NBLSET_Pos (22U)
+#define FMC_BCR4_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
+#define FMC_BCR4_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
+#define FMC_BCR4_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
+#define FMC_BCR4_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET_Pos (0U)
+#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos (4U)
+#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos (8U)
+#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos (16U)
+#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos (20U)
+#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos (24U)
+#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos (28U)
+#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BTR1_DATAHLD_Pos (30U)
+#define FMC_BTR1_DATAHLD_Msk (0x3U << FMC_BTR1_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BTR1_DATAHLD FMC_BTR1_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BTR1_DATAHLD_0 (0x1U << FMC_BTR1_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BTR1_DATAHLD_1 (0x2U << FMC_BTR1_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET_Pos (0U)
+#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos (4U)
+#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos (8U)
+#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos (16U)
+#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos (20U)
+#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos (24U)
+#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos (28U)
+#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BTR2_DATAHLD_Pos (30U)
+#define FMC_BTR2_DATAHLD_Msk (0x3U << FMC_BTR2_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BTR2_DATAHLD FMC_BTR2_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BTR2_DATAHLD_0 (0x1U << FMC_BTR2_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BTR2_DATAHLD_1 (0x2U << FMC_BTR2_DATAHLD_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET_Pos (0U)
+#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos (4U)
+#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos (8U)
+#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos (16U)
+#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos (20U)
+#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos (24U)
+#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos (28U)
+#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BTR3_DATAHLD_Pos (30U)
+#define FMC_BTR3_DATAHLD_Msk (0x3U << FMC_BTR3_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BTR3_DATAHLD FMC_BTR3_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BTR3_DATAHLD_0 (0x1U << FMC_BTR3_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BTR3_DATAHLD_1 (0x2U << FMC_BTR3_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET_Pos (0U)
+#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos (4U)
+#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos (8U)
+#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos (16U)
+#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos (20U)
+#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos (24U)
+#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos (28U)
+#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BTR4_DATAHLD_Pos (30U)
+#define FMC_BTR4_DATAHLD_Msk (0x3U << FMC_BTR4_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BTR4_DATAHLD FMC_BTR4_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BTR4_DATAHLD_0 (0x1U << FMC_BTR4_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BTR4_DATAHLD_1 (0x2U << FMC_BTR4_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PCSCNTR register *****************/
+#define FMC_PCSCNTR_CSCOUNT_Pos (0U)
+#define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFU << FMC_PCSCNTR_CSCOUNT_Pos) /*!< 0x0000FFFF */
+#define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk /*!<CSCOUNT[15:0] bits Chip Select (CS) counter */
+
+#define FMC_PCSCNTR_CNTB1EN_Pos (16U)
+#define FMC_PCSCNTR_CNTB1EN_Msk (0x1U << FMC_PCSCNTR_CNTB1EN_Pos) /*!< 0x00010000 */
+#define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk /*!<CNTB1EN bit Counter Bank1 enable */
+
+#define FMC_PCSCNTR_CNTB2EN_Pos (17U)
+#define FMC_PCSCNTR_CNTB2EN_Msk (0x1U << FMC_PCSCNTR_CNTB2EN_Pos) /*!< 0x00020000 */
+#define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk /*!<CNTB2EN bit Counter Bank2 enable */
+
+#define FMC_PCSCNTR_CNTB3EN_Pos (18U)
+#define FMC_PCSCNTR_CNTB3EN_Msk (0x1U << FMC_PCSCNTR_CNTB3EN_Pos) /*!< 0x00040000 */
+#define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk /*!<CNTB3EN bit Counter Bank3 enable */
+
+#define FMC_PCSCNTR_CNTB4EN_Pos (19U)
+#define FMC_PCSCNTR_CNTB4EN_Msk (0x1U << FMC_PCSCNTR_CNTB4EN_Pos) /*!< 0x00080000 */
+#define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk /*!<CNTB4EN bit Counter Bank4 enable */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET_Pos (0U)
+#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos (4U)
+#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos (8U)
+#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR1_CLKDIV_Pos (20U)
+#define FMC_BWTR1_CLKDIV_Msk (0xFU << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BWTR1_CLKDIV FMC_BWTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR1_CLKDIV_0 (0x1U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BWTR1_CLKDIV_1 (0x2U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BWTR1_CLKDIV_2 (0x4U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BWTR1_CLKDIV_3 (0x8U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BWTR1_DATLAT_Pos (24U)
+#define FMC_BWTR1_DATLAT_Msk (0xFU << FMC_BWTR1_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BWTR1_DATLAT FMC_BWTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR1_DATLAT_0 (0x1U << FMC_BWTR1_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BWTR1_DATLAT_1 (0x2U << FMC_BWTR1_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BWTR1_DATLAT_2 (0x4U << FMC_BWTR1_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BWTR1_DATLAT_3 (0x8U << FMC_BWTR1_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BWTR1_BUSTURN_Pos (16U)
+#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
+
+
+#define FMC_BWTR1_ACCMOD_Pos (28U)
+#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BWTR1_DATAHLD_Pos (30U)
+#define FMC_BWTR1_DATAHLD_Msk (0x3U << FMC_BWTR1_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BWTR1_DATAHLD FMC_BWTR1_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BWTR1_DATAHLD_0 (0x1U << FMC_BWTR1_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BWTR1_DATAHLD_1 (0x2U << FMC_BWTR1_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET_Pos (0U)
+#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos (4U)
+#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos (8U)
+#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR2_CLKDIV_Pos (20U)
+#define FMC_BWTR2_CLKDIV_Msk (0xFU << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BWTR2_CLKDIV FMC_BWTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR2_CLKDIV_0 (0x1U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BWTR2_CLKDIV_1 (0x2U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BWTR2_CLKDIV_2 (0x4U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BWTR2_CLKDIV_3 (0x8U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BWTR2_DATLAT_Pos (24U)
+#define FMC_BWTR2_DATLAT_Msk (0xFU << FMC_BWTR2_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BWTR2_DATLAT FMC_BWTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR2_DATLAT_0 (0x1U << FMC_BWTR2_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BWTR2_DATLAT_1 (0x2U << FMC_BWTR2_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BWTR2_DATLAT_2 (0x4U << FMC_BWTR2_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BWTR2_DATLAT_3 (0x8U << FMC_BWTR2_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BWTR2_ACCMOD_Pos (28U)
+#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BWTR2_DATAHLD_Pos (30U)
+#define FMC_BWTR2_DATAHLD_Msk (0x3U << FMC_BWTR2_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BWTR2_DATAHLD FMC_BWTR2_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BWTR2_DATAHLD_0 (0x1U << FMC_BWTR2_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BWTR2_DATAHLD_1 (0x2U << FMC_BWTR2_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET_Pos (0U)
+#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos (4U)
+#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos (8U)
+#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR3_CLKDIV_Pos (20U)
+#define FMC_BWTR3_CLKDIV_Msk (0xFU << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BWTR3_CLKDIV FMC_BWTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR3_CLKDIV_0 (0x1U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BWTR3_CLKDIV_1 (0x2U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BWTR3_CLKDIV_2 (0x4U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BWTR3_CLKDIV_3 (0x8U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BWTR3_DATLAT_Pos (24U)
+#define FMC_BWTR3_DATLAT_Msk (0xFU << FMC_BWTR3_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BWTR3_DATLAT FMC_BWTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR3_DATLAT_0 (0x1U << FMC_BWTR3_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BWTR3_DATLAT_1 (0x2U << FMC_BWTR3_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BWTR3_DATLAT_2 (0x4U << FMC_BWTR3_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BWTR3_DATLAT_3 (0x8U << FMC_BWTR3_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BWTR3_ACCMOD_Pos (28U)
+#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BWTR3_DATAHLD_Pos (30U)
+#define FMC_BWTR3_DATAHLD_Msk (0x3U << FMC_BWTR3_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BWTR3_DATAHLD FMC_BWTR3_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BWTR3_DATAHLD_0 (0x1U << FMC_BWTR3_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BWTR3_DATAHLD_1 (0x2U << FMC_BWTR3_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET_Pos (0U)
+#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos (4U)
+#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos (8U)
+#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
+
+#define FMC_BWTR4_CLKDIV_Pos (20U)
+#define FMC_BWTR4_CLKDIV_Msk (0xFU << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00F00000 */
+#define FMC_BWTR4_CLKDIV FMC_BWTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR4_CLKDIV_0 (0x1U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00100000 */
+#define FMC_BWTR4_CLKDIV_1 (0x2U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00200000 */
+#define FMC_BWTR4_CLKDIV_2 (0x4U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00400000 */
+#define FMC_BWTR4_CLKDIV_3 (0x8U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00800000 */
+
+#define FMC_BWTR4_DATLAT_Pos (24U)
+#define FMC_BWTR4_DATLAT_Msk (0xFU << FMC_BWTR4_DATLAT_Pos) /*!< 0x0F000000 */
+#define FMC_BWTR4_DATLAT FMC_BWTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR4_DATLAT_0 (0x1U << FMC_BWTR4_DATLAT_Pos) /*!< 0x01000000 */
+#define FMC_BWTR4_DATLAT_1 (0x2U << FMC_BWTR4_DATLAT_Pos) /*!< 0x02000000 */
+#define FMC_BWTR4_DATLAT_2 (0x4U << FMC_BWTR4_DATLAT_Pos) /*!< 0x04000000 */
+#define FMC_BWTR4_DATLAT_3 (0x8U << FMC_BWTR4_DATLAT_Pos) /*!< 0x08000000 */
+
+#define FMC_BWTR4_ACCMOD_Pos (28U)
+#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
+
+#define FMC_BWTR4_DATAHLD_Pos (30U)
+#define FMC_BWTR4_DATAHLD_Msk (0x3U << FMC_BWTR4_DATAHLD_Pos) /*!< 0xC0000000 */
+#define FMC_BWTR4_DATAHLD FMC_BWTR4_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
+#define FMC_BWTR4_DATAHLD_0 (0x1U << FMC_BWTR4_DATAHLD_Pos) /*!< 0x40000000 */
+#define FMC_BWTR4_DATAHLD_1 (0x2U << FMC_BWTR4_DATAHLD_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PCR register *******************/
+#define FMC_PCR_PWAITEN_Pos (1U)
+#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
+#define FMC_PCR_PBKEN_Pos (2U)
+#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
+
+#define FMC_PCR_PWID_Pos (4U)
+#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
+#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos (6U)
+#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
+
+#define FMC_PCR_ECCALG_Pos (8U)
+#define FMC_PCR_ECCALG_Msk (0x1U << FMC_PCR_ECCALG_Pos) /*!< 0x00000100 */
+#define FMC_PCR_ECCALG FMC_PCR_ECCEN_Msk /*!<ECC algorithm */
+
+#define FMC_PCR_TCLR_Pos (9U)
+#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos (13U)
+#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
+#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
+#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
+#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
+
+#define FMC_PCR_ECCSS_Pos (17U)
+#define FMC_PCR_ECCSS_Msk (0x7U << FMC_PCR_ECCSS_Pos) /*!< 0x000E0000 */
+#define FMC_PCR_ECCSS FMC_PCR_ECCSS_Msk /*!<ECCSS[1:0] bits (ECC sector size) */
+#define FMC_PCR_ECCSS_0 (0x1U << FMC_PCR_ECCSS_Pos) /*!< 0x00020000 */
+#define FMC_PCR_ECCSS_1 (0x2U << FMC_PCR_ECCSS_Pos) /*!< 0x00040000 */
+#define FMC_PCR_ECCSS_2 (0x4U << FMC_PCR_ECCSS_Pos) /*!< 0x00080000 */
+
+#define FMC_PCR_TCEH_Pos (20U)
+#define FMC_PCR_TCEH_Msk (0xFU << FMC_PCR_TCEH_Pos) /*!< 0x00F00000 */
+#define FMC_PCR_TCEH FMC_PCR_TCEH_Msk /*!<TCEH[3:0] bits (Chip select high timing) */
+
+#define FMC_PCR_BCHECC_Pos (24U)
+#define FMC_PCR_BCHECC_Msk (0x1U << FMC_PCR_BCHECC_Pos) /*!< 0x01000000 */
+#define FMC_PCR_BCHECC FMC_PCR_BCHECC_Msk /*!<BCHECC bit (BCH error correction capability) */
+
+#define FMC_PCR_WEN_Pos (25U)
+#define FMC_PCR_WEN_Msk (0x1U << FMC_PCR_WEN_Pos) /*!< 0x02000000 */
+#define FMC_PCR_WEN FMC_PCR_WEN_Msk /*!<WEN bit (Write enable) */
+
+/******************* Bit definition for FMC_SR register *******************/
+#define FMC_SR_ISOST_Pos (0U)
+#define FMC_SR_ISOST_Msk (0x3U << FMC_SR_ISOST_Pos) /*!< 0x00000003 */
+#define FMC_SR_ISOST FMC_SR_ISOST_Msk /*!<ISOST[1:0] bits (FMC isolation state with respect to the AXI interface) */
+
+#define FMC_SR_PEF_Pos (4U)
+#define FMC_SR_PEF_Msk (0x1U << FMC_SR_PEF_Pos) /*!< 0x00000010 */
+#define FMC_SR_PEF FMC_SR_PEF_Msk /*!<Pipe Empty Flag */
+
+#define FMC_SR_NWRF_Pos (6U)
+#define FMC_SR_NWRF_Msk (0x1U << FMC_SR_NWRF_Pos) /*!< 0x00000040 */
+#define FMC_SR_NWRF FMC_SR_NWRF_Msk /*!<NAND write request flag */
+
+
+/****************** Bit definition for FMC_PMEM register ******************/
+#define FMC_PMEM_MEMSET3_Pos (0U)
+#define FMC_PMEM_MEMSET3_Msk (0xFFU << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM_MEMSET3_0 (0x01U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET3_1 (0x02U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET3_2 (0x04U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET3_3 (0x08U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET3_4 (0x10U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET3_5 (0x20U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET3_6 (0x40U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET3_7 (0x80U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT3_Pos (8U)
+#define FMC_PMEM_MEMWAIT3_Msk (0xFFU << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM_MEMWAIT3_0 (0x01U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT3_1 (0x02U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT3_2 (0x04U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT3_3 (0x08U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT3_4 (0x10U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT3_5 (0x20U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT3_6 (0x40U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT3_7 (0x80U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD3_Pos (16U)
+#define FMC_PMEM_MEMHOLD3_Msk (0xFFU << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM_MEMHOLD3_0 (0x01U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD3_1 (0x02U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD3_2 (0x04U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD3_3 (0x08U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD3_4 (0x10U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD3_5 (0x20U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD3_6 (0x40U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD3_7 (0x80U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ3_Pos (24U)
+#define FMC_PMEM_MEMHIZ3_Msk (0xFFU << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM_MEMHIZ3_0 (0x01U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ3_1 (0x02U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ3_2 (0x04U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ3_3 (0x08U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ3_4 (0x10U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ3_5 (0x20U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ3_6 (0x40U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ3_7 (0x80U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PATT register ******************/
+#define FMC_PATT_ATTSET3_Pos (0U)
+#define FMC_PATT_ATTSET3_Msk (0xFFU << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
+#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT_ATTSET3_0 (0x01U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
+#define FMC_PATT_ATTSET3_1 (0x02U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
+#define FMC_PATT_ATTSET3_2 (0x04U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
+#define FMC_PATT_ATTSET3_3 (0x08U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
+#define FMC_PATT_ATTSET3_4 (0x10U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
+#define FMC_PATT_ATTSET3_5 (0x20U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
+#define FMC_PATT_ATTSET3_6 (0x40U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
+#define FMC_PATT_ATTSET3_7 (0x80U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT3_Pos (8U)
+#define FMC_PATT_ATTWAIT3_Msk (0xFFU << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT_ATTWAIT3_0 (0x01U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT3_1 (0x02U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT3_2 (0x04U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT3_3 (0x08U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT3_4 (0x10U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT3_5 (0x20U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT3_6 (0x40U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT3_7 (0x80U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD3_Pos (16U)
+#define FMC_PATT_ATTHOLD3_Msk (0xFFU << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT_ATTHOLD3_0 (0x01U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD3_1 (0x02U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD3_2 (0x04U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD3_3 (0x08U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD3_4 (0x10U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD3_5 (0x20U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD3_6 (0x40U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD3_7 (0x80U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ3_Pos (24U)
+#define FMC_PATT_ATTHIZ3_Msk (0xFFU << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT_ATTHIZ3_0 (0x01U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ3_1 (0x02U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ3_2 (0x04U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ3_3 (0x08U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ3_4 (0x10U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ3_5 (0x20U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ3_6 (0x40U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ3_7 (0x80U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4_Pos (0U)
+#define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
+#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
+#define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
+#define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
+#define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
+#define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
+#define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
+#define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
+#define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
+
+#define FMC_PIO4_IOWAIT4_Pos (8U)
+#define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
+#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
+#define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
+#define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
+#define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
+#define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
+#define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
+#define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
+#define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
+
+#define FMC_PIO4_IOHOLD4_Pos (16U)
+#define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
+#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
+#define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
+#define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
+#define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
+#define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
+#define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
+#define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
+#define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
+
+#define FMC_PIO4_IOHIZ4_Pos (24U)
+#define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
+#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
+#define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
+#define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
+#define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
+#define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
+#define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
+#define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
+#define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
+
+/********************** Bit definition for FMC_VERR register *****************/
+#define FMC_VERR_MINREV_Pos (0U)
+#define FMC_VERR_MINREV_Msk (0xFU << FMC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define FMC_VERR_MINREV FMC_VERR_MINREV_Msk /*!< Minor Revision number */
+#define FMC_VERR_MAJREV_Pos (4U)
+#define FMC_VERR_MAJREV_Msk (0xFU << FMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define FMC_VERR_MAJREV FMC_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for FMC_IPIDR register ****************/
+#define FMC_IPIDR_IPID_Pos (0U)
+#define FMC_IPIDR_IPID_Msk (0xFFFFFFFFU << FMC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define FMC_IPIDR_IPID FMC_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for FMC_SIDR register *****************/
+#define FMC_SIDR_SID_Pos (0U)
+#define FMC_SIDR_SID_Msk (0xFFFFFFFFU << FMC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define FMC_SIDR_SID FMC_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O */
+/* */
+/******************************************************************************/
+/****************** Bits definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0_Pos (0U)
+#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
+
+#define GPIO_MODER_MODER1_Pos (2U)
+#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
+
+#define GPIO_MODER_MODER2_Pos (4U)
+#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
+
+#define GPIO_MODER_MODER3_Pos (6U)
+#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
+
+#define GPIO_MODER_MODER4_Pos (8U)
+#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
+
+#define GPIO_MODER_MODER5_Pos (10U)
+#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
+
+#define GPIO_MODER_MODER6_Pos (12U)
+#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
+
+#define GPIO_MODER_MODER7_Pos (14U)
+#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
+
+#define GPIO_MODER_MODER8_Pos (16U)
+#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
+
+#define GPIO_MODER_MODER9_Pos (18U)
+#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
+
+#define GPIO_MODER_MODER10_Pos (20U)
+#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
+
+#define GPIO_MODER_MODER11_Pos (22U)
+#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
+
+#define GPIO_MODER_MODER12_Pos (24U)
+#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
+
+#define GPIO_MODER_MODER13_Pos (26U)
+#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
+
+#define GPIO_MODER_MODER14_Pos (28U)
+#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
+
+#define GPIO_MODER_MODER15_Pos (30U)
+#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT0_Pos (0U)
+#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos (1U)
+#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos (2U)
+#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos (3U)
+#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos (4U)
+#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos (5U)
+#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos (6U)
+#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos (7U)
+#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos (8U)
+#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos (9U)
+#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos (10U)
+#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos (11U)
+#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos (12U)
+#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos (13U)
+#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos (14U)
+#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos (15U)
+#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
+
+/****************** Bits definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
+#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
+#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
+
+#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
+#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
+#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
+
+#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
+#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
+#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
+
+#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
+#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
+#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
+
+#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
+#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
+#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
+
+#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
+#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
+#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
+
+#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
+#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
+#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
+
+#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
+#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
+#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
+
+#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
+#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
+#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
+
+#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
+#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
+#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
+
+#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
+#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
+#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
+
+#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
+#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
+#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
+
+#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
+#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
+#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
+
+#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
+#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
+#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
+
+#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
+#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
+#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
+
+#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
+#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
+#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0_Pos (0U)
+#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
+#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPDR1_Pos (2U)
+#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
+#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPDR2_Pos (4U)
+#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
+#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPDR3_Pos (6U)
+#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
+#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPDR4_Pos (8U)
+#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
+#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPDR5_Pos (10U)
+#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
+#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPDR6_Pos (12U)
+#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
+#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPDR7_Pos (14U)
+#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
+#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPDR8_Pos (16U)
+#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
+#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPDR9_Pos (18U)
+#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
+#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPDR10_Pos (20U)
+#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
+#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPDR11_Pos (22U)
+#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
+#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPDR12_Pos (24U)
+#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
+#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPDR13_Pos (26U)
+#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
+#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPDR14_Pos (28U)
+#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
+#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPDR15_Pos (30U)
+#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
+#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0_Pos (0U)
+#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk
+#define GPIO_IDR_IDR1_Pos (1U)
+#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk
+#define GPIO_IDR_IDR2_Pos (2U)
+#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk
+#define GPIO_IDR_IDR3_Pos (3U)
+#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk
+#define GPIO_IDR_IDR4_Pos (4U)
+#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk
+#define GPIO_IDR_IDR5_Pos (5U)
+#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk
+#define GPIO_IDR_IDR6_Pos (6U)
+#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk
+#define GPIO_IDR_IDR7_Pos (7U)
+#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk
+#define GPIO_IDR_IDR8_Pos (8U)
+#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk
+#define GPIO_IDR_IDR9_Pos (9U)
+#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk
+#define GPIO_IDR_IDR10_Pos (10U)
+#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk
+#define GPIO_IDR_IDR11_Pos (11U)
+#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk
+#define GPIO_IDR_IDR12_Pos (12U)
+#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk
+#define GPIO_IDR_IDR13_Pos (13U)
+#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk
+#define GPIO_IDR_IDR14_Pos (14U)
+#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk
+#define GPIO_IDR_IDR15_Pos (15U)
+#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0_Pos (0U)
+#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk
+#define GPIO_ODR_ODR1_Pos (1U)
+#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk
+#define GPIO_ODR_ODR2_Pos (2U)
+#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk
+#define GPIO_ODR_ODR3_Pos (3U)
+#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk
+#define GPIO_ODR_ODR4_Pos (4U)
+#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk
+#define GPIO_ODR_ODR5_Pos (5U)
+#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk
+#define GPIO_ODR_ODR6_Pos (6U)
+#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk
+#define GPIO_ODR_ODR7_Pos (7U)
+#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk
+#define GPIO_ODR_ODR8_Pos (8U)
+#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk
+#define GPIO_ODR_ODR9_Pos (9U)
+#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk
+#define GPIO_ODR_ODR10_Pos (10U)
+#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk
+#define GPIO_ODR_ODR11_Pos (11U)
+#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk
+#define GPIO_ODR_ODR12_Pos (12U)
+#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk
+#define GPIO_ODR_ODR13_Pos (13U)
+#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk
+#define GPIO_ODR_ODR14_Pos (14U)
+#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk
+#define GPIO_ODR_ODR15_Pos (15U)
+#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk
+
+/****************** Bits definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS0_Pos (0U)
+#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos (1U)
+#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos (2U)
+#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos (3U)
+#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos (4U)
+#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos (5U)
+#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos (6U)
+#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos (7U)
+#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos (8U)
+#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos (9U)
+#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos (10U)
+#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos (11U)
+#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos (12U)
+#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos (13U)
+#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos (14U)
+#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos (15U)
+#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos (16U)
+#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos (17U)
+#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos (18U)
+#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos (19U)
+#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos (20U)
+#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos (21U)
+#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos (22U)
+#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos (23U)
+#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos (24U)
+#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos (25U)
+#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos (26U)
+#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos (27U)
+#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos (28U)
+#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos (29U)
+#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos (30U)
+#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos (31U)
+#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFR0_Pos (0U)
+#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk
+#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */
+#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */
+#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */
+#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */
+#define GPIO_AFRL_AFR1_Pos (4U)
+#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk
+#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */
+#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */
+#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */
+#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */
+#define GPIO_AFRL_AFR2_Pos (8U)
+#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk
+#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */
+#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */
+#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */
+#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */
+#define GPIO_AFRL_AFR3_Pos (12U)
+#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk
+#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */
+#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */
+#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */
+#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */
+#define GPIO_AFRL_AFR4_Pos (16U)
+#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk
+#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */
+#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */
+#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */
+#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */
+#define GPIO_AFRL_AFR5_Pos (20U)
+#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk
+#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */
+#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */
+#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */
+#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */
+#define GPIO_AFRL_AFR6_Pos (24U)
+#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk
+#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */
+#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */
+#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */
+#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */
+#define GPIO_AFRL_AFR7_Pos (28U)
+#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk
+#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */
+#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */
+#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */
+#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFR8_Pos (0U)
+#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk
+#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */
+#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */
+#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */
+#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */
+#define GPIO_AFRH_AFR9_Pos (4U)
+#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk
+#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */
+#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */
+#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */
+#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */
+#define GPIO_AFRH_AFR10_Pos (8U)
+#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk
+#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */
+#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */
+#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */
+#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */
+#define GPIO_AFRH_AFR11_Pos (12U)
+#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk
+#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */
+#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */
+#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */
+#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */
+#define GPIO_AFRH_AFR12_Pos (16U)
+#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk
+#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */
+#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */
+#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */
+#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */
+#define GPIO_AFRH_AFR13_Pos (20U)
+#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk
+#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */
+#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */
+#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */
+#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */
+#define GPIO_AFRH_AFR14_Pos (24U)
+#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk
+#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */
+#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */
+#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */
+#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */
+#define GPIO_AFRH_AFR15_Pos (28U)
+#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk
+#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */
+#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */
+#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */
+#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */
+
+/****************** Bits definition for GPIO_BRR register ******************/
+#define GPIO_BRR_BR0_Pos (0U)
+#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
+#define GPIO_BRR_BR1_Pos (1U)
+#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
+#define GPIO_BRR_BR2_Pos (2U)
+#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
+#define GPIO_BRR_BR3_Pos (3U)
+#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
+#define GPIO_BRR_BR4_Pos (4U)
+#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
+#define GPIO_BRR_BR5_Pos (5U)
+#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
+#define GPIO_BRR_BR6_Pos (6U)
+#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
+#define GPIO_BRR_BR7_Pos (7U)
+#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
+#define GPIO_BRR_BR8_Pos (8U)
+#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
+#define GPIO_BRR_BR9_Pos (9U)
+#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
+#define GPIO_BRR_BR10_Pos (10U)
+#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
+#define GPIO_BRR_BR11_Pos (11U)
+#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
+#define GPIO_BRR_BR12_Pos (12U)
+#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
+#define GPIO_BRR_BR13_Pos (13U)
+#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
+#define GPIO_BRR_BR14_Pos (14U)
+#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
+#define GPIO_BRR_BR15_Pos (15U)
+#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
+
+/****************** Bits definition for GPIO_SECCFGR register ******************/
+#define GPIO_SECCFGR_SEC0_Pos (0U)
+#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */
+#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk
+#define GPIO_SECCFGR_SEC1_Pos (1U)
+#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */
+#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk
+#define GPIO_SECCFGR_SEC2_Pos (2U)
+#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */
+#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk
+#define GPIO_SECCFGR_SEC3_Pos (3U)
+#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */
+#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk
+#define GPIO_SECCFGR_SEC4_Pos (4U)
+#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */
+#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk
+#define GPIO_SECCFGR_SEC5_Pos (5U)
+#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */
+#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk
+#define GPIO_SECCFGR_SEC6_Pos (6U)
+#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */
+#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk
+#define GPIO_SECCFGR_SEC7_Pos (7U)
+#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */
+#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk
+
+/*************** Bit definition for GPIO_HWCFGR10 register ****************/
+#define GPIO_HWCFGR10_AHB_IOP_Pos (0U)
+#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */
+#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */
+#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR10_AF_SIZE_Pos (4U)
+#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */
+#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */
+#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U)
+#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */
+#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */
+#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U)
+#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */
+#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */
+#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR10_SEC_CFG_Pos (16U)
+#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */
+#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */
+#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR10_OR_CFG_Pos (20U)
+#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */
+#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */
+#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */
+
+/**************** Bit definition for GPIO_HWCFGR9 register ****************/
+#define GPIO_HWCFGR9_EN_IO_Pos (0U)
+#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */
+#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */
+#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */
+
+/**************** Bit definition for GPIO_HWCFGR8 register ****************/
+#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U)
+#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */
+#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U)
+#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */
+#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U)
+#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */
+#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U)
+#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */
+#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U)
+#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */
+#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U)
+#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */
+#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U)
+#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */
+#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U)
+#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */
+#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */
+#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR7 register ****************/
+#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U)
+#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */
+#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U)
+#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */
+#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U)
+#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */
+#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U)
+#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */
+#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U)
+#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */
+#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U)
+#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */
+#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U)
+#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */
+#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U)
+#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */
+#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */
+#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR6 register ****************/
+#define GPIO_HWCFGR6_MODER_RES_Pos (0U)
+#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */
+#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */
+#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR5 register ****************/
+#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U)
+#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */
+#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */
+#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR4 register ****************/
+#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U)
+#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */
+#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */
+#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR3 register ****************/
+#define GPIO_HWCFGR3_ODR_RES_Pos (0U)
+#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */
+#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */
+#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U)
+#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */
+#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */
+#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR2 register ****************/
+#define GPIO_HWCFGR2_AFRL_RES_Pos (0U)
+#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */
+#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */
+#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR1 register ****************/
+#define GPIO_HWCFGR1_AFRH_RES_Pos (0U)
+#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */
+#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */
+#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */
+#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */
+#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */
+#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */
+#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */
+#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */
+#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */
+#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */
+#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */
+#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */
+#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */
+#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */
+#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */
+#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */
+#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */
+#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */
+#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */
+
+/**************** Bit definition for GPIO_HWCFGR0 register ****************/
+#define GPIO_HWCFGR0_OR_RES_Pos (0U)
+#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */
+#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */
+#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */
+#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */
+#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */
+#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */
+#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */
+#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */
+#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */
+#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */
+#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */
+#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */
+#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */
+#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */
+#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */
+#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */
+#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */
+#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */
+
+/********************** Bit definition for GPIO_VERR register *****************/
+#define GPIO_VERR_MINREV_Pos (0U)
+#define GPIO_VERR_MINREV_Msk (0xFU << GPIO_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define GPIO_VERR_MINREV GPIO_VERR_MINREV_Msk /*!< Minor Revision number */
+#define GPIO_VERR_MAJREV_Pos (4U)
+#define GPIO_VERR_MAJREV_Msk (0xFU << GPIO_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define GPIO_VERR_MAJREV GPIO_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for GPIO_IPIDR register ****************/
+#define GPIO_IPIDR_IPID_Pos (0U)
+#define GPIO_IPIDR_IPID_Msk (0xFFFFFFFFU << GPIO_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define GPIO_IPIDR_IPID GPIO_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for GPIO_SIDR register *****************/
+#define GPIO_SIDR_SID_Pos (0U)
+#define GPIO_SIDR_SID_Msk (0xFFFFFFFFU << GPIO_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define GPIO_SIDR_SID GPIO_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* HSEM HW Semaphore */
+/* */
+/******************************************************************************/
+/******************** Bit definition for HSEM_R register ********************/
+#define HSEM_R_PROCID_Pos (0U)
+#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
+#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
+#define HSEM_R_COREID_Pos (8U)
+#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
+#define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
+#define HSEM_R_LOCK_Pos (31U)
+#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
+#define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
+
+/******************** Bit definition for HSEM_RLR register ******************/
+#define HSEM_RLR_PROCID_Pos (0U)
+#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
+#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
+#define HSEM_RLR_COREID_Pos (8U)
+#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
+#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
+#define HSEM_RLR_LOCK_Pos (31U)
+#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
+#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
+
+/******************** Bit definition for HSEM_C1IER register *****************/
+#define HSEM_C1IER_ISE0_Pos (0U)
+#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
+#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE1_Pos (1U)
+#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
+#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE2_Pos (2U)
+#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
+#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE3_Pos (3U)
+#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
+#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE4_Pos (4U)
+#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
+#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE5_Pos (5U)
+#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
+#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE6_Pos (6U)
+#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
+#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE7_Pos (7U)
+#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
+#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE8_Pos (8U)
+#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
+#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE9_Pos (9U)
+#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
+#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE10_Pos (10U)
+#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
+#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE11_Pos (11U)
+#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
+#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE12_Pos (12U)
+#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
+#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE13_Pos (13U)
+#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
+#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE14_Pos (14U)
+#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
+#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE15_Pos (15U)
+#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
+#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE16_Pos (16U)
+#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
+#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE17_Pos (17U)
+#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
+#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE18_Pos (18U)
+#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
+#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE19_Pos (19U)
+#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
+#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE20_Pos (20U)
+#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
+#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE21_Pos (21U)
+#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
+#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE22_Pos (22U)
+#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
+#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE23_Pos (23U)
+#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
+#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE24_Pos (24U)
+#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
+#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE25_Pos (25U)
+#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
+#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE26_Pos (26U)
+#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
+#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE27_Pos (27U)
+#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
+#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE28_Pos (28U)
+#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
+#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE29_Pos (29U)
+#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
+#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE30_Pos (30U)
+#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
+#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE31_Pos (31U)
+#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
+#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
+
+/******************** Bit definition for HSEM_C1ICR register *****************/
+#define HSEM_C1ICR_ISC0_Pos (0U)
+#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
+#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC1_Pos (1U)
+#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
+#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC2_Pos (2U)
+#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
+#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC3_Pos (3U)
+#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
+#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC4_Pos (4U)
+#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
+#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC5_Pos (5U)
+#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
+#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC6_Pos (6U)
+#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
+#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC7_Pos (7U)
+#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
+#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC8_Pos (8U)
+#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
+#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC9_Pos (9U)
+#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
+#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC10_Pos (10U)
+#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
+#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC11_Pos (11U)
+#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
+#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC12_Pos (12U)
+#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
+#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC13_Pos (13U)
+#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
+#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC14_Pos (14U)
+#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
+#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC15_Pos (15U)
+#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
+#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC16_Pos (16U)
+#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
+#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC17_Pos (17U)
+#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
+#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC18_Pos (18U)
+#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
+#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC19_Pos (19U)
+#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
+#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC20_Pos (20U)
+#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
+#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC21_Pos (21U)
+#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
+#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC22_Pos (22U)
+#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
+#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC23_Pos (23U)
+#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
+#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC24_Pos (24U)
+#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
+#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC25_Pos (25U)
+#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
+#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC26_Pos (26U)
+#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
+#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC27_Pos (27U)
+#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
+#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC28_Pos (28U)
+#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
+#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC29_Pos (29U)
+#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
+#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC30_Pos (30U)
+#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
+#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC31_Pos (31U)
+#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
+#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
+
+/******************** Bit definition for HSEM_C1ISR register *****************/
+#define HSEM_C1ISR_ISF0_Pos (0U)
+#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
+#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF1_Pos (1U)
+#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
+#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF2_Pos (2U)
+#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
+#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF3_Pos (3U)
+#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
+#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF4_Pos (4U)
+#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
+#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF5_Pos (5U)
+#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
+#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF6_Pos (6U)
+#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
+#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF7_Pos (7U)
+#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
+#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF8_Pos (8U)
+#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
+#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF9_Pos (9U)
+#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
+#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF10_Pos (10U)
+#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
+#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF11_Pos (11U)
+#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
+#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF12_Pos (12U)
+#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
+#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF13_Pos (13U)
+#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
+#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF14_Pos (14U)
+#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
+#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF15_Pos (15U)
+#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
+#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF16_Pos (16U)
+#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
+#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF17_Pos (17U)
+#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
+#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF18_Pos (18U)
+#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
+#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF19_Pos (19U)
+#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
+#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF20_Pos (20U)
+#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
+#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF21_Pos (21U)
+#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
+#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF22_Pos (22U)
+#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
+#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF23_Pos (23U)
+#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
+#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF24_Pos (24U)
+#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
+#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF25_Pos (25U)
+#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
+#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF26_Pos (26U)
+#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
+#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF27_Pos (27U)
+#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
+#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF28_Pos (28U)
+#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
+#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF29_Pos (29U)
+#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
+#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF30_Pos (30U)
+#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
+#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF31_Pos (31U)
+#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
+#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
+
+/******************** Bit definition for HSEM_C1MISR register *****************/
+#define HSEM_C1MISR_MISF0_Pos (0U)
+#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
+#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF1_Pos (1U)
+#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
+#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF2_Pos (2U)
+#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
+#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF3_Pos (3U)
+#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
+#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF4_Pos (4U)
+#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
+#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF5_Pos (5U)
+#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
+#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF6_Pos (6U)
+#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
+#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF7_Pos (7U)
+#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
+#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF8_Pos (8U)
+#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
+#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF9_Pos (9U)
+#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
+#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF10_Pos (10U)
+#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
+#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF11_Pos (11U)
+#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
+#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF12_Pos (12U)
+#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
+#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF13_Pos (13U)
+#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
+#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF14_Pos (14U)
+#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
+#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF15_Pos (15U)
+#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
+#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF16_Pos (16U)
+#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
+#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF17_Pos (17U)
+#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
+#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF18_Pos (18U)
+#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
+#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF19_Pos (19U)
+#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
+#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF20_Pos (20U)
+#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
+#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF21_Pos (21U)
+#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
+#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF22_Pos (22U)
+#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
+#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF23_Pos (23U)
+#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
+#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF24_Pos (24U)
+#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
+#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF25_Pos (25U)
+#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
+#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF26_Pos (26U)
+#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
+#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF27_Pos (27U)
+#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
+#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF28_Pos (28U)
+#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
+#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF29_Pos (29U)
+#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
+#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF30_Pos (30U)
+#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
+#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF31_Pos (31U)
+#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
+#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
+
+/******************** Bit definition for HSEM_CR register *****************/
+#define HSEM_CR_COREID_Pos (8U)
+#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
+#define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
+#define HSEM_CR_KEY_Pos (16U)
+#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
+#define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
+
+/******************** Bit definition for HSEM_KEYR register *****************/
+#define HSEM_KEYR_KEY_Pos (16U)
+#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
+#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
+
+/********************** Bit definition for HSEM_HWCFGR2 register ***************/
+#define HSEM_HWCFGR2_MASTERID1_Pos (0U)
+#define HSEM_HWCFGR2_MASTERID1_Msk (0xFU << HSEM_HWCFGR2_MASTERID1_Pos) /*!< 0x0000000F */
+#define HSEM_HWCFGR2_MASTERID1 HSEM_HWCFGR2_MASTERID1_Msk /*!< HW Config valid bus masters ID1 */
+#define HSEM_HWCFGR2_MASTERID2_Pos (4U)
+#define HSEM_HWCFGR2_MASTERID2_Msk (0xFU << HSEM_HWCFGR2_MASTERID2_Pos) /*!< 0x000000F0 */
+#define HSEM_HWCFGR2_MASTERID2 HSEM_HWCFGR2_MASTERID2_Msk /*!< HW Config valid bus masters ID2 */
+#define HSEM_HWCFGR2_MASTERID3_Pos (8U)
+#define HSEM_HWCFGR2_MASTERID3_Msk (0xFU << HSEM_HWCFGR2_MASTERID3_Pos) /*!< 0x00000F00 */
+#define HSEM_HWCFGR2_MASTERID3 HSEM_HWCFGR2_MASTERID3_Msk /*!< HW Config valid bus masters ID3 */
+#define HSEM_HWCFGR2_MASTERID4_Pos (12U)
+#define HSEM_HWCFGR2_MASTERID4_Msk (0xFU << HSEM_HWCFGR2_MASTERID4_Pos) /*!< 0x0000F000 */
+#define HSEM_HWCFGR2_MASTERID4 HSEM_HWCFGR2_MASTERID4_Msk /*!< HW Config valid bus masters ID4 */
+
+/********************** Bit definition for HSEM_HWCFGR1 register ***************/
+#define HSEM_HWCFGR1_NBSEM_Pos (0U)
+#define HSEM_HWCFGR1_NBSEM_Msk (0xFFU << HSEM_HWCFGR1_NBSEM_Pos) /*!< 0x000000FF */
+#define HSEM_HWCFGR1_NBSEM HSEM_HWCFGR1_NBSEM_Msk /*!< HW Config number of semaphores */
+#define HSEM_HWCFGR1_NBINT_Pos (8U)
+#define HSEM_HWCFGR1_NBINT_Msk (0xFU << HSEM_HWCFGR1_NBINT_Pos) /*!< 0x00000F00 */
+#define HSEM_HWCFGR1_NBINT HSEM_HWCFGR1_NBINT_Msk /*!< HW Config number of interrupts/ supported number of master IDs */
+
+
+/********************** Bit definition for HSEM_VERR register *****************/
+#define HSEM_VERR_MINREV_Pos (0U)
+#define HSEM_VERR_MINREV_Msk (0xFU << HSEM_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define HSEM_VERR_MINREV HSEM_VERR_MINREV_Msk /*!< Minor Revision number */
+#define HSEM_VERR_MAJREV_Pos (4U)
+#define HSEM_VERR_MAJREV_Msk (0xFU << HSEM_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define HSEM_VERR_MAJREV HSEM_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for HSEM_IPIDR register ****************/
+#define HSEM_IPIDR_IPID_Pos (0U)
+#define HSEM_IPIDR_IPID_Msk (0xFFFFFFFFU << HSEM_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define HSEM_IPIDR_IPID HSEM_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for HSEM_SIDR register *****************/
+#define HSEM_SIDR_SID_Pos (0U)
+#define HSEM_SIDR_SID_Msk (0xFFFFFFFFU << HSEM_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define HSEM_SIDR_SID HSEM_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* HASH */
+/* */
+/******************************************************************************/
+/****************** Bits definition for HASH_CR register ********************/
+#define HASH_CR_INIT_Pos (2U)
+#define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
+#define HASH_CR_INIT HASH_CR_INIT_Msk
+#define HASH_CR_DMAE_Pos (3U)
+#define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
+#define HASH_CR_DMAE HASH_CR_DMAE_Msk
+#define HASH_CR_DATATYPE_Pos (4U)
+#define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
+#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
+#define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos (6U)
+#define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
+#define HASH_CR_MODE HASH_CR_MODE_Msk
+#define HASH_CR_ALGO_Pos (7U)
+#define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
+#define HASH_CR_ALGO HASH_CR_ALGO_Msk
+#define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
+#define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
+#define HASH_CR_NBW_Pos (8U)
+#define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
+#define HASH_CR_NBW HASH_CR_NBW_Msk
+#define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
+#define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
+#define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
+#define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos (12U)
+#define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
+#define HASH_CR_DINNE HASH_CR_DINNE_Msk
+#define HASH_CR_MDMAT_Pos (13U)
+#define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
+#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
+#define HASH_CR_DMAA_Pos (14U)
+#define HASH_CR_DMAA_Msk (0x1U << HASH_CR_DMAA_Pos) /*!< 0x00004000 */
+#define HASH_CR_DMAA HASH_CR_DMAA_Msk
+#define HASH_CR_LKEY_Pos (16U)
+#define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
+#define HASH_CR_LKEY HASH_CR_LKEY_Msk
+
+/****************** Bits definition for HASH_STR register *******************/
+#define HASH_STR_NBLW_Pos (0U)
+#define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
+#define HASH_STR_NBLW HASH_STR_NBLW_Msk
+#define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
+#define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
+#define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
+#define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
+#define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos (8U)
+#define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
+#define HASH_STR_DCAL HASH_STR_DCAL_Msk
+
+/****************** Bits definition for HASH_IMR register *******************/
+#define HASH_IMR_DINIE_Pos (0U)
+#define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
+#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
+#define HASH_IMR_DCIE_Pos (1U)
+#define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
+#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
+
+/****************** Bits definition for HASH_SR register ********************/
+#define HASH_SR_DINIS_Pos (0U)
+#define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
+#define HASH_SR_DINIS HASH_SR_DINIS_Msk
+#define HASH_SR_DCIS_Pos (1U)
+#define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
+#define HASH_SR_DCIS HASH_SR_DCIS_Msk
+#define HASH_SR_DMAS_Pos (2U)
+#define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
+#define HASH_SR_DMAS HASH_SR_DMAS_Msk
+#define HASH_SR_BUSY_Pos (3U)
+#define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
+#define HASH_SR_BUSY HASH_SR_BUSY_Msk
+
+/********************** Bit definition for HASH_HWCFGR register ***************/
+#define HASH_HWCFGR_CFG1_Pos (0U)
+#define HASH_HWCFGR_CFG1_Msk (0xFU << HASH_HWCFGR_CFG1_Pos) /*!< 0x0000000F */
+#define HASH_HWCFGR_CFG1 HASH_HWCFGR_CFG1_Msk /*!< use_mdma generic value (0x1) */
+
+/********************** Bit definition for HASH_VERR register *****************/
+#define HASH_VERR_VER_Pos (0U)
+#define HASH_VERR_VER_Msk (0xFFU << HASH_VERR_VER_Pos) /*!< 0x0000000FF */
+#define HASH_VERR_VER HASH_VERR_VER_Msk /*!< Revision number */
+
+/********************** Bit definition for HASH_IPIDR register ****************/
+#define HASH_IPIDR_IPID_Pos (0U)
+#define HASH_IPIDR_IPID_Msk (0xFFFFFFFFU << HASH_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define HASH_IPIDR_IPID HASH_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for HASH_SIDR register *****************/
+#define HASH_MID_MID_Pos (0U)
+#define HASH_MID_MID_Msk (0xFFFFFFFFU << HASH_MID_MID_Pos) /*!< 0xFFFFFFFF */
+#define HASH_MID_MID HASH_MID_MID_Msk /*!< Magic identification */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST_Pos (13U)
+#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/********************** Bit definition for I2C_HWCFGR register ***************/
+#define I2C_HWCFGR_SMBUS_Pos (0U)
+#define I2C_HWCFGR_SMBUS_Msk (0xFU << I2C_HWCFGR_SMBUS_Pos) /*!< 0x0000000F */
+#define I2C_HWCFGR_SMBUS I2C_HWCFGR_SMBUS_Msk /*!< SMBus mode */
+#define I2C_HWCFGR_ASYN_Pos (4U)
+#define I2C_HWCFGR_ASYN_Msk (0xFU << I2C_HWCFGR_ASYN_Pos) /*!< 0x000000F0 */
+#define I2C_HWCFGR_ASYN I2C_HWCFGR_ASYN_Msk /*!< Independent kernel clock */
+#define I2C_HWCFGR_WKP_Pos (8U)
+#define I2C_HWCFGR_WKP_Msk (0xFU << I2C_HWCFGR_WKP_Pos) /*!< 0x00000F00 */
+#define I2C_HWCFGR_WKP I2C_HWCFGR_WKP_Msk /*!< Wakeup from Stop mode */
+
+/******************** Bit definition for I2C_VERR register***********************/
+#define I2C_VERR_MINREV_Pos (0U)
+#define I2C_VERR_MINREV_Msk (0xFU << I2C_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define I2C_VERR_MINREV I2C_VERR_MINREV_Msk /*Minor Revision of the IP*/
+#define I2C_VERR_MAJREV_Pos (4U)
+#define I2C_VERR_MAJREV_Msk (0xFU << I2C_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define I2C_VERR_MAJREV I2C_VERR_MAJREV_Msk /*Major Revision of the IP*/
+
+/******************** Bit definition for I2C_IPIDR register**********************/
+#define I2C_IPIDR_ID_Pos (0U)
+#define I2C_IPIDR_ID_Msk (0xFFFFFFFFU << I2C_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define I2C_IPIDR_ID I2C_IPIDR_ID_Msk /*IP Identifier*/
+
+/******************** Bit definition for I2C_SIDR register**********************/
+#define I2C_SIDR_SID_Pos (0U)
+#define I2C_SIDR_SID_Msk (0xFFFFFFFFU << I2C_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define I2C_SIDR_SID I2C_SIDR_SID_Msk /*Size Identifier*/
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0xFU << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+#define IWDG_PR_PR_3 (0x8U << IWDG_PR_PR_Pos) /*!< 0x00000008 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+#define IWDG_SR_EWU_Pos (3U)
+#define IWDG_SR_EWU_Msk (0x1U << IWDG_SR_EWU_Pos) /*!< 0x00000008 */
+#define IWDG_SR_EWU IWDG_SR_EWU_Msk /*!< Watchdog interrupt comparator value update */
+#define IWDG_SR_EWIF_Pos (14U)
+#define IWDG_SR_EWIF_Msk (0x1U << IWDG_SR_EWIF_Pos) /*!< 0x00004000 */
+#define IWDG_SR_EWIF IWDG_SR_EWIF_Msk /*!< Watchdog early interrupt flag */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************* Bit definition for IWDG_EWCR register ********************/
+#define IWDG_EWCR_EWIT_Pos (0U)
+#define IWDG_EWCR_EWIT_Msk (0xFFFU << IWDG_EWCR_EWIT_Pos) /*!< 0x00000FFF */
+#define IWDG_EWCR_EWIT IWDG_EWCR_EWIT_Msk /*!< Watchdog early wakeup comparator value */
+#define IWDG_EWCR_EWIC_Pos (14U)
+#define IWDG_EWCR_EWIC_Msk (0x1U << IWDG_EWCR_EWIC_Pos) /*!< 0x00004000 */
+#define IWDG_EWCR_EWIC IWDG_EWCR_EWIC_Msk /*!< Watchdog early interrupt acknowledge */
+#define IWDG_EWCR_EWIE_Pos (15U)
+#define IWDG_EWCR_EWIE_Msk (0x1U << IWDG_EWCR_EWIE_Pos) /*!< 0x00008000 */
+#define IWDG_EWCR_EWIE IWDG_EWCR_EWIE_Msk /*!< Watchdog early interrupt enable */
+
+/********************** Bit definition for IWDG_HWCFGR register ***************/
+#define IWDG_HWCFGR_WINDOW_Pos (0U)
+#define IWDG_HWCFGR_WINDOW_Msk (0xFU << IWDG_HWCFGR_WINDOW_Pos) /*!< 0x0000000F */
+#define IWDG_HWCFGR_WINDOW IWDG_HWCFGR_WINDOW_Msk /*!< Support of Window function */
+#define IWDG_HWCFGR_PR_DEFAULT_Pos (4U)
+#define IWDG_HWCFGR_PR_DEFAULT_Msk (0xFU << IWDG_HWCFGR_PR_DEFAULT_Pos) /*!< 0x000000F0 */
+#define IWDG_HWCFGR_PR_DEFAULT IWDG_HWCFGR_PR_DEFAULT_Msk /*!< Prescaler default value */
+
+/********************** Bit definition for IWDG_VERR register *****************/
+#define IWDG_VERR_MINREV_Pos (0U)
+#define IWDG_VERR_MINREV_Msk (0xFU << IWDG_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define IWDG_VERR_MINREV IWDG_VERR_MINREV_Msk /*!< Minor Revision number */
+#define IWDG_VERR_MAJREV_Pos (4U)
+#define IWDG_VERR_MAJREV_Msk (0xFU << IWDG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define IWDG_VERR_MAJREV IWDG_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for IWDG_IDR register ****************/
+#define IWDG_IDR_IPID_Pos (0U)
+#define IWDG_IDR_IPID_Msk (0xFFFFFFFFU << IWDG_IDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define IWDG_IDR_IPID IWDG_IDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for IWDG_SIDR register *****************/
+#define IWDG_SIDR_SID_Pos (0U)
+#define IWDG_SIDR_SID_Msk (0xFFFFFFFFU << IWDG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define IWDG_SIDR_SID IWDG_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* LCD-TFT Display Controller (LTDC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for LTDC_SSCR register *****************/
+
+#define LTDC_SSCR_VSH_Pos (0U)
+#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
+#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
+#define LTDC_SSCR_HSW_Pos (16U)
+#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
+
+/******************** Bit definition for LTDC_BPCR register *****************/
+
+#define LTDC_BPCR_AVBP_Pos (0U)
+#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
+#define LTDC_BPCR_AHBP_Pos (16U)
+#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
+
+/******************** Bit definition for LTDC_AWCR register *****************/
+
+#define LTDC_AWCR_AAH_Pos (0U)
+#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAW_Pos (16U)
+#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
+
+/******************** Bit definition for LTDC_TWCR register *****************/
+
+#define LTDC_TWCR_TOTALH_Pos (0U)
+#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALW_Pos (16U)
+#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
+
+/******************** Bit definition for LTDC_GCR register ******************/
+
+#define LTDC_GCR_LTDCEN_Pos (0U)
+#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
+#define LTDC_GCR_DBW_Pos (4U)
+#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
+#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
+#define LTDC_GCR_DGW_Pos (8U)
+#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
+#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
+#define LTDC_GCR_DRW_Pos (12U)
+#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
+#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
+#define LTDC_GCR_DEN_Pos (16U)
+#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
+#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
+#define LTDC_GCR_PCPOL_Pos (28U)
+#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
+#define LTDC_GCR_DEPOL_Pos (29U)
+#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
+#define LTDC_GCR_VSPOL_Pos (30U)
+#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
+#define LTDC_GCR_HSPOL_Pos (31U)
+#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
+
+
+/******************** Bit definition for LTDC_SRCR register *****************/
+
+#define LTDC_SRCR_IMR_Pos (0U)
+#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
+#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
+#define LTDC_SRCR_VBR_Pos (1U)
+#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
+#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
+
+/******************** Bit definition for LTDC_BCCR register *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos (0U)
+#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
+#define LTDC_BCCR_BCGREEN_Pos (8U)
+#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos (16U)
+#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
+
+/******************** Bit definition for LTDC_IER register ******************/
+
+#define LTDC_IER_LIE_Pos (0U)
+#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
+#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
+#define LTDC_IER_FUIE_Pos (1U)
+#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
+#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
+#define LTDC_IER_TERRIE_Pos (2U)
+#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
+#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
+#define LTDC_IER_RRIE_Pos (3U)
+#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
+#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
+
+/******************** Bit definition for LTDC_ISR register ******************/
+
+#define LTDC_ISR_LIF_Pos (0U)
+#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
+#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos (1U)
+#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos (2U)
+#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos (3U)
+#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_ICR register ******************/
+
+#define LTDC_ICR_CLIF_Pos (0U)
+#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
+#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos (1U)
+#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos (2U)
+#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos (3U)
+#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
+
+/******************** Bit definition for LTDC_LIPCR register ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos (0U)
+#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
+
+/******************** Bit definition for LTDC_CPSR register *****************/
+
+#define LTDC_CPSR_CYPOS_Pos (0U)
+#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos (16U)
+#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
+
+/******************** Bit definition for LTDC_CDSR register *****************/
+
+#define LTDC_CDSR_VDES_Pos (0U)
+#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
+#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
+#define LTDC_CDSR_HDES_Pos (1U)
+#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
+#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
+#define LTDC_CDSR_VSYNCS_Pos (2U)
+#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
+#define LTDC_CDSR_HSYNCS_Pos (3U)
+#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
+
+/******************** Bit definition for LTDC_LxCR register *****************/
+
+#define LTDC_LxCR_LEN_Pos (0U)
+#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
+#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
+#define LTDC_LxCR_COLKEN_Pos (1U)
+#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
+#define LTDC_LxCR_CLUTEN_Pos (4U)
+#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
+
+/******************** Bit definition for LTDC_LxWHPCR register **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
+
+/******************** Bit definition for LTDC_LxWVPCR register **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
+
+/******************** Bit definition for LTDC_LxCKCR register ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
+#define LTDC_LxCKCR_CKGREEN_Pos (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos (16U)
+#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
+
+/******************** Bit definition for LTDC_LxPFCR register ***************/
+
+#define LTDC_LxPFCR_PF_Pos (0U)
+#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
+
+/******************** Bit definition for LTDC_LxCACR register ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos (0U)
+#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
+
+/******************** Bit definition for LTDC_LxDCCR register ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
+#define LTDC_LxDCCR_DCGREEN_Pos (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos (16U)
+#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
+#define LTDC_LxDCCR_DCALPHA_Pos (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
+
+/******************** Bit definition for LTDC_LxBFCR register ***************/
+
+#define LTDC_LxBFCR_BF2_Pos (0U)
+#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos (8U)
+#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
+
+/******************** Bit definition for LTDC_LxCFBAR register **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
+
+/******************** Bit definition for LTDC_LxCFBLR register **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
+#define LTDC_LxCFBLR_CFBP_Pos (16U)
+#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
+
+/******************** Bit definition for LTDC_LxCFBLNR register *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
+
+/******************** Bit definition for LTDC_LxCLUTWR register *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
+#define LTDC_LxCLUTWR_GREEN_Pos (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
+#define LTDC_LxCLUTWR_RED_Pos (16U)
+#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
+#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
+
+/******************************************************************************/
+/* */
+/* Inter-Processor Communication Controller (IPCC) */
+/* */
+/******************************************************************************/
+
+/********************** Bit definition for IPCC_C1CR register ***************/
+#define IPCC_C1CR_RXOIE_Pos (0U)
+#define IPCC_C1CR_RXOIE_Msk (0x1U << IPCC_C1CR_RXOIE_Pos) /*!< 0x00000001 */
+#define IPCC_C1CR_RXOIE IPCC_C1CR_RXOIE_Msk /*!< Processor M4 Receive channel occupied interrupt enable */
+#define IPCC_C1CR_TXFIE_Pos (16U)
+#define IPCC_C1CR_TXFIE_Msk (0x1U << IPCC_C1CR_TXFIE_Pos) /*!< 0x00010000 */
+#define IPCC_C1CR_TXFIE IPCC_C1CR_TXFIE_Msk /*!< Processor M4 Transmit channel free interrupt enable */
+
+/********************** Bit definition for IPCC_C1MR register **************/
+#define IPCC_C1MR_CH1OM_Pos (0U)
+#define IPCC_C1MR_CH1OM_Msk (0x1U << IPCC_C1MR_CH1OM_Pos) /*!< 0x00000001 */
+#define IPCC_C1MR_CH1OM IPCC_C1MR_CH1OM_Msk /*!< M4 Channel1 occupied interrupt mask */
+#define IPCC_C1MR_CH2OM_Pos (1U)
+#define IPCC_C1MR_CH2OM_Msk (0x1U << IPCC_C1MR_CH2OM_Pos) /*!< 0x00000002 */
+#define IPCC_C1MR_CH2OM IPCC_C1MR_CH2OM_Msk /*!< M4 Channel2 occupied interrupt mask */
+#define IPCC_C1MR_CH3OM_Pos (2U)
+#define IPCC_C1MR_CH3OM_Msk (0x1U << IPCC_C1MR_CH3OM_Pos) /*!< 0x00000004 */
+#define IPCC_C1MR_CH3OM IPCC_C1MR_CH3OM_Msk /*!< M4 Channel3 occupied interrupt mask */
+#define IPCC_C1MR_CH4OM_Pos (3U)
+#define IPCC_C1MR_CH4OM_Msk (0x1U << IPCC_C1MR_CH4OM_Pos) /*!< 0x00000008 */
+#define IPCC_C1MR_CH4OM IPCC_C1MR_CH4OM_Msk /*!< M4 Channel4 occupied interrupt mask */
+#define IPCC_C1MR_CH5OM_Pos (4U)
+#define IPCC_C1MR_CH5OM_Msk (0x1U << IPCC_C1MR_CH5OM_Pos) /*!< 0x00000010 */
+#define IPCC_C1MR_CH5OM IPCC_C1MR_CH5OM_Msk /*!< M4 Channel5 occupied interrupt mask */
+#define IPCC_C1MR_CH6OM_Pos (5U)
+#define IPCC_C1MR_CH6OM_Msk (0x1U << IPCC_C1MR_CH6OM_Pos) /*!< 0x00000020 */
+#define IPCC_C1MR_CH6OM IPCC_C1MR_CH6OM_Msk /*!< M4 Channel6 occupied interrupt mask */
+
+#define IPCC_C1MR_CH1FM_Pos (16U)
+#define IPCC_C1MR_CH1FM_Msk (0x1U << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
+#define IPCC_C1MR_CH1FM IPCC_C1MR_CH1FM_Msk /*!< M4 Transmit Channel1 free interrupt mask */
+#define IPCC_C1MR_CH2FM_Pos (17U)
+#define IPCC_C1MR_CH2FM_Msk (0x1U << IPCC_C1MR_CH2FM_Pos) /*!< 0x00020000 */
+#define IPCC_C1MR_CH2FM IPCC_C1MR_CH2FM_Msk /*!< M4 Transmit Channel2 free interrupt mask */
+#define IPCC_C1MR_CH3FM_Pos (18U)
+#define IPCC_C1MR_CH3FM_Msk (0x1U << IPCC_C1MR_CH3FM_Pos) /*!< 0x00040000 */
+#define IPCC_C1MR_CH3FM IPCC_C1MR_CH3FM_Msk /*!< M4 Transmit Channel3 free interrupt mask */
+#define IPCC_C1MR_CH4FM_Pos (19U)
+#define IPCC_C1MR_CH4FM_Msk (0x1U << IPCC_C1MR_CH4FM_Pos) /*!< 0x00080000 */
+#define IPCC_C1MR_CH4FM IPCC_C1MR_CH4FM_Msk /*!< M4 Transmit Channel4 free interrupt mask */
+#define IPCC_C1MR_CH5FM_Pos (20U)
+#define IPCC_C1MR_CH5FM_Msk (0x1U << IPCC_C1MR_CH5FM_Pos) /*!< 0x00100000 */
+#define IPCC_C1MR_CH5FM IPCC_C1MR_CH5FM_Msk /*!< M4 Transmit Channel5 free interrupt mask */
+#define IPCC_C1MR_CH6FM_Pos (21U)
+#define IPCC_C1MR_CH6FM_Msk (0x1U << IPCC_C1MR_CH6FM_Pos) /*!< 0x00200000 */
+#define IPCC_C1MR_CH6FM IPCC_C1MR_CH6FM_Msk /*!< M4 Transmit Channel6 free interrupt mask */
+
+/********************** Bit definition for IPCC_C1SCR register ***************/
+#define IPCC_C1SCR_CH1C_Pos (0U)
+#define IPCC_C1SCR_CH1C_Msk (0x1U << IPCC_C1SCR_CH1C_Pos) /*!< 0x00000001 */
+#define IPCC_C1SCR_CH1C IPCC_C1SCR_CH1C_Msk /*!< M4 receive Channel1 status clear */
+#define IPCC_C1SCR_CH2C_Pos (1U)
+#define IPCC_C1SCR_CH2C_Msk (0x1U << IPCC_C1SCR_CH2C_Pos) /*!< 0x00000002 */
+#define IPCC_C1SCR_CH2C IPCC_C1SCR_CH2C_Msk /*!< M4 receive Channel2 status clear */
+#define IPCC_C1SCR_CH3C_Pos (2U)
+#define IPCC_C1SCR_CH3C_Msk (0x1U << IPCC_C1SCR_CH3C_Pos) /*!< 0x00000004 */
+#define IPCC_C1SCR_CH3C IPCC_C1SCR_CH3C_Msk /*!< M4 receive Channel3 status clear */
+#define IPCC_C1SCR_CH4C_Pos (3U)
+#define IPCC_C1SCR_CH4C_Msk (0x1U << IPCC_C1SCR_CH4C_Pos) /*!< 0x00000008 */
+#define IPCC_C1SCR_CH4C IPCC_C1SCR_CH4C_Msk /*!< M4 receive Channel4 status clear */
+#define IPCC_C1SCR_CH5C_Pos (4U)
+#define IPCC_C1SCR_CH5C_Msk (0x1U << IPCC_C1SCR_CH5C_Pos) /*!< 0x00000010 */
+#define IPCC_C1SCR_CH5C IPCC_C1SCR_CH5C_Msk /*!< M4 receive Channel5 status clear */
+#define IPCC_C1SCR_CH6C_Pos (5U)
+#define IPCC_C1SCR_CH6C_Msk (0x1U << IPCC_C1SCR_CH6C_Pos) /*!< 0x00000020 */
+#define IPCC_C1SCR_CH6C IPCC_C1SCR_CH6C_Msk /*!< M4 receive Channel6 status clear */
+
+#define IPCC_C1SCR_CH1S_Pos (16U)
+#define IPCC_C1SCR_CH1S_Msk (0x1U << IPCC_C1SCR_CH1S_Pos) /*!< 0x00010000 */
+#define IPCC_C1SCR_CH1S IPCC_C1SCR_CH1S_Msk /*!< M4 transmit Channel1 status set */
+#define IPCC_C1SCR_CH2S_Pos (17U)
+#define IPCC_C1SCR_CH2S_Msk (0x1U << IPCC_C1SCR_CH2S_Pos) /*!< 0x00020000 */
+#define IPCC_C1SCR_CH2S IPCC_C1SCR_CH2S_Msk /*!< M4 transmit Channel2 status set */
+#define IPCC_C1SCR_CH3S_Pos (18U)
+#define IPCC_C1SCR_CH3S_Msk (0x1U << IPCC_C1SCR_CH3S_Pos) /*!< 0x00040000 */
+#define IPCC_C1SCR_CH3S IPCC_C1SCR_CH3S_Msk /*!< M4 transmit Channel3 status set */
+#define IPCC_C1SCR_CH4S_Pos (19U)
+#define IPCC_C1SCR_CH4S_Msk (0x1U << IPCC_C1SCR_CH4S_Pos) /*!< 0x00080000 */
+#define IPCC_C1SCR_CH4S IPCC_C1SCR_CH4S_Msk /*!< M4 transmit Channel4 status set */
+#define IPCC_C1SCR_CH5S_Pos (20U)
+#define IPCC_C1SCR_CH5S_Msk (0x1U << IPCC_C1SCR_CH5S_Pos) /*!< 0x00100000 */
+#define IPCC_C1SCR_CH5S IPCC_C1SCR_CH5S_Msk /*!< M4 transmit Channel5 status set */
+#define IPCC_C1SCR_CH6S_Pos (21U)
+#define IPCC_C1SCR_CH6S_Msk (0x1U << IPCC_C1SCR_CH6S_Pos) /*!< 0x00200000 */
+#define IPCC_C1SCR_CH6S IPCC_C1SCR_CH6S_Msk /*!< M4 transmit Channel6 status set */
+
+/********************** Bit definition for IPCC_C1TOC2SR register ***************/
+#define IPCC_C1TOC2SR_CH1F_Pos (0U)
+#define IPCC_C1TOC2SR_CH1F_Msk (0x1U << IPCC_C1TOC2SR_CH1F_Pos) /*!< 0x00000001 */
+#define IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk /*!< M4 transmit to M4 receive Channel1 status flag before masking */
+#define IPCC_C1TOC2SR_CH2F_Pos (1U)
+#define IPCC_C1TOC2SR_CH2F_Msk (0x1U << IPCC_C1TOC2SR_CH2F_Pos) /*!< 0x00000002 */
+#define IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk /*!< M4 transmit to M4 receive Channel2 status flag before masking */
+#define IPCC_C1TOC2SR_CH3F_Pos (2U)
+#define IPCC_C1TOC2SR_CH3F_Msk (0x1U << IPCC_C1TOC2SR_CH3F_Pos) /*!< 0x00000004 */
+#define IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk /*!< M4 transmit to M4 receive Channel3 status flag before masking */
+#define IPCC_C1TOC2SR_CH4F_Pos (3U)
+#define IPCC_C1TOC2SR_CH4F_Msk (0x1U << IPCC_C1TOC2SR_CH4F_Pos) /*!< 0x00000008 */
+#define IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk /*!< M4 transmit to M4 receive Channel4 status flag before masking */
+#define IPCC_C1TOC2SR_CH5F_Pos (4U)
+#define IPCC_C1TOC2SR_CH5F_Msk (0x1U << IPCC_C1TOC2SR_CH5F_Pos) /*!< 0x00000010 */
+#define IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk /*!< M4 transmit to M4 receive Channel5 status flag before masking */
+#define IPCC_C1TOC2SR_CH6F_Pos (5U)
+#define IPCC_C1TOC2SR_CH6F_Msk (0x1U << IPCC_C1TOC2SR_CH6F_Pos) /*!< 0x00000020 */
+#define IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk /*!< M4 transmit to M4 receive Channel6 status flag before masking */
+
+/********************** Bit definition for IPCC_C2CR register ***************/
+#define IPCC_C2CR_RXOIE_Pos (0U)
+#define IPCC_C2CR_RXOIE_Msk (0x1U << IPCC_C2CR_RXOIE_Pos) /*!< 0x00000001 */
+#define IPCC_C2CR_RXOIE IPCC_C2CR_RXOIE_Msk /*!< Processor M0+ Receive channel occupied interrupt enable */
+#define IPCC_C2CR_TXFIE_Pos (16U)
+#define IPCC_C2CR_TXFIE_Msk (0x1U << IPCC_C2CR_TXFIE_Pos) /*!< 0x00010000 */
+#define IPCC_C2CR_TXFIE IPCC_C2CR_TXFIE_Msk /*!< Processor M0+ Transmit channel free interrupt enable */
+
+/********************** Bit definition for IPCC_C2MR register ***************/
+#define IPCC_C2MR_CH1OM_Pos (0U)
+#define IPCC_C2MR_CH1OM_Msk (0x1U << IPCC_C2MR_CH1OM_Pos) /*!< 0x00000001 */
+#define IPCC_C2MR_CH1OM IPCC_C2MR_CH1OM_Msk /*!< M0+ Channel1 occupied interrupt mask */
+#define IPCC_C2MR_CH2OM_Pos (1U)
+#define IPCC_C2MR_CH2OM_Msk (0x1U << IPCC_C2MR_CH2OM_Pos) /*!< 0x00000002 */
+#define IPCC_C2MR_CH2OM IPCC_C2MR_CH2OM_Msk /*!< M0+ Channel2 occupied interrupt mask */
+#define IPCC_C2MR_CH3OM_Pos (2U)
+#define IPCC_C2MR_CH3OM_Msk (0x1U << IPCC_C2MR_CH3OM_Pos) /*!< 0x00000004 */
+#define IPCC_C2MR_CH3OM IPCC_C2MR_CH3OM_Msk /*!< M0+ Channel3 occupied interrupt mask */
+#define IPCC_C2MR_CH4OM_Pos (3U)
+#define IPCC_C2MR_CH4OM_Msk (0x1U << IPCC_C2MR_CH4OM_Pos) /*!< 0x00000008 */
+#define IPCC_C2MR_CH4OM IPCC_C2MR_CH4OM_Msk /*!< M0+ Channel4 occupied interrupt mask */
+#define IPCC_C2MR_CH5OM_Pos (4U)
+#define IPCC_C2MR_CH5OM_Msk (0x1U << IPCC_C2MR_CH5OM_Pos) /*!< 0x00000010 */
+#define IPCC_C2MR_CH5OM IPCC_C2MR_CH5OM_Msk /*!< M0+ Channel5 occupied interrupt mask */
+#define IPCC_C2MR_CH6OM_Pos (5U)
+#define IPCC_C2MR_CH6OM_Msk (0x1U << IPCC_C2MR_CH6OM_Pos) /*!< 0x00000020 */
+#define IPCC_C2MR_CH6OM IPCC_C2MR_CH6OM_Msk /*!< M0+ Channel6 occupied interrupt mask */
+
+#define IPCC_C2MR_CH1FM_Pos (16U)
+#define IPCC_C2MR_CH1FM_Msk (0x1U << IPCC_C2MR_CH1FM_Pos) /*!< 0x00010000 */
+#define IPCC_C2MR_CH1FM IPCC_C2MR_CH1FM_Msk /*!< M0+ Transmit Channel1 free interrupt mask */
+#define IPCC_C2MR_CH2FM_Pos (17U)
+#define IPCC_C2MR_CH2FM_Msk (0x1U << IPCC_C2MR_CH2FM_Pos) /*!< 0x00020000 */
+#define IPCC_C2MR_CH2FM IPCC_C2MR_CH2FM_Msk /*!< M0+ Transmit Channel2 free interrupt mask */
+#define IPCC_C2MR_CH3FM_Pos (18U)
+#define IPCC_C2MR_CH3FM_Msk (0x1U << IPCC_C2MR_CH3FM_Pos) /*!< 0x00040000 */
+#define IPCC_C2MR_CH3FM IPCC_C2MR_CH3FM_Msk /*!< M0+ Transmit Channel3 free interrupt mask */
+#define IPCC_C2MR_CH4FM_Pos (19U)
+#define IPCC_C2MR_CH4FM_Msk (0x1U << IPCC_C2MR_CH4FM_Pos) /*!< 0x00080000 */
+#define IPCC_C2MR_CH4FM IPCC_C2MR_CH4FM_Msk /*!< M0+ Transmit Channel4 free interrupt mask */
+#define IPCC_C2MR_CH5FM_Pos (20U)
+#define IPCC_C2MR_CH5FM_Msk (0x1U << IPCC_C2MR_CH5FM_Pos) /*!< 0x00100000 */
+#define IPCC_C2MR_CH5FM IPCC_C2MR_CH5FM_Msk /*!< M0+ Transmit Channel5 free interrupt mask */
+#define IPCC_C2MR_CH6FM_Pos (21U)
+#define IPCC_C2MR_CH6FM_Msk (0x1U << IPCC_C2MR_CH6FM_Pos) /*!< 0x00200000 */
+#define IPCC_C2MR_CH6FM IPCC_C2MR_CH6FM_Msk /*!< M0+ Transmit Channel6 free interrupt mask */
+
+/********************** Bit definition for IPCC_C2SCR register ***************/
+#define IPCC_C2SCR_CH1C_Pos (0U)
+#define IPCC_C2SCR_CH1C_Msk (0x1U << IPCC_C2SCR_CH1C_Pos) /*!< 0x00000001 */
+#define IPCC_C2SCR_CH1C IPCC_C2SCR_CH1C_Msk /*!< M0+ receive Channel1 status clear */
+#define IPCC_C2SCR_CH2C_Pos (1U)
+#define IPCC_C2SCR_CH2C_Msk (0x1U << IPCC_C2SCR_CH2C_Pos) /*!< 0x00000002 */
+#define IPCC_C2SCR_CH2C IPCC_C2SCR_CH2C_Msk /*!< M0+ receive Channel2 status clear */
+#define IPCC_C2SCR_CH3C_Pos (2U)
+#define IPCC_C2SCR_CH3C_Msk (0x1U << IPCC_C2SCR_CH3C_Pos) /*!< 0x00000004 */
+#define IPCC_C2SCR_CH3C IPCC_C2SCR_CH3C_Msk /*!< M0+ receive Channel3 status clear */
+#define IPCC_C2SCR_CH4C_Pos (3U)
+#define IPCC_C2SCR_CH4C_Msk (0x1U << IPCC_C2SCR_CH4C_Pos) /*!< 0x00000008 */
+#define IPCC_C2SCR_CH4C IPCC_C2SCR_CH4C_Msk /*!< M0+ receive Channel4 status clear */
+#define IPCC_C2SCR_CH5C_Pos (4U)
+#define IPCC_C2SCR_CH5C_Msk (0x1U << IPCC_C2SCR_CH5C_Pos) /*!< 0x00000010 */
+#define IPCC_C2SCR_CH5C IPCC_C2SCR_CH5C_Msk /*!< M0+ receive Channel5 status clear */
+#define IPCC_C2SCR_CH6C_Pos (5U)
+#define IPCC_C2SCR_CH6C_Msk (0x1U << IPCC_C2SCR_CH6C_Pos) /*!< 0x00000020 */
+#define IPCC_C2SCR_CH6C IPCC_C2SCR_CH6C_Msk /*!< M0+ receive Channel6 status clear */
+
+#define IPCC_C2SCR_CH1S_Pos (16U)
+#define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
+#define IPCC_C2SCR_CH1S IPCC_C2SCR_CH1S_Msk /*!< M0+ transmit Channel1 status set */
+#define IPCC_C2SCR_CH2S_Pos (17U)
+#define IPCC_C2SCR_CH2S_Msk (0x1U << IPCC_C2SCR_CH2S_Pos) /*!< 0x00020000 */
+#define IPCC_C2SCR_CH2S IPCC_C2SCR_CH2S_Msk /*!< M0+ transmit Channel2 status set */
+#define IPCC_C2SCR_CH3S_Pos (18U)
+#define IPCC_C2SCR_CH3S_Msk (0x1U << IPCC_C2SCR_CH3S_Pos) /*!< 0x00040000 */
+#define IPCC_C2SCR_CH3S IPCC_C2SCR_CH3S_Msk /*!< M0+ transmit Channel3 status set */
+#define IPCC_C2SCR_CH4S_Pos (19U)
+#define IPCC_C2SCR_CH4S_Msk (0x1U << IPCC_C2SCR_CH4S_Pos) /*!< 0x00080000 */
+#define IPCC_C2SCR_CH4S IPCC_C2SCR_CH4S_Msk /*!< M0+ transmit Channel4 status set */
+#define IPCC_C2SCR_CH5S_Pos (20U)
+#define IPCC_C2SCR_CH5S_Msk (0x1U << IPCC_C2SCR_CH5S_Pos) /*!< 0x00100000 */
+#define IPCC_C2SCR_CH5S IPCC_C2SCR_CH5S_Msk /*!< M0+ transmit Channel5 status set */
+#define IPCC_C2SCR_CH6S_Pos (21U)
+#define IPCC_C2SCR_CH6S_Msk (0x1U << IPCC_C2SCR_CH6S_Pos) /*!< 0x00200000 */
+#define IPCC_C2SCR_CH6S IPCC_C2SCR_CH6S_Msk /*!< M0+ transmit Channel6 status set */
+
+/********************** Bit definition for IPCC_C2TOC1SR register ***************/
+#define IPCC_C2TOC1SR_CH1F_Pos (0U)
+#define IPCC_C2TOC1SR_CH1F_Msk (0x1U << IPCC_C2TOC1SR_CH1F_Pos) /*!< 0x00000001 */
+#define IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk /*!< M0+ transmit to M0 receive Channel1 status flag before masking */
+#define IPCC_C2TOC1SR_CH2F_Pos (1U)
+#define IPCC_C2TOC1SR_CH2F_Msk (0x1U << IPCC_C2TOC1SR_CH2F_Pos) /*!< 0x00000002 */
+#define IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk /*!< M0+ transmit to M0 receive Channel2 status flag before masking */
+#define IPCC_C2TOC1SR_CH3F_Pos (2U)
+#define IPCC_C2TOC1SR_CH3F_Msk (0x1U << IPCC_C2TOC1SR_CH3F_Pos) /*!< 0x00000004 */
+#define IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk /*!< M0+ transmit to M0 receive Channel3 status flag before masking */
+#define IPCC_C2TOC1SR_CH4F_Pos (3U)
+#define IPCC_C2TOC1SR_CH4F_Msk (0x1U << IPCC_C2TOC1SR_CH4F_Pos) /*!< 0x00000008 */
+#define IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk /*!< M0+ transmit to M0 receive Channel4 status flag before masking */
+#define IPCC_C2TOC1SR_CH5F_Pos (4U)
+#define IPCC_C2TOC1SR_CH5F_Msk (0x1U << IPCC_C2TOC1SR_CH5F_Pos) /*!< 0x00000010 */
+#define IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk /*!< M0+ transmit to M0 receive Channel5 status flag before masking */
+#define IPCC_C2TOC1SR_CH6F_Pos (5U)
+#define IPCC_C2TOC1SR_CH6F_Msk (0x1U << IPCC_C2TOC1SR_CH6F_Pos) /*!< 0x00000020 */
+#define IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk /*!< M0+ transmit to M0 receive Channel6 status flag before masking */
+
+/********************** Bit definition for IPCC_HWCFGR register ***************/
+#define IPCC_HWCFGR_CHANNELS_Pos (0U)
+#define IPCC_HWCFGR_CHANNELS_Msk (0xFFU << IPCC_HWCFGR_CHANNELS_Pos) /*!< 0x000000FF */
+#define IPCC_HWCFGR_CHANNELS IPCC_HWCFGR_CHANNELS_Msk /*!< Number of channels per CPU */
+
+/********************** Bit definition for IPCC_VERR register *****************/
+#define IPCC_VERR_MINREV_Pos (0U)
+#define IPCC_VERR_MINREV_Msk (0xFU << IPCC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define IPCC_VERR_MINREV IPCC_VERR_MINREV_Msk /*!< Minor Revision number */
+#define IPCC_VERR_MAJREV_Pos (4U)
+#define IPCC_VERR_MAJREV_Msk (0xFU << IPCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define IPCC_VERR_MAJREV IPCC_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for IPCC_IPIDR register ****************/
+#define IPCC_IPIDR_IPID_Pos (0U)
+#define IPCC_IPIDR_IPID_Msk (0xFFFFFFFFU << IPCC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define IPCC_IPIDR_IPID IPCC_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for IPCC_SIDR register *****************/
+#define IPCC_SIDR_SID_Pos (0U)
+#define IPCC_SIDR_SID_Msk (0xFFFFFFFFU << IPCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define IPCC_SIDR_SID IPCC_SIDR_SID_Msk /*!< IP size identification */
+
+/********************** Bit definition for IPCC_C1CR register ***************/
+#define IPCC_CR_RXOIE_Pos IPCC_C1CR_RXOIE_Pos
+#define IPCC_CR_RXOIE_Msk IPCC_C1CR_RXOIE_Msk
+#define IPCC_CR_RXOIE IPCC_C1CR_RXOIE
+#define IPCC_CR_TXFIE_Pos IPCC_C1CR_TXFIE_Pos
+#define IPCC_CR_TXFIE_Msk IPCC_C1CR_TXFIE_Msk
+#define IPCC_CR_TXFIE IPCC_C1CR_TXFIE
+
+/********************** Bit definition for IPCC_C1MR register **************/
+#define IPCC_MR_CH1OM_Pos IPCC_C1MR_CH1OM_Pos
+#define IPCC_MR_CH1OM_Msk IPCC_C1MR_CH1OM_Msk
+#define IPCC_MR_CH1OM IPCC_C1MR_CH1OM
+#define IPCC_MR_CH2OM_Pos IPCC_C1MR_CH2OM_Pos
+#define IPCC_MR_CH2OM_Msk IPCC_C1MR_CH2OM_Msk
+#define IPCC_MR_CH2OM IPCC_C1MR_CH2OM
+#define IPCC_MR_CH3OM_Pos IPCC_C1MR_CH3OM_Pos
+#define IPCC_MR_CH3OM_Msk IPCC_C1MR_CH3OM_Msk
+#define IPCC_MR_CH3OM IPCC_C1MR_CH3OM
+#define IPCC_MR_CH4OM_Pos IPCC_C1MR_CH4OM_Pos
+#define IPCC_MR_CH4OM_Msk IPCC_C1MR_CH4OM_Msk
+#define IPCC_MR_CH4OM IPCC_C1MR_CH4OM
+#define IPCC_MR_CH5OM_Pos IPCC_C1MR_CH5OM_Pos
+#define IPCC_MR_CH5OM_Msk IPCC_C1MR_CH5OM_Msk
+#define IPCC_MR_CH5OM IPCC_C1MR_CH5OM
+#define IPCC_MR_CH6OM_Pos IPCC_C1MR_CH6OM_Pos
+#define IPCC_MR_CH6OM_Msk IPCC_C1MR_CH6OM_Msk
+#define IPCC_MR_CH6OM IPCC_C1MR_CH6OM
+
+#define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
+#define IPCC_MR_CH1FM_Msk IPCC_C1MR_CH1FM_Msk
+#define IPCC_MR_CH1FM IPCC_C1MR_CH1FM
+#define IPCC_MR_CH2FM_Pos IPCC_C1MR_CH2FM_Pos
+#define IPCC_MR_CH2FM_Msk IPCC_C1MR_CH2FM_Msk
+#define IPCC_MR_CH2FM IPCC_C1MR_CH2FM
+#define IPCC_MR_CH3FM_Pos IPCC_C1MR_CH3FM_Pos
+#define IPCC_MR_CH3FM_Msk IPCC_C1MR_CH3FM_Msk
+#define IPCC_MR_CH3FM IPCC_C1MR_CH3FM
+#define IPCC_MR_CH4FM_Pos IPCC_C1MR_CH4FM_Pos
+#define IPCC_MR_CH4FM_Msk IPCC_C1MR_CH4FM_Msk
+#define IPCC_MR_CH4FM IPCC_C1MR_CH4FM
+#define IPCC_MR_CH5FM_Pos IPCC_C1MR_CH5FM_Pos
+#define IPCC_MR_CH5FM_Msk IPCC_C1MR_CH5FM_Msk
+#define IPCC_MR_CH5FM IPCC_C1MR_CH5FM
+#define IPCC_MR_CH6FM_Pos IPCC_C1MR_CH6FM_Pos
+#define IPCC_MR_CH6FM_Msk IPCC_C1MR_CH6FM_Msk
+#define IPCC_MR_CH6FM IPCC_C1MR_CH6FM
+
+/********************** Bit definition for IPCC_C1SCR register ***************/
+#define IPCC_SCR_CH1C_Pos IPCC_C1SCR_CH1C_Pos
+#define IPCC_SCR_CH1C_Msk IPCC_C1SCR_CH1C_Msk
+#define IPCC_SCR_CH1C IPCC_C1SCR_CH1C
+#define IPCC_SCR_CH2C_Pos IPCC_C1SCR_CH2C_Pos
+#define IPCC_SCR_CH2C_Msk IPCC_C1SCR_CH2C_Msk
+#define IPCC_SCR_CH2C IPCC_C1SCR_CH2C
+#define IPCC_SCR_CH3C_Pos IPCC_C1SCR_CH3C_Pos
+#define IPCC_SCR_CH3C_Msk IPCC_C1SCR_CH3C_Msk
+#define IPCC_SCR_CH3C IPCC_C1SCR_CH3C
+#define IPCC_SCR_CH4C_Pos IPCC_C1SCR_CH4C_Pos
+#define IPCC_SCR_CH4C_Msk IPCC_C1SCR_CH4C_Msk
+#define IPCC_SCR_CH4C IPCC_C1SCR_CH4C
+#define IPCC_SCR_CH5C_Pos IPCC_C1SCR_CH5C_Pos
+#define IPCC_SCR_CH5C_Msk IPCC_C1SCR_CH5C_Msk
+#define IPCC_SCR_CH5C IPCC_C1SCR_CH5C
+#define IPCC_SCR_CH6C_Pos IPCC_C1SCR_CH6C_Pos
+#define IPCC_SCR_CH6C_Msk IPCC_C1SCR_CH6C_Msk
+#define IPCC_SCR_CH6C IPCC_C1SCR_CH6C
+
+#define IPCC_SCR_CH1S_Pos IPCC_C1SCR_CH1S_Pos
+#define IPCC_SCR_CH1S_Msk IPCC_C1SCR_CH1S_Msk
+#define IPCC_SCR_CH1S IPCC_C1SCR_CH1S
+#define IPCC_SCR_CH2S_Pos IPCC_C1SCR_CH2S_Pos
+#define IPCC_SCR_CH2S_Msk IPCC_C1SCR_CH2S_Msk
+#define IPCC_SCR_CH2S IPCC_C1SCR_CH2S
+#define IPCC_SCR_CH3S_Pos IPCC_C1SCR_CH3S_Pos
+#define IPCC_SCR_CH3S_Msk IPCC_C1SCR_CH3S_Msk
+#define IPCC_SCR_CH3S IPCC_C1SCR_CH3S
+#define IPCC_SCR_CH4S_Pos IPCC_C1SCR_CH4S_Pos
+#define IPCC_SCR_CH4S_Msk IPCC_C1SCR_CH4S_Msk
+#define IPCC_SCR_CH4S IPCC_C1SCR_CH4S
+#define IPCC_SCR_CH5S_Pos IPCC_C1SCR_CH5S_Pos
+#define IPCC_SCR_CH5S_Msk IPCC_C1SCR_CH5S_Msk
+#define IPCC_SCR_CH5S IPCC_C1SCR_CH5S
+#define IPCC_SCR_CH6S_Pos IPCC_C1SCR_CH6S_Pos
+#define IPCC_SCR_CH6S_Msk IPCC_C1SCR_CH6S_Msk
+#define IPCC_SCR_CH6S IPCC_C1SCR_CH6S
+
+/********************** Bit definition for IPCC_C1TOC2SR register ***************/
+#define IPCC_SR_CH1F_Pos IPCC_C1TOC2SR_CH1F_Pos
+#define IPCC_SR_CH1F_Msk IPCC_C1TOC2SR_CH1F_Msk
+#define IPCC_SR_CH1F IPCC_C1TOC2SR_CH1F
+#define IPCC_SR_CH2F_Pos IPCC_C1TOC2SR_CH2F_Pos
+#define IPCC_SR_CH2F_Msk IPCC_C1TOC2SR_CH2F_Msk
+#define IPCC_SR_CH2F IPCC_C1TOC2SR_CH2F
+#define IPCC_SR_CH3F_Pos IPCC_C1TOC2SR_CH3F_Pos
+#define IPCC_SR_CH3F_Msk IPCC_C1TOC2SR_CH3F_Msk
+#define IPCC_SR_CH3F IPCC_C1TOC2SR_CH3F
+#define IPCC_SR_CH4F_Pos IPCC_C1TOC2SR_CH4F_Pos
+#define IPCC_SR_CH4F_Msk IPCC_C1TOC2SR_CH4F_Msk
+#define IPCC_SR_CH4F IPCC_C1TOC2SR_CH4F
+#define IPCC_SR_CH5F_Pos IPCC_C1TOC2SR_CH5F_Pos
+#define IPCC_SR_CH5F_Msk IPCC_C1TOC2SR_CH5F_Msk
+#define IPCC_SR_CH5F IPCC_C1TOC2SR_CH5F
+#define IPCC_SR_CH6F_Pos IPCC_C1TOC2SR_CH6F_Pos
+#define IPCC_SR_CH6F_Msk IPCC_C1TOC2SR_CH6F_Msk
+#define IPCC_SR_CH6F IPCC_C1TOC2SR_CH6F
+
+/******************** Number of IPCC channels ******************************/
+#define IPCC_CHANNEL_NUMBER 6U
+
+/******************************************************************************/
+/* */
+/* MDMA */
+/* */
+/******************************************************************************/
+/******************** Bit definition for MDMA_GISR0 register ****************/
+#define MDMA_GISR0_GIF0_Pos (0U)
+#define MDMA_GISR0_GIF0_Msk (0x1U << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
+#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
+#define MDMA_GISR0_GIF1_Pos (1U)
+#define MDMA_GISR0_GIF1_Msk (0x1U << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
+#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
+#define MDMA_GISR0_GIF2_Pos (2U)
+#define MDMA_GISR0_GIF2_Msk (0x1U << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
+#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
+#define MDMA_GISR0_GIF3_Pos (3U)
+#define MDMA_GISR0_GIF3_Msk (0x1U << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
+#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
+#define MDMA_GISR0_GIF4_Pos (4U)
+#define MDMA_GISR0_GIF4_Msk (0x1U << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
+#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
+#define MDMA_GISR0_GIF5_Pos (5U)
+#define MDMA_GISR0_GIF5_Msk (0x1U << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
+#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
+#define MDMA_GISR0_GIF6_Pos (6U)
+#define MDMA_GISR0_GIF6_Msk (0x1U << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
+#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
+#define MDMA_GISR0_GIF7_Pos (7U)
+#define MDMA_GISR0_GIF7_Msk (0x1U << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
+#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
+#define MDMA_GISR0_GIF8_Pos (8U)
+#define MDMA_GISR0_GIF8_Msk (0x1U << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
+#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
+#define MDMA_GISR0_GIF9_Pos (9U)
+#define MDMA_GISR0_GIF9_Msk (0x1U << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
+#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
+#define MDMA_GISR0_GIF10_Pos (10U)
+#define MDMA_GISR0_GIF10_Msk (0x1U << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
+#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
+#define MDMA_GISR0_GIF11_Pos (11U)
+#define MDMA_GISR0_GIF11_Msk (0x1U << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
+#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
+#define MDMA_GISR0_GIF12_Pos (12U)
+#define MDMA_GISR0_GIF12_Msk (0x1U << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
+#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
+#define MDMA_GISR0_GIF13_Pos (13U)
+#define MDMA_GISR0_GIF13_Msk (0x1U << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
+#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
+#define MDMA_GISR0_GIF14_Pos (14U)
+#define MDMA_GISR0_GIF14_Msk (0x1U << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
+#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
+#define MDMA_GISR0_GIF15_Pos (15U)
+#define MDMA_GISR0_GIF15_Msk (0x1U << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
+#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
+#define MDMA_GISR0_GIF16_Pos (16U)
+#define MDMA_GISR0_GIF16_Msk (0x1U << MDMA_GISR0_GIF16_Pos) /*!< 0x00010000 */
+#define MDMA_GISR0_GIF16 MDMA_GISR0_GIF16_Msk /*!< Channel 16 global interrupt flag */
+#define MDMA_GISR0_GIF17_Pos (17U)
+#define MDMA_GISR0_GIF17_Msk (0x1U << MDMA_GISR0_GIF17_Pos) /*!< 0x00020000 */
+#define MDMA_GISR0_GIF17 MDMA_GISR0_GIF17_Msk /*!< Channel 17 global interrupt flag */
+#define MDMA_GISR0_GIF18_Pos (18U)
+#define MDMA_GISR0_GIF18_Msk (0x1U << MDMA_GISR0_GIF18_Pos) /*!< 0x00040000 */
+#define MDMA_GISR0_GIF18 MDMA_GISR0_GIF18_Msk /*!< Channel 18 global interrupt flag */
+#define MDMA_GISR0_GIF19_Pos (19U)
+#define MDMA_GISR0_GIF19_Msk (0x1U << MDMA_GISR0_GIF19_Pos) /*!< 0x00080000 */
+#define MDMA_GISR0_GIF19 MDMA_GISR0_GIF19_Msk /*!< Channel 19 global interrupt flag */
+#define MDMA_GISR0_GIF20_Pos (20U)
+#define MDMA_GISR0_GIF20_Msk (0x1U << MDMA_GISR0_GIF20_Pos) /*!< 0x00100000 */
+#define MDMA_GISR0_GIF20 MDMA_GISR0_GIF20_Msk /*!< Channel 20 global interrupt flag */
+#define MDMA_GISR0_GIF21_Pos (21U)
+#define MDMA_GISR0_GIF21_Msk (0x1U << MDMA_GISR0_GIF21_Pos) /*!< 0x00200000 */
+#define MDMA_GISR0_GIF21 MDMA_GISR0_GIF21_Msk /*!< Channel 21 global interrupt flag */
+#define MDMA_GISR0_GIF22_Pos (22U)
+#define MDMA_GISR0_GIF22_Msk (0x1U << MDMA_GISR0_GIF22_Pos) /*!< 0x00400000 */
+#define MDMA_GISR0_GIF22 MDMA_GISR0_GIF22_Msk /*!< Channel 22 global interrupt flag */
+#define MDMA_GISR0_GIF23_Pos (23U)
+#define MDMA_GISR0_GIF23_Msk (0x1U << MDMA_GISR0_GIF23_Pos) /*!< 0x00800000 */
+#define MDMA_GISR0_GIF23 MDMA_GISR0_GIF23_Msk /*!< Channel 23 global interrupt flag */
+#define MDMA_GISR0_GIF24_Pos (24U)
+#define MDMA_GISR0_GIF24_Msk (0x1U << MDMA_GISR0_GIF24_Pos) /*!< 0x01000000 */
+#define MDMA_GISR0_GIF24 MDMA_GISR0_GIF24_Msk /*!< Channel 24 global interrupt flag */
+#define MDMA_GISR0_GIF25_Pos (25U)
+#define MDMA_GISR0_GIF25_Msk (0x1U << MDMA_GISR0_GIF25_Pos) /*!< 0x02000000 */
+#define MDMA_GISR0_GIF25 MDMA_GISR0_GIF25_Msk /*!< Channel 25 global interrupt flag */
+#define MDMA_GISR0_GIF26_Pos (26U)
+#define MDMA_GISR0_GIF26_Msk (0x1U << MDMA_GISR0_GIF26_Pos) /*!< 0x04000000 */
+#define MDMA_GISR0_GIF26 MDMA_GISR0_GIF26_Msk /*!< Channel 26 global interrupt flag */
+#define MDMA_GISR0_GIF27_Pos (27U)
+#define MDMA_GISR0_GIF27_Msk (0x1U << MDMA_GISR0_GIF27_Pos) /*!< 0x08000000 */
+#define MDMA_GISR0_GIF27 MDMA_GISR0_GIF27_Msk /*!< Channel 27 global interrupt flag */
+#define MDMA_GISR0_GIF28_Pos (28U)
+#define MDMA_GISR0_GIF28_Msk (0x1U << MDMA_GISR0_GIF28_Pos) /*!< 0x10000000 */
+#define MDMA_GISR0_GIF28 MDMA_GISR0_GIF28_Msk /*!< Channel 28 global interrupt flag */
+#define MDMA_GISR0_GIF29_Pos (29U)
+#define MDMA_GISR0_GIF29_Msk (0x1U << MDMA_GISR0_GIF29_Pos) /*!< 0x20000000 */
+#define MDMA_GISR0_GIF29 MDMA_GISR0_GIF29_Msk /*!< Channel 29 global interrupt flag */
+#define MDMA_GISR0_GIF30_Pos (30U)
+#define MDMA_GISR0_GIF30_Msk (0x1U << MDMA_GISR0_GIF30_Pos) /*!< 0x40000000 */
+#define MDMA_GISR0_GIF30 MDMA_GISR0_GIF30_Msk /*!< Channel 30 global interrupt flag */
+#define MDMA_GISR0_GIF31_Pos (31U)
+#define MDMA_GISR0_GIF31_Msk (0x1U << MDMA_GISR0_GIF31_Pos) /*!< 0x80000000 */
+#define MDMA_GISR0_GIF31 MDMA_GISR0_GIF31_Msk /*!< Channel 31 global interrupt flag */
+
+/******************** Bit definition for MDMA_GISR1 register ****************/
+#define MDMA_GISR1_GIF32_Pos (0U)
+#define MDMA_GISR1_GIF32_Msk (0x1U << MDMA_GISR1_GIF32_Pos) /*!< 0x00000001 */
+#define MDMA_GISR1_GIF32 MDMA_GISR1_GIF32_Msk /*!< Channel 32 global interrupt flag */
+#define MDMA_GISR1_GIF33_Pos (1U)
+#define MDMA_GISR1_GIF33_Msk (0x1U << MDMA_GISR1_GIF33_Pos) /*!< 0x00000002 */
+#define MDMA_GISR1_GIF33 MDMA_GISR1_GIF33_Msk /*!< Channel 33 global interrupt flag */
+#define MDMA_GISR1_GIF34_Pos (2U)
+#define MDMA_GISR1_GIF34_Msk (0x1U << MDMA_GISR1_GIF34_Pos) /*!< 0x00000004 */
+#define MDMA_GISR1_GIF34 MDMA_GISR1_GIF34_Msk /*!< Channel 34 global interrupt flag */
+#define MDMA_GISR1_GIF35_Pos (3U)
+#define MDMA_GISR1_GIF35_Msk (0x1U << MDMA_GISR1_GIF35_Pos) /*!< 0x00000008 */
+#define MDMA_GISR1_GIF35 MDMA_GISR1_GIF35_Msk /*!< Channel 35 global interrupt flag */
+#define MDMA_GISR1_GIF36_Pos (4U)
+#define MDMA_GISR1_GIF36_Msk (0x1U << MDMA_GISR1_GIF36_Pos) /*!< 0x00000010 */
+#define MDMA_GISR1_GIF36 MDMA_GISR1_GIF36_Msk /*!< Channel 36 global interrupt flag */
+#define MDMA_GISR1_GIF37_Pos (5U)
+#define MDMA_GISR1_GIF37_Msk (0x1U << MDMA_GISR1_GIF37_Pos) /*!< 0x00000020 */
+#define MDMA_GISR1_GIF37 MDMA_GISR1_GIF37_Msk /*!< Channel 37 global interrupt flag */
+#define MDMA_GISR1_GIF38_Pos (6U)
+#define MDMA_GISR1_GIF38_Msk (0x1U << MDMA_GISR1_GIF38_Pos) /*!< 0x00000040 */
+#define MDMA_GISR1_GIF38 MDMA_GISR1_GIF38_Msk /*!< Channel 38 global interrupt flag */
+#define MDMA_GISR1_GIF39_Pos (7U)
+#define MDMA_GISR1_GIF39_Msk (0x1U << MDMA_GISR1_GIF39_Pos) /*!< 0x00000080 */
+#define MDMA_GISR1_GIF39 MDMA_GISR1_GIF39_Msk /*!< Channel 39 global interrupt flag */
+#define MDMA_GISR1_GIF40_Pos (8U)
+#define MDMA_GISR1_GIF40_Msk (0x1U << MDMA_GISR1_GIF40_Pos) /*!< 0x00000100 */
+#define MDMA_GISR1_GIF40 MDMA_GISR1_GIF40_Msk /*!< Channel 40 global interrupt flag */
+#define MDMA_GISR1_GIF41_Pos (9U)
+#define MDMA_GISR1_GIF41_Msk (0x1U << MDMA_GISR1_GIF41_Pos) /*!< 0x00000200 */
+#define MDMA_GISR1_GIF41 MDMA_GISR1_GIF41_Msk /*!< Channel 41 global interrupt flag */
+#define MDMA_GISR1_GIF42_Pos (10U)
+#define MDMA_GISR1_GIF42_Msk (0x1U << MDMA_GISR1_GIF42_Pos) /*!< 0x00000400 */
+#define MDMA_GISR1_GIF42 MDMA_GISR1_GIF42_Msk /*!< Channel 42 global interrupt flag */
+#define MDMA_GISR1_GIF43_Pos (11U)
+#define MDMA_GISR1_GIF43_Msk (0x1U << MDMA_GISR1_GIF43_Pos) /*!< 0x00000800 */
+#define MDMA_GISR1_GIF43 MDMA_GISR1_GIF43_Msk /*!< Channel 43 global interrupt flag */
+#define MDMA_GISR1_GIF44_Pos (12U)
+#define MDMA_GISR1_GIF44_Msk (0x1U << MDMA_GISR1_GIF44_Pos) /*!< 0x00001000 */
+#define MDMA_GISR1_GIF44 MDMA_GISR1_GIF44_Msk /*!< Channel 44 global interrupt flag */
+#define MDMA_GISR1_GIF45_Pos (13U)
+#define MDMA_GISR1_GIF45_Msk (0x1U << MDMA_GISR1_GIF45_Pos) /*!< 0x00002000 */
+#define MDMA_GISR1_GIF45 MDMA_GISR1_GIF45_Msk /*!< Channel 45 global interrupt flag */
+#define MDMA_GISR1_GIF46_Pos (14U)
+#define MDMA_GISR1_GIF46_Msk (0x1U << MDMA_GISR1_GIF46_Pos) /*!< 0x00004000 */
+#define MDMA_GISR1_GIF46 MDMA_GISR1_GIF46_Msk /*!< Channel 46 global interrupt flag */
+#define MDMA_GISR1_GIF47_Pos (15U)
+#define MDMA_GISR1_GIF47_Msk (0x1U << MDMA_GISR1_GIF47_Pos) /*!< 0x00008000 */
+#define MDMA_GISR1_GIF47 MDMA_GISR1_GIF47_Msk /*!< Channel 47 global interrupt flag */
+#define MDMA_GISR1_GIF48_Pos (16U)
+#define MDMA_GISR1_GIF48_Msk (0x1U << MDMA_GISR1_GIF48_Pos) /*!< 0x00010000 */
+#define MDMA_GISR1_GIF48 MDMA_GISR1_GIF48_Msk /*!< Channel 48 global interrupt flag */
+#define MDMA_GISR1_GIF49_Pos (17U)
+#define MDMA_GISR1_GIF49_Msk (0x1U << MDMA_GISR1_GIF49_Pos) /*!< 0x00020000 */
+#define MDMA_GISR1_GIF49 MDMA_GISR1_GIF49_Msk /*!< Channel 49 global interrupt flag */
+#define MDMA_GISR1_GIF50_Pos (18U)
+#define MDMA_GISR1_GIF50_Msk (0x1U << MDMA_GISR1_GIF50_Pos) /*!< 0x00040000 */
+#define MDMA_GISR1_GIF50 MDMA_GISR1_GIF50_Msk /*!< Channel 50 global interrupt flag */
+#define MDMA_GISR1_GIF51_Pos (19U)
+#define MDMA_GISR1_GIF51_Msk (0x1U << MDMA_GISR1_GIF51_Pos) /*!< 0x00080000 */
+#define MDMA_GISR1_GIF51 MDMA_GISR1_GIF51_Msk /*!< Channel 51 global interrupt flag */
+#define MDMA_GISR1_GIF52_Pos (20U)
+#define MDMA_GISR1_GIF52_Msk (0x1U << MDMA_GISR1_GIF52_Pos) /*!< 0x00100000 */
+#define MDMA_GISR1_GIF52 MDMA_GISR1_GIF52_Msk /*!< Channel 52 global interrupt flag */
+#define MDMA_GISR1_GIF53_Pos (21U)
+#define MDMA_GISR1_GIF53_Msk (0x1U << MDMA_GISR1_GIF53_Pos) /*!< 0x00200000 */
+#define MDMA_GISR1_GIF53 MDMA_GISR1_GIF53_Msk /*!< Channel 53 global interrupt flag */
+#define MDMA_GISR1_GIF54_Pos (22U)
+#define MDMA_GISR1_GIF54_Msk (0x1U << MDMA_GISR1_GIF54_Pos) /*!< 0x00400000 */
+#define MDMA_GISR1_GIF54 MDMA_GISR1_GIF54_Msk /*!< Channel 54 global interrupt flag */
+#define MDMA_GISR1_GIF55_Pos (23U)
+#define MDMA_GISR1_GIF55_Msk (0x1U << MDMA_GISR1_GIF55_Pos) /*!< 0x00800000 */
+#define MDMA_GISR1_GIF55 MDMA_GISR1_GIF55_Msk /*!< Channel 55 global interrupt flag */
+#define MDMA_GISR1_GIF56_Pos (24U)
+#define MDMA_GISR1_GIF56_Msk (0x1U << MDMA_GISR1_GIF56_Pos) /*!< 0x01000000 */
+#define MDMA_GISR1_GIF56 MDMA_GISR1_GIF56_Msk /*!< Channel 56 global interrupt flag */
+#define MDMA_GISR1_GIF57_Pos (25U)
+#define MDMA_GISR1_GIF57_Msk (0x1U << MDMA_GISR1_GIF57_Pos) /*!< 0x02000000 */
+#define MDMA_GISR1_GIF57 MDMA_GISR1_GIF57_Msk /*!< Channel 57 global interrupt flag */
+#define MDMA_GISR1_GIF58_Pos (26U)
+#define MDMA_GISR1_GIF58_Msk (0x1U << MDMA_GISR1_GIF58_Pos) /*!< 0x04000000 */
+#define MDMA_GISR1_GIF58 MDMA_GISR1_GIF58_Msk /*!< Channel 58 global interrupt flag */
+#define MDMA_GISR1_GIF59_Pos (27U)
+#define MDMA_GISR1_GIF59_Msk (0x1U << MDMA_GISR1_GIF59_Pos) /*!< 0x08000000 */
+#define MDMA_GISR1_GIF59 MDMA_GISR1_GIF59_Msk /*!< Channel 59 global interrupt flag */
+#define MDMA_GISR1_GIF60_Pos (28U)
+#define MDMA_GISR1_GIF60_Msk (0x1U << MDMA_GISR1_GIF60_Pos) /*!< 0x10000000 */
+#define MDMA_GISR1_GIF60 MDMA_GISR1_GIF60_Msk /*!< Channel 60 global interrupt flag */
+#define MDMA_GISR1_GIF61_Pos (29U)
+#define MDMA_GISR1_GIF61_Msk (0x1U << MDMA_GISR1_GIF61_Pos) /*!< 0x20000000 */
+#define MDMA_GISR1_GIF61 MDMA_GISR1_GIF61_Msk /*!< Channel 61 global interrupt flag */
+#define MDMA_GISR1_GIF62_Pos (30U)
+#define MDMA_GISR1_GIF62_Msk (0x1U << MDMA_GISR1_GIF62_Pos) /*!< 0x40000000 */
+#define MDMA_GISR1_GIF62 MDMA_GISR1_GIF62_Msk /*!< Channel 62 global interrupt flag */
+
+/******************** Bit definition for MDMA_CxISR register ****************/
+#define MDMA_CISR_TEIF_Pos (0U)
+#define MDMA_CISR_TEIF_Msk (0x1U << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
+#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
+#define MDMA_CISR_CTCIF_Pos (1U)
+#define MDMA_CISR_CTCIF_Msk (0x1U << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
+#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
+#define MDMA_CISR_BRTIF_Pos (2U)
+#define MDMA_CISR_BRTIF_Msk (0x1U << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
+#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
+#define MDMA_CISR_BTIF_Pos (3U)
+#define MDMA_CISR_BTIF_Msk (0x1U << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
+#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
+#define MDMA_CISR_TCIF_Pos (4U)
+#define MDMA_CISR_TCIF_Msk (0x1U << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
+#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
+#define MDMA_CISR_CRQA_Pos (16U)
+#define MDMA_CISR_CRQA_Msk (0x1U << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+
+/******************** Bit definition for MDMA_CxIFCR register ****************/
+#define MDMA_CIFCR_CTEIF_Pos (0U)
+#define MDMA_CIFCR_CTEIF_Msk (0x1U << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
+#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
+#define MDMA_CIFCR_CCTCIF_Pos (1U)
+#define MDMA_CIFCR_CCTCIF_Msk (0x1U << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
+#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
+#define MDMA_CIFCR_CBRTIF_Pos (2U)
+#define MDMA_CIFCR_CBRTIF_Msk (0x1U << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
+#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
+#define MDMA_CIFCR_CBTIF_Pos (3U)
+#define MDMA_CIFCR_CBTIF_Msk (0x1U << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
+#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
+#define MDMA_CIFCR_CLTCIF_Pos (4U)
+#define MDMA_CIFCR_CLTCIF_Msk (0x1U << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
+#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
+
+/******************** Bit definition for MDMA_CxESR register ****************/
+#define MDMA_CESR_TEA_Pos (0U)
+#define MDMA_CESR_TEA_Msk (0x7FU << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
+#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
+#define MDMA_CESR_TED_Pos (7U)
+#define MDMA_CESR_TED_Msk (0x1U << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
+#define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
+#define MDMA_CESR_TELD_Pos (8U)
+#define MDMA_CESR_TELD_Msk (0x1U << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
+#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
+#define MDMA_CESR_TEMD_Pos (9U)
+#define MDMA_CESR_TEMD_Msk (0x1U << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
+#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
+#define MDMA_CESR_ASE_Pos (10U)
+#define MDMA_CESR_ASE_Msk (0x1U << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
+#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
+#define MDMA_CESR_BSE_Pos (11U)
+#define MDMA_CESR_BSE_Msk (0x1U << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
+#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
+
+/******************** Bit definition for MDMA_CxCR register ****************/
+#define MDMA_CCR_EN_Pos (0U)
+#define MDMA_CCR_EN_Msk (0x1U << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
+#define MDMA_CCR_TEIE_Pos (1U)
+#define MDMA_CCR_TEIE_Msk (0x1U << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
+#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define MDMA_CCR_CTCIE_Pos (2U)
+#define MDMA_CCR_CTCIE_Msk (0x1U << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
+#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
+#define MDMA_CCR_BRTIE_Pos (3U)
+#define MDMA_CCR_BRTIE_Msk (0x1U << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
+#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
+#define MDMA_CCR_BTIE_Pos (4U)
+#define MDMA_CCR_BTIE_Msk (0x1U << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
+#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
+#define MDMA_CCR_TCIE_Pos (5U)
+#define MDMA_CCR_TCIE_Msk (0x1U << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
+#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
+#define MDMA_CCR_PL_Pos (6U)
+#define MDMA_CCR_PL_Msk (0x3U << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
+#define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
+#define MDMA_CCR_PL_0 (0x1U << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
+#define MDMA_CCR_PL_1 (0x2U << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
+#define MDMA_CCR_SM_Pos (8U)
+#define MDMA_CCR_SM_Msk (0x1U << MDMA_CCR_SM_Pos) /*!< 0x00000100 */
+#define MDMA_CCR_SM MDMA_CCR_SM_Msk /*!< Secure Mode Eanble */
+#define MDMA_CCR_BEX_Pos (12U)
+#define MDMA_CCR_BEX_Msk (0x1U << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_HEX_Pos (13U)
+#define MDMA_CCR_HEX_Msk (0x1U << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_WEX_Pos (14U)
+#define MDMA_CCR_WEX_Msk (0x1U << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_SWRQ_Pos (16U)
+#define MDMA_CCR_SWRQ_Msk (0x1U << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
+#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
+
+/******************** Bit definition for MDMA_CxTCR register ****************/
+#define MDMA_CTCR_SINC_Pos (0U)
+#define MDMA_CTCR_SINC_Msk (0x3U << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
+#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
+#define MDMA_CTCR_SINC_0 (0x1U << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
+#define MDMA_CTCR_SINC_1 (0x2U << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
+#define MDMA_CTCR_DINC_Pos (2U)
+#define MDMA_CTCR_DINC_Msk (0x3U << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
+#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
+#define MDMA_CTCR_DINC_0 (0x1U << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
+#define MDMA_CTCR_DINC_1 (0x2U << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
+#define MDMA_CTCR_SSIZE_Pos (4U)
+#define MDMA_CTCR_SSIZE_Msk (0x3U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
+#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
+#define MDMA_CTCR_SSIZE_0 (0x1U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
+#define MDMA_CTCR_SSIZE_1 (0x2U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
+#define MDMA_CTCR_DSIZE_Pos (6U)
+#define MDMA_CTCR_DSIZE_Msk (0x3U << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
+#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
+#define MDMA_CTCR_DSIZE_0 (0x1U << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
+#define MDMA_CTCR_DSIZE_1 (0x2U << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
+#define MDMA_CTCR_SINCOS_Pos (8U)
+#define MDMA_CTCR_SINCOS_Msk (0x3U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
+#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
+#define MDMA_CTCR_SINCOS_0 (0x1U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
+#define MDMA_CTCR_SINCOS_1 (0x2U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
+#define MDMA_CTCR_DINCOS_Pos (10U)
+#define MDMA_CTCR_DINCOS_Msk (0x3U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
+#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
+#define MDMA_CTCR_DINCOS_0 (0x1U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
+#define MDMA_CTCR_DINCOS_1 (0x2U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
+#define MDMA_CTCR_SBURST_Pos (12U)
+#define MDMA_CTCR_SBURST_Msk (0x7U << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
+#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
+#define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
+#define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
+#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */
+#define MDMA_CTCR_DBURST_Pos (15U)
+#define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
+#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
+#define MDMA_CTCR_DBURST_0 (0x1U << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
+#define MDMA_CTCR_DBURST_1 (0x2U << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
+#define MDMA_CTCR_DBURST_2 (0x4U << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
+#define MDMA_CTCR_TLEN_Pos (18U)
+#define MDMA_CTCR_TLEN_Msk (0x7FU << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
+#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
+#define MDMA_CTCR_PKE_Pos (25U)
+#define MDMA_CTCR_PKE_Msk (0x1U << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
+#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
+#define MDMA_CTCR_PAM_Pos (26U)
+#define MDMA_CTCR_PAM_Msk (0x3U << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM_0 (0x1U << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
+#define MDMA_CTCR_PAM_1 (0x2U << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
+#define MDMA_CTCR_TRGM_Pos (28U)
+#define MDMA_CTCR_TRGM_Msk (0x3U << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
+#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
+#define MDMA_CTCR_TRGM_0 (0x1U << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
+#define MDMA_CTCR_TRGM_1 (0x2U << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
+#define MDMA_CTCR_SWRM_Pos (30U)
+#define MDMA_CTCR_SWRM_Msk (0x1U << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
+#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
+#define MDMA_CTCR_BWM_Pos (31U)
+#define MDMA_CTCR_BWM_Msk (0x1U << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
+#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
+
+/******************** Bit definition for MDMA_CxBNDTR register ****************/
+#define MDMA_CBNDTR_BNDT_Pos (0U)
+#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFU << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
+#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
+#define MDMA_CBNDTR_BRSUM_Pos (18U)
+#define MDMA_CBNDTR_BRSUM_Msk (0x1U << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
+#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
+#define MDMA_CBNDTR_BRDUM_Pos (19U)
+#define MDMA_CBNDTR_BRDUM_Msk (0x1U << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
+#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
+#define MDMA_CBNDTR_BRC_Pos (20U)
+#define MDMA_CBNDTR_BRC_Msk (0xFFFU << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
+#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
+
+/******************** Bit definition for MDMA_CxSAR register ****************/
+#define MDMA_CSAR_SAR_Pos (0U)
+#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFU << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
+#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
+
+/******************** Bit definition for MDMA_CxDAR register ****************/
+#define MDMA_CDAR_DAR_Pos (0U)
+#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFU << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
+#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
+
+/******************** Bit definition for MDMA_CxBRUR ************************/
+#define MDMA_CBRUR_SUV_Pos (0U)
+#define MDMA_CBRUR_SUV_Msk (0xFFFFU << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
+#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
+#define MDMA_CBRUR_DUV_Pos (16U)
+#define MDMA_CBRUR_DUV_Msk (0xFFFFU << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
+#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
+
+/******************** Bit definition for MDMA_CxLAR *************************/
+#define MDMA_CLAR_LAR_Pos (0U)
+#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFU << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
+#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
+
+/******************** Bit definition for MDMA_CxTBR) ************************/
+#define MDMA_CTBR_TSEL_Pos (0U)
+#define MDMA_CTBR_TSEL_Msk (0xFFU << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
+#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
+#define MDMA_CTBR_SBUS_Pos (16U)
+#define MDMA_CTBR_SBUS_Msk (0x1U << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
+#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
+#define MDMA_CTBR_DBUS_Pos (17U)
+#define MDMA_CTBR_DBUS_Msk (0x1U << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
+#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
+
+/******************** Bit definition for MDMA_CxMAR) ************************/
+#define MDMA_CMAR_MAR_Pos (0U)
+#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFU << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
+#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
+
+/******************** Bit definition for MDMA_CxMDR) ************************/
+#define MDMA_CMDR_MDR_Pos (0U)
+#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFU << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
+#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask address */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos (1U)
+#define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
+
+#define OPAMP_CSR_VPSEL_Pos (2U)
+#define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
+
+#define OPAMP_CSR_VMSEL_Pos (5U)
+#define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
+
+#define OPAMP_CSR_OPAHSM_Pos (8U)
+#define OPAMP_CSR_OPAHSM_Msk (0x1U << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
+#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
+#define OPAMP_CSR_CALON_Pos (11U)
+#define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
+#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
+
+#define OPAMP_CSR_CALSEL_Pos (12U)
+#define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
+
+#define OPAMP_CSR_PGGAIN_Pos (14U)
+#define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
+
+#define OPAMP_CSR_USERTRIM_Pos (18U)
+#define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP_CSR_TSTREF_Pos (29U)
+#define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
+#define OPAMP_CSR_CALOUT_Pos (30U)
+#define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
+#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
+
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAEN_Pos (0U)
+#define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_FORCEVP_Pos (1U)
+#define OPAMP1_CSR_FORCEVP_Msk (0x1U << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
+
+#define OPAMP1_CSR_VPSEL_Pos (2U)
+#define OPAMP1_CSR_VPSEL_Msk (0x3U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP1_CSR_VPSEL_0 (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1 (0x2U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
+
+#define OPAMP1_CSR_VMSEL_Pos (5U)
+#define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
+
+#define OPAMP1_CSR_OPAHSM_Pos (8U)
+#define OPAMP1_CSR_OPAHSM_Msk (0x1U << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
+#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
+#define OPAMP1_CSR_CALON_Pos (11U)
+#define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
+
+#define OPAMP1_CSR_CALSEL_Pos (12U)
+#define OPAMP1_CSR_CALSEL_Msk (0x3U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0 (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1 (0x2U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
+
+#define OPAMP1_CSR_PGGAIN_Pos (14U)
+#define OPAMP1_CSR_PGGAIN_Msk (0xFU << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGGAIN_0 (0x1U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1 (0x2U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2 (0x4U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3 (0x8U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
+
+#define OPAMP1_CSR_USERTRIM_Pos (18U)
+#define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP1_CSR_TSTREF_Pos (29U)
+#define OPAMP1_CSR_TSTREF_Msk (0x1U << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
+#define OPAMP1_CSR_CALOUT_Pos (30U)
+#define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
+#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAEN_Pos (0U)
+#define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_FORCEVP_Pos (1U)
+#define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
+
+#define OPAMP2_CSR_VPSEL_Pos (2U)
+#define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
+#define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
+
+#define OPAMP2_CSR_VMSEL_Pos (5U)
+#define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
+
+#define OPAMP2_CSR_OPAHSM_Pos (8U)
+#define OPAMP2_CSR_OPAHSM_Msk (0x1U << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
+#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
+#define OPAMP2_CSR_CALON_Pos (11U)
+#define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
+
+#define OPAMP2_CSR_CALSEL_Pos (12U)
+#define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
+
+#define OPAMP2_CSR_PGGAIN_Pos (14U)
+#define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
+
+#define OPAMP2_CSR_USERTRIM_Pos (18U)
+#define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
+#define OPAMP2_CSR_TSTREF_Pos (29U)
+#define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
+#define OPAMP2_CSR_CALOUT_Pos (30U)
+#define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
+#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
+
+/******************* Bit definition for OPAMP_OTR register ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP1_OTR register ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP2_OTR register ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP_HSOTR register ****************/
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP1_HSOTR register ****************/
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************* Bit definition for OPAMP2_HSOTR register ****************/
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR1 register ********************/
+#define PWR_CR1_RESERVED3_Pos (19U)
+#define PWR_CR1_RESERVED3_Msk (0x1FFFU << PWR_CR1_RESERVED3_Pos) /*!< 0xFFF80000 */
+#define PWR_CR1_RESERVED3 PWR_CR1_RESERVED3_Msk /*!< Reserved, must be kept at reset value */
+#define PWR_CR1_ALS_Pos (17U)
+#define PWR_CR1_ALS_Msk (0x3U << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
+#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
+#define PWR_CR1_AVDEN_Pos (16U)
+#define PWR_CR1_AVDEN_Msk (0x1U << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
+#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Peripheral Voltage Monitor on VDDA enable */
+#define PWR_CR1_RESERVED2_Pos (11U)
+#define PWR_CR1_RESERVED2_Msk (0x1FU << PWR_CR1_RESERVED2_Pos) /*!< 0x0000F800 */
+#define PWR_CR1_RESERVED2 PWR_CR1_RESERVED2_Msk /*!< Reserved, must be kept at reset value */
+#define PWR_CR1_RESERVED1_Pos (9U)
+#define PWR_CR1_RESERVED1_Msk (0x1U << PWR_CR1_RESERVED1_Pos) /*!< 0x00000200 */
+#define PWR_CR1_RESERVED1 PWR_CR1_RESERVED1_Msk /*!< Reserved, must be kept at reset value */
+#define PWR_CR1_DBP_Pos (8U)
+#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
+#define PWR_CR1_PLS_Pos (5U)
+#define PWR_CR1_PLS_Msk (0x7U << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
+#define PWR_CR1_PVDEN_Pos (4U)
+#define PWR_CR1_PVDEN_Msk (0x1U << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
+#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
+#define PWR_CR1_RESERVED0_Pos (3U)
+#define PWR_CR1_RESERVED0_Msk (0x1U << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
+#define PWR_CR1_RESERVED0 PWR_CR1_RESERVED0_Msk /*!< Reserved, must be kept at reset value */
+#define PWR_CR1_LVDS_Pos (2U)
+#define PWR_CR1_LVDS_Msk (0x1U << PWR_CR1_LVDS_Pos) /*!< 0x00000004 */
+#define PWR_CR1_LVDS PWR_CR1_LVDS_Msk /*!< Low Voltage Deepsleep LP-STOP mode selection */
+#define PWR_CR1_LPCFG_Pos (1U)
+#define PWR_CR1_LPCFG_Msk (0x1U << PWR_CR1_LPCFG_Pos) /*!< 0x00000002 */
+#define PWR_CR1_LPCFG PWR_CR1_LPCFG_Msk /*!< PWR_ON pin configuration */
+#define PWR_CR1_LPDS_Pos (0U)
+#define PWR_CR1_LPDS_Msk (0x1U << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
+#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep STOP mode selection */
+
+/*!< AVD level configuration */
+#define PWR_CR1_ALS_LEV0 ((uint32_t)0x00000000) /*!< AVD level 0 */
+#define PWR_CR1_ALS_LEV1_Pos (17U)
+#define PWR_CR1_ALS_LEV1_Msk (0x1U << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
+#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
+#define PWR_CR1_ALS_LEV2_Pos (18U)
+#define PWR_CR1_ALS_LEV2_Msk (0x1U << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
+#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
+#define PWR_CR1_ALS_LEV3_Pos (17U)
+#define PWR_CR1_ALS_LEV3_Msk (0x3U << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
+#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
+
+/*!< PVD level configuration */
+#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR1_PLS_LEV1_Pos (5U)
+#define PWR_CR1_PLS_LEV1_Msk (0x1U << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
+#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
+#define PWR_CR1_PLS_LEV2_Pos (6U)
+#define PWR_CR1_PLS_LEV2_Msk (0x1U << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
+#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
+#define PWR_CR1_PLS_LEV3_Pos (5U)
+#define PWR_CR1_PLS_LEV3_Msk (0x3U << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
+#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
+#define PWR_CR1_PLS_LEV4_Pos (7U)
+#define PWR_CR1_PLS_LEV4_Msk (0x1U << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
+#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
+#define PWR_CR1_PLS_LEV5_Pos (5U)
+#define PWR_CR1_PLS_LEV5_Msk (0x5U << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
+#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
+#define PWR_CR1_PLS_LEV6_Pos (6U)
+#define PWR_CR1_PLS_LEV6_Msk (0x3U << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
+#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
+#define PWR_CR1_PLS_LEV7_Pos (5U)
+#define PWR_CR1_PLS_LEV7_Msk (0x7U << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
+#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
+
+/******************** Bit definition for PWR_CSR1 register ********************/
+#define PWR_CSR1_AVDO_Pos (16U)
+#define PWR_CSR1_AVDO_Msk (0x1U << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
+#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage detector Output on VDDA */
+#define PWR_CSR1_PVDO_Pos (4U)
+#define PWR_CSR1_PVDO_Msk (0x1U << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
+#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
+
+/******************** Bit definition for PWR_CR2 register ********************/
+#define PWR_CR2_BREN_Pos (0U)
+#define PWR_CR2_BREN_Msk (0x1U << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
+#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
+#define PWR_CR2_RREN_Pos (1U)
+#define PWR_CR2_RREN_Msk (0x1U << PWR_CR2_RREN_Pos) /*!< 0x00000002 */
+#define PWR_CR2_RREN PWR_CR2_RREN_Msk /*!< Retention Regulator enable */
+#define PWR_CR2_MONEN_Pos (4U)
+#define PWR_CR2_MONEN_Msk (0x1U << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
+#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
+#define PWR_CR2_BRRDY_Pos (16U)
+#define PWR_CR2_BRRDY_Msk (0x1U << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
+#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup Regulator ready */
+#define PWR_CR2_RRRDY_Pos (17U)
+#define PWR_CR2_RRRDY_Msk (0x1U << PWR_CR2_RRRDY_Pos) /*!< 0x00020000 */
+#define PWR_CR2_RRRDY PWR_CR2_RRRDY_Msk /*!< Retention Regulator ready */
+#define PWR_CR2_VBATL_Pos (20U)
+#define PWR_CR2_VBATL_Msk (0x1U << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
+#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level equal or below low threshold */
+#define PWR_CR2_VBATH_Pos (21U)
+#define PWR_CR2_VBATH_Msk (0x1U << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
+#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level equal or above high threshold */
+#define PWR_CR2_TEMPL_Pos (22U)
+#define PWR_CR2_TEMPL_Msk (0x1U << PWR_CR2_TEMPL_Pos) /*!< 0x00300000 */
+#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level equal or below low threshold */
+#define PWR_CR2_TEMPH_Pos (23U)
+#define PWR_CR2_TEMPH_Msk (0x1U << PWR_CR2_TEMPH_Pos) /*!< 0x00400000 */
+#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level equal or below high threshold */
+
+/******************** Bit definition for PWR_CR3 register ********************/
+#define PWR_CR3_VBE_Pos (8U)
+#define PWR_CR3_VBE_Msk (0x1U << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
+#define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
+#define PWR_CR3_VBRS_Pos (9U)
+#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
+#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
+#define PWR_CR3_DDRSREN_Pos (10U)
+#define PWR_CR3_DDRSREN_Msk (0x1U << PWR_CR3_DDRSREN_Pos) /*!< 0x00000400 */
+#define PWR_CR3_DDRSREN PWR_CR3_DDRSREN_Msk /*!< DDR self-refresh in standby mode enable */
+#define PWR_CR3_DDRSRDIS_Pos (11U)
+#define PWR_CR3_DDRSRDIS_Msk (0x1U << PWR_CR3_DDRSRDIS_Pos) /*!< 0x00000800 */
+#define PWR_CR3_DDRSRDIS PWR_CR3_DDRSRDIS_Msk /*!< DDR self-refresh retention after standby disable */
+#define PWR_CR3_DDRRETEN_Pos (12U)
+#define PWR_CR3_DDRRETEN_Msk (0x1U << PWR_CR3_DDRRETEN_Pos) /*!< 0x00001000 */
+#define PWR_CR3_DDRRETEN PWR_CR3_DDRRETEN_Msk /*!< DDR retention enable */
+#define PWR_CR3_POPL_Pos (17U)
+#define PWR_CR3_POPL_Msk (0x1FU << PWR_CR3_POPL_Pos) /*!< 0x003E0000 */
+#define PWR_CR3_POPL PWR_CR3_POPL_Msk /*!< PWR_ON pulse low configuration */
+#define PWR_CR3_USB33DEN_Pos (24U)
+#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
+#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< USB33DEN: USB 3.3V voltage level detector enable */
+#define PWR_CR3_USB33RDY_Pos (26U)
+#define PWR_CR3_USB33RDY_Msk (0x1U << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
+#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB 3.3V supply ready */
+#define PWR_CR3_REG18EN_Pos (28U)
+#define PWR_CR3_REG18EN_Msk (0x1U << PWR_CR3_REG18EN_Pos) /*!< 0x10000000 */
+#define PWR_CR3_REG18EN PWR_CR3_REG18EN_Msk /*!< 1V8 regulator enable */
+#define PWR_CR3_REG18RDY_Pos (29U)
+#define PWR_CR3_REG18RDY_Msk (0x1U << PWR_CR3_REG18RDY_Pos) /*!< 0x20000000 */
+#define PWR_CR3_REG18RDY PWR_CR3_REG18RDY_Msk /*!< 1V8 regulator supply ready */
+#define PWR_CR3_REG11EN_Pos (30U)
+#define PWR_CR3_REG11EN_Msk (0x1U << PWR_CR3_REG11EN_Pos) /*!< 0x40000000 */
+#define PWR_CR3_REG11EN PWR_CR3_REG11EN_Msk /*!< 1V1 regulator enable */
+#define PWR_CR3_REG11RDY_Pos (31U)
+#define PWR_CR3_REG11RDY_Msk (0x1U << PWR_CR3_REG11RDY_Pos) /*!< 0x80000000 */
+#define PWR_CR3_REG11RDY PWR_CR3_REG11RDY_Msk /*!< 1V1 regulator supply ready */
+
+/******************** Bit definition for PWR_MPUCR register ********************/
+#define PWR_MPUCR_PDDS_Pos (0U)
+#define PWR_MPUCR_PDDS_Msk (0x1U << PWR_MPUCR_PDDS_Pos) /*!< 0x00000001 */
+#define PWR_MPUCR_PDDS PWR_MPUCR_PDDS_Msk /*!< System Power Down Deepsleep selection */
+#define PWR_MPUCR_CSTBYDIS_Pos (3U)
+#define PWR_MPUCR_CSTBYDIS_Msk (0x1U << PWR_MPUCR_CSTBYDIS_Pos) /*!< 0x00000008 */
+#define PWR_MPUCR_CSTBYDIS PWR_MPUCR_CSTBYDIS_Msk /*!< MPU CStandby mode disable */
+#define PWR_MPUCR_STOPF_Pos (5U)
+#define PWR_MPUCR_STOPF_Msk (0x1U << PWR_MPUCR_STOPF_Pos) /*!< 0x00000020 */
+#define PWR_MPUCR_STOPF PWR_MPUCR_STOPF_Msk /*!< Stop Flag */
+#define PWR_MPUCR_SBF_Pos (6U)
+#define PWR_MPUCR_SBF_Msk (0x1U << PWR_MPUCR_SBF_Pos) /*!< 0x00000040 */
+#define PWR_MPUCR_SBF PWR_MPUCR_SBF_Msk /*!< System Standby Flag */
+#define PWR_MPUCR_SBF_MPU_Pos (7U)
+#define PWR_MPUCR_SBF_MPU_Msk (0x1U << PWR_MPUCR_SBF_MPU_Pos) /*!< 0x00000080 */
+#define PWR_MPUCR_SBF_MPU PWR_MPUCR_SBF_MPU_Msk /*!< MPU Standby Flag */
+#define PWR_MPUCR_CSSF_Pos (9U)
+#define PWR_MPUCR_CSSF_Msk (0x1U << PWR_MPUCR_CSSF_Pos) /*!< 0x00000200 */
+#define PWR_MPUCR_CSSF PWR_MPUCR_CSSF_Msk /*!< Clear MCU STANDBY, STOP and HOLD flags.(always read as 0) */
+#define PWR_MPUCR_STANDBYWFIL2_Pos (15U)
+#define PWR_MPUCR_STANDBYWFIL2_Msk (0x1U << PWR_MPUCR_STANDBYWFIL2_Pos) /*!< 0x00008000 */
+#define PWR_MPUCR_STANDBYWFIL2 PWR_MPUCR_STANDBYWFIL2_Msk /*!< MPU system idle indication */
+
+/******************** Bit definition for PWR_MCUCR register ********************/
+#define PWR_MCUCR_PDDS_Pos (0U)
+#define PWR_MCUCR_PDDS_Msk (0x1U << PWR_MCUCR_PDDS_Pos) /*!< 0x00000001 */
+#define PWR_MCUCR_PDDS PWR_MCUCR_PDDS_Msk /*!< System Power Down Deepsleep selection */
+#define PWR_MCUCR_STOPF_Pos (5U)
+#define PWR_MCUCR_STOPF_Msk (0x1U << PWR_MCUCR_STOPF_Pos) /*!< 0x00000020 */
+#define PWR_MCUCR_STOPF PWR_MCUCR_STOPF_Msk /*!< Stop Flag */
+#define PWR_MCUCR_SBF_Pos (6U)
+#define PWR_MCUCR_SBF_Msk (0x1U << PWR_MCUCR_SBF_Pos) /*!< 0x00000040 */
+#define PWR_MCUCR_SBF PWR_MCUCR_SBF_Msk /*!< System Standby Flag */
+#define PWR_MCUCR_CSSF_Pos (9U)
+#define PWR_MCUCR_CSSF_Msk (0x1U << PWR_MCUCR_CSSF_Pos) /*!< 0x00000200 */
+#define PWR_MCUCR_CSSF PWR_MCUCR_CSSF_Msk /*!< Clear MCU Standby, Stop flags */
+#define PWR_MCUCR_DEEPSLEEP_Pos (15U)
+#define PWR_MCUCR_DEEPSLEEP_Msk (0x1U << PWR_MCUCR_DEEPSLEEP_Pos) /*!< 0x00008000 */
+#define PWR_MCUCR_DEEPSLEEP PWR_MCUCR_DEEPSLEEP_Msk /*!< MCU system idle indication */
+
+/******************** Bit definition for PWR_WKUPCR register ********************/
+#define PWR_WKUPCR_WKUPPUPD_Pos (16U)
+#define PWR_WKUPCR_WKUPPUPD_Msk (0xFFFU << PWR_WKUPCR_WKUPPUPD_Pos) /*!< 0x0FFF0000 */
+#define PWR_WKUPCR_WKUPPUPD PWR_WKUPCR_WKUPPUPD_Msk /*!< Wakeup Pin pull configuration mask*/
+#define PWR_WKUPCR_WKUPPUPD6_Pos (26U)
+#define PWR_WKUPCR_WKUPPUPD6_Msk (0x3U << PWR_WKUPCR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
+#define PWR_WKUPCR_WKUPPUPD6 PWR_WKUPCR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
+#define PWR_WKUPCR_WKUPPUPD6_0 (0x1U << PWR_WKUPCR_WKUPPUPD6_Pos) /*!< 0x04000000 */
+#define PWR_WKUPCR_WKUPPUPD6_1 (0x2U << PWR_WKUPCR_WKUPPUPD6_Pos) /*!< 0x08000000 */
+#define PWR_WKUPCR_WKUPPUPD5_Pos (24U)
+#define PWR_WKUPCR_WKUPPUPD5_Msk (0x3U << PWR_WKUPCR_WKUPPUPD5_Pos) /*!< 0x03000000 */
+#define PWR_WKUPCR_WKUPPUPD5 PWR_WKUPCR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
+#define PWR_WKUPCR_WKUPPUPD5_0 (0x1U << PWR_WKUPCR_WKUPPUPD5_Pos) /*!< 0x01000000 */
+#define PWR_WKUPCR_WKUPPUPD5_1 (0x2U << PWR_WKUPCR_WKUPPUPD5_Pos) /*!< 0x02000000 */
+#define PWR_WKUPCR_WKUPPUPD4_Pos (22U)
+#define PWR_WKUPCR_WKUPPUPD4_Msk (0x3U << PWR_WKUPCR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
+#define PWR_WKUPCR_WKUPPUPD4 PWR_WKUPCR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
+#define PWR_WKUPCR_WKUPPUPD4_0 (0x1U << PWR_WKUPCR_WKUPPUPD4_Pos) /*!< 0x00400000 */
+#define PWR_WKUPCR_WKUPPUPD4_1 (0x2U << PWR_WKUPCR_WKUPPUPD4_Pos) /*!< 0x00800000 */
+#define PWR_WKUPCR_WKUPPUPD3_Pos (20U)
+#define PWR_WKUPCR_WKUPPUPD3_Msk (0x3U << PWR_WKUPCR_WKUPPUPD3_Pos) /*!< 0x00300000 */
+#define PWR_WKUPCR_WKUPPUPD3 PWR_WKUPCR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
+#define PWR_WKUPCR_WKUPPUPD3_0 (0x1U << PWR_WKUPCR_WKUPPUPD3_Pos) /*!< 0x00100000 */
+#define PWR_WKUPCR_WKUPPUPD3_1 (0x2U << PWR_WKUPCR_WKUPPUPD3_Pos) /*!< 0x00200000 */
+#define PWR_WKUPCR_WKUPPUPD2_Pos (18U)
+#define PWR_WKUPCR_WKUPPUPD2_Msk (0x3U << PWR_WKUPCR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
+#define PWR_WKUPCR_WKUPPUPD2 PWR_WKUPCR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
+#define PWR_WKUPCR_WKUPPUPD2_0 (0x1U << PWR_WKUPCR_WKUPPUPD2_Pos) /*!< 0x00040000 */
+#define PWR_WKUPCR_WKUPPUPD2_1 (0x2U << PWR_WKUPCR_WKUPPUPD2_Pos) /*!< 0x00080000 */
+#define PWR_WKUPCR_WKUPPUPD1_Pos (16U)
+#define PWR_WKUPCR_WKUPPUPD1_Msk (0x3U << PWR_WKUPCR_WKUPPUPD1_Pos) /*!< 0x00030000 */
+#define PWR_WKUPCR_WKUPPUPD1 PWR_WKUPCR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
+#define PWR_WKUPCR_WKUPPUPD1_0 (0x1U << PWR_WKUPCR_WKUPPUPD1_Pos) /*!< 0x00010000 */
+#define PWR_WKUPCR_WKUPPUPD1_1 (0x2U << PWR_WKUPCR_WKUPPUPD1_Pos) /*!< 0x00020000 */
+
+#define PWR_WKUPCR_WKUPP_Pos (8U)
+#define PWR_WKUPCR_WKUPP_Msk (0x3FU << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00003F00 */
+#define PWR_WKUPCR_WKUPP PWR_WKUPCR_WKUPP_Msk /*!< Wakeup Pin Polarity mask*/
+#define PWR_WKUPCR_WKUPP_6 (0x20U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00002000 */
+#define PWR_WKUPCR_WKUPP_5 (0x10U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00001000 */
+#define PWR_WKUPCR_WKUPP_4 (0x08U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000800 */
+#define PWR_WKUPCR_WKUPP_3 (0x04U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000400 */
+#define PWR_WKUPCR_WKUPP_2 (0x02U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000200 */
+#define PWR_WKUPCR_WKUPP_1 (0x01U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000100 */
+
+#define PWR_WKUPCR_WKUPC_Pos (0U)
+#define PWR_WKUPCR_WKUPC_Msk (0x3FU << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000003F */
+#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Wakeup Pin Mask */
+#define PWR_WKUPCR_WKUPC6_Pos (5U)
+#define PWR_WKUPCR_WKUPC6_Msk (0x1U << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
+#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
+#define PWR_WKUPCR_WKUPC5_Pos (4U)
+#define PWR_WKUPCR_WKUPC5_Msk (0x1U << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
+#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
+#define PWR_WKUPCR_WKUPC4_Pos (3U)
+#define PWR_WKUPCR_WKUPC4_Msk (0x1U << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
+#define PWR_WKUPCR_WKUPC3_Pos (2U)
+#define PWR_WKUPCR_WKUPC3_Msk (0x1U << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
+#define PWR_WKUPCR_WKUPC2_Pos (1U)
+#define PWR_WKUPCR_WKUPC2_Msk (0x1U << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
+#define PWR_WKUPCR_WKUPC1_Pos (0U)
+#define PWR_WKUPCR_WKUPC1_Msk (0x1U << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
+
+/******************** Bit definition for PWR_WKUPFR register ********************/
+#define PWR_WKUPFR_WKUPF6_Pos (5U)
+#define PWR_WKUPFR_WKUPF6_Msk (0x1U << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
+#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
+#define PWR_WKUPFR_WKUPF5_Pos (4U)
+#define PWR_WKUPFR_WKUPF5_Msk (0x1U << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
+#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
+#define PWR_WKUPFR_WKUPF4_Pos (3U)
+#define PWR_WKUPFR_WKUPF4_Msk (0x1U << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
+#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
+#define PWR_WKUPFR_WKUPF3_Pos (2U)
+#define PWR_WKUPFR_WKUPF3_Msk (0x1U << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
+#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
+#define PWR_WKUPFR_WKUPF2_Pos (1U)
+#define PWR_WKUPFR_WKUPF2_Msk (0x1U << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
+#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
+#define PWR_WKUPFR_WKUPF1_Pos (0U)
+#define PWR_WKUPFR_WKUPF1_Msk (0x1U << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
+#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
+
+/******************** Bit definition for PWR_MPUWKUPENR register ********************/
+#define PWR_MPUWKUPENR_WKUPEN_Pos (0U)
+#define PWR_MPUWKUPENR_WKUPEN_Msk (0x3FU << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x0000003F */
+#define PWR_MPUWKUPENR_WKUPEN PWR_MPUWKUPENR_WKUPEN_Msk /*!< Enable Wakeup and interrupt for CPU1 */
+#define PWR_MPUWKUPENR_WKUPEN_6 (0x20U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000020 */
+#define PWR_MPUWKUPENR_WKUPEN_5 (0x10U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000010 */
+#define PWR_MPUWKUPENR_WKUPEN_4 (0x08U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000008 */
+#define PWR_MPUWKUPENR_WKUPEN_3 (0x04U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000004 */
+#define PWR_MPUWKUPENR_WKUPEN_2 (0x02U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000002 */
+#define PWR_MPUWKUPENR_WKUPEN_1 (0x01U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000001 */
+
+/******************** Bit definition for PWR_MCUWKUPENR register ********************/
+#define PWR_MCUWKUPENR_WKUPEN_Pos (0U)
+#define PWR_MCUWKUPENR_WKUPEN_Msk (0x3FU << PWR_MCUWKUPENR_WKUPEN_Pos) /*!< 0x0000003F */
+#define PWR_MCUWKUPENR_WKUPEN PWR_MCUWKUPENR_WKUPEN_Msk /*!< Enable Wakeup and interrupt for CPU2 */
+#define PWR_MCUWKUPENR_WKUPEN6_Pos (5U)
+#define PWR_MCUWKUPENR_WKUPEN6_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN6_Pos) /*!< 0x00000020 */
+#define PWR_MCUWKUPENR_WKUPEN6 PWR_MCUWKUPENR_WKUPEN6_Msk /*!< Enable Wakeup WKUP6 pin and interrupt for CPU2 */
+#define PWR_MCUWKUPENR_WKUPEN5_Pos (4U)
+#define PWR_MCUWKUPENR_WKUPEN5_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN5_Pos) /*!< 0x00000010 */
+#define PWR_MCUWKUPENR_WKUPEN5 PWR_MCUWKUPENR_WKUPEN5_Msk /*!< Enable Wakeup WKUP5 pin and interrupt for CPU2 */
+#define PWR_MCUWKUPENR_WKUPEN4_Pos (3U)
+#define PWR_MCUWKUPENR_WKUPEN4_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN4_Pos) /*!< 0x00000008 */
+#define PWR_MCUWKUPENR_WKUPEN4 PWR_MCUWKUPENR_WKUPEN4_Msk /*!< Enable Wakeup WKUP4 pin and interrupt for CPU2 */
+#define PWR_MCUWKUPENR_WKUPEN3_Pos (2U)
+#define PWR_MCUWKUPENR_WKUPEN3_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN3_Pos) /*!< 0x00000004 */
+#define PWR_MCUWKUPENR_WKUPEN3 PWR_MCUWKUPENR_WKUPEN3_Msk /*!< Enable Wakeup WKUP3 pin and interrupt for CPU2 */
+#define PWR_MCUWKUPENR_WKUPEN2_Pos (1U)
+#define PWR_MCUWKUPENR_WKUPEN2_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN2_Pos) /*!< 0x00000002 */
+#define PWR_MCUWKUPENR_WKUPEN2 PWR_MCUWKUPENR_WKUPEN2_Msk /*!< Enable Wakeup WKUP2 pin and interrupt for CPU2 */
+#define PWR_MCUWKUPENR_WKUPEN1_Pos (0U)
+#define PWR_MCUWKUPENR_WKUPEN1_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN1_Pos) /*!< 0x00000001 */
+#define PWR_MCUWKUPENR_WKUPEN1 PWR_MCUWKUPENR_WKUPEN1_Msk /*!< Enable Wakeup WKUP1 pin and interrupt for CPU2 */
+
+/******************** Bit definition for PWR_VER register ********************/
+#define PWR_VER_MAJREV_Pos (4U)
+#define PWR_VER_MAJREV_Msk (0xFU << PWR_VER_MAJREV_Pos) /*!< 0x000000F0 */
+#define PWR_VER_MAJREV PWR_VER_MAJREV_Msk /*!< Major Revision number */
+#define PWR_VER_MINREV_Pos (0U)
+#define PWR_VER_MINREV_Msk (0xFU << PWR_VER_MINREV_Pos) /*!< 0x0000000F */
+#define PWR_VER_MINREV PWR_VER_MINREV_Msk /*!< Minor Revision number */
+
+/******************** Bit definition for PWR_ID register ********************/
+#define PWR_ID_IPID_Pos (0U)
+#define PWR_ID_IPID_Msk (0xFFFFFFFFU << PWR_ID_IPID_Pos) /*!< 0xFFFFFFFF */
+#define PWR_ID_IPID PWR_ID_IPID_Msk /*!< IP identification */
+
+/******************** Bit definition for PWR_SID register ********************/
+#define PWR_SID_SID_Pos (0U)
+#define PWR_SID_SID_Msk (0xFFFFFFFFU << PWR_SID_SID_Pos) /*!< 0xFFFFFFFF */
+#define PWR_SID_SID PWR_SID_SID_Msk /*!< Size identification */
+
+
+/******************************************************************************/
+/* */
+/* Boot and Security and OTP Control (BSEC) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for BSEC_OTP_CONFIG register *****************/
+#define BSEC_OTP_CONFIG_PWRUP_Pos (0U)
+#define BSEC_OTP_CONFIG_PWRUP_Msk (0x1U << BSEC_OTP_CONFIG_PWRUP_Pos) /*!< 0x00000001 */
+#define BSEC_OTP_CONFIG_PWRUP BSEC_OTP_CONFIG_PWRUP_Msk /*!< OTP power-up control */
+#define BSEC_OTP_CONFIG_FRC_Pos (1U)
+#define BSEC_OTP_CONFIG_FRC_Msk (0x3U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000006 */
+#define BSEC_OTP_CONFIG_FRC BSEC_OTP_CONFIG_FRC_Msk /*!< OTP clock frequency range selection */
+#define BSEC_OTP_CONFIG_FRC_0 (0x1U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000002 */
+#define BSEC_OTP_CONFIG_FRC_1 (0x2U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000004 */
+#define BSEC_OTP_CONFIG_PRGWIDTH_Pos (3U)
+#define BSEC_OTP_CONFIG_PRGWIDTH_Msk (0xFU << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000078 */
+#define BSEC_OTP_CONFIG_PRGWIDTH BSEC_OTP_CONFIG_PRGWIDTH_Msk /*!< OTP programming pulse width */
+#define BSEC_OTP_CONFIG_PRGWIDTH_0 (0x1U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000008 */
+#define BSEC_OTP_CONFIG_PRGWIDTH_1 (0x2U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000010 */
+#define BSEC_OTP_CONFIG_PRGWIDTH_2 (0x4U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000020 */
+#define BSEC_OTP_CONFIG_PRGWIDTH_3 (0x8U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000040 */
+#define BSEC_OTP_CONFIG_TREAD_Pos (7U)
+#define BSEC_OTP_CONFIG_TREAD_Msk (0x3U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000180 */
+#define BSEC_OTP_CONFIG_TREAD BSEC_OTP_CONFIG_TREAD_Msk /*!< set OTP reading current level */
+#define BSEC_OTP_CONFIG_TREAD_0 (0x1U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000080 */
+#define BSEC_OTP_CONFIG_TREAD_1 (0x2U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000100 */
+
+/****************** Bit definition for BSEC_OTP_CONTROL register ****************/
+#define BSEC_OTP_CONTROL_ADDR_Pos (0U)
+#define BSEC_OTP_CONTROL_ADDR_Msk (0x7FU << BSEC_OTP_CONTROL_ADDR_Pos) /*!< 0x0000007F */
+#define BSEC_OTP_CONTROL_ADDR BSEC_OTP_CONTROL_ADDR_Msk /*!< OTP word address */
+#define BSEC_OTP_CONTROL_PROG_Pos (8U)
+#define BSEC_OTP_CONTROL_PROG_Msk (0x1U << BSEC_OTP_CONTROL_PROG_Pos) /*!< 0x00000100 */
+#define BSEC_OTP_CONTROL_PROG BSEC_OTP_CONTROL_PROG_Msk /*!< OTP operation control */
+#define BSEC_OTP_CONTROL_LOCK_Pos (9U)
+#define BSEC_OTP_CONTROL_LOCK_Msk (0x1U << BSEC_OTP_CONTROL_LOCK_Pos) /*!< 0x00000200 */
+#define BSEC_OTP_CONTROL_LOCK BSEC_OTP_CONTROL_LOCK_Msk /*!< OTP permanent word lock control */
+
+/****************** Bit definition for BSEC_OTP_STATUS register *****************/
+#define BSEC_OTP_STATUS_SECURE_Pos (0U)
+#define BSEC_OTP_STATUS_SECURE_Msk (0x1U << BSEC_OTP_STATUS_SECURE_Pos) /*!< 0x00000001 */
+#define BSEC_OTP_STATUS_SECURE BSEC_OTP_STATUS_SECURE_Msk /*!< OTP secured mode */
+#define BSEC_OTP_STATUS_FULLDBG_Pos (1U)
+#define BSEC_OTP_STATUS_FULLDBG_Msk (0x1U << BSEC_OTP_STATUS_FULLDBG_Pos) /*!< 0x00000002 */
+#define BSEC_OTP_STATUS_FULLDBG BSEC_OTP_STATUS_FULLDBG_Msk /*!< OTP mode in full debug */
+#define BSEC_OTP_STATUS_INVALID_Pos (2U)
+#define BSEC_OTP_STATUS_INVALID_Msk (0x1U << BSEC_OTP_STATUS_INVALID_Pos) /*!< 0x00000004 */
+#define BSEC_OTP_STATUS_INVALID BSEC_OTP_STATUS_INVALID_Msk /*!< OTP invalid mode */
+#define BSEC_OTP_STATUS_BUSY_Pos (3U)
+#define BSEC_OTP_STATUS_BUSY_Msk (0x1U << BSEC_OTP_STATUS_BUSY_Pos) /*!< 0x00000008 */
+#define BSEC_OTP_STATUS_BUSY BSEC_OTP_STATUS_BUSY_Msk /*!< OTP operation status */
+#define BSEC_OTP_STATUS_PROGFAIL_Pos (4U)
+#define BSEC_OTP_STATUS_PROGFAIL_Msk (0x1U << BSEC_OTP_STATUS_PROGFAIL_Pos) /*!< 0x00000010 */
+#define BSEC_OTP_STATUS_PROGFAIL BSEC_OTP_STATUS_PROGFAIL_Msk /*!< last programming status */
+#define BSEC_OTP_STATUS_PWRON_Pos (5U)
+#define BSEC_OTP_STATUS_PWRON_Msk (0x1U << BSEC_OTP_STATUS_PWRON_Pos) /*!< 0x00000020 */
+#define BSEC_OTP_STATUS_PWRON BSEC_OTP_STATUS_PWRON_Msk /*!< OTP power status */
+#define BSEC_OTP_STATUS_BIST1LOCK_Pos (6U)
+#define BSEC_OTP_STATUS_BIST1LOCK_Msk (0x1U << BSEC_OTP_STATUS_BIST1LOCK_Pos) /*!< 0x00000040 */
+#define BSEC_OTP_STATUS_BIST1LOCK BSEC_OTP_STATUS_BIST1LOCK_Msk /*!< BIST1 locked */
+#define BSEC_OTP_STATUS_BIST2LOCK_Pos (7U)
+#define BSEC_OTP_STATUS_BIST2LOCK_Msk (0x1U << BSEC_OTP_STATUS_BIST2LOCK_Pos) /*!< 0x00000080 */
+#define BSEC_OTP_STATUS_BIST2LOCK BSEC_OTP_STATUS_BIST2LOCK_Msk /*!< BIST2 locked */
+
+/****************** Bit definition for BSEC_OTP_LOCK register ********************/
+#define BSEC_OTP_LOCK_OTP_Pos (0U)
+#define BSEC_OTP_LOCK_OTP_Msk (0x1U << BSEC_OTP_LOCK_OTP_Pos) /*!< 0x00000001 */
+#define BSEC_OTP_LOCK_OTP BSEC_OTP_LOCK_OTP_Msk /*!< upper OTP read lock */
+#define BSEC_OTP_LOCK_DENREG_Pos (2U)
+#define BSEC_OTP_LOCK_DENREG_Msk (0x1U << BSEC_OTP_LOCK_DENREG_Pos) /*!< 0x00000004 */
+#define BSEC_OTP_LOCK_DENREG BSEC_OTP_LOCK_DENREG_Msk /*!< debug enable register sticky lock */
+#define BSEC_OTP_LOCK_FENREG_Pos (3U)
+#define BSEC_OTP_LOCK_FENREG_Msk (0x1U << BSEC_OTP_LOCK_FENREG_Pos) /*!< 0x00000008 */
+#define BSEC_OTP_LOCK_FENREG BSEC_OTP_LOCK_FENREG_Msk /*!< feature enable register sticky lock */
+#define BSEC_OTP_LOCK_GPLOCK_Pos (4U)
+#define BSEC_OTP_LOCK_GPLOCK_Msk (0x1U << BSEC_OTP_LOCK_GPLOCK_Pos) /*!< 0x00000010 */
+#define BSEC_OTP_LOCK_GPLOCK BSEC_OTP_LOCK_GPLOCK_Msk /*!< programming sticky lock */
+
+/******************** Bit definition for BSEC_DENABLE register********************/
+#define BSEC_DENABLE_DFTEN_Pos (0U)
+#define BSEC_DENABLE_DFTEN_Msk (0x1U << BSEC_DENABLE_DFTEN_Pos) /*!< 0x00000001 */
+#define BSEC_DENABLE_DFTEN BSEC_DENABLE_DFTEN_Msk /*!< DFT enable with signal dften */
+#define BSEC_DENABLE_DBGEN_Pos (1U)
+#define BSEC_DENABLE_DBGEN_Msk (0x1U << BSEC_DENABLE_DBGEN_Pos) /*!< 0x00000002 */
+#define BSEC_DENABLE_DBGEN BSEC_DENABLE_DBGEN_Msk /*!< debug enable with signal dbgen */
+#define BSEC_DENABLE_NIDEN_Pos (2U)
+#define BSEC_DENABLE_NIDEN_Msk (0x1U << BSEC_DENABLE_NIDEN_Pos) /*!< 0x00000004 */
+#define BSEC_DENABLE_NIDEN BSEC_DENABLE_NIDEN_Msk /*!< non-invasive debug enable with signal niden */
+#define BSEC_DENABLE_DEVICEEN_Pos (3U)
+#define BSEC_DENABLE_DEVICEEN_Msk (0x1U << BSEC_DENABLE_DEVICEEN_Pos) /*!< 0x00000008 */
+#define BSEC_DENABLE_DEVICEEN BSEC_DENABLE_DEVICEEN_Msk /*!< controls access to debug component via external debug port by signal deviceen */
+#define BSEC_DENABLE_HDPEN_Pos (4U)
+#define BSEC_DENABLE_HDPEN_Msk (0x1U << BSEC_DENABLE_HDPEN_Pos) /*!< 0x00000010 */
+#define BSEC_DENABLE_HDPEN BSEC_DENABLE_HDPEN_Msk /*!< hardware debug port enable with signal hdpen */
+#define BSEC_DENABLE_SPIDEN_Pos (5U)
+#define BSEC_DENABLE_SPIDEN_Msk (0x1U << BSEC_DENABLE_SPIDEN_Pos) /*!< 0x00000020 */
+#define BSEC_DENABLE_SPIDEN BSEC_DENABLE_SPIDEN_Msk /*!< secure privilege invasive debug enable with signal spniden */
+#define BSEC_DENABLE_SPNIDEN_Pos (6U)
+#define BSEC_DENABLE_SPNIDEN_Msk (0x1U << BSEC_DENABLE_SPNIDEN_Pos) /*!< 0x00000040 */
+#define BSEC_DENABLE_SPNIDEN BSEC_DENABLE_SPNIDEN_Msk /*!< secure privilege non-invasive debug enable with signal spiden */
+#define BSEC_DENABLE_CP15SDISABLE_Pos (7U)
+#define BSEC_DENABLE_CP15SDISABLE_Msk (0x3U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000180 */
+#define BSEC_DENABLE_CP15SDISABLE BSEC_DENABLE_CP15SDISABLE_Msk /*!< write access to some secure Cortex®-A7 CP15 registers disable CPDISABLE[0] applies to CPU0. CPDISABLE[1] applies to CPU1 */
+#define BSEC_DENABLE_CP15SDISABLE_0 (0x1U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000080 */
+#define BSEC_DENABLE_CP15SDISABLE_1 (0x2U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000100 */
+#define BSEC_DENABLE_CFGSDISABLE_Pos (9U)
+#define BSEC_DENABLE_CFGSDISABLE_Msk (0x1U << BSEC_DENABLE_CFGSDISABLE_Pos) /*!< 0x00000200 */
+#define BSEC_DENABLE_CFGSDISABLE BSEC_DENABLE_CFGSDISABLE_Msk /*!< write access to secure GIC registers disable with signal cfgsdisable */
+#define BSEC_DENABLE_DBGSWENABLE_Pos (10U)
+#define BSEC_DENABLE_DBGSWENABLE_Msk (0x1U << BSEC_DENABLE_DBGSWENABLE_Pos) /*!< 0x00000400 */
+#define BSEC_DENABLE_DBGSWENABLE BSEC_DENABLE_DBGSWENABLE_Msk /*!< control self hosted debug enable with signal dbgswenable */
+
+/******************** Bit definition for BSEC_HWCFGR register ***************/
+#define BSEC_HWCFGR_SIZE_Pos (0U)
+#define BSEC_HWCFGR_SIZE_Msk (0xFU << BSEC_HWCFGR_SIZE_Pos) /*!< 0x0000000F */
+#define BSEC_HWCFGR_SIZE BSEC_HWCFGR_SIZE_Msk /*!< OTP Block Size */
+#define BSEC_HWCFGR_ECC_USE_Pos (4U)
+#define BSEC_HWCFGR_ECC_USE_Msk (0xFU << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */
+#define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */
+
+/******************** Bit definition for BSEC_VERR register********************/
+#define BSEC_VERR_MINREV_Pos (0U)
+#define BSEC_VERR_MINREV_Msk (0xFU << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define BSEC_VERR_MINREV BSEC_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
+#define BSEC_VERR_MAJREV_Pos (4U)
+#define BSEC_VERR_MAJREV_Msk (0xFU << BSEC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define BSEC_VERR_MAJREV BSEC_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
+
+/********************** Bit definition for BSEC_IPIDR register ****************/
+#define BSEC_IPIDR_IPID_Pos (0U)
+#define BSEC_IPIDR_IPID_Msk (0xFFFFFFFFU << BSEC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define BSEC_IPIDR_IPID BSEC_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for BSEC_SIDR register *****************/
+#define BSEC_SIDR_SID_Pos (0U)
+#define BSEC_SIDR_SID_Msk (0xFFFFFFFFU << BSEC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define BSEC_SIDR_SID BSEC_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Hardware Debug Port */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for HDP_CTRL register********************/
+#define HDP_CTRL_EN_Pos (0U)
+#define HDP_CTRL_EN_Msk (0x1U << HDP_CTRL_EN_Pos) /*!< 0x00000001 */
+#define HDP_CTRL_EN HDP_CTRL_EN_Msk /*Enable HDP, valid if enabled in BSEC*/
+
+/******************** Bit definition for HDP_MUX register*********************/
+#define HDP_MUX_MUX0_Pos (0U)
+#define HDP_MUX_MUX0_Msk (0xFU << HDP_MUX_MUX0_Pos) /*!< 0x0000000F */
+#define HDP_MUX_MUX0 HDP_MUX_MUX0_Msk /*Select the HDP0 output among the 16 available signals*/
+#define HDP_MUX_MUX0_0 (0x1U << HDP_MUX_MUX0_Pos) /*!< 0x00000001 */
+#define HDP_MUX_MUX0_1 (0x2U << HDP_MUX_MUX0_Pos) /*!< 0x00000002 */
+#define HDP_MUX_MUX0_2 (0x4U << HDP_MUX_MUX0_Pos) /*!< 0x00000004 */
+#define HDP_MUX_MUX0_3 (0x8U << HDP_MUX_MUX0_Pos) /*!< 0x00000008 */
+#define HDP_MUX_MUX1_Pos (4U)
+#define HDP_MUX_MUX1_Msk (0xFU << HDP_MUX_MUX1_Pos) /*!< 0x000000F0 */
+#define HDP_MUX_MUX1 HDP_MUX_MUX1_Msk /*Select the HDP1 output among the 16 available signals*/
+#define HDP_MUX_MUX1_0 (0x1U << HDP_MUX_MUX1_Pos) /*!< 0x00000010 */
+#define HDP_MUX_MUX1_1 (0x2U << HDP_MUX_MUX1_Pos) /*!< 0x00000020 */
+#define HDP_MUX_MUX1_2 (0x4U << HDP_MUX_MUX1_Pos) /*!< 0x00000040 */
+#define HDP_MUX_MUX1_3 (0x8U << HDP_MUX_MUX1_Pos) /*!< 0x00000080 */
+#define HDP_MUX_MUX2_Pos (8U)
+#define HDP_MUX_MUX2_Msk (0xFU << HDP_MUX_MUX2_Pos) /*!< 0x00000F00 */
+#define HDP_MUX_MUX2 HDP_MUX_MUX2_Msk /*Select the HDP2 output among the 16 available signals*/
+#define HDP_MUX_MUX2_0 (0x1U << HDP_MUX_MUX2_Pos) /*!< 0x00000100 */
+#define HDP_MUX_MUX2_1 (0x2U << HDP_MUX_MUX2_Pos) /*!< 0x00000200 */
+#define HDP_MUX_MUX2_2 (0x4U << HDP_MUX_MUX2_Pos) /*!< 0x00000400 */
+#define HDP_MUX_MUX2_3 (0x8U << HDP_MUX_MUX2_Pos) /*!< 0x00000800 */
+#define HDP_MUX_MUX3_Pos (12U)
+#define HDP_MUX_MUX3_Msk (0xFU << HDP_MUX_MUX3_Pos) /*!< 0x0000F000 */
+#define HDP_MUX_MUX3 HDP_MUX_MUX3_Msk /*Select the HDP3 output among the 16 available signals*/
+#define HDP_MUX_MUX3_0 (0x1U << HDP_MUX_MUX3_Pos) /*!< 0x00001000 */
+#define HDP_MUX_MUX3_1 (0x2U << HDP_MUX_MUX3_Pos) /*!< 0x00002000 */
+#define HDP_MUX_MUX3_2 (0x4U << HDP_MUX_MUX3_Pos) /*!< 0x00004000 */
+#define HDP_MUX_MUX3_3 (0x8U << HDP_MUX_MUX3_Pos) /*!< 0x00008000 */
+#define HDP_MUX_MUX4_Pos (16U)
+#define HDP_MUX_MUX4_Msk (0xFU << HDP_MUX_MUX4_Pos) /*!< 0x000F0000 */
+#define HDP_MUX_MUX4 HDP_MUX_MUX4_Msk /*Select the HDP4 output among the 16 available signals*/
+#define HDP_MUX_MUX4_0 (0x1U << HDP_MUX_MUX4_Pos) /*!< 0x00010000 */
+#define HDP_MUX_MUX4_1 (0x2U << HDP_MUX_MUX4_Pos) /*!< 0x00020000 */
+#define HDP_MUX_MUX4_2 (0x4U << HDP_MUX_MUX4_Pos) /*!< 0x00040000 */
+#define HDP_MUX_MUX4_3 (0x8U << HDP_MUX_MUX4_Pos) /*!< 0x00080000 */
+#define HDP_MUX_MUX5_Pos (20U)
+#define HDP_MUX_MUX5_Msk (0xFU << HDP_MUX_MUX5_Pos) /*!< 0x00F00000 */
+#define HDP_MUX_MUX5 HDP_MUX_MUX5_Msk /*Select the HDP5 output among the 16 available signals*/
+#define HDP_MUX_MUX5_0 (0x1U << HDP_MUX_MUX5_Pos) /*!< 0x00100000 */
+#define HDP_MUX_MUX5_1 (0x2U << HDP_MUX_MUX5_Pos) /*!< 0x00200000 */
+#define HDP_MUX_MUX5_2 (0x4U << HDP_MUX_MUX5_Pos) /*!< 0x00400000 */
+#define HDP_MUX_MUX5_3 (0x8U << HDP_MUX_MUX5_Pos) /*!< 0x00800000 */
+#define HDP_MUX_MUX6_Pos (24U)
+#define HDP_MUX_MUX6_Msk (0xFU << HDP_MUX_MUX6_Pos) /*!< 0x0F000000 */
+#define HDP_MUX_MUX6 HDP_MUX_MUX6_Msk /*Select the HDP6 output among the 16 available signals*/
+#define HDP_MUX_MUX6_0 (0x1U << HDP_MUX_MUX6_Pos) /*!< 0x01000000 */
+#define HDP_MUX_MUX6_1 (0x2U << HDP_MUX_MUX6_Pos) /*!< 0x02000000 */
+#define HDP_MUX_MUX6_2 (0x4U << HDP_MUX_MUX6_Pos) /*!< 0x04000000 */
+#define HDP_MUX_MUX6_3 (0x8U << HDP_MUX_MUX6_Pos) /*!< 0x08000000 */
+#define HDP_MUX_MUX7_Pos (28U)
+#define HDP_MUX_MUX7_Msk (0xFU << HDP_MUX_MUX7_Pos) /*!< 0xF0000000 */
+#define HDP_MUX_MUX7 HDP_MUX_MUX7_Msk /*Select the HDP7 output among the 16 available signals*/
+#define HDP_MUX_MUX7_0 (0x1U << HDP_MUX_MUX7_Pos) /*!< 0x10000000 */
+#define HDP_MUX_MUX7_1 (0x2U << HDP_MUX_MUX7_Pos) /*!< 0x20000000 */
+#define HDP_MUX_MUX7_2 (0x4U << HDP_MUX_MUX7_Pos) /*!< 0x40000000 */
+#define HDP_MUX_MUX7_3 (0x8U << HDP_MUX_MUX7_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition for HDP_VAL register*********************/
+#define HDP_VAL_HDPVAL_Pos (0U)
+#define HDP_VAL_HDPVAL_Msk (0xFFU << HDP_VAL_HDPVAL_Pos) /*!< 0x000000FF */
+#define HDP_VAL_HDPVAL HDP_VAL_HDPVAL_Msk /*Provide the value of the HDP signals*/
+
+/******************** Bit definition for HDP_GPOSET register*********************/
+#define HDP_GPOSET_HDPGPOSET_Pos (0U)
+#define HDP_GPOSET_HDPGPOSET_Msk (0xFFU << HDP_GPOSET_HDPGPOSET_Pos) /*!< 0x000000FF */
+#define HDP_GPOSET_HDPGPOSET HDP_GPOSET_HDPGPOSET_Msk /*When a bit is written to 1, the corresponding HDP GPO is seT*/
+
+/******************** Bit definition for HDP_GPOCLR register*********************/
+#define HDP_GPOCLR_HDPGPOCLR_Pos (0U)
+#define HDP_GPOCLR_HDPGPOCLR_Msk (0xFFU << HDP_GPOCLR_HDPGPOCLR_Pos) /*!< 0x000000FF */
+#define HDP_GPOCLR_HDPGPOCLR HDP_GPOCLR_HDPGPOCLR_Msk /*When a bit is written to 1, the corresponding HDP GPO is cleared*/
+
+/******************** Bit definition for HDP_GPOVAL register*********************/
+#define HDP_GPOVAL_HDPGPOVAL_Pos (0U)
+#define HDP_GPOVAL_HDPGPOVAL_Msk (0xFFU << HDP_GPOVAL_HDPGPOVAL_Pos) /*!< 0x000000FF */
+#define HDP_GPOVAL_HDPGPOVAL HDP_GPOVAL_HDPGPOVAL_Msk /*When written, define the value of the HDP GPO*/
+
+/******************** Bit definition for HDP_VERR register***********************/
+#define HDP_VERR_MINREV_Pos (0U)
+#define HDP_VERR_MINREV_Msk (0xFU << HDP_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define HDP_VERR_MINREV HDP_VERR_MINREV_Msk /*Minor Revision of the IP*/
+#define HDP_VERR_MAJREV_Pos (4U)
+#define HDP_VERR_MAJREV_Msk (0xFU << HDP_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define HDP_VERR_MAJREV HDP_VERR_MAJREV_Msk /*Major Revision of the IP*/
+
+/******************** Bit definition for HDP_IPIDR register**********************/
+#define HDP_IPIDR_ID_Pos (0U)
+#define HDP_IPIDR_ID_Msk (0xFFFFFFFFU << HDP_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define HDP_IPIDR_ID HDP_IPIDR_ID_Msk /*IP Identifier*/
+
+/******************** Bit definition for HDP_SIDR register**********************/
+#define HDP_SIDR_SID_Pos (0U)
+#define HDP_SIDR_SID_Msk (0xFFFFFFFFU << HDP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define HDP_SIDR_SID HDP_SIDR_SID_Msk /*Size Identifier*/
+
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_TZCR register********************/
+#define RCC_TZCR_TZEN_Pos (0U)
+#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */
+#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/
+#define RCC_TZCR_MCKPROT_Pos (1U)
+#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */
+#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/
+
+/******************** Bit definition for RCC_OCENSETR register********************/
+#define RCC_OCENSETR_HSION_Pos (0U)
+#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/
+#define RCC_OCENSETR_HSIKERON_Pos (1U)
+#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/
+#define RCC_OCENSETR_CSION_Pos (4U)
+#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */
+#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/
+#define RCC_OCENSETR_CSIKERON_Pos (5U)
+#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */
+#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/
+#define RCC_OCENSETR_DIGBYP_Pos (7U)
+#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */
+#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/
+#define RCC_OCENSETR_HSEON_Pos (8U)
+#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */
+#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/
+#define RCC_OCENSETR_HSEKERON_Pos (9U)
+#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */
+#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/
+#define RCC_OCENSETR_HSEBYP_Pos (10U)
+#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/
+#define RCC_OCENSETR_HSECSSON_Pos (11U)
+#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */
+#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/
+
+/******************** Bit definition for RCC_OCENCLRR register********************/
+#define RCC_OCENCLRR_HSION_Pos (0U)
+#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/
+#define RCC_OCENCLRR_HSIKERON_Pos (1U)
+#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/
+#define RCC_OCENCLRR_CSION_Pos (4U)
+#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */
+#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/
+#define RCC_OCENCLRR_CSIKERON_Pos (5U)
+#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */
+#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/
+#define RCC_OCENCLRR_DIGBYP_Pos (7U)
+#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */
+#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/
+#define RCC_OCENCLRR_HSEON_Pos (8U)
+#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */
+#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/
+#define RCC_OCENCLRR_HSEKERON_Pos (9U)
+#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */
+#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/
+#define RCC_OCENCLRR_HSEBYP_Pos (10U)
+#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/
+
+/******************** Bit definition for RCC_OCRDYR register********************/
+#define RCC_OCRDYR_HSIRDY_Pos (0U)
+#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */
+#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/
+#define RCC_OCRDYR_HSIDIVRDY_Pos (2U)
+#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */
+#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/
+#define RCC_OCRDYR_CSIRDY_Pos (4U)
+#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */
+#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/
+#define RCC_OCRDYR_HSERDY_Pos (8U)
+#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */
+#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/
+#define RCC_OCRDYR_AXICKRDY_Pos (24U)
+#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */
+#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/
+#define RCC_OCRDYR_CKREST_Pos (25U)
+#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */
+#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/
+
+/******************** Bit definition for RCC_DBGCFGR register********************/
+#define RCC_DBGCFGR_TRACEDIV_Pos (0U)
+#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */
+#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/
+#define RCC_DBGCFGR_DBGCKEN_Pos (8U)
+#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */
+#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/
+#define RCC_DBGCFGR_TRACECKEN_Pos (9U)
+#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */
+#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/
+#define RCC_DBGCFGR_DBGRST_Pos (12U)
+#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */
+#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/
+
+/******************** Bit definition for RCC_HSICFGR register********************/
+#define RCC_HSICFGR_HSIDIV_Pos (0U)
+#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos)
+#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/
+#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/
+#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */
+#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */
+#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */
+
+#define RCC_HSICFGR_HSITRIM_Pos (8U)
+#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos)
+#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/
+
+#define RCC_HSICFGR_HSICAL_Pos (16U)
+#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos)
+#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/
+
+/******************** Bit definition for RCC_CSICFGR register********************/
+#define RCC_CSICFGR_CSITRIM_Pos (8U)
+#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos)
+#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/
+
+#define RCC_CSICFGR_CSICAL_Pos (16U)
+#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos)
+#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/
+
+/******************** Bit definition for RCC_MCO1CFGR register********************/
+#define RCC_MCO1CFGR_MCO1SEL_Pos (0U)
+#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */
+#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/
+#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */
+#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */
+#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */
+#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */
+#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_MCO1CFGR_MCO1DIV_Pos (4U)
+#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
+#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/
+#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */
+#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */
+#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */
+#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */
+#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */
+#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */
+#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */
+#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */
+#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */
+#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */
+#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */
+#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */
+#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */
+#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */
+#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */
+#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
+
+#define RCC_MCO1CFGR_MCO1ON_Pos (12U)
+#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */
+#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/
+
+/******************** Bit definition for RCC_MCO2CFGR register********************/
+#define RCC_MCO2CFGR_MCO2SEL_Pos (0U)
+#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */
+#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/
+#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */
+#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */
+#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */
+#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */
+#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */
+#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */
+
+#define RCC_MCO2CFGR_MCO2DIV_Pos (4U)
+#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
+#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/
+#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */
+#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */
+#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */
+#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */
+#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */
+#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */
+#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */
+#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */
+#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */
+#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */
+#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */
+#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */
+#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */
+#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */
+#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */
+#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
+
+#define RCC_MCO2CFGR_MCO2ON_Pos (12U)
+#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */
+#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/
+
+/******************** Bit definition for RCC_MPCKSELR register********************/
+#define RCC_MPCKSELR_MPUSRC_Pos (0U)
+#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
+#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/
+#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */
+#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */
+#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */
+#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
+
+
+#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U)
+#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/
+
+/******************** Bit definition for RCC_ASSCKSELR register********************/
+#define RCC_ASSCKSELR_AXISSRC_Pos (0U)
+#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
+#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/
+#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */
+#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */
+#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */
+#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */
+#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */
+#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */
+#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */
+#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
+
+#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U)
+#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/
+
+/******************** Bit definition for RCC_MSSCKSELR register********************/
+#define RCC_MSSCKSELR_MCUSSRC_Pos (0U)
+#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
+#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/
+#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */
+#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */
+#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */
+#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
+
+#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U)
+#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/
+
+/******************** Bit definition for RCC_RCK12SELR register********************/
+#define RCC_RCK12SELR_PLL12SRC_Pos (0U)
+#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/
+#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */
+#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */
+#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */
+#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */
+#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */
+#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */
+#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */
+
+#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U)
+#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/
+
+/******************** Bit definition for RCC_RCK3SELR register********************/
+#define RCC_RCK3SELR_PLL3SRC_Pos (0U)
+#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/
+#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */
+#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */
+#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */
+#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
+
+#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U)
+#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/
+
+/******************** Bit definition for RCC_RCK4SELR register********************/
+#define RCC_RCK4SELR_PLL4SRC_Pos (0U)
+#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
+#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/
+#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */
+#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */
+#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */
+#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
+
+#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U)
+#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */
+#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/
+
+/******************** Bit definition for RCC_TIMG1PRER register********************/
+#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U)
+#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */
+#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/
+#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */
+ /*corresponding to a division by 1 or 2, else it is equal to
+ 2 x Fck_pclk1 (default after reset)*/
+#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is
+ corresponding to division by 1, 2 or 4, else it is equal to
+ 4 x Fck_pclk1 */
+
+#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U)
+#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */
+#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/
+
+/******************** Bit definition for RCC_TIMG2PRER register********************/
+#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U)
+#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */
+#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/
+#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */
+ /*corresponding to a division by 1 or 2, else it is equal
+ to 2 x Fck_pclk2 (default after reset)*/
+#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is
+ corresponding to division by 1, 2 or 4, else it is equal to
+ 4 x Fck_pclk2 */
+
+#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U)
+#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */
+#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/
+
+/******************** Bit definition for RCC_RTCDIVR register********************/
+#define RCC_RTCDIVR_RTCDIV_Pos (0U)
+#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */
+#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/
+#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos)
+#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos)
+
+#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/
+
+/******************** Bit definition for RCC_MPCKDIVR register********************/
+#define RCC_MPCKDIVR_MPUDIV_Pos (0U)
+#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
+#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/
+#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */
+#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */
+#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */
+#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */
+#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */
+#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */
+#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */
+#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
+
+#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U)
+#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/
+
+/******************** Bit definition for RCC_AXIDIVR register********************/
+#define RCC_AXIDIVR_AXIDIV_Pos (0U)
+#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
+#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/
+#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */
+#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */
+#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */
+#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */
+#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */
+#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */
+#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */
+#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
+
+#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U)
+#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/
+
+/******************** Bit definition for RCC_APB4DIVR register********************/
+#define RCC_APB4DIVR_APB4DIV_Pos (0U)
+#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */
+#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */
+#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */
+#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */
+#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */
+#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
+
+#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U)
+#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/
+
+/******************** Bit definition for RCC_APB5DIVR register********************/
+#define RCC_APB5DIVR_APB5DIV_Pos (0U)
+#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/
+#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */
+#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */
+#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */
+#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */
+#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */
+#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
+
+#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U)
+#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/
+
+/******************** Bit definition for RCC_MCUDIVR register********************/
+#define RCC_MCUDIVR_MCUDIV_Pos (0U)
+#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */
+#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/
+#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */
+#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */
+#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */
+#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */
+#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */
+#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */
+#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */
+#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */
+#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */
+#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */
+/* @note others: ck_mcuss divided by 512 */
+
+#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U)
+#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/
+/******************** Bit definition for RCC_APB1DIVR register********************/
+#define RCC_APB1DIVR_APB1DIV_Pos (0U)
+#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/
+#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */
+#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */
+#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */
+/* @note others: ck_hclk/16 */
+
+#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U)
+#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/
+
+/******************** Bit definition for RCC_APB2DIV register********************/
+#define RCC_APB2DIVR_APB2DIV_Pos (0U)
+#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/
+#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */
+#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */
+#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */
+/* @note others: ck_hclk/16 */
+
+#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U)
+#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/
+
+/******************** Bit definition for RCC_APB3DIV register********************/
+#define RCC_APB3DIVR_APB3DIV_Pos (0U)
+#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */
+#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/
+#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */
+#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */
+#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */
+#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */
+#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */
+/* @note others: ck_hclk/16 */
+
+#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U)
+#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */
+#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/
+
+/******************** Bit definition for RCC_PLL1CR register********************/
+#define RCC_PLL1CR_PLLON_Pos (0U)
+#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/
+#define RCC_PLL1CR_PLL1RDY_Pos (1U)
+#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/
+#define RCC_PLL1CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/
+#define RCC_PLL1CR_DIVPEN_Pos (4U)
+#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/
+#define RCC_PLL1CR_DIVQEN_Pos (5U)
+#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/
+#define RCC_PLL1CR_DIVREN_Pos (6U)
+#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/
+
+/******************** Bit definition for RCC_PLL1CFGR1 register********************/
+#define RCC_PLL1CFGR1_DIVN_Pos (0U)
+#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/
+/* @note Valid division rations for DIVN: between 25 and 100 */
+#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
+#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
+#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */
+
+#define RCC_PLL1CFGR1_DIVM1_Pos (16U)
+#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */
+#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/
+
+/* @note "y" division factor must be an integer value between 1 and 64 */
+#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+
+/******************** Bit definition for RCC_PLL1CFGR2 register********************/
+/* @TODO To compleate as needed */
+#define RCC_PLL1CFGR2_DIVP_Pos (0U)
+#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/
+#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */
+#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
+
+#define RCC_PLL1CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/
+#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */
+#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+
+#define RCC_PLL1CFGR2_DIVR_Pos (16U)
+#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/
+#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */
+#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+
+/******************** Bit definition for RCC_PLL1FRACR register********************/
+#define RCC_PLL1FRACR_FRACV_Pos (3U)
+#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/
+/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
+
+#define RCC_PLL1FRACR_FRACLE_Pos (16U)
+#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/
+
+/******************** Bit definition for RCC_PLL1CSGR register********************/
+#define RCC_PLL1CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/
+#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
+#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
+#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
+#define RCC_PLL1CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/
+
+/******************** Bit definition for RCC_PLL2CR register********************/
+#define RCC_PLL2CR_PLLON_Pos (0U)
+#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/
+#define RCC_PLL2CR_PLL2RDY_Pos (1U)
+#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/
+#define RCC_PLL2CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/
+#define RCC_PLL2CR_DIVPEN_Pos (4U)
+#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/
+#define RCC_PLL2CR_DIVQEN_Pos (5U)
+#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/
+#define RCC_PLL2CR_DIVREN_Pos (6U)
+#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/
+/******************** Bit definition for RCC_PLL2CFGR1 register********************/
+#define RCC_PLL2CFGR1_DIVN_Pos (0U)
+#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/
+/* @note Valid division rations for DIVN: between 25 and 100 */
+#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
+#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
+#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */
+
+#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
+#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
+#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */
+#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/
+/* @note "y" division factor must be an integer value between 1 and 64 */
+#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+
+/******************** Bit definition for RCC_PLL2CFGR2 register********************/
+/* @TODO To compleate as needed */
+#define RCC_PLL2CFGR2_DIVP_Pos (0U)
+#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/
+#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */
+#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
+
+#define RCC_PLL2CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/
+#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */
+#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+
+#define RCC_PLL2CFGR2_DIVR_Pos (16U)
+#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/
+#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */
+#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+
+/******************** Bit definition for RCC_PLL2FRACR register********************/
+#define RCC_PLL2FRACR_FRACV_Pos (3U)
+#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/
+/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
+
+#define RCC_PLL2FRACR_FRACLE_Pos (16U)
+#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/
+
+/******************** Bit definition for RCC_PLL2CSGR register********************/
+#define RCC_PLL2CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/
+#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
+#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
+#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
+#define RCC_PLL2CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/
+
+/******************** Bit definition for RCC_PLL3CR register********************/
+#define RCC_PLL3CR_PLLON_Pos (0U)
+#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/
+#define RCC_PLL3CR_PLL3RDY_Pos (1U)
+#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/
+#define RCC_PLL3CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/
+#define RCC_PLL3CR_DIVPEN_Pos (4U)
+#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/
+#define RCC_PLL3CR_DIVQEN_Pos (5U)
+#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/
+#define RCC_PLL3CR_DIVREN_Pos (6U)
+#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/
+
+/******************** Bit definition for RCC_PLL3CFGR1 register********************/
+#define RCC_PLL3CFGR1_DIVN_Pos (0U)
+#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/
+/* @note Valid division rations for DIVN: between 25 and 200 */
+#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
+#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
+#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */
+
+
+#define RCC_PLL3CFGR1_DIVM3_Pos (16U)
+#define RCC_PLL3CFGR1_DIVM3_Pos (16U)
+#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */
+#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/
+/* @note "y" division factor must be an integer value between 1 and 64 */
+#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+
+#define RCC_PLL3CFGR1_IFRGE_Pos (24U)
+#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */
+#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/
+#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */
+ /* between 4 and 8 MHz (default after reset) */
+#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is
+ between 8 and 16 MHz */
+/* @note other IFRGE values are reserved */
+
+/******************** Bit definition for RCC_PLL3CFGR2 register********************/
+/* @TODO To compleate as needed */
+#define RCC_PLL3CFGR2_DIVP_Pos (0U)
+#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/
+#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */
+#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
+
+#define RCC_PLL3CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/
+#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */
+#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+
+#define RCC_PLL3CFGR2_DIVR_Pos (16U)
+#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/
+#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */
+#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+
+/******************** Bit definition for RCC_PLL3FRACR register********************/
+#define RCC_PLL3FRACR_FRACV_Pos (3U)
+#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/
+/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
+
+#define RCC_PLL3FRACR_FRACLE_Pos (16U)
+#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/
+
+/******************** Bit definition for RCC_PLL3CSGR register********************/
+#define RCC_PLL3CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL3CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL3CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL3CSGR_MOD_PER RCC_PLL3CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL3*/
+#define RCC_PLL3CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL3CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL3CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL3CSGR_TPDFN_DIS RCC_PLL3CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
+#define RCC_PLL3CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL3CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL3CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL3CSGR_RPDFN_DIS RCC_PLL3CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
+#define RCC_PLL3CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL3CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL3CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
+#define RCC_PLL3CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/
+
+/******************** Bit definition for RCC_PLL4CR register********************/
+#define RCC_PLL4CR_PLLON_Pos (0U)
+#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */
+#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/
+#define RCC_PLL4CR_PLL4RDY_Pos (1U)
+#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */
+#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/
+#define RCC_PLL4CR_SSCG_CTRL_Pos (2U)
+#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
+#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/
+#define RCC_PLL4CR_DIVPEN_Pos (4U)
+#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */
+#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/
+#define RCC_PLL4CR_DIVQEN_Pos (5U)
+#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */
+#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/
+#define RCC_PLL4CR_DIVREN_Pos (6U)
+#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */
+#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/
+
+/******************** Bit definition for RCC_PLL4CFGR1 register********************/
+#define RCC_PLL4CFGR1_DIVN_Pos (0U)
+#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */
+#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/
+/* @note Valid division rations for DIVN: between 25 and 200 */
+#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
+#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
+#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */
+
+#define RCC_PLL4CFGR1_DIVM4_Pos (16U)
+#define RCC_PLL4CFGR1_DIVM4_Pos (16U)
+#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */
+#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/
+/* @note "y" division factor must be an integer value between 1 and 64 */
+#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
+
+#define RCC_PLL4CFGR1_IFRGE_Pos (24U)
+#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */
+#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/
+#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */
+ /*between 4 and 8 MHz (default after reset) */
+#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is
+ between 8 and 16 MHz */
+/* @note other IFRGE values are reserved */
+
+/******************** Bit definition for RCC_PLL4CFGR2 register********************/
+/* @TODO To compleate as needed */
+#define RCC_PLL4CFGR2_DIVP_Pos (0U)
+#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
+#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/
+#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */
+#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */
+#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
+
+#define RCC_PLL4CFGR2_DIVQ_Pos (8U)
+#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/
+#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */
+#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */
+#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
+
+#define RCC_PLL4CFGR2_DIVR_Pos (16U)
+#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/
+#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */
+#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */
+#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
+
+/******************** Bit definition for RCC_PLL4FRACR register********************/
+#define RCC_PLL4FRACR_FRACV_Pos (3U)
+#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/
+/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
+
+#define RCC_PLL4FRACR_FRACLE_Pos (16U)
+#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */
+#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/
+
+/******************** Bit definition for RCC_PLL4CSGR register********************/
+#define RCC_PLL4CSGR_MOD_PER_Pos (0U)
+#define RCC_PLL4CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL4CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
+#define RCC_PLL4CSGR_MOD_PER RCC_PLL4CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL4*/
+#define RCC_PLL4CSGR_TPDFN_DIS_Pos (13U)
+#define RCC_PLL4CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL4CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
+#define RCC_PLL4CSGR_TPDFN_DIS RCC_PLL4CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
+#define RCC_PLL4CSGR_RPDFN_DIS_Pos (14U)
+#define RCC_PLL4CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL4CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
+#define RCC_PLL4CSGR_RPDFN_DIS RCC_PLL4CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
+#define RCC_PLL4CSGR_SSCG_MODE_Pos (15U)
+#define RCC_PLL4CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL4CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
+#define RCC_PLL4CSGR_SSCG_MODE RCC_PLL4CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
+#define RCC_PLL4CSGR_INC_STEP_Pos (16U)
+#define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
+#define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/
+
+/******************** Bit definition for RCC_I2C12CKSELR register********************/
+#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U)
+#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */
+#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/
+#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */
+#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */
+#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */
+#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_I2C35CKSELR register********************/
+#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U)
+#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */
+#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/
+#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */
+#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */
+#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */
+#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_I2C46CKSELR register********************/
+#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U)
+#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */
+#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/
+#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */
+#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */
+#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */
+#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_SAI1CKSELR register********************/
+#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U)
+#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/
+#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */
+#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */
+#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_SAI2CKSELR register********************/
+#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U)
+#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/
+#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */
+#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */
+#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */
+#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */
+
+/******************** Bit definition for RCC_SAI3CKSELR register********************/
+#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U)
+#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/
+#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */
+#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */
+#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_SAI4CKSELR register********************/
+#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U)
+#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */
+#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/
+#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */
+#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */
+#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */
+#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */
+#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_SPI2S1CKSELR register********************/
+#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U)
+#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/
+#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */
+#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */
+#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_SPI2S23CKSELR register********************/
+#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U)
+#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/
+#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */
+#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */
+#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_SPI45CKSELR register********************/
+#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U)
+#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/
+#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */
+#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */
+#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_SPI6CKSELR register********************/
+#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U)
+#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */
+#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/
+#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */
+#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */
+#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */
+#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */
+#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */
+#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */
+
+/******************** Bit definition for RCC_UART6CKSELR register********************/
+#define RCC_UART6CKSELR_UART6SRC_Pos (0U)
+#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/
+#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */
+#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */
+#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_UART24CKSELR register********************/
+#define RCC_UART24CKSELR_UART24SRC_Pos (0U)
+#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/
+#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */
+#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */
+#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_UART35CKSELR register********************/
+#define RCC_UART35CKSELR_UART35SRC_Pos (0U)
+#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/
+#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */
+#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */
+#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_UART78CKSELR register********************/
+#define RCC_UART78CKSELR_UART78SRC_Pos (0U)
+#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/
+#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */
+#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */
+#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */
+
+/******************** Bit definition for RCC_UART1CKSELR register********************/
+#define RCC_UART1CKSELR_UART1SRC_Pos (0U)
+#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */
+#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/
+#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */
+#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */
+#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */
+#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */
+#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */
+#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */
+
+/******************** Bit definition for RCC_SDMMC12CKSELR register********************/
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U)
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */
+#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_SDMMC3CKSELR register********************/
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U)
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */
+#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_ETHCKSELR register********************/
+#define RCC_ETHCKSELR_ETHSRC_Pos (0U)
+#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */
+#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/
+#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */
+#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */
+#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */
+
+#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U)
+#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
+#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/
+#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */
+#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */
+#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */
+#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */
+#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */
+#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */
+#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */
+#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */
+#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */
+#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */
+#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */
+#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */
+#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */
+#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */
+#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */
+#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
+
+/******************** Bit definition for RCC_QSPICKSELR register********************/
+#define RCC_QSPICKSELR_QSPISRC_Pos (0U)
+#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
+#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/
+#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */
+#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */
+#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */
+#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_FMCCKSELR register********************/
+#define RCC_FMCCKSELR_FMCSRC_Pos (0U)
+#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
+#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/
+#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */
+#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */
+#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */
+#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_FDCANCKSELR register********************/
+#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U)
+#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */
+#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/
+#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */
+#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */
+#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */
+#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_SPDIFCKSELR register********************/
+#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U)
+#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */
+#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/
+#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */
+#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */
+#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */
+
+/******************** Bit definition for RCC_CECCKSELR register********************/
+#define RCC_CECCKSELR_CECSRC_Pos (0U)
+#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */
+#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/
+#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */
+#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */
+#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */
+
+/******************** Bit definition for RCC_USBCKSELR register********************/
+#define RCC_USBCKSELR_USBPHYSRC_Pos (0U)
+#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */
+#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/
+#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */
+#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */
+#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */
+
+#define RCC_USBCKSELR_USBOSRC_Pos (4U)
+#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
+#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/
+#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */
+#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
+
+/******************** Bit definition for RCC_RNG1CKSELR register********************/
+#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U)
+#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
+#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/
+#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */
+#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */
+#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */
+#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_RNG2CKSELR register********************/
+#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U)
+#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
+#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/
+#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */
+#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */
+#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */
+#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_CPERCKSELR register********************/
+#define RCC_CPERCKSELR_CKPERSRC_Pos (0U)
+#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
+#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/
+#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */
+#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */
+#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */
+#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
+
+/******************** Bit definition for RCC_CSTGENCKSELR register******************/
+#define RCC_STGENCKSELR_STGENSRC_Pos (0U)
+#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */
+#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/
+#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */
+#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */
+#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */
+
+/******************** Bit definition for RCC_DDRITFCR register*********************/
+#define RCC_DDRITFCR_DDRC1EN B(0)
+#define RCC_DDRITFCR_DDRC1LPEN B(1)
+#define RCC_DDRITFCR_DDRC2EN B(2)
+#define RCC_DDRITFCR_DDRC2LPEN B(3)
+#define RCC_DDRITFCR_DDRPHYCEN B(4)
+#define RCC_DDRITFCR_DDRPHYCLPEN B(5)
+#define RCC_DDRITFCR_DDRCAPBEN B(6)
+#define RCC_DDRITFCR_DDRCAPBLPEN B(7)
+#define RCC_DDRITFCR_AXIDCGEN B(8)
+#define RCC_DDRITFCR_DDRPHYCAPBEN B(9)
+#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10)
+
+#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U)
+#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
+#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/
+#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */
+#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */
+#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */
+#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */
+#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */
+#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */
+#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */
+#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */
+#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */
+#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */
+#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */
+#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */
+#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */
+#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */
+#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */
+#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
+
+#define RCC_DDRITFCR_DDRCAPBRST B(14)
+#define RCC_DDRITFCR_DDRCAXIRST B(15)
+#define RCC_DDRITFCR_DDRCORERST B(16)
+#define RCC_DDRITFCR_DPHYAPBRST B(17)
+#define RCC_DDRITFCR_DPHYRST B(18)
+#define RCC_DDRITFCR_DPHYCTLRST B(19)
+
+#define RCC_DDRITFCR_DDRCKMOD_Pos (20U)
+#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */
+#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/
+#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */
+#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */
+#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */
+#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */
+#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */
+
+/******************** Bit definition for RCC_DSICKSELR register********************/
+#define RCC_DSICKSELR_DSISRC_Pos (0U)
+#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */
+#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/
+#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */
+#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */
+
+/******************** Bit definition for RCC_ADCCKSELR register********************/
+#define RCC_ADCCKSELR_ADCSRC_Pos (0U)
+#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */
+#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/
+#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */
+#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */
+#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */
+
+/******************** Bit definition for RCC_LPTIM45CKSELR register********************/
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U)
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */
+#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */
+
+/******************** Bit definition for RCC_LPTIM23CKSELR register********************/
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U)
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */
+#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */
+
+/******************** Bit definition for RCC_LPTIM1CKSELR register********************/
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U)
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */
+#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */
+
+/******************** Bit definition for RCC_MP_BOOTCR register*********************/
+#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U)
+#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/
+#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U)
+#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */
+#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/
+
+/******************** Bit definition for RCC_MP_SREQSETR register********************/
+/* @note The MCU cannot access to this register */
+#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U)
+#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */
+#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/
+#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U)
+#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */
+#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/
+
+/******************** Bit definition for RCC_MP_SREQCLRR register********************/
+/* @note The MCU cannot access to this register */
+#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U)
+#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */
+#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/
+#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U)
+#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */
+#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/
+
+/******************** Bit definition for RCC_MP_GCR register********************/
+#define RCC_MP_GCR_BOOT_MCU_Pos (0U)
+#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
+#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/
+#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */
+#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
+
+/******************** Bit definition for RCC_MP_APRSTCR register ********************/
+#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U)
+#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */
+#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/
+#define RCC_MP_APRSTCR_RSTTO_Pos (8U)
+#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */
+#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/
+
+/******************** Bit definition for RCC_MP_APRSTSR register ********************/
+#define RCC_MP_APRSTSR_RSTTOV_Pos (8U)
+#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */
+#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/
+
+/******************* Bit definition for RCC_BDCR register ********************/
+#define RCC_BDCR_LSEON_Pos (0U)
+#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/
+#define RCC_BDCR_LSEBYP_Pos (1U)
+#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/
+#define RCC_BDCR_LSERDY_Pos (2U)
+#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/
+
+#define RCC_BDCR_DIGBYP_Pos (3U)
+#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */
+#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */
+
+#define RCC_BDCR_LSEDRV_Pos (4U)
+#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/
+#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */
+#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
+#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
+
+#define RCC_BDCR_LSECSSON_Pos (8U)
+#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */
+#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/
+#define RCC_BDCR_LSECSSD_Pos (9U)
+#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */
+#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/
+
+#define RCC_BDCR_RTCSRC_Pos (16U)
+#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
+#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/
+#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */
+#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */
+#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */
+#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
+
+#define RCC_BDCR_RTCCKEN_Pos (20U)
+#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */
+#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/
+#define RCC_BDCR_VSWRST_Pos (31U)
+#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */
+#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/
+
+/******************* Bit definition for RCC_RDLSICR register ********************/
+#define RCC_RDLSICR_LSION_Pos (0U)
+#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/
+#define RCC_RDLSICR_LSIRDY_Pos (1U)
+#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/
+#define RCC_RDLSICR_MRD_Pos (16U)
+#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */
+#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/
+#define RCC_RDLSICR_EADLY_Pos (24U)
+#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */
+#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/
+#define RCC_RDLSICR_SPARE_Pos (27U)
+#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */
+#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/
+
+/******************* Bit definition for RCC_MP_CIER register *******************/
+#define RCC_MP_CIER_LSIRDYIE_Pos (0U)
+#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/
+#define RCC_MP_CIER_LSERDYIE_Pos (1U)
+#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/
+#define RCC_MP_CIER_HSIRDYIE_Pos (2U)
+#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/
+#define RCC_MP_CIER_HSERDYIE_Pos (3U)
+#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/
+#define RCC_MP_CIER_CSIRDYIE_Pos (4U)
+#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/
+#define RCC_MP_CIER_PLL1DYIE_Pos (8U)
+#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
+#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/
+#define RCC_MP_CIER_PLL2DYIE_Pos (9U)
+#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
+#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/
+#define RCC_MP_CIER_PLL3DYIE_Pos (10U)
+#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
+#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/
+#define RCC_MP_CIER_PLL4DYIE_Pos (11U)
+#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
+#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/
+#define RCC_MP_CIER_LSECSSIE_Pos (16U)
+#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
+#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/
+#define RCC_MP_CIER_WKUPIE_Pos (20U)
+#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */
+#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/
+
+/******************* Bit definition for RCC_MP_CIFR register ********************/
+#define RCC_MP_CIFR_LSIRDYF_Pos (0U)
+#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/
+#define RCC_MP_CIFR_LSERDYF_Pos (1U)
+#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/
+#define RCC_MP_CIFR_HSIRDYF_Pos (2U)
+#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/
+#define RCC_MP_CIFR_HSERDYF_Pos (3U)
+#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/
+#define RCC_MP_CIFR_CSIRDYF_Pos (4U)
+#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/
+#define RCC_MP_CIFR_PLL1DYF_Pos (8U)
+#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
+#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/
+#define RCC_MP_CIFR_PLL2DYF_Pos (9U)
+#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
+#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/
+#define RCC_MP_CIFR_PLL3DYF_Pos (10U)
+#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
+#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/
+#define RCC_MP_CIFR_PLL4DYF_Pos (11U)
+#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
+#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/
+#define RCC_MP_CIFR_LSECSSF_Pos (16U)
+#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
+#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/
+#define RCC_MP_CIFR_WKUPF_Pos (20U)
+#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */
+#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/
+
+/******************* Bit definition for RCC_MC_CIER register *******************/
+#define RCC_MC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/
+#define RCC_MC_CIER_LSERDYIE_Pos (1U)
+#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/
+#define RCC_MC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/
+#define RCC_MC_CIER_HSERDYIE_Pos (3U)
+#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/
+#define RCC_MC_CIER_CSIRDYIE_Pos (4U)
+#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/
+#define RCC_MC_CIER_PLL1DYIE_Pos (8U)
+#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
+#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/
+#define RCC_MC_CIER_PLL2DYIE_Pos (9U)
+#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
+#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/
+#define RCC_MC_CIER_PLL3DYIE_Pos (10U)
+#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
+#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/
+#define RCC_MC_CIER_PLL4DYIE_Pos (11U)
+#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
+#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/
+#define RCC_MC_CIER_LSECSSIE_Pos (16U)
+#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
+#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/
+#define RCC_MC_CIER_WKUPIE_Pos (20U)
+#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */
+#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/
+
+/******************* Bit definition for RCC_MC_CIFR register ********************/
+#define RCC_MC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/
+#define RCC_MC_CIFR_LSERDYF_Pos (1U)
+#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/
+#define RCC_MC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/
+#define RCC_MC_CIFR_HSERDYF_Pos (3U)
+#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/
+#define RCC_MC_CIFR_CSIRDYF_Pos (4U)
+#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/
+#define RCC_MC_CIFR_PLL1DYF_Pos (8U)
+#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
+#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/
+#define RCC_MC_CIFR_PLL2DYF_Pos (9U)
+#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
+#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/
+#define RCC_MC_CIFR_PLL3DYF_Pos (10U)
+#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
+#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/
+#define RCC_MC_CIFR_PLL4DYF_Pos (11U)
+#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
+#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/
+#define RCC_MC_CIFR_LSECSSF_Pos (16U)
+#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
+#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/
+#define RCC_MC_CIFR_WKUPF_Pos (20U)
+#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */
+#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/
+
+
+/******************* Bit definition for RCC_PWRLPDLYCR register ********************/
+#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */
+#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/
+#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/
+
+#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/
+
+
+/******************* Bit definition for RCC_MP_RSTSSETR register *********************/
+/*!< This register is dedicated to the BOOTROM code in order to update the reset source.
+ * This register is updated by the BOOTROM code, after a power-on reset (por_rst), a
+ * system reset (nreset), or an exit from Standby or CStandby.
+ *@note The application software shall not use this register. In order to identify the
+ * reset source, the MPU application must use RCC MPU Reset Status Clear Register
+ * (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status
+ * Clear Register (RCC_MC_RSTSCLRR).
+ *@note Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '1'.
+ *@note The register is located in VDDCORE.
+ *@note If TZEN = '1', this register can only be modified in secure mode.
+ */
+#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U)
+#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/
+
+#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U)
+#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/
+
+#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U)
+#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/
+
+#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U)
+#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/
+
+#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U)
+#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/
+
+#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U)
+#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/
+
+#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U)
+#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/
+
+#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U)
+#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+
+#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U)
+#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+
+#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U)
+#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */
+#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/
+
+#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U)
+#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
+#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/
+
+#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U)
+#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */
+#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
+
+#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U)
+#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */
+#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
+
+#define RCC_MP_RSTSSETR_SPARE_Pos (15U)
+#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */
+#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/
+
+/******************* Bit definition for RCC_APB1RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_APB1RSTSETR_TIM2RST B(0)
+#define RCC_APB1RSTSETR_TIM3RST B(1)
+#define RCC_APB1RSTSETR_TIM4RST B(2)
+#define RCC_APB1RSTSETR_TIM5RST B(3)
+#define RCC_APB1RSTSETR_TIM6RST B(4)
+#define RCC_APB1RSTSETR_TIM7RST B(5)
+#define RCC_APB1RSTSETR_TIM12RST B(6)
+#define RCC_APB1RSTSETR_TIM13RST B(7)
+#define RCC_APB1RSTSETR_TIM14RST B(8)
+#define RCC_APB1RSTSETR_LPTIM1RST B(9)
+#define RCC_APB1RSTSETR_SPI2RST B(11)
+#define RCC_APB1RSTSETR_SPI3RST B(12)
+#define RCC_APB1RSTSETR_USART2RST B(14)
+#define RCC_APB1RSTSETR_USART3RST B(15)
+#define RCC_APB1RSTSETR_UART4RST B(16)
+#define RCC_APB1RSTSETR_UART5RST B(17)
+#define RCC_APB1RSTSETR_UART7RST B(18)
+#define RCC_APB1RSTSETR_UART8RST B(19)
+#define RCC_APB1RSTSETR_I2C1RST B(21)
+#define RCC_APB1RSTSETR_I2C2RST B(22)
+#define RCC_APB1RSTSETR_I2C3RST B(23)
+#define RCC_APB1RSTSETR_I2C5RST B(24)
+#define RCC_APB1RSTSETR_SPDIFRST B(26)
+#define RCC_APB1RSTSETR_CECRST B(27)
+#define RCC_APB1RSTSETR_DAC12RST B(29)
+#define RCC_APB1RSTSETR_MDIOSRST B(31)
+
+/******************* Bit definition for RCC_APB1RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_APB1RSTCLRR_TIM2RST B(0)
+#define RCC_APB1RSTCLRR_TIM3RST B(1)
+#define RCC_APB1RSTCLRR_TIM4RST B(2)
+#define RCC_APB1RSTCLRR_TIM5RST B(3)
+#define RCC_APB1RSTCLRR_TIM6RST B(4)
+#define RCC_APB1RSTCLRR_TIM7RST B(5)
+#define RCC_APB1RSTCLRR_TIM12RST B(6)
+#define RCC_APB1RSTCLRR_TIM13RST B(7)
+#define RCC_APB1RSTCLRR_TIM14RST B(8)
+#define RCC_APB1RSTCLRR_LPTIM1RST B(9)
+#define RCC_APB1RSTCLRR_SPI2RST B(11)
+#define RCC_APB1RSTCLRR_SPI3RST B(12)
+#define RCC_APB1RSTCLRR_USART2RST B(14)
+#define RCC_APB1RSTCLRR_USART3RST B(15)
+#define RCC_APB1RSTCLRR_UART4RST B(16)
+#define RCC_APB1RSTCLRR_UART5RST B(17)
+#define RCC_APB1RSTCLRR_UART7RST B(18)
+#define RCC_APB1RSTCLRR_UART8RST B(19)
+#define RCC_APB1RSTCLRR_I2C1RST B(21)
+#define RCC_APB1RSTCLRR_I2C2RST B(22)
+#define RCC_APB1RSTCLRR_I2C3RST B(23)
+#define RCC_APB1RSTCLRR_I2C5RST B(24)
+#define RCC_APB1RSTCLRR_SPDIFRST B(26)
+#define RCC_APB1RSTCLRR_CECRST B(27)
+#define RCC_APB1RSTCLRR_DAC12RST B(29)
+#define RCC_APB1RSTCLRR_MDIOSRST B(31)
+
+/******************* Bit definition for RCC_APB2RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_APB2RSTSETR_TIM1RST B(0)
+#define RCC_APB2RSTSETR_TIM8RST B(1)
+#define RCC_APB2RSTSETR_TIM15RST B(2)
+#define RCC_APB2RSTSETR_TIM16RST B(3)
+#define RCC_APB2RSTSETR_TIM17RST B(4)
+#define RCC_APB2RSTSETR_SPI1RST B(8)
+#define RCC_APB2RSTSETR_SPI4RST B(9)
+#define RCC_APB2RSTSETR_SPI5RST B(10)
+#define RCC_APB2RSTSETR_USART6RST B(13)
+#define RCC_APB2RSTSETR_SAI1RST B(16)
+#define RCC_APB2RSTSETR_SAI2RST B(17)
+#define RCC_APB2RSTSETR_SAI3RST B(18)
+#define RCC_APB2RSTSETR_DFSDMRST B(20)
+#define RCC_APB2RSTSETR_FDCANRST B(24)
+
+/******************* Bit definition for RCC_APB2RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_APB2RSTCLRR_TIM1RST B(0)
+#define RCC_APB2RSTCLRR_TIM8RST B(1)
+#define RCC_APB2RSTCLRR_TIM15RST B(2)
+#define RCC_APB2RSTCLRR_TIM16RST B(3)
+#define RCC_APB2RSTCLRR_TIM17RST B(4)
+#define RCC_APB2RSTCLRR_SPI1RST B(8)
+#define RCC_APB2RSTCLRR_SPI4RST B(9)
+#define RCC_APB2RSTCLRR_SPI5RST B(10)
+#define RCC_APB2RSTCLRR_USART6RST B(13)
+#define RCC_APB2RSTCLRR_SAI1RST B(16)
+#define RCC_APB2RSTCLRR_SAI2RST B(17)
+#define RCC_APB2RSTCLRR_SAI3RST B(18)
+#define RCC_APB2RSTCLRR_DFSDMRST B(20)
+#define RCC_APB2RSTCLRR_FDCANRST B(24)
+
+/******************* Bit definition for RCC_APB3RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_APB3RSTSETR_LPTIM2RST B(0)
+#define RCC_APB3RSTSETR_LPTIM3RST B(1)
+#define RCC_APB3RSTSETR_LPTIM4RST B(2)
+#define RCC_APB3RSTSETR_LPTIM5RST B(3)
+#define RCC_APB3RSTSETR_SAI4RST B(8)
+#define RCC_APB3RSTSETR_SYSCFGRST B(11)
+#define RCC_APB3RSTSETR_VREFRST B(13)
+#define RCC_APB3RSTSETR_DTSRST B(16)
+#define RCC_APB3RSTSETR_PMBCTRLRST B(17)
+
+/******************* Bit definition for RCC_APB3RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_APB3RSTCLRR_LPTIM2RST B(0)
+#define RCC_APB3RSTCLRR_LPTIM3RST B(1)
+#define RCC_APB3RSTCLRR_LPTIM4RST B(2)
+#define RCC_APB3RSTCLRR_LPTIM5RST B(3)
+#define RCC_APB3RSTCLRR_SAI4RST B(8)
+#define RCC_APB3RSTCLRR_SYSCFGRST B(11)
+#define RCC_APB3RSTCLRR_VREFRST B(13)
+#define RCC_APB3RSTCLRR_DTSRST B(16)
+#define RCC_APB3RSTCLRR_PMBCTRLRST B(17)
+
+/******************* Bit definition for RCC_AHB2RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_AHB2RSTSETR_DMA1RST B(0)
+#define RCC_AHB2RSTSETR_DMA2RST B(1)
+#define RCC_AHB2RSTSETR_DMAMUXRST B(2)
+#define RCC_AHB2RSTSETR_ADC12RST B(5)
+#define RCC_AHB2RSTSETR_USBORST B(8)
+#define RCC_AHB2RSTSETR_SDMMC3RST B(16)
+
+/******************* Bit definition for RCC_AHB2RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_AHB2RSTCLRR_DMA1RST B(0)
+#define RCC_AHB2RSTCLRR_DMA2RST B(1)
+#define RCC_AHB2RSTCLRR_DMAMUXRST B(2)
+#define RCC_AHB2RSTCLRR_ADC12RST B(5)
+#define RCC_AHB2RSTCLRR_USBORST B(8)
+#define RCC_AHB2RSTCLRR_SDMMC3RST B(16)
+
+/******************* Bit definition for RCC_AHB3RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_AHB3RSTSETR_DCMIRST B(0)
+#define RCC_AHB3RSTSETR_CRYP2RST B(4)
+#define RCC_AHB3RSTSETR_HASH2RST B(5)
+#define RCC_AHB3RSTSETR_RNG2RST B(6)
+#define RCC_AHB3RSTSETR_CRC2RST B(7)
+#define RCC_AHB3RSTSETR_HSEMRST B(11)
+#define RCC_AHB3RSTSETR_IPCCRST B(12)
+
+/******************* Bit definition for RCC_AHB3RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_AHB3RSTCLRR_DCMIRST B(0)
+#define RCC_AHB3RSTCLRR_CRYP2RST B(4)
+#define RCC_AHB3RSTCLRR_HASH2RST B(5)
+#define RCC_AHB3RSTCLRR_RNG2RST B(6)
+#define RCC_AHB3RSTCLRR_CRC2RST B(7)
+#define RCC_AHB3RSTCLRR_HSEMRST B(11)
+#define RCC_AHB3RSTCLRR_IPCCRST B(12)
+
+/******************* Bit definition for RCC_AHB4RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_AHB4RSTSETR_GPIOARST B(0)
+#define RCC_AHB4RSTSETR_GPIOBRST B(1)
+#define RCC_AHB4RSTSETR_GPIOCRST B(2)
+#define RCC_AHB4RSTSETR_GPIODRST B(3)
+#define RCC_AHB4RSTSETR_GPIOERST B(4)
+#define RCC_AHB4RSTSETR_GPIOFRST B(5)
+#define RCC_AHB4RSTSETR_GPIOGRST B(6)
+#define RCC_AHB4RSTSETR_GPIOHRST B(7)
+#define RCC_AHB4RSTSETR_GPIOIRST B(8)
+#define RCC_AHB4RSTSETR_GPIOJRST B(9)
+#define RCC_AHB4RSTSETR_GPIOKRST B(10)
+
+/******************* Bit definition for RCC_AHB4RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_AHB4RSTCLRR_GPIOARST B(0)
+#define RCC_AHB4RSTCLRR_GPIOBRST B(1)
+#define RCC_AHB4RSTCLRR_GPIOCRST B(2)
+#define RCC_AHB4RSTCLRR_GPIODRST B(3)
+#define RCC_AHB4RSTCLRR_GPIOERST B(4)
+#define RCC_AHB4RSTCLRR_GPIOFRST B(5)
+#define RCC_AHB4RSTCLRR_GPIOGRST B(6)
+#define RCC_AHB4RSTCLRR_GPIOHRST B(7)
+#define RCC_AHB4RSTCLRR_GPIOIRST B(8)
+#define RCC_AHB4RSTCLRR_GPIOJRST B(9)
+#define RCC_AHB4RSTCLRR_GPIOKRST B(10)
+
+/******************* Bit definition for RCC_APB4RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_APB4RSTSETR_LTDCRST B(0)
+#define RCC_APB4RSTSETR_DSIRST B(4)
+#define RCC_APB4RSTSETR_DDRPERFMRST B(8)
+#define RCC_APB4RSTSETR_USBPHYRST B(16)
+
+/******************* Bit definition for RCC_APB4RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_APB4RSTCLRR_LTDCRST B(0)
+#define RCC_APB4RSTCLRR_DSIRST B(4)
+#define RCC_APB4RSTCLRR_DDRPERFMRST B(8)
+#define RCC_APB4RSTCLRR_USBPHYRST B(16)
+
+/******************* Bit definition for RCC_APB5RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_APB5RSTSETR_SPI6RST B(0)
+#define RCC_APB5RSTSETR_I2C4RST B(2)
+#define RCC_APB5RSTSETR_I2C6RST B(3)
+#define RCC_APB5RSTSETR_USART1RST B(4)
+#define RCC_APB5RSTSETR_STGENRST B(20)
+
+/******************* Bit definition for RCC_APB5RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_APB5RSTCLRR_SPI6RST B(0)
+#define RCC_APB5RSTCLRR_I2C4RST B(2)
+#define RCC_APB5RSTCLRR_I2C6RST B(3)
+#define RCC_APB5RSTCLRR_USART1RST B(4)
+#define RCC_APB5RSTCLRR_STGENRST B(20)
+
+/******************* Bit definition for RCC_AHB5RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_AHB5RSTSETR_GPIOZRST B(0)
+#define RCC_AHB5RSTSETR_CRYP1RST B(4)
+#define RCC_AHB5RSTSETR_HASH1RST B(5)
+#define RCC_AHB5RSTSETR_RNG1RST B(6)
+#define RCC_AHB5RSTSETR_AXIMCRST B(16)
+
+/******************* Bit definition for RCC_AHB5RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_AHB5RSTCLRR_GPIOZRST B(0)
+#define RCC_AHB5RSTCLRR_CRYP1RST B(4)
+#define RCC_AHB5RSTCLRR_HASH1RST B(5)
+#define RCC_AHB5RSTCLRR_RNG1RST B(6)
+#define RCC_AHB5RSTCLRR_AXIMCRST B(16)
+
+/******************* Bit definition for RCC_AHB6RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_AHB6RSTSETR_GPURST B(5)
+#define RCC_AHB6RSTSETR_ETHMACRST B(10)
+#define RCC_AHB6RSTSETR_FMCRST B(12)
+#define RCC_AHB6RSTSETR_QSPIRST B(14)
+#define RCC_AHB6RSTSETR_SDMMC1RST B(16)
+#define RCC_AHB6RSTSETR_SDMMC2RST B(17)
+#define RCC_AHB6RSTSETR_CRC1RST B(20)
+#define RCC_AHB6RSTSETR_USBHRST B(24)
+
+/******************* Bit definition for RCC_AHB6RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_AHB6RSTCLRR_ETHMACRST B(10)
+#define RCC_AHB6RSTCLRR_FMCRST B(12)
+#define RCC_AHB6RSTCLRR_QSPIRST B(14)
+#define RCC_AHB6RSTCLRR_SDMMC1RST B(16)
+#define RCC_AHB6RSTCLRR_SDMMC2RST B(17)
+#define RCC_AHB6RSTCLRR_CRC1RST B(20)
+#define RCC_AHB6RSTCLRR_USBHRST B(24)
+
+/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/
+/*!< This register is used to activate the reset of the corresponding peripheral */
+#define RCC_TZAHB6RSTSETR_MDMARST B(0)
+
+/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/
+/*!< This register is used to release the reset of the corresponding peripheral */
+#define RCC_TZAHB6RSTCLRR_MDMARST B(0)
+
+/******************* Bit definition for RCC_MP_GRSTCSETR register ************/
+/*!< This register is used by the MPU in order to generate either a MCU reset
+ * or a system reset or a reset of one of the two MPU processors. Writing '0' has
+ * no effect, reading will return the effective values of the corresponding bits.
+ * Writing a '1' activates the reset */
+#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U)
+#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */
+#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */
+#define RCC_MP_GRSTCSETR_MCURST_Pos (1U)
+#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */
+#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */
+#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U)
+#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */
+#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/
+#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U)
+#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */
+#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/
+
+/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_APB1ENSETR_TIM2EN B(0)
+#define RCC_MC_APB1ENSETR_TIM3EN B(1)
+#define RCC_MC_APB1ENSETR_TIM4EN B(2)
+#define RCC_MC_APB1ENSETR_TIM5EN B(3)
+#define RCC_MC_APB1ENSETR_TIM6EN B(4)
+#define RCC_MC_APB1ENSETR_TIM7EN B(5)
+#define RCC_MC_APB1ENSETR_TIM12EN B(6)
+#define RCC_MC_APB1ENSETR_TIM13EN B(7)
+#define RCC_MC_APB1ENSETR_TIM14EN B(8)
+#define RCC_MC_APB1ENSETR_LPTIM1EN B(9)
+#define RCC_MC_APB1ENSETR_SPI2EN B(11)
+#define RCC_MC_APB1ENSETR_SPI3EN B(12)
+#define RCC_MC_APB1ENSETR_USART2EN B(14)
+#define RCC_MC_APB1ENSETR_USART3EN B(15)
+#define RCC_MC_APB1ENSETR_UART4EN B(16)
+#define RCC_MC_APB1ENSETR_UART5EN B(17)
+#define RCC_MC_APB1ENSETR_UART7EN B(18)
+#define RCC_MC_APB1ENSETR_UART8EN B(19)
+#define RCC_MC_APB1ENSETR_I2C1EN B(21)
+#define RCC_MC_APB1ENSETR_I2C2EN B(22)
+#define RCC_MC_APB1ENSETR_I2C3EN B(23)
+#define RCC_MC_APB1ENSETR_I2C5EN B(24)
+#define RCC_MC_APB1ENSETR_SPDIFEN B(26)
+#define RCC_MC_APB1ENSETR_CECEN B(27)
+#define RCC_MC_APB1ENSETR_WWDG1EN B(28)
+#define RCC_MC_APB1ENSETR_DAC12EN B(29)
+#define RCC_MC_APB1ENSETR_MDIOSEN B(31)
+
+/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_APB1ENCLRR_TIM2EN B(0)
+#define RCC_MC_APB1ENCLRR_TIM3EN B(1)
+#define RCC_MC_APB1ENCLRR_TIM4EN B(2)
+#define RCC_MC_APB1ENCLRR_TIM5EN B(3)
+#define RCC_MC_APB1ENCLRR_TIM6EN B(4)
+#define RCC_MC_APB1ENCLRR_TIM7EN B(5)
+#define RCC_MC_APB1ENCLRR_TIM12EN B(6)
+#define RCC_MC_APB1ENCLRR_TIM13EN B(7)
+#define RCC_MC_APB1ENCLRR_TIM14EN B(8)
+#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9)
+#define RCC_MC_APB1ENCLRR_SPI2EN B(11)
+#define RCC_MC_APB1ENCLRR_SPI3EN B(12)
+#define RCC_MC_APB1ENCLRR_USART2EN B(14)
+#define RCC_MC_APB1ENCLRR_USART3EN B(15)
+#define RCC_MC_APB1ENCLRR_UART4EN B(16)
+#define RCC_MC_APB1ENCLRR_UART5EN B(17)
+#define RCC_MC_APB1ENCLRR_UART7EN B(18)
+#define RCC_MC_APB1ENCLRR_UART8EN B(19)
+#define RCC_MC_APB1ENCLRR_I2C1EN B(21)
+#define RCC_MC_APB1ENCLRR_I2C2EN B(22)
+#define RCC_MC_APB1ENCLRR_I2C3EN B(23)
+#define RCC_MC_APB1ENCLRR_I2C5EN B(24)
+#define RCC_MC_APB1ENCLRR_SPDIFEN B(26)
+#define RCC_MC_APB1ENCLRR_CECEN B(27)
+#define RCC_MC_APB1ENCLRR_WWDG1EN B(28)
+#define RCC_MC_APB1ENCLRR_DAC12EN B(29)
+#define RCC_MC_APB1ENCLRR_MDIOSEN B(31)
+
+/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_APB2ENSETR_TIM1EN B(0)
+#define RCC_MC_APB2ENSETR_TIM8EN B(1)
+#define RCC_MC_APB2ENSETR_TIM15EN B(2)
+#define RCC_MC_APB2ENSETR_TIM16EN B(3)
+#define RCC_MC_APB2ENSETR_TIM17EN B(4)
+#define RCC_MC_APB2ENSETR_SPI1EN B(8)
+#define RCC_MC_APB2ENSETR_SPI4EN B(9)
+#define RCC_MC_APB2ENSETR_SPI5EN B(10)
+#define RCC_MC_APB2ENSETR_USART6EN B(13)
+#define RCC_MC_APB2ENSETR_SAI1EN B(16)
+#define RCC_MC_APB2ENSETR_SAI2EN B(17)
+#define RCC_MC_APB2ENSETR_SAI3EN B(18)
+#define RCC_MC_APB2ENSETR_DFSDMEN B(20)
+#define RCC_MC_APB2ENSETR_ADFSDMEN B(21)
+#define RCC_MC_APB2ENSETR_FDCANEN B(24)
+
+/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_APB2ENCLRR_TIM1EN B(0)
+#define RCC_MC_APB2ENCLRR_TIM8EN B(1)
+#define RCC_MC_APB2ENCLRR_TIM15EN B(2)
+#define RCC_MC_APB2ENCLRR_TIM16EN B(3)
+#define RCC_MC_APB2ENCLRR_TIM17EN B(4)
+#define RCC_MC_APB2ENCLRR_SPI1EN B(8)
+#define RCC_MC_APB2ENCLRR_SPI4EN B(9)
+#define RCC_MC_APB2ENCLRR_SPI5EN B(10)
+#define RCC_MC_APB2ENCLRR_USART6EN B(13)
+#define RCC_MC_APB2ENCLRR_SAI1EN B(16)
+#define RCC_MC_APB2ENCLRR_SAI2EN B(17)
+#define RCC_MC_APB2ENCLRR_SAI3EN B(18)
+#define RCC_MC_APB2ENCLRR_DFSDMEN B(20)
+#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21)
+#define RCC_MC_APB2ENCLRR_FDCANEN B(24)
+
+/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_APB3ENSETR_LPTIM2EN B(0)
+#define RCC_MC_APB3ENSETR_LPTIM3EN B(1)
+#define RCC_MC_APB3ENSETR_LPTIM4EN B(2)
+#define RCC_MC_APB3ENSETR_LPTIM5EN B(3)
+#define RCC_MC_APB3ENSETR_SAI4EN B(8)
+#define RCC_MC_APB3ENSETR_SYSCFGEN B(11)
+#define RCC_MC_APB3ENSETR_VREFEN B(13)
+#define RCC_MC_APB3ENSETR_DTSEN B(16)
+#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17)
+#define RCC_MC_APB3ENSETR_HDPEN B(20)
+
+/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0)
+#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1)
+#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2)
+#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3)
+#define RCC_MC_APB3ENCLRR_SAI4EN B(8)
+#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11)
+#define RCC_MC_APB3ENCLRR_VREFEN B(13)
+#define RCC_MC_APB3ENCLRR_DTSEN B(16)
+#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17)
+#define RCC_MC_APB3ENCLRR_HDPEN B(20)
+
+/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_APB4ENSETR_LTDCEN B(0)
+#define RCC_MC_APB4ENSETR_DSIEN B(4)
+#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8)
+#define RCC_MC_APB4ENSETR_USBPHYEN B(16)
+#define RCC_MC_APB4ENSETR_STGENROEN B(20)
+
+/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */
+#define RCC_MP_APB4ENSETR_LTDCEN B(0)
+#define RCC_MP_APB4ENSETR_DSIEN B(4)
+#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15)
+#define RCC_MP_APB4ENSETR_USBPHYEN B(16)
+#define RCC_MP_APB4ENSETR_STGENROEN B(20)
+
+/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_APB4ENCLRR_LTDCEN B(0)
+#define RCC_MC_APB4ENCLRR_DSIEN B(4)
+#define RCC_MC_APB4ENCLRR_USBPHYEN B(16)
+#define RCC_MC_APB4ENCLRR_STGENROEN B(20)
+
+/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MP_APB4ENCLRR_LTDCEN B(0)
+#define RCC_MP_APB4ENCLRR_DSIEN B(4)
+#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15)
+#define RCC_MP_APB4ENCLRR_USBPHYEN B(16)
+#define RCC_MP_APB4ENCLRR_STGENROEN B(20)
+
+/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_APB5ENSETR_SPI6EN B(0)
+#define RCC_MC_APB5ENSETR_I2C4EN B(2)
+#define RCC_MC_APB5ENSETR_I2C6EN B(3)
+#define RCC_MC_APB5ENSETR_USART1EN B(4)
+#define RCC_MC_APB5ENSETR_RTCAPBEN B(8)
+#define RCC_MC_APB5ENSETR_TZC1EN B(11)
+#define RCC_MC_APB5ENSETR_TZC2EN B(12)
+#define RCC_MC_APB5ENSETR_TZPCEN B(13)
+#define RCC_MC_APB5ENSETR_BSECEN B(16)
+#define RCC_MC_APB5ENSETR_STGENEN B(20)
+
+/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MPU.
+ * This bit can also be used to test if IWDG1 peripheral clock is enabled
+ * If TZEN = 1, this register can only be modified in secure mode. */
+#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15)
+
+/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_APB5ENCLRR_SPI6EN B(0)
+#define RCC_MC_APB5ENCLRR_I2C4EN B(2)
+#define RCC_MC_APB5ENCLRR_I2C6EN B(3)
+#define RCC_MC_APB5ENCLRR_USART1EN B(4)
+#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8)
+#define RCC_MC_APB5ENCLRR_TZC1EN B(11)
+#define RCC_MC_APB5ENCLRR_TZC2EN B(12)
+#define RCC_MC_APB5ENCLRR_TZPCEN B(13)
+#define RCC_MC_APB5ENCLRR_BSECEN B(16)
+#define RCC_MC_APB5ENCLRR_STGENEN B(20)
+
+/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_AHB5ENSETR_GPIOZEN B(0)
+#define RCC_MC_AHB5ENSETR_CRYP1EN B(4)
+#define RCC_MC_AHB5ENSETR_HASH1EN B(5)
+#define RCC_MC_AHB5ENSETR_RNG1EN B(6)
+#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8)
+#define RCC_MC_AHB5ENSETR_AXIMC B(16)
+
+/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0)
+#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4)
+#define RCC_MC_AHB5ENCLRR_HASH1EN B(5)
+#define RCC_MC_AHB5ENCLRR_RNG1EN B(6)
+#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8)
+
+/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_AHB6ENSETR_MDMAEN B(0)
+#define RCC_MC_AHB6ENSETR_GPUEN B(5)
+#define RCC_MC_AHB6ENSETR_ETHCKEN B(7)
+#define RCC_MC_AHB6ENSETR_ETHTXEN B(8)
+#define RCC_MC_AHB6ENSETR_ETHRXEN B(9)
+#define RCC_MC_AHB6ENSETR_ETHMACEN B(10)
+#define RCC_MC_AHB6ENSETR_FMCEN B(12)
+#define RCC_MC_AHB6ENSETR_QSPIEN B(14)
+#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16)
+#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17)
+#define RCC_MC_AHB6ENSETR_CRC1EN B(20)
+#define RCC_MC_AHB6ENSETR_USBHEN B(24)
+
+/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_AHB6ENCLRR_MDMAEN B(0)
+#define RCC_MC_AHB6ENCLRR_GPUEN B(5)
+#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7)
+#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8)
+#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9)
+#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10)
+#define RCC_MC_AHB6ENCLRR_FMCEN B(12)
+#define RCC_MC_AHB6ENCLRR_QSPIEN B(14)
+#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16)
+#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17)
+#define RCC_MC_AHB6ENCLRR_CRC1EN B(20)
+#define RCC_MC_AHB6ENCLRR_USBHEN B(24)
+
+/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MPU. */
+#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0)
+
+/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MPU */
+#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0)
+
+/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_AHB2ENSETR_DMA1EN B(0)
+#define RCC_MC_AHB2ENSETR_DMA2EN B(1)
+#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2)
+#define RCC_MC_AHB2ENSETR_ADC12EN B(5)
+#define RCC_MC_AHB2ENSETR_USBOEN B(8)
+#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16)
+
+/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_AHB2ENCLRR_DMA1EN B(0)
+#define RCC_MC_AHB2ENCLRR_DMA2EN B(1)
+#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2)
+#define RCC_MC_AHB2ENCLRR_ADC12EN B(5)
+#define RCC_MC_AHB2ENCLRR_USBOEN B(8)
+#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16)
+
+/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_AHB3ENSETR_DCMIEN B(0)
+#define RCC_MC_AHB3ENSETR_CRYP2EN B(4)
+#define RCC_MC_AHB3ENSETR_HASH2EN B(5)
+#define RCC_MC_AHB3ENSETR_RNG2EN B(6)
+#define RCC_MC_AHB3ENSETR_CRC2EN B(7)
+#define RCC_MC_AHB3ENSETR_HSEMEN B(11)
+#define RCC_MC_AHB3ENSETR_IPCCEN B(12)
+
+/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_AHB3ENCLRR_DCMIEN B(0)
+#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4)
+#define RCC_MC_AHB3ENCLRR_HASH2EN B(5)
+#define RCC_MC_AHB3ENCLRR_RNG2EN B(6)
+#define RCC_MC_AHB3ENCLRR_CRC2EN B(7)
+#define RCC_MC_AHB3ENCLRR_HSEMEN B(11)
+#define RCC_MC_AHB3ENCLRR_IPCCEN B(12)
+
+/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_AHB4ENSETR_GPIOAEN B(0)
+#define RCC_MC_AHB4ENSETR_GPIOBEN B(1)
+#define RCC_MC_AHB4ENSETR_GPIOCEN B(2)
+#define RCC_MC_AHB4ENSETR_GPIODEN B(3)
+#define RCC_MC_AHB4ENSETR_GPIOEEN B(4)
+#define RCC_MC_AHB4ENSETR_GPIOFEN B(5)
+#define RCC_MC_AHB4ENSETR_GPIOGEN B(6)
+#define RCC_MC_AHB4ENSETR_GPIOHEN B(7)
+#define RCC_MC_AHB4ENSETR_GPIOIEN B(8)
+#define RCC_MC_AHB4ENSETR_GPIOJEN B(9)
+#define RCC_MC_AHB4ENSETR_GPIOKEN B(10)
+
+/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0)
+#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1)
+#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2)
+#define RCC_MC_AHB4ENCLRR_GPIODEN B(3)
+#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4)
+#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5)
+#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6)
+#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7)
+#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8)
+#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9)
+#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10)
+
+/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_AXIMENSETR_SYSRAMEN B(0)
+
+/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0)
+
+/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/
+/*!< This register is used to set the peripheral clock enable bit of the corresponding
+ * peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
+#define RCC_MC_MLAHBENSETR_RETRAMEN B(4)
+
+/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/
+/*!< This register is used to clear the peripheral clock enable bit of the corresponding
+ * peripheral. It shall be used to deallocate a peripheral from MCU */
+#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4)
+
+
+/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0)
+#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1)
+#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2)
+#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3)
+#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4)
+#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5)
+#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6)
+#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7)
+#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8)
+#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9)
+#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11)
+#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12)
+#define RCC_MC_APB1LPENSETR_USART2LPEN B(14)
+#define RCC_MC_APB1LPENSETR_USART3LPEN B(15)
+#define RCC_MC_APB1LPENSETR_UART4LPEN B(16)
+#define RCC_MC_APB1LPENSETR_UART5LPEN B(17)
+#define RCC_MC_APB1LPENSETR_UART7LPEN B(18)
+#define RCC_MC_APB1LPENSETR_UART8LPEN B(19)
+#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21)
+#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22)
+#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23)
+#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24)
+#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26)
+#define RCC_MC_APB1LPENSETR_CECLPEN B(27)
+#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28)
+#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29)
+#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31)
+
+/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0)
+#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1)
+#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2)
+#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3)
+#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4)
+#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5)
+#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6)
+#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7)
+#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8)
+#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9)
+#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11)
+#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12)
+#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14)
+#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15)
+#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16)
+#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17)
+#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18)
+#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19)
+#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21)
+#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22)
+#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23)
+#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24)
+#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26)
+#define RCC_MC_APB1LPENCLRR_CECLPEN B(27)
+#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28)
+#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29)
+#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31)
+
+/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0)
+#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1)
+#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2)
+#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3)
+#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4)
+#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8)
+#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9)
+#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10)
+#define RCC_MC_APB2LPENSETR_USART6LPEN B(13)
+#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16)
+#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17)
+#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18)
+#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20)
+#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21)
+#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24)
+
+/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0)
+#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1)
+#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2)
+#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3)
+#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4)
+#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8)
+#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9)
+#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10)
+#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13)
+#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16)
+#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17)
+#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18)
+#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20)
+#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21)
+#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24)
+
+/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0)
+#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1)
+#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2)
+#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3)
+#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8)
+#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11)
+#define RCC_MC_APB3LPENSETR_VREFLPEN B(13)
+#define RCC_MC_APB3LPENSETR_DTSLPEN B(16)
+#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17)
+
+/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0)
+#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1)
+#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2)
+#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3)
+#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8)
+#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11)
+#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13)
+#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16)
+#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17)
+
+/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0)
+#define RCC_MC_APB4LPENSETR_DSILPEN B(4)
+#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16)
+#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20)
+#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21)
+
+/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/
+/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0)
+#define RCC_MP_APB4LPENSETR_DSILPEN B(4)
+#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15)
+#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16)
+#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20)
+#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21)
+
+/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0)
+#define RCC_MC_APB4LPENCLRR_DSILPEN B(4)
+#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16)
+#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20)
+#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21)
+
+/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0)
+#define RCC_MP_APB4LPENCLRR_DSILPEN B(4)
+#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15)
+#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16)
+#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20)
+#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21)
+
+/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0)
+#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2)
+#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3)
+#define RCC_MC_APB5LPENSETR_USART1LPEN B(4)
+#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8)
+#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11)
+#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12)
+#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13)
+#define RCC_MC_APB5LPENSETR_BSECLPEN B(16)
+#define RCC_MC_APB5LPENSETR_STGENLPEN B(20)
+#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21)
+
+
+/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0)
+#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2)
+#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3)
+#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4)
+#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8)
+#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11)
+#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12)
+#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13)
+#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16)
+#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20)
+#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21)
+
+/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0)
+#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4)
+#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5)
+#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6)
+#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8)
+
+/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0)
+#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4)
+#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5)
+#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6)
+#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8)
+
+/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0)
+#define RCC_MC_AHB6LPENSETR_GPULPEN B(5)
+#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7)
+#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8)
+#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9)
+#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10)
+#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11)
+#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12)
+#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14)
+#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16)
+#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17)
+#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20)
+#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24)
+
+/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0)
+#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5)
+#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7)
+#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8)
+#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9)
+#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10)
+#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11)
+#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12)
+#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14)
+#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16)
+#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17)
+#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20)
+#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24)
+
+/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0)
+
+/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0)
+
+/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0)
+#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1)
+#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2)
+#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5)
+#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8)
+#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16)
+
+/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0)
+#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1)
+#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2)
+#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5)
+#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8)
+#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16)
+
+/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0)
+#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4)
+#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5)
+#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6)
+#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7)
+#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11)
+#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12)
+
+/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0)
+#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4)
+#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5)
+#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6)
+#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7)
+#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11)
+#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12)
+
+/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0)
+#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1)
+#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2)
+#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3)
+#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4)
+#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5)
+#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6)
+#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7)
+#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8)
+#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9)
+#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10)
+
+/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0)
+#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1)
+#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2)
+#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3)
+#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4)
+#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5)
+#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6)
+#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7)
+#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8)
+#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9)
+#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10)
+
+/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0)
+
+/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0)
+
+/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/
+/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
+ * peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
+ * CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
+#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0)
+#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1)
+#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2)
+#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4)
+
+/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/
+/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
+ * peripheral. Writing '0' has no effect, reading will return the effective values of the
+ * corresponding bits. Writing a '1' sets the corresponding bit to '0' */
+#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0)
+#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1)
+#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2)
+#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4)
+
+
+/******************* Bit definition for RCC_BR_RSTSCLRR register ************/
+/*!< This register is used by the BOOTROM to check the reset source.
+ * Writing "0" has no effect, reading will return the effective values of the corresponding
+ * bits. Writing a '1' clears the corresponding bit to '0'
+ *
+ * @note In order to identify the reset source, the MPU application must use
+ * RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application
+ * must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).
+ * @note This register except MPUP[1:0]RSTF flags is located into VDD domain,
+ * and is reset by por_rst reset.
+ * @note If TZEN = '1', this register can only be modified in secure mode.
+ */
+#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U)
+#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
+
+#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U)
+#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
+
+#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U)
+#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
+
+#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U)
+#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
+
+#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U)
+#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
+
+#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U)
+#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
+
+#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U)
+#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
+
+#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U)
+#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+
+#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U)
+#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+
+#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U)
+#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
+#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
+
+#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U)
+#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
+#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
+
+
+/******************* Bit definition for RCC_MC_RSTSCLRR register ************/
+/*!< This register is used by the MCU to check the reset source.
+ * Writing "0" has no effect, reading will return the effective values of the corresponding
+ * bits. Writing a "1" clears the corresponding bit to 0
+ * @note This register is located into VDD domain, and is reset by rst_por reset.
+ */
+#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U)
+#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
+
+#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U)
+#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
+
+#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U)
+#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
+
+#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U)
+#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
+
+#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U)
+#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
+
+#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U)
+#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */
+#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/
+
+#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U)
+#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
+
+#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U)
+#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
+
+#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U)
+#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+
+#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U)
+#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+
+#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U)
+#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */
+#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/
+
+/******************* Bit definition for RCC_MP_RSTSCLRR register ************/
+/*!< This register is used by the MPU to check the reset source. This register is updated
+ * by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or
+ * exit from STANDBY or CSTANDBY.
+ *
+ * @note Writing '0' has no effect, reading will return the effective values of
+ * the corresponding bits. Writing a '1' clears the corresponding bit to '0'.
+ * @note The register is located in VDD_CORE.
+ * @note If TZEN = '1', this register can only be modified in secure mode.
+ */
+#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U)
+#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
+#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
+
+#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U)
+#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
+#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
+
+#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U)
+#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
+#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
+
+#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U)
+#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
+#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
+
+#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U)
+#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
+#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
+
+#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U)
+#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
+#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
+
+#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U)
+#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
+#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
+
+#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U)
+#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
+#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
+
+#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U)
+#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
+#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
+
+#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U)
+#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */
+#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/
+
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U)
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
+#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/
+
+#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U)
+#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
+#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
+
+#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U)
+#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
+#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
+
+#define RCC_MP_RSTSCLRR_SPARE_Pos (15U)
+#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */
+#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/
+
+/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/
+/*!< This register is used by the MPU in order to freeze the IWDGs clocks.
+ * After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby)
+ * the MPU is allowed to write it once.
+ * Writing "0" has no effect, reading will return the effective values of the corresponding
+ * bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be
+ * modified in secure mode.
+ */
+#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0)
+#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1)
+
+
+/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/
+/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks.
+ * Writing "0" has no effect, reading will return the effective values of the corresponding
+ * bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only
+ * be modified in secure mode.
+ */
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0)
+#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1)
+
+/******************* Bit definition for RCC_VERR register ************/
+/*!< This register gives the IP version. */
+#define RCC_VERR_MINREV_Pos (0U)
+#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk
+#define RCC_VERR_MAJREV_Pos (4U)
+#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk
+
+/******************* Bit definition for RCC_IDR register ************/
+/*!< This register gives the unique identifier of the RCC */
+#define RCC_VERR_ID_Pos (0U)
+#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */
+#define RCC_VERR_ID RCC_VERR_ID_Msk
+
+/******************* Bit definition for RCC_IDR register ************/
+/*!< This register gives the decoding space, which is for the RCC of 4 kB */
+#define RCC_VERR_SIDR_Pos (0U)
+#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */
+#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos (5U)
+#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
+#define RNG_CR_CED RNG_CR_CED_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/********************** Bit definition for RNG_VERR register *****************/
+#define RNG_VERR_MINREV_Pos (0U)
+#define RNG_VERR_MINREV_Msk (0xFU << RNG_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define RNG_VERR_MINREV RNG_VERR_MINREV_Msk /*!< Minor Revision number */
+#define RNG_VERR_MAJREV_Pos (4U)
+#define RNG_VERR_MAJREV_Msk (0xFU << RNG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define RNG_VERR_MAJREV RNG_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for RNG_IPIDR register ****************/
+#define RNG_IPIDR_ID_Pos (0U)
+#define RNG_IPIDR_ID_Msk (0xFFFFFFFFU << RNG_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define RNG_IPIDR_ID RNG_IPIDR_ID_Msk /*!< IP Identification */
+
+/********************** Bit definition for RNG_SIDR register *****************/
+#define RNG_SIDR_SID_Pos (0U)
+#define RNG_SIDR_SID_Msk (0xFFFFFFFFU << RNG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define RNG_SIDR_SID RNG_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk
+#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk
+#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk
+#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk
+#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk
+#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk
+#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk
+#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk
+#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk
+#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk
+
+/**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/
+#define RTC_ICSR_RECALPF_Pos (16U)
+#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
+#define RTC_ICSR_INIT_Pos (7U)
+#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
+#define RTC_ICSR_INITF_Pos (6U)
+#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
+#define RTC_ICSR_RSF_Pos (5U)
+#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
+#define RTC_ICSR_INITS_Pos (4U)
+#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
+#define RTC_ICSR_SHPF_Pos (3U)
+#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
+#define RTC_ICSR_WUTWF_Pos (2U)
+#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
+#define RTC_ICSR_ALRBWF_Pos (1U)
+#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
+#define RTC_ICSR_ALRAWF_Pos (0U)
+#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
+
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_OUT2EN_Pos (31U)
+#define RTC_CR_OUT2EN_Msk (0x1U << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
+#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk
+#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
+#define RTC_CR_TAMPALRM_TYPE_Msk (0x1U << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
+#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk
+#define RTC_CR_TAMPALRM_PU_Pos (29U)
+#define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
+#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk
+#define RTC_CR_TAMPOE_Pos (26U)
+#define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
+#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk
+#define RTC_CR_TAMPTS_Pos (25U)
+#define RTC_CR_TAMPTS_Msk (0x1U << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
+#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk
+#define RTC_CR_ITSE_Pos (24U)
+#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_SMCR register *******************/
+#define RTC_SMCR_DECPROT_Pos (15U)
+#define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */
+#define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk
+#define RTC_SMCR_INITDPROT_Pos (14U)
+#define RTC_SMCR_INITDPROT_Msk (0x1U << RTC_SMCR_INITDPROT_Pos) /*!< 0x00004000 */
+#define RTC_SMCR_INITDPROT RTC_SMCR_INITDPROT_Msk
+#define RTC_SMCR_CALDPROT_Pos (13U)
+#define RTC_SMCR_CALDPROT_Msk (0x1U << RTC_SMCR_CALDPROT_Pos) /*!< 0x00002000 */
+#define RTC_SMCR_CALDPROT RTC_SMCR_CALDPROT_Msk
+#define RTC_SMCR_TSDPROT_Pos (3U)
+#define RTC_SMCR_TSDPROT_Msk (0x1U << RTC_SMCR_TSDPROT_Pos) /*!< 0x00000008 */
+#define RTC_SMCR_TSDPROT RTC_SMCR_TSDPROT_Msk
+#define RTC_SMCR_WUTDPROT_Pos (2U)
+#define RTC_SMCR_WUTDPROT_Msk (0x1U << RTC_SMCR_WUTDPROT_Pos) /*!< 0x00000004 */
+#define RTC_SMCR_WUTDPROT RTC_SMCR_WUTDPROT_Msk
+#define RTC_SMCR_ALRBDPROT_Pos (1U)
+#define RTC_SMCR_ALRBDPROT_Msk (0x1U << RTC_SMCR_ALRBDPROT_Pos) /*!< 0x00000002 */
+#define RTC_SMCR_ALRBDPROT RTC_SMCR_ALRBDPROT_Msk
+#define RTC_SMCR_ALRADPROT_Pos (0U)
+#define RTC_SMCR_ALRADPROT_Msk (0x1U << RTC_SMCR_ALRADPROT_Pos) /*!< 0x00000001 */
+#define RTC_SMCR_ALRADPROT RTC_SMCR_ALRADPROT_Msk
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ******************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_SR register *************/
+#define RTC_SR_ITSF_Pos (5U)
+#define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
+#define RTC_SR_ITSF RTC_SR_ITSF_Msk
+#define RTC_SR_TSOVF_Pos (4U)
+#define RTC_SR_TSOVF_Msk (0x1U << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
+#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
+#define RTC_SR_TSF_Pos (3U)
+#define RTC_SR_TSF_Msk (0x1U << RTC_SR_TSF_Pos) /*!< 0x00000008 */
+#define RTC_SR_TSF RTC_SR_TSF_Msk
+#define RTC_SR_WUTF_Pos (2U)
+#define RTC_SR_WUTF_Msk (0x1U << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
+#define RTC_SR_WUTF RTC_SR_WUTF_Msk
+#define RTC_SR_ALRBF_Pos (1U)
+#define RTC_SR_ALRBF_Msk (0x1U << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
+#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
+#define RTC_SR_ALRAF_Pos (0U)
+#define RTC_SR_ALRAF_Msk (0x1U << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
+#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
+
+/******************** Bits definition for RTC_MISR register *************/
+#define RTC_MISR_ITSMF_Pos (5U)
+#define RTC_MISR_ITSMF_Msk (0x1U << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
+#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
+#define RTC_MISR_TSOVMF_Pos (4U)
+#define RTC_MISR_TSOVMF_Msk (0x1U << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
+#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
+#define RTC_MISR_TSMF_Pos (3U)
+#define RTC_MISR_TSMF_Msk (0x1U << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
+#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
+#define RTC_MISR_WUTMF_Pos (2U)
+#define RTC_MISR_WUTMF_Msk (0x1U << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
+#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
+#define RTC_MISR_ALRBMF_Pos (1U)
+#define RTC_MISR_ALRBMF_Msk (0x1U << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
+#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
+#define RTC_MISR_ALRAMF_Pos (0U)
+#define RTC_MISR_ALRAMF_Msk (0x1U << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
+#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
+
+/******************** Bits definition for RTC_SMISR register *************/
+#define RTC_SMISR_ITSMF_Pos (5U)
+#define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */
+#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk
+#define RTC_SMISR_TSOVMF_Pos (4U)
+#define RTC_SMISR_TSOVMF_Msk (0x1U << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */
+#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk
+#define RTC_SMISR_TSMF_Pos (3U)
+#define RTC_SMISR_TSMF_Msk (0x1U << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */
+#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk
+#define RTC_SMISR_WUTMF_Pos (2U)
+#define RTC_SMISR_WUTMF_Msk (0x1U << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */
+#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk
+#define RTC_SMISR_ALRBMF_Pos (1U)
+#define RTC_SMISR_ALRBMF_Msk (0x1U << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */
+#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk
+#define RTC_SMISR_ALRAMF_Pos (0U)
+#define RTC_SMISR_ALRAMF_Msk (0x1U << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */
+#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk
+
+/******************** Bits definition for RTC_SCR register *************/
+#define RTC_SCR_CITSF_Pos (5U)
+#define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
+#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
+#define RTC_SCR_CTSOVF_Pos (4U)
+#define RTC_SCR_CTSOVF_Msk (0x1U << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
+#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
+#define RTC_SCR_CTSF_Pos (3U)
+#define RTC_SCR_CTSF_Msk (0x1U << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
+#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
+#define RTC_SCR_CWUTF_Pos (2U)
+#define RTC_SCR_CWUTF_Msk (0x1U << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
+#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
+#define RTC_SCR_CALRBF_Pos (1U)
+#define RTC_SCR_CALRBF_Msk (0x1U << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
+#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
+#define RTC_SCR_CALRAF_Pos (0U)
+#define RTC_SCR_CALRAF_Msk (0x1U << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
+#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_CFGR_LSCOEN_Pos (1U)
+#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */
+#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk
+#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */
+#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */
+#define RTC_CFGR_OUT2_RMP_Pos (0U)
+#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */
+#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk
+
+/******************** Bits definition for RTC_HWCFGR register *************/
+
+#define RTC_HWCFGR_TRUST_ZONE_Pos (24U)
+#define RTC_HWCFGR_TRUST_ZONE_Msk (0xFU << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x0F000000 */
+#define RTC_HWCFGR_TRUST_ZONE RTC_HWCFGR_TRUST_ZONE_Msk
+#define RTC_HWCFGR_TRUST_ZONE_0 (0x1U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x01000000 */
+#define RTC_HWCFGR_TRUST_ZONE_1 (0x2U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x02000000 */
+#define RTC_HWCFGR_TRUST_ZONE_2 (0x4U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x04000000 */
+#define RTC_HWCFGR_TRUST_ZONE_3 (0x8U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x08000000 */
+
+#define RTC_HWCFGR_OPTIONREG_OUT_Pos (16U)
+#define RTC_HWCFGR_OPTIONREG_OUT_Msk (0xFFU << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00FF0000 */
+#define RTC_HWCFGR_OPTIONREG_OUT RTC_HWCFGR_OPTIONREG_OUT_Msk
+#define RTC_HWCFGR_OPTIONREG_OUT_0 (0x01U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00010000 */
+#define RTC_HWCFGR_OPTIONREG_OUT_1 (0x02U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00020000 */
+#define RTC_HWCFGR_OPTIONREG_OUT_2 (0x04U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00040000 */
+#define RTC_HWCFGR_OPTIONREG_OUT_3 (0x08U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00080000 */
+#define RTC_HWCFGR_OPTIONREG_OUT_4 (0x10U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00100000 */
+#define RTC_HWCFGR_OPTIONREG_OUT_5 (0x20U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00200000 */
+#define RTC_HWCFGR_OPTIONREG_OUT_6 (0x40U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00400000 */
+#define RTC_HWCFGR_OPTIONREG_OUT_7 (0x80U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00800000 */
+
+#define RTC_HWCFGR_TIMESTAMP_Pos (12U)
+#define RTC_HWCFGR_TIMESTAMP_Msk (0xFU << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x0000F000 */
+#define RTC_HWCFGR_TIMESTAMP RTC_HWCFGR_TIMESTAMP_Msk
+#define RTC_HWCFGR_TIMESTAMP_0 (0x1U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00001000 */
+#define RTC_HWCFGR_TIMESTAMP_1 (0x2U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00002000 */
+#define RTC_HWCFGR_TIMESTAMP_2 (0x4U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00004000 */
+#define RTC_HWCFGR_TIMESTAMP_3 (0x8U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00008000 */
+
+#define RTC_HWCFGR_SMOOTH_CALIB_Pos (8U)
+#define RTC_HWCFGR_SMOOTH_CALIB_Msk (0xFU << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000F00 */
+#define RTC_HWCFGR_SMOOTH_CALIB RTC_HWCFGR_SMOOTH_CALIB_Msk
+#define RTC_HWCFGR_SMOOTH_CALIB_0 (0x1U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000100 */
+#define RTC_HWCFGR_SMOOTH_CALIB_1 (0x2U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000200 */
+#define RTC_HWCFGR_SMOOTH_CALIB_2 (0x4U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000400 */
+#define RTC_HWCFGR_SMOOTH_CALIB_3 (0x8U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000800 */
+
+#define RTC_HWCFGR_WAKEUP_Pos (4U)
+#define RTC_HWCFGR_WAKEUP_Msk (0xFU << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x000000F0 */
+#define RTC_HWCFGR_WAKEUP RTC_HWCFGR_WAKEUP_Msk
+#define RTC_HWCFGR_WAKEUP_0 (0x1U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000010 */
+#define RTC_HWCFGR_WAKEUP_1 (0x2U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000020 */
+#define RTC_HWCFGR_WAKEUP_2 (0x4U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000040 */
+#define RTC_HWCFGR_WAKEUP_3 (0x8U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000080 */
+
+#define RTC_HWCFGR_ALARMB_Pos (0U)
+#define RTC_HWCFGR_ALARMB_Msk (0xFU << RTC_HWCFGR_ALARMB_Pos) /*!< 0x0000000F */
+#define RTC_HWCFGR_ALARMB RTC_HWCFGR_ALARMB_Msk
+#define RTC_HWCFGR_ALARMB_0 (0x1U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000001 */
+#define RTC_HWCFGR_ALARMB_1 (0x2U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000002 */
+#define RTC_HWCFGR_ALARMB_2 (0x4U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000004 */
+#define RTC_HWCFGR_ALARMB_3 (0x8U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000008 */
+
+
+/******************** Bits definition for RTC_VERR register ****************/
+#define RTC_VERR_MAJREV_Pos (4U)
+#define RTC_VERR_MAJREV_Msk (0xFU << RTC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define RTC_VERR_MAJREV RTC_VERR_MAJREV_Msk
+#define RTC_VERR_MAJREV_0 (0x1U << RTC_VERR_MAJREV_Pos) /*!< 0x00000010 */
+#define RTC_VERR_MAJREV_1 (0x2U << RTC_VERR_MAJREV_Pos) /*!< 0x00000020 */
+#define RTC_VERR_MAJREV_2 (0x4U << RTC_VERR_MAJREV_Pos) /*!< 0x00000040 */
+#define RTC_VERR_MAJREV_3 (0x8U << RTC_VERR_MAJREV_Pos) /*!< 0x00000080 */
+#define RTC_VERR_MINREV_Pos (0U)
+#define RTC_VERR_MINREV_Msk (0xFU << RTC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define RTC_VERR_MINREV RTC_VERR_MINREV_Msk
+#define RTC_VERR_MINREV_0 (0x1U << RTC_VERR_MINREV_Pos) /*!< 0x00000001 */
+#define RTC_VERR_MINREV_1 (0x2U << RTC_VERR_MINREV_Pos) /*!< 0x00000002 */
+#define RTC_VERR_MINREV_2 (0x4U << RTC_VERR_MINREV_Pos) /*!< 0x00000004 */
+#define RTC_VERR_MINREV_3 (0x8U << RTC_VERR_MINREV_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_IPIDR register ****************/
+#define RTC_IPIDR_ID_Pos (0U)
+#define RTC_IPIDR_ID_Msk (0xFFFFFFFFU << RTC_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define RTC_IPIDR_ID RTC_IPIDR_ID_Msk
+
+/******************** Bits definition for RTC_SIDR register ****************/
+#define RTC_SIDR_SID_Pos (0U)
+#define RTC_SIDR_SID_Msk (0xFFFFFFFFU << RTC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define RTC_SIDR_SID RTC_SIDR_SID_Msk
+
+/******************************************************************************/
+/* */
+/* Tamper and Backup registers (TAMP) */
+/* */
+/******************************************************************************/
+
+/******************** Bits definition for TAMP_CR1 register ***************/
+#define TAMP_CR1_TAMPE_Pos (0U)
+#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */
+#define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk
+#define TAMP_CR1_TAMP1E_Pos (0U)
+#define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
+#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
+#define TAMP_CR1_TAMP2E_Pos (1U)
+#define TAMP_CR1_TAMP2E_Msk (0x1U << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
+#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
+#define TAMP_CR1_TAMP3E_Pos (2U)
+#define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
+#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
+#define TAMP_CR1_ITAMPE_Pos (16U)
+#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */
+#define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk
+#define TAMP_CR1_ITAMP1E_Pos (16U)
+#define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */
+#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk
+#define TAMP_CR1_ITAMP2E_Pos (17U)
+#define TAMP_CR1_ITAMP2E_Msk (0x1U << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */
+#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk
+#define TAMP_CR1_ITAMP3E_Pos (18U)
+#define TAMP_CR1_ITAMP3E_Msk (0x1U << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
+#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
+#define TAMP_CR1_ITAMP4E_Pos (19U)
+#define TAMP_CR1_ITAMP4E_Msk (0x1U << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
+#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
+#define TAMP_CR1_ITAMP5E_Pos (20U)
+#define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
+#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
+#define TAMP_CR1_ITAMP8E_Pos (23U)
+#define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */
+#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk
+
+
+/******************** Bits definition for TAMP_CR2 register ***************/
+#define TAMP_CR2_TAMPNOERASE_Pos (0U)
+#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */
+#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk
+#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
+#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
+#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
+#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
+#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
+#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
+#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
+#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
+#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
+#define TAMP_CR2_TAMPMSK_Pos (16U)
+#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */
+#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk
+#define TAMP_CR2_TAMP1MSK_Pos (16U)
+#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
+#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
+#define TAMP_CR2_TAMP2MSK_Pos (17U)
+#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
+#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
+#define TAMP_CR2_TAMP3MSK_Pos (18U)
+#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
+#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
+#define TAMP_CR2_TAMPTRG_Pos (24U)
+#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */
+#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk
+#define TAMP_CR2_TAMP1TRG_Pos (24U)
+#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
+#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
+#define TAMP_CR2_TAMP2TRG_Pos (25U)
+#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
+#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
+#define TAMP_CR2_TAMP3TRG_Pos (26U)
+#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
+#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
+
+
+/******************** Bits definition for TAMP_FLTCR register ***************/
+#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
+#define TAMP_FLTCR_TAMPFREQ_Msk (0x7U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
+#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
+#define TAMP_FLTCR_TAMPFREQ_0 (0x1U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */
+#define TAMP_FLTCR_TAMPFREQ_1 (0x2U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */
+#define TAMP_FLTCR_TAMPFREQ_2 (0x4U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */
+#define TAMP_FLTCR_TAMPFLT_Pos (3U)
+#define TAMP_FLTCR_TAMPFLT_Msk (0x3U << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
+#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
+#define TAMP_FLTCR_TAMPFLT_0 (0x1U << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */
+#define TAMP_FLTCR_TAMPFLT_1 (0x2U << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */
+#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
+#define TAMP_FLTCR_TAMPPRCH_Msk (0x3U << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
+#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
+#define TAMP_FLTCR_TAMPPRCH_0 (0x1U << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */
+#define TAMP_FLTCR_TAMPPRCH_1 (0x2U << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */
+#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
+#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
+#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
+
+/******************** Bits definition for TAMP_ATCR1 register ***************/
+#define TAMP_ATCR1_TAMPAM_Pos (0U)
+#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */
+#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk
+#define TAMP_ATCR1_TAMP1AM_Pos (0U)
+#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <<TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
+#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
+#define TAMP_ATCR1_TAMP2AM_Pos (1U)
+#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL <<TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
+#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
+#define TAMP_ATCR1_TAMP3AM_Pos (2U)
+#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL <<TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
+#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
+#define TAMP_ATCR1_TAMP4AM_Pos (3U)
+#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL <<TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */
+#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk
+#define TAMP_ATCR1_TAMP5AM_Pos (4U)
+#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL <<TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */
+#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk
+#define TAMP_ATCR1_TAMP6AM_Pos (6U)
+#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL <<TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000020 */
+#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk
+#define TAMP_ATCR1_TAMP7AM_Pos (6U)
+#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL <<TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */
+#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk
+#define TAMP_ATCR1_TAMP8AM_Pos (7U)
+#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL <<TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */
+#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk
+#define TAMP_ATCR1_ATOSEL1_Pos (8U)
+#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL <<TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
+#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
+#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
+#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
+#define TAMP_ATCR1_ATOSEL2_Pos (10U)
+#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL <<TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
+#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
+#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
+#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
+#define TAMP_ATCR1_ATOSEL3_Pos (12U)
+#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL <<TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
+#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
+#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
+#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
+#define TAMP_ATCR1_ATOSEL4_Pos (14U)
+#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL <<TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
+#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
+#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
+#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
+#define TAMP_ATCR1_ATCKSEL_Pos (16U)
+#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL <<TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
+#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
+#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
+#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
+#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
+#define TAMP_ATCR1_ATPER_Pos (24U)
+#define TAMP_ATCR1_ATPER_Msk (0x7UL <<TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
+#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
+#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */
+#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */
+#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */
+#define TAMP_ATCR1_ATOSHARE_Pos (30U)
+#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL <<TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
+#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
+#define TAMP_ATCR1_FLTEN_Pos (31U)
+#define TAMP_ATCR1_FLTEN_Msk (0x1UL <<TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
+#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
+
+/******************** Bits definition for TAMP_ATSEEDR register ***************/
+#define TAMP_ATSEEDR_SEED_Pos (0U)
+#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFU << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
+
+/******************** Bits definition for TAMP_ATOR register ***************/
+#define TAMP_ATOR_PRNG_Pos (0U)
+#define TAMP_ATOR_PRNG_Msk (0xFFU << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */
+#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk
+#define TAMP_ATOR_PRNG_0 (0x01U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */
+#define TAMP_ATOR_PRNG_1 (0x02U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */
+#define TAMP_ATOR_PRNG_2 (0x04U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */
+#define TAMP_ATOR_PRNG_3 (0x08U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */
+#define TAMP_ATOR_PRNG_4 (0x10U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */
+#define TAMP_ATOR_PRNG_5 (0x20U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */
+#define TAMP_ATOR_PRNG_6 (0x40U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */
+#define TAMP_ATOR_PRNG_7 (0x80U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */
+#define TAMP_ATOR_SEEDF_Pos (14U)
+#define TAMP_ATOR_SEEDF_Msk (0x1U << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */
+#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk
+#define TAMP_ATOR_INITS_Pos (15U)
+#define TAMP_ATOR_INITS_Msk (0x1U << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */
+#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
+
+/******************** Bits definition for TAMP_SMCR register ***************/
+#define TAMP_SMCR_BKPRWDPROT_Pos (0U)
+#define TAMP_SMCR_BKPRWDPROT_Msk (0xFFU << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x000000FF */
+#define TAMP_SMCR_BKPRWDPROT TAMP_SMCR_BKPRWDPROT_Msk
+#define TAMP_SMCR_BKPRWDPROT_0 (0x01U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000001 */
+#define TAMP_SMCR_BKPRWDPROT_1 (0x02U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000002 */
+#define TAMP_SMCR_BKPRWDPROT_2 (0x04U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000004 */
+#define TAMP_SMCR_BKPRWDPROT_3 (0x08U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000008 */
+#define TAMP_SMCR_BKPRWDPROT_4 (0x10U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000010 */
+#define TAMP_SMCR_BKPRWDPROT_5 (0x20U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000020 */
+#define TAMP_SMCR_BKPRWDPROT_6 (0x40U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000040 */
+#define TAMP_SMCR_BKPRWDPROT_7 (0x80U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000080 */
+#define TAMP_SMCR_BKPWDPROT_Pos (16U)
+#define TAMP_SMCR_BKPWDPROT_Msk (0xFFU << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00FF0000 */
+#define TAMP_SMCR_BKPWDPROT TAMP_SMCR_BKPWDPROT_Msk
+#define TAMP_SMCR_BKPWDPROT_0 (0x01U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00010000 */
+#define TAMP_SMCR_BKPWDPROT_1 (0x02U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00020000 */
+#define TAMP_SMCR_BKPWDPROT_2 (0x04U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00040000 */
+#define TAMP_SMCR_BKPWDPROT_3 (0x08U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00080000 */
+#define TAMP_SMCR_BKPWDPROT_4 (0x10U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00100000 */
+#define TAMP_SMCR_BKPWDPROT_5 (0x20U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00200000 */
+#define TAMP_SMCR_BKPWDPROT_6 (0x40U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00400000 */
+#define TAMP_SMCR_BKPWDPROT_7 (0x80U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00800000 */
+#define TAMP_SMCR_TAMPDPROT_Pos (31U)
+#define TAMP_SMCR_TAMPDPROT_Msk (0x1U << TAMP_SMCR_TAMPDPROT_Pos) /*!< 0x80000000 */
+#define TAMP_SMCR_TAMPDPROT TAMP_SMCR_TAMPDPROT_Msk
+
+/******************** Bits definition for TAMP_IER register ***************/
+#define TAMP_IER_TAMPIE_Pos (0U)
+#define TAMP_IER_TAMPIE_Msk (0x7U << TAMP_IER_TAMPIE_Pos) /*!< 0x000000FF */
+#define TAMP_IER_TAMPIE TAMP_IER_TAMPIE_Msk
+#define TAMP_IER_TAMP1IE_Pos (0U)
+#define TAMP_IER_TAMP1IE_Msk (0x1U << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
+#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
+#define TAMP_IER_TAMP2IE_Pos (1U)
+#define TAMP_IER_TAMP2IE_Msk (0x1U << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
+#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
+#define TAMP_IER_TAMP3IE_Pos (2U)
+#define TAMP_IER_TAMP3IE_Msk (0x1U << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
+#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
+#define TAMP_IER_ITAMPIE_Pos (16U)
+#define TAMP_IER_ITAMPIE_Msk (0x9FU << TAMP_IER_ITAMPIE_Pos) /*!< 0xFFFF0000 */
+#define TAMP_IER_ITAMPIE TAMP_IER_ITAMPIE_Msk
+#define TAMP_IER_ITAMP1IE_Pos (16U)
+#define TAMP_IER_ITAMP1IE_Msk (0x1U << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */
+#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk
+#define TAMP_IER_ITAMP2IE_Pos (17U)
+#define TAMP_IER_ITAMP2IE_Msk (0x1U << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */
+#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk
+#define TAMP_IER_ITAMP3IE_Pos (18U)
+#define TAMP_IER_ITAMP3IE_Msk (0x1U << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
+#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
+#define TAMP_IER_ITAMP4IE_Pos (19U)
+#define TAMP_IER_ITAMP4IE_Msk (0x1U << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
+#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
+#define TAMP_IER_ITAMP5IE_Pos (20U)
+#define TAMP_IER_ITAMP5IE_Msk (0x1U << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
+#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
+#define TAMP_IER_ITAMP8IE_Pos (23U)
+#define TAMP_IER_ITAMP8IE_Msk (0x1U << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */
+#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk
+
+
+/******************** Bits definition for TAMP_SR register ***************/
+#define TAMP_SR_TAMPF_Pos (0U)
+#define TAMP_SR_TAMPF_Msk (0x7U << TAMP_SR_TAMPF_Pos) /*!< 0x000000FF */
+#define TAMP_SR_TAMPF TAMP_SR_TAMPF_Msk
+#define TAMP_SR_TAMP1F_Pos (0U)
+#define TAMP_SR_TAMP1F_Msk (0x1U << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
+#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
+#define TAMP_SR_TAMP2F_Pos (1U)
+#define TAMP_SR_TAMP2F_Msk (0x1U << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
+#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
+#define TAMP_SR_TAMP3F_Pos (2U)
+#define TAMP_SR_TAMP3F_Msk (0x1U << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
+#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
+#define TAMP_SR_ITAMPF_Pos (16U)
+#define TAMP_SR_ITAMPF_Msk (0x9FU << TAMP_SR_ITAMPF_Pos) /*!< 0xFFFF0000 */
+#define TAMP_SR_ITAMPF TAMP_SR_ITAMPF_Msk
+#define TAMP_SR_ITAMP1F_Pos (16U)
+#define TAMP_SR_ITAMP1F_Msk (0x1U << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */
+#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk
+#define TAMP_SR_ITAMP2F_Pos (17U)
+#define TAMP_SR_ITAMP2F_Msk (0x1U << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */
+#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk
+#define TAMP_SR_ITAMP3F_Pos (18U)
+#define TAMP_SR_ITAMP3F_Msk (0x1U << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
+#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
+#define TAMP_SR_ITAMP4F_Pos (19U)
+#define TAMP_SR_ITAMP4F_Msk (0x1U << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
+#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
+#define TAMP_SR_ITAMP5F_Pos (20U)
+#define TAMP_SR_ITAMP5F_Msk (0x1U << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
+#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
+#define TAMP_SR_ITAMP8F_Pos (23U)
+#define TAMP_SR_ITAMP8F_Msk (0x1U << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */
+#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk
+
+
+/******************** Bits definition for TAMP_MISR register ***************/
+#define TAMP_MISR_TAMPMF_Pos (0U)
+#define TAMP_MISR_TAMPMF_Msk (0x7U << TAMP_MISR_TAMPMF_Pos) /*!< 0x000000FF */
+#define TAMP_MISR_TAMPMF TAMP_MISR_TAMPMF_Msk
+#define TAMP_MISR_TAMP1MF_Pos (0U)
+#define TAMP_MISR_TAMP1MF_Msk (0x1U << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
+#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
+#define TAMP_MISR_TAMP2MF_Pos (1U)
+#define TAMP_MISR_TAMP2MF_Msk (0x1U << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
+#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
+#define TAMP_MISR_TAMP3MF_Pos (2U)
+#define TAMP_MISR_TAMP3MF_Msk (0x1U << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
+#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
+#define TAMP_MISR_ITAMPMF_Pos (16U)
+#define TAMP_MISR_ITAMPMF_Msk (0x9FU << TAMP_MISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
+#define TAMP_MISR_ITAMPMF TAMP_MISR_ITAMPMF_Msk
+#define TAMP_MISR_ITAMP1MF_Pos (16U)
+#define TAMP_MISR_ITAMP1MF_Msk (0x1U << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */
+#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk
+#define TAMP_MISR_ITAMP2MF_Pos (17U)
+#define TAMP_MISR_ITAMP2MF_Msk (0x1U << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */
+#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk
+#define TAMP_MISR_ITAMP3MF_Pos (18U)
+#define TAMP_MISR_ITAMP3MF_Msk (0x1U << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
+#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
+#define TAMP_MISR_ITAMP4MF_Pos (19U)
+#define TAMP_MISR_ITAMP4MF_Msk (0x1U << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
+#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
+#define TAMP_MISR_ITAMP5MF_Pos (20U)
+#define TAMP_MISR_ITAMP5MF_Msk (0x1U << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
+#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
+#define TAMP_MISR_ITAMP8MF_Pos (23U)
+#define TAMP_MISR_ITAMP8MF_Msk (0x1U << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */
+#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk
+
+
+/******************** Bits definition for TAMP_SMISR register ***************/
+#define TAMP_SMISR_TAMPMF_Pos (0U)
+#define TAMP_SMISR_TAMPMF_Msk (0x7U << TAMP_SMISR_TAMPMF_Pos) /*!< 0x000000FF */
+#define TAMP_SMISR_TAMPMF TAMP_SMISR_TAMPMF_Msk
+#define TAMP_SMISR_TAMP1MF_Pos (0U)
+#define TAMP_SMISR_TAMP1MF_Msk (0x1U << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */
+#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk
+#define TAMP_SMISR_TAMP2MF_Pos (1U)
+#define TAMP_SMISR_TAMP2MF_Msk (0x1U << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */
+#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk
+#define TAMP_SMISR_TAMP3MF_Pos (2U)
+#define TAMP_SMISR_TAMP3MF_Msk (0x1U << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */
+#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk
+#define TAMP_SMISR_ITAMPMF_Pos (16U)
+#define TAMP_SMISR_ITAMPMF_Msk (0x9FU << TAMP_SMISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
+#define TAMP_SMISR_ITAMPMF TAMP_SMISR_ITAMPMF_Msk
+#define TAMP_SMISR_ITAMP1MF_Pos (16U)
+#define TAMP_SMISR_ITAMP1MF_Msk (0x1U << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */
+#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk
+#define TAMP_SMISR_ITAMP2MF_Pos (17U)
+#define TAMP_SMISR_ITAMP2MF_Msk (0x1U << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */
+#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk
+#define TAMP_SMISR_ITAMP3MF_Pos (18U)
+#define TAMP_SMISR_ITAMP3MF_Msk (0x1U << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */
+#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk
+#define TAMP_SMISR_ITAMP4MF_Pos (19U)
+#define TAMP_SMISR_ITAMP4MF_Msk (0x1U << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */
+#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk
+#define TAMP_SMISR_ITAMP5MF_Pos (20U)
+#define TAMP_SMISR_ITAMP5MF_Msk (0x1U << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */
+#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk
+#define TAMP_SMISR_ITAMP8MF_Pos (23U)
+#define TAMP_SMISR_ITAMP8MF_Msk (0x1U << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */
+#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk
+
+
+/******************** Bits definition for TAMP_SCR register ***************/
+#define TAMP_SCR_CTAMPF_Pos (0U)
+#define TAMP_SCR_CTAMPF_Msk (0x7U << TAMP_SCR_CTAMPF_Pos) /*!< 0x000000FF */
+#define TAMP_SCR_CTAMPF TAMP_SCR_CTAMPF_Msk
+#define TAMP_SCR_CTAMP1F_Pos (0U)
+#define TAMP_SCR_CTAMP1F_Msk (0x1U << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
+#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
+#define TAMP_SCR_CTAMP2F_Pos (1U)
+#define TAMP_SCR_CTAMP2F_Msk (0x1U << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
+#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
+#define TAMP_SCR_CTAMP3F_Pos (2U)
+#define TAMP_SCR_CTAMP3F_Msk (0x1U << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
+#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
+#define TAMP_SCR_CITAMPF_Pos (16U)
+#define TAMP_SCR_CITAMPF_Msk (0x9FU << TAMP_SCR_CITAMPF_Pos) /*!< 0xFFFF0000 */
+#define TAMP_SCR_CITAMPF TAMP_SCR_CITAMPF_Msk
+#define TAMP_SCR_CITAMP1F_Pos (16U)
+#define TAMP_SCR_CITAMP1F_Msk (0x1U << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */
+#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk
+#define TAMP_SCR_CITAMP2F_Pos (17U)
+#define TAMP_SCR_CITAMP2F_Msk (0x1U << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */
+#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk
+#define TAMP_SCR_CITAMP3F_Pos (18U)
+#define TAMP_SCR_CITAMP3F_Msk (0x1U << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
+#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
+#define TAMP_SCR_CITAMP4F_Pos (19U)
+#define TAMP_SCR_CITAMP4F_Msk (0x1U << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
+#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
+#define TAMP_SCR_CITAMP5F_Pos (20U)
+#define TAMP_SCR_CITAMP5F_Msk (0x1U << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
+#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
+#define TAMP_SCR_CITAMP8F_Pos (23U)
+#define TAMP_SCR_CITAMP8F_Msk (0x1U << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */
+#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
+
+
+/******************** Bits definition for TAMP_OR register (TAMP_CFGR) ****************/
+#define TAMP_CFGR_OUT3_RMP_Pos (0U)
+#define TAMP_CFGR_OUT3_RMP_Msk (0x1U << TAMP_CFGR_OUT3_RMP_Pos) /*!< 0x00000001 */
+#define TAMP_CFGR_OUT3_RMP TAMP_CFGR_OUT3_RMP_Msk
+
+
+/******************** Bits definition for TAMP_COUNTR register ****************/
+#define TAMP_COUNTR_COUNT_Pos (0U)
+#define TAMP_COUNTR_COUNT_Msk (0xFFFFFFFFU << TAMP_COUNTR_COUNT_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_COUNTR_COUNT TAMP_COUNTR_COUNT_Msk
+
+
+/******************** Bits definition for TAMP_BKPxR register ****************/
+#define TAMP_BKP0R_Pos (0U)
+#define TAMP_BKP0R_Msk (0xFFFFFFFFU << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP0R TAMP_BKP0R_Msk
+#define TAMP_BKP1R_Pos (0U)
+#define TAMP_BKP1R_Msk (0xFFFFFFFFU << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP1R TAMP_BKP1R_Msk
+#define TAMP_BKP2R_Pos (0U)
+#define TAMP_BKP2R_Msk (0xFFFFFFFFU << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP2R TAMP_BKP2R_Msk
+#define TAMP_BKP3R_Pos (0U)
+#define TAMP_BKP3R_Msk (0xFFFFFFFFU << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP3R TAMP_BKP3R_Msk
+#define TAMP_BKP4R_Pos (0U)
+#define TAMP_BKP4R_Msk (0xFFFFFFFFU << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP4R TAMP_BKP4R_Msk
+#define TAMP_BKP5R_Pos (0U)
+#define TAMP_BKP5R_Msk (0xFFFFFFFFU << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP5R TAMP_BKP5R_Msk
+#define TAMP_BKP6R_Pos (0U)
+#define TAMP_BKP6R_Msk (0xFFFFFFFFU << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP6R TAMP_BKP6R_Msk
+#define TAMP_BKP7R_Pos (0U)
+#define TAMP_BKP7R_Msk (0xFFFFFFFFU << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP7R TAMP_BKP7R_Msk
+#define TAMP_BKP8R_Pos (0U)
+#define TAMP_BKP8R_Msk (0xFFFFFFFFU << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP8R TAMP_BKP8R_Msk
+#define TAMP_BKP9R_Pos (0U)
+#define TAMP_BKP9R_Msk (0xFFFFFFFFU << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP9R TAMP_BKP9R_Msk
+#define TAMP_BKP10R_Pos (0U)
+#define TAMP_BKP10R_Msk (0xFFFFFFFFU << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP10R TAMP_BKP10R_Msk
+#define TAMP_BKP11R_Pos (0U)
+#define TAMP_BKP11R_Msk (0xFFFFFFFFU << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP11R TAMP_BKP11R_Msk
+#define TAMP_BKP12R_Pos (0U)
+#define TAMP_BKP12R_Msk (0xFFFFFFFFU << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP12R TAMP_BKP12R_Msk
+#define TAMP_BKP13R_Pos (0U)
+#define TAMP_BKP13R_Msk (0xFFFFFFFFU << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP13R TAMP_BKP13R_Msk
+#define TAMP_BKP14R_Pos (0U)
+#define TAMP_BKP14R_Msk (0xFFFFFFFFU << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP14R TAMP_BKP14R_Msk
+#define TAMP_BKP15R_Pos (0U)
+#define TAMP_BKP15R_Msk (0xFFFFFFFFU << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP15R TAMP_BKP15R_Msk
+#define TAMP_BKP16R_Pos (0U)
+#define TAMP_BKP16R_Msk (0xFFFFFFFFU << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP16R TAMP_BKP16R_Msk
+#define TAMP_BKP17R_Pos (0U)
+#define TAMP_BKP17R_Msk (0xFFFFFFFFU << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP17R TAMP_BKP17R_Msk
+#define TAMP_BKP18R_Pos (0U)
+#define TAMP_BKP18R_Msk (0xFFFFFFFFU << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP18R TAMP_BKP18R_Msk
+#define TAMP_BKP19R_Pos (0U)
+#define TAMP_BKP19R_Msk (0xFFFFFFFFU << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP19R TAMP_BKP19R_Msk
+#define TAMP_BKP20R_Pos (0U)
+#define TAMP_BKP20R_Msk (0xFFFFFFFFU << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP20R TAMP_BKP20R_Msk
+#define TAMP_BKP21R_Pos (0U)
+#define TAMP_BKP21R_Msk (0xFFFFFFFFU << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP21R TAMP_BKP21R_Msk
+#define TAMP_BKP22R_Pos (0U)
+#define TAMP_BKP22R_Msk (0xFFFFFFFFU << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP22R TAMP_BKP22R_Msk
+#define TAMP_BKP23R_Pos (0U)
+#define TAMP_BKP23R_Msk (0xFFFFFFFFU << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP23R TAMP_BKP23R_Msk
+#define TAMP_BKP24R_Pos (0U)
+#define TAMP_BKP24R_Msk (0xFFFFFFFFU << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP24R TAMP_BKP24R_Msk
+#define TAMP_BKP25R_Pos (0U)
+#define TAMP_BKP25R_Msk (0xFFFFFFFFU << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP25R TAMP_BKP25R_Msk
+#define TAMP_BKP26R_Pos (0U)
+#define TAMP_BKP26R_Msk (0xFFFFFFFFU << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP26R TAMP_BKP26R_Msk
+#define TAMP_BKP27R_Pos (0U)
+#define TAMP_BKP27R_Msk (0xFFFFFFFFU << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP27R TAMP_BKP27R_Msk
+#define TAMP_BKP28R_Pos (0U)
+#define TAMP_BKP28R_Msk (0xFFFFFFFFU << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP28R TAMP_BKP28R_Msk
+#define TAMP_BKP29R_Pos (0U)
+#define TAMP_BKP29R_Msk (0xFFFFFFFFU << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP29R TAMP_BKP29R_Msk
+#define TAMP_BKP30R_Pos (0U)
+#define TAMP_BKP30R_Msk (0xFFFFFFFFU << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP30R TAMP_BKP30R_Msk
+#define TAMP_BKP31R_Pos (0U)
+#define TAMP_BKP31R_Msk (0xFFFFFFFFU << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_BKP31R TAMP_BKP31R_Msk
+
+
+/******************** Bits definition for TAMP_HWCFGR2 register *************/
+#define TAMP_HWCFGR2_TRUST_ZONE_Pos (8U)
+#define TAMP_HWCFGR2_TRUST_ZONE_Msk (0xFU << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000F00 */
+#define TAMP_HWCFGR2_TRUST_ZONE TAMP_HWCFGR2_TRUST_ZONE_Msk
+#define TAMP_HWCFGR2_TRUST_ZONE_0 (0x1U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000100 */
+#define TAMP_HWCFGR2_TRUST_ZONE_1 (0x2U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000200 */
+#define TAMP_HWCFGR2_TRUST_ZONE_2 (0x4U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000400 */
+#define TAMP_HWCFGR2_TRUST_ZONE_3 (0x8U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000800 */
+
+#define TAMP_HWCFGR2_OPTIONREG_OUT_Pos (0U)
+#define TAMP_HWCFGR2_OPTIONREG_OUT_Msk (0xFFU << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x000000FF */
+#define TAMP_HWCFGR2_OPTIONREG_OUT TAMP_HWCFGR2_OPTIONREG_OUT_Msk
+#define TAMP_HWCFGR2_OPTIONREG_OUT_0 (0x01U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000001 */
+#define TAMP_HWCFGR2_OPTIONREG_OUT_1 (0x02U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000002 */
+#define TAMP_HWCFGR2_OPTIONREG_OUT_2 (0x04U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000004 */
+#define TAMP_HWCFGR2_OPTIONREG_OUT_3 (0x08U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000008 */
+#define TAMP_HWCFGR2_OPTIONREG_OUT_4 (0x10U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000010 */
+#define TAMP_HWCFGR2_OPTIONREG_OUT_5 (0x20U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000020 */
+#define TAMP_HWCFGR2_OPTIONREG_OUT_6 (0x40U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000040 */
+#define TAMP_HWCFGR2_OPTIONREG_OUT_7 (0x80U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000080 */
+
+/******************** Bits definition for TAMP_HWCFGR1 register *************/
+#define TAMP_HWCFGR1_INT_TAMPER_Pos (16U)
+#define TAMP_HWCFGR1_INT_TAMPER_Msk (0xFFFFU << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0xFFFF0000 */
+#define TAMP_HWCFGR1_INT_TAMPER TAMP_HWCFGR1_INT_TAMPER_Msk
+#define TAMP_HWCFGR1_INT_TAMPER_0 (0x0001U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00010000 */
+#define TAMP_HWCFGR1_INT_TAMPER_1 (0x0002U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00020000 */
+#define TAMP_HWCFGR1_INT_TAMPER_2 (0x0004U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00040000 */
+#define TAMP_HWCFGR1_INT_TAMPER_3 (0x0008U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00080000 */
+#define TAMP_HWCFGR1_INT_TAMPER_4 (0x0010U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00100000 */
+#define TAMP_HWCFGR1_INT_TAMPER_5 (0x0020U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00200000 */
+#define TAMP_HWCFGR1_INT_TAMPER_6 (0x0040U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00400000 */
+#define TAMP_HWCFGR1_INT_TAMPER_7 (0x0080U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00800000 */
+#define TAMP_HWCFGR1_INT_TAMPER_8 (0x0100U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x01000000 */
+#define TAMP_HWCFGR1_INT_TAMPER_9 (0x0200U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x02000000 */
+#define TAMP_HWCFGR1_INT_TAMPER_10 (0x0400U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x04000000 */
+#define TAMP_HWCFGR1_INT_TAMPER_11 (0x0800U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x08000000 */
+#define TAMP_HWCFGR1_INT_TAMPER_12 (0x1000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x10000000 */
+#define TAMP_HWCFGR1_INT_TAMPER_13 (0x2000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x20000000 */
+#define TAMP_HWCFGR1_INT_TAMPER_14 (0x4000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x40000000 */
+#define TAMP_HWCFGR1_INT_TAMPER_15 (0x8000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x80000000 */
+
+#define TAMP_HWCFGR1_ACTIVE_TAMPER_Pos (12U)
+#define TAMP_HWCFGR1_ACTIVE_TAMPER_Msk (0xFU << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x0000F000 */
+#define TAMP_HWCFGR1_ACTIVE_TAMPER TAMP_HWCFGR1_ACTIVE_TAMPER_Msk
+#define TAMP_HWCFGR1_ACTIVE_TAMPER_0 (0x1U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00001000 */
+#define TAMP_HWCFGR1_ACTIVE_TAMPER_1 (0x2U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00002000 */
+#define TAMP_HWCFGR1_ACTIVE_TAMPER_2 (0x4U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00004000 */
+#define TAMP_HWCFGR1_ACTIVE_TAMPER_3 (0x8U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00008000 */
+
+#define TAMP_HWCFGR1_TAMPER_Pos (8U)
+#define TAMP_HWCFGR1_TAMPER_Msk (0xFU << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000F00 */
+#define TAMP_HWCFGR1_TAMPER TAMP_HWCFGR1_TAMPER_Msk
+#define TAMP_HWCFGR1_TAMPER_0 (0x1U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000100 */
+#define TAMP_HWCFGR1_TAMPER_1 (0x2U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000200 */
+#define TAMP_HWCFGR1_TAMPER_2 (0x4U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000400 */
+#define TAMP_HWCFGR1_TAMPER_3 (0x8U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000800 */
+
+#define TAMP_HWCFGR1_BACKUP_REGS_Pos (0U)
+#define TAMP_HWCFGR1_BACKUP_REGS_Msk (0xFFU << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x000000FF */
+#define TAMP_HWCFGR1_BACKUP_REGS TAMP_HWCFGR1_BACKUP_REGS_Msk
+#define TAMP_HWCFGR1_BACKUP_REGS_0 (0x01U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000001 */
+#define TAMP_HWCFGR1_BACKUP_REGS_1 (0x02U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000002 */
+#define TAMP_HWCFGR1_BACKUP_REGS_2 (0x04U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000004 */
+#define TAMP_HWCFGR1_BACKUP_REGS_3 (0x08U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000008 */
+#define TAMP_HWCFGR1_BACKUP_REGS_4 (0x10U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000010 */
+#define TAMP_HWCFGR1_BACKUP_REGS_5 (0x20U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000020 */
+#define TAMP_HWCFGR1_BACKUP_REGS_6 (0x40U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000040 */
+#define TAMP_HWCFGR1_BACKUP_REGS_7 (0x80U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000080 */
+
+/******************** Bits definition for TAMP_VERR register ****************/
+#define TAMP_VERR_MAJREV_Pos (4U)
+#define TAMP_VERR_MAJREV_Msk (0xFU << TAMP_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define TAMP_VERR_MAJREV TAMP_VERR_MAJREV_Msk
+#define TAMP_VERR_MAJREV_0 (0x1U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000010 */
+#define TAMP_VERR_MAJREV_1 (0x2U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000020 */
+#define TAMP_VERR_MAJREV_2 (0x4U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000040 */
+#define TAMP_VERR_MAJREV_3 (0x8U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000080 */
+#define TAMP_VERR_MINREV_Pos (0U)
+#define TAMP_VERR_MINREV_Msk (0xFU << TAMP_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define TAMP_VERR_MINREV TAMP_VERR_MINREV_Msk
+#define TAMP_VERR_MINREV_0 (0x1U << TAMP_VERR_MINREV_Pos) /*!< 0x00000001 */
+#define TAMP_VERR_MINREV_1 (0x2U << TAMP_VERR_MINREV_Pos) /*!< 0x00000002 */
+#define TAMP_VERR_MINREV_2 (0x4U << TAMP_VERR_MINREV_Pos) /*!< 0x00000004 */
+#define TAMP_VERR_MINREV_3 (0x8U << TAMP_VERR_MINREV_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for TAMP_IPIDR register ****************/
+#define TAMP_IPIDR_ID_Pos (0U)
+#define TAMP_IPIDR_ID_Msk (0xFFFFFFFFU << TAMP_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_IPIDR_ID TAMP_IPIDR_ID_Msk
+
+/******************** Bits definition for TAMP_SIDR register ****************/
+#define TAMP_SIDR_SID_Pos (0U)
+#define TAMP_SIDR_SID_Msk (0xFFFFFFFFU << TAMP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define TAMP_SIDR_SID TAMP_SIDR_SID_Msk
+
+/******************** Number of backup registers ******************************/
+#define TAMP_BKP_NUMBER_Pos (5U)
+#define TAMP_BKP_NUMBER_Msk (0x1U << TAMP_BKP_NUMBER_Pos) /*!< 0x00000020 */
+#define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk
+
+/******************** Number of tamper registers ******************************/
+#define TAMP_TAMPER_NUMBER_Pos (0U)
+#define TAMP_TAMPER_NUMBER_Msk (0x3U << TAMP_TAMPER_NUMBER_Pos) /*!< 0x00000003 */
+#define TAMP_TAMPER_NUMBER TAMP_TAMPER_NUMBER_Msk
+
+/******************************************************************************/
+/* */
+/* SPDIF-RX Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SPDIF_CR register *******************/
+#define SPDIFRX_CR_SPDIFEN_Pos (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
+#define SPDIFRX_CR_RXDMAEN_Pos (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
+#define SPDIFRX_CR_RXSTEO_Pos (3U)
+#define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
+#define SPDIFRX_CR_DRFMT_Pos (4U)
+#define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
+#define SPDIFRX_CR_PMSK_Pos (6U)
+#define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
+#define SPDIFRX_CR_VMSK_Pos (7U)
+#define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
+#define SPDIFRX_CR_CUMSK_Pos (8U)
+#define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
+#define SPDIFRX_CR_PTMSK_Pos (9U)
+#define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
+#define SPDIFRX_CR_CBDMAEN_Pos (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
+#define SPDIFRX_CR_CHSEL_Pos (11U)
+#define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
+#define SPDIFRX_CR_NBTR_Pos (12U)
+#define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos (14U)
+#define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
+#define SPDIFRX_CR_INSEL_Pos (16U)
+#define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
+
+/******************* Bit definition for SPDIFRX_IMR register *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
+#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
+#define SPDIFRX_IMR_PERRIE_Pos (2U)
+#define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
+#define SPDIFRX_IMR_OVRIE_Pos (3U)
+#define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
+#define SPDIFRX_IMR_SBLKIE_Pos (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
+#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
+#define SPDIFRX_IMR_IFEIE_Pos (6U)
+#define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
+
+/******************* Bit definition for SPDIFRX_SR register *******************/
+#define SPDIFRX_SR_RXNE_Pos (0U)
+#define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
+#define SPDIFRX_SR_CSRNE_Pos (1U)
+#define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
+#define SPDIFRX_SR_PERR_Pos (2U)
+#define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
+#define SPDIFRX_SR_OVR_Pos (3U)
+#define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
+#define SPDIFRX_SR_SBD_Pos (4U)
+#define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
+#define SPDIFRX_SR_SYNCD_Pos (5U)
+#define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
+#define SPDIFRX_SR_FERR_Pos (6U)
+#define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
+#define SPDIFRX_SR_SERR_Pos (7U)
+#define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
+#define SPDIFRX_SR_TERR_Pos (8U)
+#define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
+#define SPDIFRX_SR_WIDTH5_Pos (16U)
+#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
+
+/******************* Bit definition for SPDIFRX_IFCR register *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
+#define SPDIFRX_IFCR_OVRCF_Pos (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
+#define SPDIFRX_IFCR_SBDCF_Pos (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
+#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos (0U)
+#define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
+#define SPDIFRX_DR0_PE_Pos (24U)
+#define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
+#define SPDIFRX_DR0_V_Pos (25U)
+#define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
+#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
+#define SPDIFRX_DR0_U_Pos (26U)
+#define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
+#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
+#define SPDIFRX_DR0_C_Pos (27U)
+#define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
+#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
+#define SPDIFRX_DR0_PT_Pos (28U)
+#define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos (8U)
+#define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
+#define SPDIFRX_DR1_PT_Pos (4U)
+#define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
+#define SPDIFRX_DR1_C_Pos (3U)
+#define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
+#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
+#define SPDIFRX_DR1_U_Pos (2U)
+#define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
+#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
+#define SPDIFRX_DR1_V_Pos (1U)
+#define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
+#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
+#define SPDIFRX_DR1_PE_Pos (0U)
+#define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
+
+/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos (16U)
+#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
+#define SPDIFRX_DR1_DRNL2_Pos (0U)
+#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
+
+/******************* Bit definition for SPDIFRX_CSR register *******************/
+#define SPDIFRX_CSR_USR_Pos (0U)
+#define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
+#define SPDIFRX_CSR_CS_Pos (16U)
+#define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
+#define SPDIFRX_CSR_SOB_Pos (24U)
+#define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
+
+/******************* Bit definition for SPDIFRX_DIR register *******************/
+#define SPDIFRX_DIR_THI_Pos (0U)
+#define SPDIFRX_DIR_THI_Msk (0x1FFFU << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
+#define SPDIFRX_DIR_TLO_Pos (16U)
+#define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
+
+/********************** Bit definition for SPDIFRX_VERR register *****************/
+#define SPDIFRX_VERR_MINREV_Pos (0U)
+#define SPDIFRX_VERR_MINREV_Msk (0xFU << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!< Minor Revision number */
+#define SPDIFRX_VERR_MAJREV_Pos (4U)
+#define SPDIFRX_VERR_MAJREV_Msk (0xFU << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for SPDIFRX_IPIDR register ****************/
+#define SPDIFRX_IPIDR_IPID_Pos (0U)
+#define SPDIFRX_IPIDR_IPID_Msk (0xFFFFFFFFU << SPDIFRX_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define SPDIFRX_IPIDR_IPID SPDIFRX_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for SPDIFRX_SIDR register *****************/
+#define SPDIFRX_SIDR_SID_Pos (0U)
+#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFU << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Serial Audio Interface */
+/* */
+/******************************************************************************/
+/******************** Bit definition for SAI_GCR register *******************/
+#define SAI_GCR_SYNCIN_Pos (0U)
+#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
+#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos (4U)
+#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
+
+/******************* Bit definition for SAI_xCR1 register *******************/
+#define SAI_xCR1_MODE_Pos (0U)
+#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
+#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos (2U)
+#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
+#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos (5U)
+#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
+#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
+#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos (8U)
+#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
+#define SAI_xCR1_CKSTR_Pos (9U)
+#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
+
+#define SAI_xCR1_SYNCEN_Pos (10U)
+#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos (12U)
+#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
+#define SAI_xCR1_OUTDRIV_Pos (13U)
+#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
+#define SAI_xCR1_SAIEN_Pos (16U)
+#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
+#define SAI_xCR1_DMAEN_Pos (17U)
+#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
+#define SAI_xCR1_NODIV_Pos (19U)
+#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
+
+#define SAI_xCR1_MCKDIV_Pos (20U)
+#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
+#define SAI_xCR1_MCKDIV_0 (0x01U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1 (0x02U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2 (0x04U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3 (0x08U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
+#define SAI_xCR1_MCKDIV_4 (0x10U << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
+#define SAI_xCR1_MCKDIV_5 (0x20U << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
+
+#define SAI_xCR1_MCKEN_Pos (27U)
+#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
+
+#define SAI_xCR1_OSR_Pos (26U)
+#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
+#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
+
+/* Legacy define */
+#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
+
+/******************* Bit definition for SAI_xCR2 register *******************/
+#define SAI_xCR2_FTH_Pos (0U)
+#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
+#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos (3U)
+#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
+#define SAI_xCR2_TRIS_Pos (4U)
+#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos (5U)
+#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
+#define SAI_xCR2_MUTEVAL_Pos (6U)
+#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
+
+#define SAI_xCR2_MUTECNT_Pos (7U)
+#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos (13U)
+#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
+
+#define SAI_xCR2_COMP_Pos (14U)
+#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for SAI_xFRCR register *******************/
+#define SAI_xFRCR_FRL_Pos (0U)
+#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
+#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos (8U)
+#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
+#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos (16U)
+#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos (17U)
+#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
+#define SAI_xFRCR_FSOFF_Pos (18U)
+#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
+
+/* Legacy define */
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
+
+/****************** Bit definition for SAI_xSLOTR register *******************/
+#define SAI_xSLOTR_FBOFF_Pos (0U)
+#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
+#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
+#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos (8U)
+#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
+#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos (16U)
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
+
+/******************* Bit definition for SAI_xIMR register *******************/
+#define SAI_xIMR_OVRUDRIE_Pos (0U)
+#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
+#define SAI_xIMR_MUTEDETIE_Pos (1U)
+#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
+#define SAI_xIMR_WCKCFGIE_Pos (2U)
+#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
+#define SAI_xIMR_FREQIE_Pos (3U)
+#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
+#define SAI_xIMR_CNRDYIE_Pos (4U)
+#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
+#define SAI_xIMR_AFSDETIE_Pos (5U)
+#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
+#define SAI_xIMR_LFSDETIE_Pos (6U)
+#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
+
+/******************** Bit definition for SAI_xSR register *******************/
+#define SAI_xSR_OVRUDR_Pos (0U)
+#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
+#define SAI_xSR_MUTEDET_Pos (1U)
+#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
+#define SAI_xSR_WCKCFG_Pos (2U)
+#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
+#define SAI_xSR_FREQ_Pos (3U)
+#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
+#define SAI_xSR_CNRDY_Pos (4U)
+#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
+#define SAI_xSR_AFSDET_Pos (5U)
+#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
+#define SAI_xSR_LFSDET_Pos (6U)
+#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
+
+#define SAI_xSR_FLVL_Pos (16U)
+#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
+#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
+
+/****************** Bit definition for SAI_xCLRFR register ******************/
+#define SAI_xCLRFR_COVRUDR_Pos (0U)
+#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
+#define SAI_xCLRFR_CFREQ_Pos (3U)
+#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
+#define SAI_xCLRFR_CCNRDY_Pos (4U)
+#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
+#define SAI_xCLRFR_CAFSDET_Pos (5U)
+#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
+#define SAI_xCLRFR_CLFSDET_Pos (6U)
+#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
+
+/****************** Bit definition for SAI_xDR register *********************/
+#define SAI_xDR_DATA_Pos (0U)
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk
+
+/******************* Bit definition for SAI_PDMCR register ******************/
+#define SAI_PDMCR_PDMEN_Pos (0U)
+#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
+
+#define SAI_PDMCR_MICNBR_Pos (4U)
+#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
+#define SAI_PDMCR_MICNBR_0 (0x1U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1 (0x2U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos (8U)
+#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
+#define SAI_PDMCR_CKEN2_Pos (9U)
+#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
+#define SAI_PDMCR_CKEN3_Pos (10U)
+#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
+#define SAI_PDMCR_CKEN4_Pos (11U)
+#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
+
+/****************** Bit definition for SAI_PDMDLY register ******************/
+#define SAI_PDMDLY_DLYM1L_Pos (0U)
+#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0 (0x1U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1 (0x2U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2 (0x4U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos (4U)
+#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0 (0x1U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1 (0x2U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2 (0x4U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos (8U)
+#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0 (0x1U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1 (0x2U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2 (0x4U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos (12U)
+#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
+#define SAI_PDMDLY_DLYM2R_0 (0x1U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1 (0x2U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2 (0x4U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos (16U)
+#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3L_0 (0x1U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1 (0x2U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2 (0x4U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos (20U)
+#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3R_0 (0x1U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1 (0x2U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2 (0x4U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos (24U)
+#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4L_0 (0x1U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1 (0x2U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2 (0x4U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos (28U)
+#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4R_0 (0x1U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1 (0x2U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2 (0x4U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
+
+/********************** Bit definition for SAI_HWCFGR register ***************/
+#define SAI_HWCFGR_FIFO_SIZE_Pos (0U)
+#define SAI_HWCFGR_FIFO_SIZE_Msk (0xFFU << SAI_HWCFGR_FIFO_SIZE_Pos) /*!< 0x000000FF */
+#define SAI_HWCFGR_FIFO_SIZE SAI_HWCFGR_FIFO_SIZE_Msk /*!< FIFO size for SAIA and SAIB */
+#define SAI_HWCFGR_SPDIF_PDM_Pos (8U)
+#define SAI_HWCFGR_SPDIF_PDM_Msk (0xFU << SAI_HWCFGR_SPDIF_PDM_Pos) /*!< 0x00000F00 */
+#define SAI_HWCFGR_SPDIF_PDM SAI_HWCFGR_SPDIF_PDM_Msk /*!< Support of SPDIF-OUT and PDM interfaces */
+#define SAI_HWCFGR_OPTION_REGOUT_Pos (12U)
+#define SAI_HWCFGR_OPTION_REGOUT_Msk (0xFFU << SAI_HWCFGR_OPTION_REGOUT_Pos) /*!< 0x000FF000 */
+#define SAI_HWCFGR_OPTION_REGOUT SAI_HWCFGR_OPTION_REGOUT_Msk /*!< Support of SAI_IOR register */
+
+/********************** Bit definition for SAI_VERR register *****************/
+#define SAI_VERR_MINREV_Pos (0U)
+#define SAI_VERR_MINREV_Msk (0xFU << SAI_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define SAI_VERR_MINREV SAI_VERR_MINREV_Msk /*!< Minor Revision number */
+#define SAI_VERR_MAJREV_Pos (4U)
+#define SAI_VERR_MAJREV_Msk (0xFU << SAI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define SAI_VERR_MAJREV SAI_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for SAI_IPIDR register ****************/
+#define SAI_IPIDR_IPID_Pos (0U)
+#define SAI_IPIDR_IPID_Msk (0xFFFFFFFFU << SAI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define SAI_IPIDR_IPID SAI_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for SAI_SIDR register *****************/
+#define SAI_SIDR_SID_Pos (0U)
+#define SAI_SIDR_SID_Msk (0xFFFFFFFFU << SAI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define SAI_SIDR_SID SAI_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* LCD Controller (LCD) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CR register *********************/
+#define LCD_CR_LCDEN_Pos (0U)
+#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
+#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos (1U)
+#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
+#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos (2U)
+#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
+#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
+#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
+#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos (5U)
+#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
+#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
+#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos (7U)
+#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
+#define LCD_CR_BUFEN_Pos (8U)
+#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
+#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable */
+/******************* Bit definition for LCD_FCR register ********************/
+#define LCD_FCR_HD_Pos (0U)
+#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
+#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos (1U)
+#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
+#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos (3U)
+#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
+#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos (4U)
+#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
+#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
+#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos (7U)
+#define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
+#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos (10U)
+#define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
+#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
+#define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
+#define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos (13U)
+#define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos (16U)
+#define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
+#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos (18U)
+#define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
+#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos (22U)
+#define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
+#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
+
+/******************* Bit definition for LCD_SR register *********************/
+#define LCD_SR_ENS_Pos (0U)
+#define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
+#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos (1U)
+#define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
+#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos (2U)
+#define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
+#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos (3U)
+#define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
+#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos (4U)
+#define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
+#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos (5U)
+#define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
+#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
+
+/******************* Bit definition for LCD_CLR register ********************/
+#define LCD_CLR_SOFC_Pos (1U)
+#define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
+#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos (3U)
+#define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
+#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
+
+/******************* Bit definition for LCD_RAM register ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos (0U)
+#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
+
+/******************************************************************************/
+/* */
+/* SDMMC Interface */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SDMMC_POWER register ******************/
+#define SDMMC_POWER_PWRCTRL_Pos (0U)
+#define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos (2U)
+#define SDMMC_POWER_VSWITCH_Msk (0x1U << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk (0x1U << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos (4U)
+#define SDMMC_POWER_DIRPOL_Msk (0x1U << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
+
+/****************** Bit definition for SDMMC_CLKCR register ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
+#define SDMMC_CLKCR_PWRSAV_Pos (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
+#define SDMMC_CLKCR_DDR_Pos (18U)
+#define SDMMC_CLKCR_DDR_Msk (0x1U << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
+#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk (0x1U << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
+#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk (0x3U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0 (0x1U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1 (0x2U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
+
+/******************* Bit definition for SDMMC_ARG register *******************/
+#define SDMMC_ARG_CMDARG_Pos (0U)
+#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
+
+/******************* Bit definition for SDMMC_CMD register *******************/
+#define SDMMC_CMD_CMDINDEX_Pos (0U)
+#define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
+#define SDMMC_CMD_CMDTRANS_Pos (6U)
+#define SDMMC_CMD_CMDTRANS_Msk (0x1U << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
+#define SDMMC_CMD_CMDSTOP_Pos (7U)
+#define SDMMC_CMD_CMDSTOP_Msk (0x1U << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
+
+#define SDMMC_CMD_WAITRESP_Pos (8U)
+#define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos (10U)
+#define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
+#define SDMMC_CMD_WAITPEND_Pos (11U)
+#define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos (12U)
+#define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
+#define SDMMC_CMD_DTHOLD_Pos (13U)
+#define SDMMC_CMD_DTHOLD_Msk (0x1U << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
+#define SDMMC_CMD_BOOTMODE_Pos (14U)
+#define SDMMC_CMD_BOOTMODE_Msk (0x1U << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
+#define SDMMC_CMD_BOOTEN_Pos (15U)
+#define SDMMC_CMD_BOOTEN_Msk (0x1U << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
+#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk (0x1U << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
+
+/***************** Bit definition for SDMMC_RESPCMD register *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
+
+/****************** Bit definition for SDMMC_RESP0 register ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
+#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP1 register ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP2 register ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP3 register ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_RESP4 register ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
+
+/****************** Bit definition for SDMMC_DTIMER register *****************/
+#define SDMMC_DTIMER_DATATIME_Pos (0U)
+#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
+
+/****************** Bit definition for SDMMC_DLEN register *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
+
+/****************** Bit definition for SDMMC_DCTRL register ******************/
+#define SDMMC_DCTRL_DTEN_Pos (0U)
+#define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
+#define SDMMC_DCTRL_DTDIR_Pos (1U)
+#define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos (2U)
+#define SDMMC_DCTRL_DTMODE_Msk (0x3U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0 (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0004 */
+#define SDMMC_DCTRL_DTMODE_1 (0x2U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos (8U)
+#define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
+#define SDMMC_DCTRL_RWSTOP_Pos (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
+#define SDMMC_DCTRL_RWMOD_Pos (10U)
+#define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
+#define SDMMC_DCTRL_SDIOEN_Pos (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
+#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1U << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos (13U)
+#define SDMMC_DCTRL_FIFORST_Msk (0x1U << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
+
+/****************** Bit definition for SDMMC_DCOUNT register *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
+
+/****************** Bit definition for SDMMC_STA register ********************/
+#define SDMMC_STA_CCRCFAIL_Pos (0U)
+#define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
+#define SDMMC_STA_DCRCFAIL_Pos (1U)
+#define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
+#define SDMMC_STA_CTIMEOUT_Pos (2U)
+#define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
+#define SDMMC_STA_DTIMEOUT_Pos (3U)
+#define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
+#define SDMMC_STA_TXUNDERR_Pos (4U)
+#define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
+#define SDMMC_STA_RXOVERR_Pos (5U)
+#define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
+#define SDMMC_STA_CMDREND_Pos (6U)
+#define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
+#define SDMMC_STA_CMDSENT_Pos (7U)
+#define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
+#define SDMMC_STA_DATAEND_Pos (8U)
+#define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
+#define SDMMC_STA_DHOLD_Pos (9U)
+#define SDMMC_STA_DHOLD_Msk (0x1U << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
+#define SDMMC_STA_DBCKEND_Pos (10U)
+#define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
+#define SDMMC_STA_DABORT_Pos (11U)
+#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
+#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
+#define SDMMC_STA_CPSMACT_Pos (12U)
+#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
+#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
+#define SDMMC_STA_DPSMACT_Pos (13U)
+#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
+#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
+#define SDMMC_STA_TXFIFOHE_Pos (14U)
+#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos (15U)
+#define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos (16U)
+#define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
+#define SDMMC_STA_RXFIFOF_Pos (17U)
+#define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
+#define SDMMC_STA_TXFIFOE_Pos (18U)
+#define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
+#define SDMMC_STA_RXFIFOE_Pos (19U)
+#define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
+#define SDMMC_STA_BUSYD0_Pos (20U)
+#define SDMMC_STA_BUSYD0_Msk (0x1U << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
+#define SDMMC_STA_BUSYD0END_Pos (21U)
+#define SDMMC_STA_BUSYD0END_Msk (0x1U << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
+#define SDMMC_STA_SDIOIT_Pos (22U)
+#define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
+#define SDMMC_STA_ACKFAIL_Pos (23U)
+#define SDMMC_STA_ACKFAIL_Msk (0x1U << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
+#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk (0x1U << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
+#define SDMMC_STA_VSWEND_Pos (25U)
+#define SDMMC_STA_VSWEND_Msk (0x1U << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
+#define SDMMC_STA_CKSTOP_Pos (26U)
+#define SDMMC_STA_CKSTOP_Msk (0x1U << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
+#define SDMMC_STA_IDMATE_Pos (27U)
+#define SDMMC_STA_IDMATE_Msk (0x1U << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
+#define SDMMC_STA_IDMABTC_Pos (28U)
+#define SDMMC_STA_IDMABTC_Msk (0x1U << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
+
+/******************* Bit definition for SDMMC_ICR register *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos (5U)
+#define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
+#define SDMMC_ICR_CMDRENDC_Pos (6U)
+#define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
+#define SDMMC_ICR_CMDSENTC_Pos (7U)
+#define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
+#define SDMMC_ICR_DATAENDC_Pos (8U)
+#define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
+#define SDMMC_ICR_DHOLDC_Pos (9U)
+#define SDMMC_ICR_DHOLDC_Msk (0x1U << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos (10U)
+#define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
+#define SDMMC_ICR_DABORTC_Pos (11U)
+#define SDMMC_ICR_DABORTC_Msk (0x1U << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
+#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1U << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
+#define SDMMC_ICR_SDIOITC_Pos (22U)
+#define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
+#define SDMMC_ICR_ACKFAILC_Pos (23U)
+#define SDMMC_ICR_ACKFAILC_Msk (0x1U << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1U << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos (25U)
+#define SDMMC_ICR_VSWENDC_Msk (0x1U << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
+#define SDMMC_ICR_CKSTOPC_Pos (26U)
+#define SDMMC_ICR_CKSTOPC_Msk (0x1U << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
+#define SDMMC_ICR_IDMATEC_Pos (27U)
+#define SDMMC_ICR_IDMATEC_Msk (0x1U << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
+#define SDMMC_ICR_IDMABTCC_Pos (28U)
+#define SDMMC_ICR_IDMABTCC_Msk (0x1U << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
+
+/****************** Bit definition for SDMMC_MASK register *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
+#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
+#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
+#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
+#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
+#define SDMMC_MASK_RXOVERRIE_Pos (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
+#define SDMMC_MASK_CMDRENDIE_Pos (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
+#define SDMMC_MASK_DATAENDIE_Pos (8U)
+#define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
+#define SDMMC_MASK_DHOLDIE_Pos (9U)
+#define SDMMC_MASK_DHOLDIE_Msk (0x1U << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
+#define SDMMC_MASK_DBCKENDIE_Pos (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
+#define SDMMC_MASK_DABORTIE_Pos (11U)
+#define SDMMC_MASK_DABORTIE_Msk (0x1U << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
+
+#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
+#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
+
+#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
+#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
+
+#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos (22U)
+#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos (25U)
+#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDMMC_FIFO register *******************/
+#define SDMMC_FIFO_FIFODATA_Pos (0U)
+#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
+
+/****************** Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos (0U)
+#define SDMMC_IDMA_IDMAEN_Msk (0x1U << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk (0x1U << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos (2U)
+#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
+
+/********************** Bit definition for SDMMC_VERR register *****************/
+#define SDMMC_VERR_MINREV_Pos (0U)
+#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< Minor Revision number */
+#define SDMMC_VERR_MAJREV_Pos (4U)
+#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for SDMMC_IPIDR register ****************/
+#define SDMMC_IPIDR_IPID_Pos (0U)
+#define SDMMC_IPIDR_IPID_Msk (0xFFFFFFFFU << SDMMC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_IPIDR_IPID SDMMC_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for SDMMC_SIDR register *****************/
+#define SDMMC_SIDR_SID_Pos (0U)
+#define SDMMC_SIDR_SID_Msk (0xFFFFFFFFU << SDMMC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_SIDR_SID SDMMC_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Delay Block Interface (DLYB) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DLYB_CR register ********************/
+#define DLYB_CR_DEN_Pos (0U)
+#define DLYB_CR_DEN_Msk (0x1U << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
+#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos (1U)
+#define DLYB_CR_SEN_Msk (0x1U << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
+#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
+
+
+/******************* Bit definition for DLYB_CFGR register ********************/
+#define DLYB_CFGR_SEL_Pos (0U)
+#define DLYB_CFGR_SEL_Msk (0xFU << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
+#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0 (0x1U << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1 (0x2U << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2 (0x3U << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3 (0x8U << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos (8U)
+#define DLYB_CFGR_UNIT_Msk (0x7FU << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0 (0x01U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1 (0x02U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2 (0x04U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3 (0x08U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4 (0x10U << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5 (0x20U << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6 (0x40U << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos (16U)
+#define DLYB_CFGR_LNG_Msk (0xFFFU << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0 (0x001U << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1 (0x002U << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2 (0x004U << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3 (0x008U << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4 (0x010U << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5 (0x020U << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6 (0x040U << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7 (0x080U << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8 (0x100U << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9 (0x200U << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10 (0x400U << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11 (0x800U << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos (31U)
+#define DLYB_CFGR_LNGF_Msk (0x1U << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
+
+/********************** Bit definition for DLYB_VERR register *****************/
+#define DLYB_VERR_MINREV_Pos (0U)
+#define DLYB_VERR_MINREV_Msk (0xFU << DLYB_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define DLYB_VERR_MINREV DLYB_VERR_MINREV_Msk /*!< Minor Revision number */
+#define DLYB_VERR_MAJREV_Pos (4U)
+#define DLYB_VERR_MAJREV_Msk (0xFU << DLYB_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define DLYB_VERR_MAJREV DLYB_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for DLYB_IPIDR register ****************/
+#define DLYB_IPIDR_IPID_Pos (0U)
+#define DLYB_IPIDR_IPID_Msk (0xFFFFFFFFU << DLYB_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define DLYB_IPIDR_IPID DLYB_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for DLYB_SIDR register *****************/
+#define DLYB_SIDR_SID_Pos (0U)
+#define DLYB_SIDR_SID_Msk (0xFFFFFFFFU << DLYB_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define DLYB_SIDR_SID DLYB_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_SPE_Pos (0U)
+#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
+#define SPI_CR1_MASRX_Pos (8U)
+#define SPI_CR1_MASRX_Msk (0x1U << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
+#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
+#define SPI_CR1_CSTART_Pos (9U)
+#define SPI_CR1_CSTART_Msk (0x1U << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
+#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
+#define SPI_CR1_CSUSP_Pos (10U)
+#define SPI_CR1_CSUSP_Msk (0x1U << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
+#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
+#define SPI_CR1_HDDIR_Pos (11U)
+#define SPI_CR1_HDDIR_Msk (0x1U << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
+#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
+#define SPI_CR1_SSI_Pos (12U)
+#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
+#define SPI_CR1_CRC33_17_Pos (13U)
+#define SPI_CR1_CRC33_17_Msk (0x1U << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
+#define SPI_CR1_RCRCINI_Pos (14U)
+#define SPI_CR1_RCRCINI_Msk (0x1U << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC calculation initialization pattern control for receiver */
+#define SPI_CR1_TCRCINI_Pos (15U)
+#define SPI_CR1_TCRCINI_Msk (0x1U << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC calculation initialization pattern control for transmitter */
+#define SPI_CR1_IOLOCK_Pos (16U)
+#define SPI_CR1_IOLOCK_Msk (0x1U << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_TSER_Pos (16U)
+#define SPI_CR2_TSER_Msk (0xFFFFU << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
+#define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
+#define SPI_CR2_TSIZE_Pos (0U)
+#define SPI_CR2_TSIZE_Msk (0xFFFFU << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
+
+/******************* Bit definition for SPI_CFG1 register ********************/
+#define SPI_CFG1_DSIZE_Pos (0U)
+#define SPI_CFG1_DSIZE_Msk (0x1FU << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE [4:0]: Number of bits in at single SPI data frame */
+#define SPI_CFG1_DSIZE_0 (0x01U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1 (0x02U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2 (0x04U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3 (0x08U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4 (0x10U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
+
+#define SPI_CFG1_FTHLV_Pos (5U)
+#define SPI_CFG1_FTHLV_Msk (0xFU << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0 (0x1U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1 (0x2U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2 (0x4U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3 (0x8U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
+
+#define SPI_CFG1_UDRCFG_Pos (9U)
+#define SPI_CFG1_UDRCFG_Msk (0x3U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG [1:0]: Behavior of slave transmitter at underrun condition*/
+#define SPI_CFG1_UDRCFG_0 (0x1U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
+#define SPI_CFG1_UDRCFG_1 (0x2U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
+
+
+#define SPI_CFG1_UDRDET_Pos (11U)
+#define SPI_CFG1_UDRDET_Msk (0x3U << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
+#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET [1:0]: Detection of underrun condition at slave transmitter*/
+#define SPI_CFG1_UDRDET_0 (0x1U << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
+#define SPI_CFG1_UDRDET_1 (0x2U << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
+
+#define SPI_CFG1_RXDMAEN_Pos (14U)
+#define SPI_CFG1_RXDMAEN_Msk (0x1U << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
+#define SPI_CFG1_TXDMAEN_Pos (15U)
+#define SPI_CFG1_TXDMAEN_Msk (0x1U << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
+
+#define SPI_CFG1_CRCSIZE_Pos (16U)
+#define SPI_CFG1_CRCSIZE_Msk (0x1FU << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
+#define SPI_CFG1_CRCSIZE_0 (0x01U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1 (0x02U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2 (0x04U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3 (0x08U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4 (0x10U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
+
+#define SPI_CFG1_CRCEN_Pos (22U)
+#define SPI_CFG1_CRCEN_Msk (0x1U << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
+
+#define SPI_CFG1_MBR_Pos (28U)
+#define SPI_CFG1_MBR_Msk (0x7U << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
+#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
+#define SPI_CFG1_MBR_0 (0x1U << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1 (0x2U << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2 (0x4U << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
+
+/******************* Bit definition for SPI_CFG2 register ********************/
+#define SPI_CFG2_MSSI_Pos (0U)
+#define SPI_CFG2_MSSI_Msk (0xFU << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
+#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0 (0x1U << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1 (0x2U << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2 (0x4U << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3 (0x8U << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
+
+#define SPI_CFG2_MIDI_Pos (4U)
+#define SPI_CFG2_MIDI_Msk (0xFU << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0 (0x1U << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1 (0x2U << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2 (0x4U << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3 (0x8U << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
+
+#define SPI_CFG2_IOSWP_Pos (15U)
+#define SPI_CFG2_IOSWP_Msk (0x1U << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
+
+#define SPI_CFG2_COMM_Pos (17U)
+#define SPI_CFG2_COMM_Msk (0x3U << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
+#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0 (0x1U << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1 (0x2U << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
+
+#define SPI_CFG2_SP_Pos (19U)
+#define SPI_CFG2_SP_Msk (0x7U << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
+#define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0 (0x1U << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
+#define SPI_CFG2_SP_1 (0x2U << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
+#define SPI_CFG2_SP_2 (0x4U << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
+
+#define SPI_CFG2_MASTER_Pos (22U)
+#define SPI_CFG2_MASTER_Msk (0x1U << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
+#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
+#define SPI_CFG2_LSBFRST_Pos (23U)
+#define SPI_CFG2_LSBFRST_Msk (0x1U << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
+#define SPI_CFG2_CPHA_Pos (24U)
+#define SPI_CFG2_CPHA_Msk (0x1U << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
+#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
+#define SPI_CFG2_CPOL_Pos (25U)
+#define SPI_CFG2_CPOL_Msk (0x1U << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
+#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
+#define SPI_CFG2_SSM_Pos (26U)
+#define SPI_CFG2_SSM_Msk (0x1U << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
+#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
+
+#define SPI_CFG2_SSIOP_Pos (28U)
+#define SPI_CFG2_SSIOP_Msk (0x1U << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos (29U)
+#define SPI_CFG2_SSOE_Msk (0x1U << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
+#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos (30U)
+#define SPI_CFG2_SSOM_Msk (0x1U << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
+#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
+
+#define SPI_CFG2_AFCNTR_Pos (31U)
+#define SPI_CFG2_AFCNTR_Msk (0x1U << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
+
+/******************* Bit definition for SPI_IER register ********************/
+#define SPI_IER_RXPIE_Pos (0U)
+#define SPI_IER_RXPIE_Msk (0x1U << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
+#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
+#define SPI_IER_TXPIE_Pos (1U)
+#define SPI_IER_TXPIE_Msk (0x1U << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
+#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
+#define SPI_IER_DXPIE_Pos (2U)
+#define SPI_IER_DXPIE_Msk (0x1U << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
+#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
+#define SPI_IER_EOTIE_Pos (3U)
+#define SPI_IER_EOTIE_Msk (0x1U << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
+#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
+#define SPI_IER_TXTFIE_Pos (4U)
+#define SPI_IER_TXTFIE_Msk (0x1U << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
+#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
+#define SPI_IER_UDRIE_Pos (5U)
+#define SPI_IER_UDRIE_Msk (0x1U << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
+#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
+#define SPI_IER_OVRIE_Pos (6U)
+#define SPI_IER_OVRIE_Msk (0x1U << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
+#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
+#define SPI_IER_CRCEIE_Pos (7U)
+#define SPI_IER_CRCEIE_Msk (0x1U << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
+#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRC interrupt enable */
+#define SPI_IER_TIFREIE_Pos (8U)
+#define SPI_IER_TIFREIE_Msk (0x1U << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
+#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos (9U)
+#define SPI_IER_MODFIE_Msk (0x1U << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
+#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
+#define SPI_IER_TSERFIE_Pos (10U)
+#define SPI_IER_TSERFIE_Msk (0x1U << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
+#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
+
+/******************* Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXP_Pos (0U)
+#define SPI_SR_RXP_Msk (0x1U << SPI_SR_RXP_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
+#define SPI_SR_TXP_Pos (1U)
+#define SPI_SR_TXP_Msk (0x1U << SPI_SR_TXP_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
+#define SPI_SR_DXP_Pos (2U)
+#define SPI_SR_DXP_Msk (0x1U << SPI_SR_DXP_Pos) /*!< 0x00000004 */
+#define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
+#define SPI_SR_EOT_Pos (3U)
+#define SPI_SR_EOT_Msk (0x1U << SPI_SR_EOT_Pos) /*!< 0x00000008 */
+#define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
+#define SPI_SR_TXTF_Pos (4U)
+#define SPI_SR_TXTF_Msk (0x1U << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
+#define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
+#define SPI_SR_UDR_Pos (5U)
+#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000020 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
+#define SPI_SR_CRCE_Pos (7U)
+#define SPI_SR_CRCE_Msk (0x1U << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
+#define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
+#define SPI_SR_TIFRE_Pos (8U)
+#define SPI_SR_TIFRE_Msk (0x1U << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
+#define SPI_SR_MODF_Pos (9U)
+#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000200 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
+#define SPI_SR_TSERF_Pos (10U)
+#define SPI_SR_TSERF_Msk (0x1U << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
+#define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Additional number of SPI data to be transacted was reload */
+#define SPI_SR_SUSP_Pos (11U)
+#define SPI_SR_SUSP_Msk (0x1U << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
+#define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
+#define SPI_SR_TXC_Pos (12U)
+#define SPI_SR_TXC_Msk (0x1U << SPI_SR_TXC_Pos) /*!< 0x00001000 */
+#define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos (13U)
+#define SPI_SR_RXPLVL_Msk (0x3U << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
+#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
+#define SPI_SR_RXPLVL_0 (0x1U << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1 (0x2U << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos (15U)
+#define SPI_SR_RXWNE_Msk (0x1U << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
+#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
+#define SPI_SR_CTSIZE_Pos (16U)
+#define SPI_SR_CTSIZE_Msk (0xFFFFU << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
+
+/******************* Bit definition for SPI_IFCR register ********************/
+#define SPI_IFCR_EOTC_Pos (3U)
+#define SPI_IFCR_EOTC_Msk (0x1U << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
+#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
+#define SPI_IFCR_TXTFC_Pos (4U)
+#define SPI_IFCR_TXTFC_Msk (0x1U << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos (5U)
+#define SPI_IFCR_UDRC_Msk (0x1U << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
+#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
+#define SPI_IFCR_OVRC_Pos (6U)
+#define SPI_IFCR_OVRC_Msk (0x1U << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
+#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
+#define SPI_IFCR_CRCEC_Pos (7U)
+#define SPI_IFCR_CRCEC_Msk (0x1U << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
+#define SPI_IFCR_TIFREC_Pos (8U)
+#define SPI_IFCR_TIFREC_Msk (0x1U << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
+#define SPI_IFCR_MODFC_Pos (9U)
+#define SPI_IFCR_MODFC_Msk (0x1U << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
+#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
+#define SPI_IFCR_TSERFC_Pos (10U)
+#define SPI_IFCR_TSERFC_Msk (0x1U << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
+#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
+#define SPI_IFCR_SUSPC_Pos (11U)
+#define SPI_IFCR_SUSPC_Msk (0x1U << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
+
+/******************* Bit definition for SPI_TXDR register ********************/
+#define SPI_TXDR_TXDR_Pos (0U)
+#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFU << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
+
+/******************* Bit definition for SPI_RXDR register ********************/
+#define SPI_RXDR_RXDR_Pos (0U)
+#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFU << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
+
+/******************* Bit definition for SPI_CRCPOLY register ********************/
+#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
+
+/******************* Bit definition for SPI_TXCRC register ********************/
+#define SPI_TXCRC_TXCRC_Pos (0U)
+#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
+
+/******************* Bit definition for SPI_RXCRC register ********************/
+#define SPI_RXCRC_RXCRC_Pos (0U)
+#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
+
+/******************* Bit definition for SPI_UDRDR register ********************/
+#define SPI_UDRDR_UDRDR_Pos (0U)
+#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFU << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x7U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2 (0x4U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_DATLEN_Pos (8U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos (10U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos (11U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
+#define SPI_I2SCFGR_FIXCH_Pos (12U)
+#define SPI_I2SCFGR_FIXCH_Msk (0x1U << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
+#define SPI_I2SCFGR_WSINV_Pos (13U)
+#define SPI_I2SCFGR_WSINV_Msk (0x1U << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
+#define SPI_I2SCFGR_DATFMT_Pos (14U)
+#define SPI_I2SCFGR_DATFMT_Msk (0x1U << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00003000 */
+#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
+#define SPI_I2SCFGR_I2SDIV_Pos (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk (0xFFU << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos (24U)
+#define SPI_I2SCFGR_ODD_Msk (0x1U << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos (25U)
+#define SPI_I2SCFGR_MCKOE_Msk (0x1U << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/********************** Bit definition for SPI_HWCFGR register ***************/
+#define SPI_HWCFGR_TXFCFG_Pos (0U)
+#define SPI_HWCFGR_TXFCFG_Msk (0xFU << SPI_HWCFGR_TXFCFG_Pos) /*!< 0x0000000F */
+#define SPI_HWCFGR_TXFCFG SPI_HWCFGR_TXFCFG_Msk /*!< TxFIFO size */
+#define SPI_HWCFGR_RXFCFG_Pos (4U)
+#define SPI_HWCFGR_RXFCFG_Msk (0xFU << SPI_HWCFGR_RXFCFG_Pos) /*!< 0x0000000F */
+#define SPI_HWCFGR_RXFCFG SPI_HWCFGR_RXFCFG_Msk /*!< RxFIFO size */
+#define SPI_HWCFGR_CRCCFG_Pos (8U)
+#define SPI_HWCFGR_CRCCFG_Msk (0xFU << SPI_HWCFGR_CRCCFG_Pos) /*!< 0x0000000F */
+#define SPI_HWCFGR_CRCCFG SPI_HWCFGR_CRCCFG_Msk /*!< CRC configuration for SPI */
+#define SPI_HWCFGR_I2SCFG_Pos (12U)
+#define SPI_HWCFGR_I2SCFG_Msk (0xFU << SPI_HWCFGR_I2SCFG_Pos) /*!< 0x0000000F */
+#define SPI_HWCFGR_I2SCFG SPI_HWCFGR_I2SCFG_Msk /*!< I2S configuration */
+#define SPI_HWCFGR_DSCFG_Pos (16U)
+#define SPI_HWCFGR_DSCFG_Msk (0xFU << SPI_HWCFGR_DSCFG_Pos) /*!< 0x0000000F */
+#define SPI_HWCFGR_DSCFG SPI_HWCFGR_DSCFG_Msk /*!< SPI data size configuration */
+
+/********************** Bit definition for SPI_VERR register *****************/
+#define SPI_VERR_MINREV_Pos (0U)
+#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< Minor Revision number */
+#define SPI_VERR_MAJREV_Pos (4U)
+#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for SPI_IPIDR register ****************/
+#define SPI_IPIDR_IPID_Pos (0U)
+#define SPI_IPIDR_IPID_Msk (0xFFFFFFFFU << SPI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define SPI_IPIDR_IPID SPI_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for SPI_SIDR register *****************/
+#define SPI_SIDR_SID_Pos (0U)
+#define SPI_SIDR_SID_Msk (0xFFFFFFFFU << SPI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define SPI_SIDR_SID SPI_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* QUADSPI */
+/* */
+/******************************************************************************/
+/***************** Bit definition for QUADSPI_CR register *******************/
+#define QUADSPI_CR_EN_Pos (0U)
+#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos (1U)
+#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos (2U)
+#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos (3U)
+#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos (4U)
+#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos (6U)
+#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos (7U)
+#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos (8U)
+#define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0 (0x1U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1 (0x2U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2 (0x4U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3 (0x8U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
+#define QUADSPI_CR_TEIE_Pos (16U)
+#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos (17U)
+#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos (18U)
+#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos (19U)
+#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos (20U)
+#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos (22U)
+#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos (23U)
+#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos (24U)
+#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
+
+/***************** Bit definition for QUADSPI_DCR register ******************/
+#define QUADSPI_DCR_CKMODE_Pos (0U)
+#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos (8U)
+#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos (16U)
+#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
+
+/****************** Bit definition for QUADSPI_SR register *******************/
+#define QUADSPI_SR_TEF_Pos (0U)
+#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos (1U)
+#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos (2U)
+#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos (3U)
+#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos (4U)
+#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos (5U)
+#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos (8U)
+#define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
+
+/****************** Bit definition for QUADSPI_FCR register ******************/
+#define QUADSPI_FCR_CTEF_Pos (0U)
+#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos (1U)
+#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos (3U)
+#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos (4U)
+#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
+
+/****************** Bit definition for QUADSPI_DLR register ******************/
+#define QUADSPI_DLR_DL_Pos (0U)
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
+
+/****************** Bit definition for QUADSPI_CCR register ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos (8U)
+#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos (10U)
+#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos (12U)
+#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos (14U)
+#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos (16U)
+#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos (18U)
+#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos (24U)
+#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos (26U)
+#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos (28U)
+#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos (30U)
+#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
+#define QUADSPI_CCR_DDRM_Pos (31U)
+#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
+
+/****************** Bit definition for QUADSPI_AR register *******************/
+#define QUADSPI_AR_ADDRESS_Pos (0U)
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
+
+/****************** Bit definition for QUADSPI_ABR register ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/****************** Bit definition for QUADSPI_DR register *******************/
+#define QUADSPI_DR_DATA_Pos (0U)
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
+
+/****************** Bit definition for QUADSPI_PSMKR register ****************/
+#define QUADSPI_PSMKR_MASK_Pos (0U)
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
+
+/****************** Bit definition for QUADSPI_PSMAR register ****************/
+#define QUADSPI_PSMAR_MATCH_Pos (0U)
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
+
+/****************** Bit definition for QUADSPI_PIR register *****************/
+#define QUADSPI_PIR_INTERVAL_Pos (0U)
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
+
+/****************** Bit definition for QUADSPI_LPTR register *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
+
+/********************** Bit definition for QUADSPI_HWCFGR register ***************/
+#define QUADSPI_HWCFGR_FIFOSIZE_Pos (0U)
+#define QUADSPI_HWCFGR_FIFOSIZE_Msk (0xFU << QUADSPI_HWCFGR_FIFOSIZE_Pos) /*!< 0x0000000F */
+#define QUADSPI_HWCFGR_FIFOSIZE QUADSPI_HWCFGR_FIFOSIZE_Msk /*!< size of FIFO in words */
+#define QUADSPI_HWCFGR_IDLENGTH_Pos (4U)
+#define QUADSPI_HWCFGR_IDLENGTH_Msk (0xFU << QUADSPI_HWCFGR_IDLENGTH_Pos) /*!< 0x0000000F */
+#define QUADSPI_HWCFGR_IDLENGTH QUADSPI_HWCFGR_IDLENGTH_Msk /*!< size in bit of the FIFO pointer */
+#define QUADSPI_HWCFGR_PRESCVAL_Pos (8U)
+#define QUADSPI_HWCFGR_PRESCVAL_Msk (0xFU << QUADSPI_HWCFGR_PRESCVAL_Pos) /*!< 0x0000000F */
+#define QUADSPI_HWCFGR_PRESCVAL QUADSPI_HWCFGR_PRESCVAL_Msk /*!< reset value of the prescaler */
+#define QUADSPI_HWCFGR_IDLENGTH_Pos (4U)
+#define QUADSPI_HWCFGR_IDLENGTH_Msk (0xFU << QUADSPI_HWCFGR_IDLENGTH_Pos) /*!< 0x0000000F */
+#define QUADSPI_HWCFGR_IDLENGTH QUADSPI_HWCFGR_IDLENGTH_Msk /*!< length of the AXI IDs. */
+
+/********************** Bit definition for QUADSPI_VERR register *****************/
+#define QUADSPI_VERR_MINREV_Pos (0U)
+#define QUADSPI_VERR_MINREV_Msk (0xFU << QUADSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define QUADSPI_VERR_MINREV QUADSPI_VERR_MINREV_Msk /*!< Minor Revision number */
+#define QUADSPI_VERR_MAJREV_Pos (4U)
+#define QUADSPI_VERR_MAJREV_Msk (0xFU << QUADSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define QUADSPI_VERR_MAJREV QUADSPI_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for QUADSPI_IPIDR register ****************/
+#define QUADSPI_IPIDR_ID_Pos (0U)
+#define QUADSPI_IPIDR_ID_Msk (0xFFFFFFFFU << QUADSPI_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_IPIDR_ID QUADSPI_IPIDR_ID_Msk /*!< IP Identification */
+
+/********************** Bit definition for QUADSPI_SIDR register *****************/
+#define QUADSPI_SIDR_SID_Pos (0U)
+#define QUADSPI_SIDR_SID_Msk (0xFFFFFFFFU << QUADSPI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_SIDR_SID QUADSPI_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* SYSCFG */
+/* */
+/******************************************************************************/
+/****************** Bit definition for SYSCFG_BOOTR register *****************/
+#define SYSCFG_BOOTR_BOOT0_Pos (0U)
+#define SYSCFG_BOOTR_BOOT0_Msk (0x1U << SYSCFG_BOOTR_BOOT0_Pos) /*!< 0x00000001 */
+#define SYSCFG_BOOTR_BOOT0 SYSCFG_BOOTR_BOOT0_Msk /*!< BOOT0 pin value */
+#define SYSCFG_BOOTR_BOOT1_Pos (1U)
+#define SYSCFG_BOOTR_BOOT1_Msk (0x1U << SYSCFG_BOOTR_BOOT1_Pos) /*!< 0x00000002 */
+#define SYSCFG_BOOTR_BOOT1 SYSCFG_BOOTR_BOOT1_Msk /*!< BOOT1 pin value */
+#define SYSCFG_BOOTR_BOOT2_Pos (2U)
+#define SYSCFG_BOOTR_BOOT2_Msk (0x1U << SYSCFG_BOOTR_BOOT2_Pos) /*!< 0x00000004 */
+#define SYSCFG_BOOTR_BOOT2 SYSCFG_BOOTR_BOOT2_Msk /*!< BOOT2 pin value */
+#define SYSCFG_BOOTR_BOOT0_PD_Pos (4U)
+#define SYSCFG_BOOTR_BOOT0_PD_Msk (0x1U << SYSCFG_BOOTR_BOOT0_PD_Pos) /*!< 0x00000010 */
+#define SYSCFG_BOOTR_BOOT0_PD SYSCFG_BOOTR_BOOT0_PD_Msk /*!< BOOT0 pin pull-down disable */
+#define SYSCFG_BOOTR_BOOT1_PD_Pos (5U)
+#define SYSCFG_BOOTR_BOOT1_PD_Msk (0x1U << SYSCFG_BOOTR_BOOT1_PD_Pos) /*!< 0x00000020 */
+#define SYSCFG_BOOTR_BOOT1_PD SYSCFG_BOOTR_BOOT1_PD_Msk /*!< BOOT1 pin pull-down disable */
+#define SYSCFG_BOOTR_BOOT2_PD_Pos (6U)
+#define SYSCFG_BOOTR_BOOT2_PD_Msk (0x1U << SYSCFG_BOOTR_BOOT2_PD_Pos) /*!< 0x00000040 */
+#define SYSCFG_BOOTR_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD_Msk /*!< BOOT2 pin pull-down disable */
+
+
+/****************** Bit definition for SYSCFG_PMCSETR register ******************/
+#define SYSCFG_PMCSETR_I2C1_FMP_Pos (0U)
+#define SYSCFG_PMCSETR_I2C1_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C1_FMP_Pos) /*!< 0x00000001 */
+#define SYSCFG_PMCSETR_I2C1_FMP SYSCFG_PMCSETR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCSETR_I2C2_FMP_Pos (1U)
+#define SYSCFG_PMCSETR_I2C2_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C2_FMP_Pos) /*!< 0x00000002 */
+#define SYSCFG_PMCSETR_I2C2_FMP SYSCFG_PMCSETR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCSETR_I2C3_FMP_Pos (2U)
+#define SYSCFG_PMCSETR_I2C3_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C3_FMP_Pos) /*!< 0x00000004 */
+#define SYSCFG_PMCSETR_I2C3_FMP SYSCFG_PMCSETR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCSETR_I2C4_FMP_Pos (3U)
+#define SYSCFG_PMCSETR_I2C4_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C4_FMP_Pos) /*!< 0x00000008 */
+#define SYSCFG_PMCSETR_I2C4_FMP SYSCFG_PMCSETR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCSETR_I2C5_FMP_Pos (4U)
+#define SYSCFG_PMCSETR_I2C5_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C5_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCSETR_I2C5_FMP SYSCFG_PMCSETR_I2C5_FMP_Msk /*!< I2C5 Fast mode plus */
+#define SYSCFG_PMCSETR_I2C6_FMP_Pos (5U)
+#define SYSCFG_PMCSETR_I2C6_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C6_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCSETR_I2C6_FMP SYSCFG_PMCSETR_I2C6_FMP_Msk /*!< I2C6 Fast mode plus */
+
+#define SYSCFG_PMCSETR_EN_BOOSTER_Pos (8U)
+#define SYSCFG_PMCSETR_EN_BOOSTER_Msk (0x1U << SYSCFG_PMCSETR_EN_BOOSTER_Pos) /*!< 0x00000100 */
+#define SYSCFG_PMCSETR_EN_BOOSTER SYSCFG_PMCSETR_EN_BOOSTER_Msk /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCSETR_ANASWVDD_Pos (9U)
+#define SYSCFG_PMCSETR_ANASWVDD_Msk (0x1U << SYSCFG_PMCSETR_ANASWVDD_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCSETR_ANASWVDD SYSCFG_PMCSETR_ANASWVDD_Msk /*!< GPIO analog switches control voltage selection */
+
+#define SYSCFG_PMCSETR_ETH_CLK_SEL_Pos (16U)
+#define SYSCFG_PMCSETR_ETH_CLK_SEL_Msk (0x1U << SYSCFG_PMCSETR_ETH_CLK_SEL_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMCSETR_ETH_CLK_SEL SYSCFG_PMCSETR_ETH_CLK_SEL_Msk /*!< Internal clock ETH_CLK1 from RCC is used regardless AFMux */
+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos (17U)
+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk (0x1U << SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos) /*!< 0x00020000 */
+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk /*!< Ethernet 50MHz RMII clock selection */
+#define SYSCFG_PMCSETR_ETH_SELMII_Pos (20U)
+#define SYSCFG_PMCSETR_ETH_SELMII_Msk (0x1U << SYSCFG_PMCSETR_ETH_SELMII_Pos) /*!< 0x00100000 */
+#define SYSCFG_PMCSETR_ETH_SELMII_SEL SYSCFG_PMCSETR_ETH_SELMII_Msk /*!< controls MII or GMII when ETH_SEL[2:0] = 0b000 */
+#define SYSCFG_PMCSETR_ETH_SEL_Pos (21U)
+#define SYSCFG_PMCSETR_ETH_SEL_Msk (0x7U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00E00000 */
+#define SYSCFG_PMCSETR_ETH_SEL SYSCFG_PMCSETR_ETH_SEL_Msk /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCSETR_ETH_SEL_0 (0x1U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00200000 */
+#define SYSCFG_PMCSETR_ETH_SEL_1 (0x2U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00400000 */
+#define SYSCFG_PMCSETR_ETH_SEL_2 (0x4U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMCSETR_ETH_SEL_CONF_Pos (20U)
+#define SYSCFG_PMCSETR_ETH_SEL_CONF_Msk (0xFU << SYSCFG_PMCSETR_ETH_SEL_CONF_Pos) /*!< 0x00F00000 */
+#define SYSCFG_PMCSETR_ETH_SEL_CONF SYSCFG_PMCSETR_ETH_SEL_CONF_Msk /*!< Ethernet PHY Interface Configuration */
+
+#define SYSCFG_PMCSETR_ANA0_SEL_Pos (24U)
+#define SYSCFG_PMCSETR_ANA0_SEL_Msk (0x1U << SYSCFG_PMCSETR_ANA0_SEL_Pos) /*!< 0x01000000 */
+#define SYSCFG_PMCSETR_ANA0_SEL_SEL SYSCFG_PMCSETR_ANA0_SEL_Msk /*!< controls analog connection between ANA0 and PA0 pin */
+#define SYSCFG_PMCSETR_ANA1_SEL_Pos (25U)
+#define SYSCFG_PMCSETR_ANA1_SEL_Msk (0x1U << SYSCFG_PMCSETR_ANA1_SEL_Pos) /*!< 0x02000000 */
+#define SYSCFG_PMCSETR_ANA1_SEL_SEL SYSCFG_PMCSETR_ANA1_SEL_Msk /*!< controls analog connection between ANA1 and PA1 pin */
+
+/****************** Bit definition for SYSCFG_PMCCLRR register ******************/
+#define SYSCFG_PMCCLRR_I2C1_FMP_Pos (0U)
+#define SYSCFG_PMCCLRR_I2C1_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C1_FMP_Pos) /*!< 0x00000001 */
+#define SYSCFG_PMCCLRR_I2C1_FMP SYSCFG_PMCCLRR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCCLRR_I2C2_FMP_Pos (1U)
+#define SYSCFG_PMCCLRR_I2C2_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C2_FMP_Pos) /*!< 0x00000002 */
+#define SYSCFG_PMCCLRR_I2C2_FMP SYSCFG_PMCCLRR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCCLRR_I2C3_FMP_Pos (2U)
+#define SYSCFG_PMCCLRR_I2C3_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C3_FMP_Pos) /*!< 0x00000004 */
+#define SYSCFG_PMCCLRR_I2C3_FMP SYSCFG_PMCCLRR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCCLRR_I2C4_FMP_Pos (3U)
+#define SYSCFG_PMCCLRR_I2C4_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C4_FMP_Pos) /*!< 0x00000008 */
+#define SYSCFG_PMCCLRR_I2C4_FMP SYSCFG_PMCCLRR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCCLRR_I2C5_FMP_Pos (4U)
+#define SYSCFG_PMCCLRR_I2C5_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C5_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCCLRR_I2C5_FMP SYSCFG_PMCCLRR_I2C5_FMP_Msk /*!< I2C5 Fast mode plus */
+#define SYSCFG_PMCCLRR_I2C6_FMP_Pos (5U)
+#define SYSCFG_PMCCLRR_I2C6_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C6_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCCLRR_I2C6_FMP SYSCFG_PMCCLRR_I2C6_FMP_Msk /*!< I2C6 Fast mode plus */
+
+#define SYSCFG_PMCCLRR_EN_BOOSTER_Pos (8U)
+#define SYSCFG_PMCCLRR_EN_BOOSTER_Msk (0x1U << SYSCFG_PMCCLRR_EN_BOOSTER_Pos) /*!< 0x00000100 */
+#define SYSCFG_PMCCLRR_EN_BOOSTER SYSCFG_PMCCLRR_EN_BOOSTER_Msk /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCCLRR_ANASWVDD_Pos (9U)
+#define SYSCFG_PMCCLRR_ANASWVDD_Msk (0x1U << SYSCFG_PMCCLRR_ANASWVDD_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCCLRR_ANASWVDD SYSCFG_PMCCLRR_ANASWVDD_Msk /*!< GPIO analog switches control voltage selection */
+
+#define SYSCFG_PMCCLRR_ETH_CLK_SEL_Pos (16U)
+#define SYSCFG_PMCCLRR_ETH_CLK_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ETH_CLK_SEL_Pos) /*!< 0x00010000 */
+#define SYSCFG_PMCCLRR_ETH_CLK_SEL SYSCFG_PMCCLRR_ETH_CLK_SEL_Msk /*!< Internal clock ETH_CLK1 from RCC is used regardless AFMux */
+#define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U)
+#define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) /*!< 0x00020000 */
+#define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk /*!< Ethernet 50MHz RMII clock selection */
+#define SYSCFG_PMCCLRR_ETH_SELMII_Pos (20U)
+#define SYSCFG_PMCCLRR_ETH_SELMII_Msk (0x1U << SYSCFG_PMCCLRR_ETH_SELMII_Pos) /*!< 0x00100000 */
+#define SYSCFG_PMCCLRR_ETH_SELMII_SEL SYSCFG_PMCCLRR_ETH_SELMII_Msk /*!< controls MII or GMII when ETH_SEL[2:0] = 0b000 */
+#define SYSCFG_PMCCLRR_ETH_SEL_Pos (21U)
+#define SYSCFG_PMCCLRR_ETH_SEL_Msk (0x7U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00E00000 */
+#define SYSCFG_PMCCLRR_ETH_SEL SYSCFG_PMCCLRR_ETH_SEL_Msk /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCCLRR_ETH_SEL_0 (0x1U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00200000 */
+#define SYSCFG_PMCCLRR_ETH_SEL_1 (0x2U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00400000 */
+#define SYSCFG_PMCCLRR_ETH_SEL_2 (0x4U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMCCLRR_ETH_SEL_CONF_Pos (20U)
+#define SYSCFG_PMCCLRR_ETH_SEL_CONF_Msk (0xFU << SYSCFG_PMCCLRR_ETH_SEL_CONF_Pos) /*!< 0x00F00000 */
+#define SYSCFG_PMCCLRR_ETH_SEL_CONF SYSCFG_PMCCLRR_ETH_SEL_CONF_Msk /*!< Ethernet PHY Interface Configuration */
+
+#define SYSCFG_PMCCLRR_ANA0_SEL_Pos (24U)
+#define SYSCFG_PMCCLRR_ANA0_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ANA0_SEL_Pos) /*!< 0x01000000 */
+#define SYSCFG_PMCCLRR_ANA0_SEL_SEL SYSCFG_PMCCLRR_ANA0_SEL_Msk /*!< controls analog connection between ANA0 and PA0 pin */
+#define SYSCFG_PMCCLRR_ANA1_SEL_Pos (25U)
+#define SYSCFG_PMCCLRR_ANA1_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ANA1_SEL_Pos) /*!< 0x02000000 */
+#define SYSCFG_PMCCLRR_ANA1_SEL_SEL SYSCFG_PMCCLRR_ANA1_SEL_Msk /*!< controls analog connection between ANA1 and PA1 pin */
+
+/****************** Bit definition for SYSCFG_IOCTRLSETR register *****************/
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos (0U)
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos (1U)
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos (2U)
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos (3U)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos (4U)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+
+/****************** Bit definition for SYSCFG_IOCTRLCLRR register *****************/
+#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos (0U)
+#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos (1U)
+#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos (2U)
+#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos (3U)
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos (4U)
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
+#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
+
+/****************** Bit definition for SYSCFG_ICNR register ********************/
+#define SYSCFG_ICNR_AXI_M0_Pos (0U)
+#define SYSCFG_ICNR_AXI_M0_Msk (0x1U << SYSCFG_ICNR_AXI_M0_Pos) /*!< 0x00000001 */
+#define SYSCFG_ICNR_AXI_M0 SYSCFG_ICNR_AXI_M0_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M1_Pos (1U)
+#define SYSCFG_ICNR_AXI_M1_Msk (0x1U << SYSCFG_ICNR_AXI_M1_Pos) /*!< 0x00000002 */
+#define SYSCFG_ICNR_AXI_M1 SYSCFG_ICNR_AXI_M1_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M2_Pos (2U)
+#define SYSCFG_ICNR_AXI_M2_Msk (0x1U << SYSCFG_ICNR_AXI_M2_Pos) /*!< 0x00000004 */
+#define SYSCFG_ICNR_AXI_M2 SYSCFG_ICNR_AXI_M2_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M3_Pos (3U)
+#define SYSCFG_ICNR_AXI_M3_Msk (0x1U << SYSCFG_ICNR_AXI_M3_Pos) /*!< 0x00000008 */
+#define SYSCFG_ICNR_AXI_M3 SYSCFG_ICNR_AXI_M3_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M5_Pos (5U)
+#define SYSCFG_ICNR_AXI_M5_Msk (0x1U << SYSCFG_ICNR_AXI_M5_Pos) /*!< 0x00000020 */
+#define SYSCFG_ICNR_AXI_M5 SYSCFG_ICNR_AXI_M5_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M6_Pos (6U)
+#define SYSCFG_ICNR_AXI_M6_Msk (0x1U << SYSCFG_ICNR_AXI_M6_Pos) /*!< 0x00000040 */
+#define SYSCFG_ICNR_AXI_M6 SYSCFG_ICNR_AXI_M6_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M7_Pos (7U)
+#define SYSCFG_ICNR_AXI_M7_Msk (0x1U << SYSCFG_ICNR_AXI_M7_Pos) /*!< 0x00000080 */
+#define SYSCFG_ICNR_AXI_M7 SYSCFG_ICNR_AXI_M7_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M8_Pos (8U)
+#define SYSCFG_ICNR_AXI_M8_Msk (0x1U << SYSCFG_ICNR_AXI_M8_Pos) /*!< 0x00000100 */
+#define SYSCFG_ICNR_AXI_M8 SYSCFG_ICNR_AXI_M8_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M9_Pos (9U)
+#define SYSCFG_ICNR_AXI_M9_Msk (0x1U << SYSCFG_ICNR_AXI_M9_Pos) /*!< 0x00000200 */
+#define SYSCFG_ICNR_AXI_M9 SYSCFG_ICNR_AXI_M9_Msk /*!< controls which slave port is used by the master to access the DDR */
+#define SYSCFG_ICNR_AXI_M10_Pos (10U)
+#define SYSCFG_ICNR_AXI_M10_Msk (0x1U << SYSCFG_ICNR_AXI_M10_Pos) /*!< 0x00000400 */
+#define SYSCFG_ICNR_AXI_M10 SYSCFG_ICNR_AXI_M10_Msk /*!< controls which slave port is used by the master to access the DDR */
+
+/****************** Bit definition for SYSCFG_CMPCR register ********************/
+#define SYSCFG_CMPCR_SW_CTRL_Pos (1U)
+#define SYSCFG_CMPCR_SW_CTRL_Msk (0x1U << SYSCFG_CMPCR_SW_CTRL_Pos) /*!< 0x00000002 */
+#define SYSCFG_CMPCR_SW_CTRL SYSCFG_CMPCR_SW_CTRL_Msk /*!< Compensation Software Control */
+#define SYSCFG_CMPCR_READY_Pos (8U)
+#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!< Compensation cell ready flag */
+#define SYSCFG_CMPCR_RANSRC_Pos (16U)
+#define SYSCFG_CMPCR_RANSRC_Msk (0xFU << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x000F0000 */
+#define SYSCFG_CMPCR_RANSRC SYSCFG_CMPCR_RANSRC_Msk /*!< NMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
+#define SYSCFG_CMPCR_RANSRC_0 (0x1U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00010000 */
+#define SYSCFG_CMPCR_RANSRC_1 (0x2U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00020000 */
+#define SYSCFG_CMPCR_RANSRC_2 (0x4U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00040000 */
+#define SYSCFG_CMPCR_RANSRC_3 (0x8U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00080000 */
+#define SYSCFG_CMPCR_RAPSRC_Pos (20U)
+#define SYSCFG_CMPCR_RAPSRC_Msk (0xFU << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00F00000 */
+#define SYSCFG_CMPCR_RAPSRC SYSCFG_CMPCR_RAPSRC_Msk /*!< PMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
+#define SYSCFG_CMPCR_RAPSRC_0 (0x1U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00100000 */
+#define SYSCFG_CMPCR_RAPSRC_1 (0x2U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00200000 */
+#define SYSCFG_CMPCR_RAPSRC_2 (0x4U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00400000 */
+#define SYSCFG_CMPCR_RAPSRC_3 (0x8U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00800000 */
+#define SYSCFG_CMPCR_ANSRC_Pos (24U)
+#define SYSCFG_CMPCR_ANSRC_Msk (0xFU << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x0F000000 */
+#define SYSCFG_CMPCR_ANSRC SYSCFG_CMPCR_ANSRC_Msk /*!< NMOS I/O Compensation value provided by compensation cell */
+#define SYSCFG_CMPCR_ANSRC_0 (0x1U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x01000000 */
+#define SYSCFG_CMPCR_ANSRC_1 (0x2U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x02000000 */
+#define SYSCFG_CMPCR_ANSRC_2 (0x4U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x04000000 */
+#define SYSCFG_CMPCR_ANSRC_3 (0x8U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x08000000 */
+#define SYSCFG_CMPCR_APSRC_Pos (28U)
+#define SYSCFG_CMPCR_APSRC_Msk (0xFU << SYSCFG_CMPCR_APSRC_Pos) /*!< 0xF0000000 */
+#define SYSCFG_CMPCR_APSRC SYSCFG_CMPCR_APSRC_Msk /*!< PMOS I/O Compensation value provided by compensation cell */
+#define SYSCFG_CMPCR_APSRC_0 (0x1U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x10000000 */
+#define SYSCFG_CMPCR_APSRC_1 (0x2U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x20000000 */
+#define SYSCFG_CMPCR_APSRC_2 (0x4U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x40000000 */
+#define SYSCFG_CMPCR_APSRC_3 (0x8U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for SYSCFG_CMPENSETR register ********************/
+#define SYSCFG_CMPENSETR_MPU_EN_Pos (0U)
+#define SYSCFG_CMPENSETR_MPU_EN_Msk (0x1U << SYSCFG_CMPENSETR_MPU_EN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPENSETR_MPU_EN SYSCFG_CMPENSETR_MPU_EN_Msk /*!< Compensation cell enable */
+#define SYSCFG_CMPENSETR_MCU_EN_Pos (1U)
+#define SYSCFG_CMPENSETR_MCU_EN_Msk (0x1U << SYSCFG_CMPENSETR_MCU_EN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPENSETR_MCU_EN SYSCFG_CMPENSETR_MCU_EN_Msk /*!< Compensation cell enable */
+
+
+/****************** Bit definition for SYSCFG_CMPENCLRR register ********************/
+#define SYSCFG_CMPENCLRR_MPU_EN_Pos (0U)
+#define SYSCFG_CMPENCLRR_MPU_EN_Msk (0x1U << SYSCFG_CMPENCLRR_MPU_EN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPENCLRR_MPU_EN SYSCFG_CMPENCLRR_MPU_EN_Msk /*!< Compensation cell disable */
+#define SYSCFG_CMPENCLRR_MCU_EN_Pos (0U)
+#define SYSCFG_CMPENCLRR_MCU_EN_Msk (0x1U << SYSCFG_CMPENCLRR_MCU_EN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPENCLRR_MCU_EN SYSCFG_CMPENCLRR_MCU_EN_Msk /*!< Compensation cell disable */
+
+/****************** Bit definition for SYSCFG_CBR register ******************/
+#define SYSCFG_CBR_CLL_Pos (0U)
+#define SYSCFG_CBR_CLL_Msk (0x1U << SYSCFG_CBR_CLL_Pos) /*!< 0x00000001 */
+#define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!< Cortex-M4 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CBR_PVDL_Pos (2U)
+#define SYSCFG_CBR_PVDL_Msk (0x1U << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */
+#define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!< PVD lock enable bit */
+
+/********************** Bit definition for SYSCFG_VERR register *****************/
+#define SYSCFG_VERR_MINREV_Pos (0U)
+#define SYSCFG_VERR_MINREV_Msk (0xFU << SYSCFG_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define SYSCFG_VERR_MINREV SYSCFG_VERR_MINREV_Msk /*!< Minor Revision number */
+#define SYSCFG_VERR_MAJREV_Pos (4U)
+#define SYSCFG_VERR_MAJREV_Msk (0xFU << SYSCFG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define SYSCFG_VERR_MAJREV SYSCFG_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for SYSCFG_IPIDR register ****************/
+#define SYSCFG_IPIDR_IPID_Pos (0U)
+#define SYSCFG_IPIDR_IPID_Msk (0xFFFFFFFFU << SYSCFG_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define SYSCFG_IPIDR_IPID SYSCFG_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for SYSCFG_SIDR register *****************/
+#define SYSCFG_SIDR_SID_Pos (0U)
+#define SYSCFG_SIDR_SID_Msk (0xFFFFFFFFU << SYSCFG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define SYSCFG_SIDR_SID SYSCFG_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Temperature Sensor (DTS) */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for DTS_CFGR1 register ******************/
+#define DTS_CFGR1_TS1_EN_Pos (0U)
+#define DTS_CFGR1_TS1_EN_Msk (0x1U << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
+#define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk /*!< DTS1 Enable */
+#define DTS_CFGR1_TS1_START_Pos (4U)
+#define DTS_CFGR1_TS1_START_Msk (0x1U << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
+#define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk /*!< Proceed to a frequency measurement on DTS1 */
+#define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U)
+#define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFU << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
+#define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS1 */
+#define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
+#define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
+#define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
+#define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
+#define DTS_CFGR1_TS1_SMP_TIME_Pos (16U)
+#define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFU << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
+#define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk /*!< Sample time [3:0] for DTS1 */
+#define DTS_CFGR1_TS1_SMP_TIME_0 (0x1U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
+#define DTS_CFGR1_TS1_SMP_TIME_1 (0x2U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
+#define DTS_CFGR1_TS1_SMP_TIME_2 (0x4U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
+#define DTS_CFGR1_TS1_SMP_TIME_3 (0x8U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
+#define DTS_CFGR1_REFCLK_SEL_Pos (20U)
+#define DTS_CFGR1_REFCLK_SEL_Msk (0x1U << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
+#define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selection */
+#define DTS_CFGR1_Q_MEAS_OPT_Pos (21U)
+#define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1U << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
+#define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk /*!< Quick measure option bit */
+#define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U)
+#define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FU << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
+#define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
+
+/****************** Bit definition for DTS_T0VALR1 register ******************/
+#define DTS_T0VALR1_TS1_FMT0_Pos (0U)
+#define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFU << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
+#define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk /*!< Engineering value of the measured frequency at T0 for DTS1 */
+#define DTS_T0VALR1_TS1_T0_Pos (16U)
+#define DTS_T0VALR1_TS1_T0_Msk (0x3U << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
+#define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk /*!< Engineering value of the DTSerature T0 for DTS1 */
+
+/****************** Bit definition for DTS_RAMPVALR register ******************/
+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U)
+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFU << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
+#define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS1 */
+
+/****************** Bit definition for DTS_ITR1 register ******************/
+#define DTS_ITR1_TS1_LITTHD_Pos (0U)
+#define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFU << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
+#define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk /*!< Low interrupt threshold[15:0] for DTS1 */
+#define DTS_ITR1_TS1_HITTHD_Pos (16U)
+#define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFU << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
+#define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk /*!< High interrupt threshold[15:0] for DTS1 */
+
+/****************** Bit definition for DTS_DR register ******************/
+#define DTS_DR_TS1_MFREQ_Pos (0U)
+#define DTS_DR_TS1_MFREQ_Msk (0xFFFFU << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
+#define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk /*!< Measured Frequency[15:0] for DTS1 */
+
+/****************** Bit definition for DTS_SR register ******************/
+#define DTS_SR_TS1_ITEF_Pos (0U)
+#define DTS_SR_TS1_ITEF_Msk (0x1U << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
+#define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk /*!< Interrupt flag for end of measure for DTS1 */
+#define DTS_SR_TS1_ITLF_Pos (1U)
+#define DTS_SR_TS1_ITLF_Msk (0x1U << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
+#define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk /*!< Interrupt flag for low threshold for DTS1 */
+#define DTS_SR_TS1_ITHF_Pos (2U)
+#define DTS_SR_TS1_ITHF_Msk (0x1U << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
+#define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk /*!< Interrupt flag for high threshold for DTS1 */
+#define DTS_SR_TS1_AITEF_Pos (4U)
+#define DTS_SR_TS1_AITEF_Msk (0x1U << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
+#define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk /*!< Asynchronous interrupt flag for end of measure for DTS1 */
+#define DTS_SR_TS1_AITLF_Pos (5U)
+#define DTS_SR_TS1_AITLF_Msk (0x1U << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
+#define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk /*!< Asynchronous interrupt flag for low threshold for DTS1 */
+#define DTS_SR_TS1_AITHF_Pos (6U)
+#define DTS_SR_TS1_AITHF_Msk (0x1U << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
+#define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk /*!< Asynchronous interrupt flag for high threshold for DTS1 */
+#define DTS_SR_TS1_RDY_Pos (15U)
+#define DTS_SR_TS1_RDY_Msk (0x1U << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
+#define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk /*!< DTS1 ready flag */
+
+/****************** Bit definition for DTS_ITENR register ******************/
+#define DTS_ITENR_TS1_ITEEN_Pos (0U)
+#define DTS_ITENR_TS1_ITEEN_Msk (0x1U << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
+#define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk /*!< Enable interrupt flag for end of measure for DTS1 */
+#define DTS_ITENR_TS1_ITLEN_Pos (1U)
+#define DTS_ITENR_TS1_ITLEN_Msk (0x1U << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
+#define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk /*!< Enable interrupt flag for low threshold for DTS1 */
+#define DTS_ITENR_TS1_ITHEN_Pos (2U)
+#define DTS_ITENR_TS1_ITHEN_Msk (0x1U << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
+#define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk /*!< Enable interrupt flag for high threshold for DTS1 */
+#define DTS_ITENR_TS1_AITEEN_Pos (4U)
+#define DTS_ITENR_TS1_AITEEN_Msk (0x1U << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
+#define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
+#define DTS_ITENR_TS1_AITLEN_Pos (5U)
+#define DTS_ITENR_TS1_AITLEN_Msk (0x1U << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
+#define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk /*!< Enable Asynchronous interrupt flag for low threshold for DTS1 */
+#define DTS_ITENR_TS1_AITHEN_Pos (6U)
+#define DTS_ITENR_TS1_AITHEN_Msk (0x1U << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
+#define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
+
+/****************** Bit definition for DTS_ICIFR register ******************/
+#define DTS_ICIFR_TS1_CITEF_Pos (0U)
+#define DTS_ICIFR_TS1_CITEF_Msk (0x1U << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
+#define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk /*!< Clear the IT flag for End Of Measure for DTS1 */
+#define DTS_ICIFR_TS1_CITLF_Pos (1U)
+#define DTS_ICIFR_TS1_CITLF_Msk (0x1U << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
+#define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk /*!< Clear the IT flag for low threshold for DTS1 */
+#define DTS_ICIFR_TS1_CITHF_Pos (2U)
+#define DTS_ICIFR_TS1_CITHF_Msk (0x1U << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
+#define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk /*!< Clear the IT flag for high threshold on DTS1 */
+#define DTS_ICIFR_TS1_CAITEF_Pos (4U)
+#define DTS_ICIFR_TS1_CAITEF_Msk (0x1U << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
+#define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk /*!< Clear the asynchronous IT flag for End Of Measure for DTS1 */
+#define DTS_ICIFR_TS1_CAITLF_Pos (5U)
+#define DTS_ICIFR_TS1_CAITLF_Msk (0x1U << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
+#define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk /*!< Clear the asynchronous IT flag for low threshold for DTS1 */
+#define DTS_ICIFR_TS1_CAITHF_Pos (6U)
+#define DTS_ICIFR_TS1_CAITHF_Msk (0x1U << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
+#define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk /*!< Clear the asynchronous IT flag for high threshold on DTS1 */
+
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC_Pos (0U)
+#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos (2U)
+#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos (8U)
+#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos (9U)
+#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos (10U)
+#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos (11U)
+#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos (12U)
+#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos (13U)
+#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos (14U)
+#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos (16U)
+#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos (18U)
+#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos (20U)
+#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x30007U << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x00001U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x00002U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x00004U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+#define TIM_SMCR_TS_3 (0x10000U << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
+#define TIM_SMCR_TS_4 (0x20000U << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos (5U)
+#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos (7U)
+#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos (8U)
+#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos (16U)
+#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos (17U)
+#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_SBIF_Pos (13U)
+#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */
+#define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */
+
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos (2U)
+#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos (6U)
+#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos (10U)
+#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos (16U)
+#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos (17U)
+#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos (20U)
+#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos (21U)
+#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos (31U)
+#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5_Pos (0U)
+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos (29U)
+#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos (30U)
+#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos (31U)
+#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG_Pos (0U)
+#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos (8U)
+#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos (10U)
+#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos (11U)
+#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos (12U)
+#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos (13U)
+#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos (14U)
+#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos (15U)
+#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos (16U)
+#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos (20U)
+#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos (24U)
+#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos (25U)
+#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
+
+#define TIM_BDTR_BKDSRM_Pos (26U)
+#define TIM_BDTR_BKDSRM_Msk (0x1U << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarmed for Break1 */
+#define TIM_BDTR_BK2DSRM_Pos (27U)
+#define TIM_BDTR_BK2DSRM_Msk (0x1U << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break Disarmed for Break2 */
+
+#define TIM_BDTR_BKBID_Pos (28U)
+#define TIM_BDTR_BKBID_Msk (0x1U << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
+#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectionnal for Break1 */
+#define TIM_BDTR_BK2BID_Pos (29U)
+#define TIM_BDTR_BK2BID_Msk (0x1U << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break Bidirectionnal for Break2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM16_OR register *********************/
+#define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
+#define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
+
+/******************* Bit definition for TIM1_OR register *********************/
+#define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM8_OR register *********************/
+#define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
+#define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE_Pos (2U)
+#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos (3U)
+#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos (4U)
+#define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos (7U)
+#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos (10U)
+#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos (11U)
+#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos (12U)
+#define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos (15U)
+#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
+/******************* Bit definition for TIM1_AF1 register *********************/
+#define TIM1_AF1_BKINE_Pos (0U)
+#define TIM1_AF1_BKINE_Msk (0x1U << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
+#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
+#define TIM1_AF1_BKDF1BK0E_Pos (8U)
+#define TIM1_AF1_BKDF1BK0E_Msk (0x1U << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
+#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
+#define TIM1_AF1_BKINP_Pos (9U)
+#define TIM1_AF1_BKINP_Msk (0x1U << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
+#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
+
+#define TIM1_AF1_ETRSEL_Pos (14U)
+#define TIM1_AF1_ETRSEL_Msk (0xFU << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR SEL) */
+#define TIM1_AF1_ETRSEL_0 (0x1U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1 (0x2U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2 (0x4U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3 (0x8U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
+
+/******************* Bit definition for TIM1_AF2 register *********************/
+#define TIM1_AF2_BK2INE_Pos (0U)
+#define TIM1_AF2_BK2INE_Msk (0x1U << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
+#define TIM1_AF2_BK2DF1BK1E_Pos (8U)
+#define TIM1_AF2_BK2DF1BK1E_Msk (0x1U << TIM1_AF2_BK2DF1BK1E_Pos) /*!< 0x00000100 */
+#define TIM1_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E_Msk /*!<BK2DF1BK1E Break input2 DFSDM Break 1 */
+#define TIM1_AF2_BK2INP_Pos (9U)
+#define TIM1_AF2_BK2INP_Msk (0x1U << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
+
+/******************* Bit definition for TIM1_TISEL register *********************/
+#define TIM1_TISEL_TI1SEL_Pos (0U)
+#define TIM1_TISEL_TI1SEL_Msk (0xFU << TIM1_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM1_TISEL_TI1SEL TIM1_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
+#define TIM1_TISEL_TI1SEL_0 (0x1U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM1_TISEL_TI1SEL_1 (0x2U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM1_TISEL_TI1SEL_2 (0x4U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM1_TISEL_TI1SEL_3 (0x8U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM1_TISEL_TI2SEL_Pos (8U)
+#define TIM1_TISEL_TI2SEL_Msk (0xFU << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM1_TISEL_TI2SEL TIM1_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
+#define TIM1_TISEL_TI2SEL_0 (0x1U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM1_TISEL_TI2SEL_1 (0x2U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM1_TISEL_TI2SEL_2 (0x4U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM1_TISEL_TI2SEL_3 (0x8U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+#define TIM1_TISEL_TI3SEL_Pos (16U)
+#define TIM1_TISEL_TI3SEL_Msk (0xFU << TIM1_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
+#define TIM1_TISEL_TI3SEL TIM1_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
+#define TIM1_TISEL_TI3SEL_0 (0x1U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
+#define TIM1_TISEL_TI3SEL_1 (0x2U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
+#define TIM1_TISEL_TI3SEL_2 (0x4U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
+#define TIM1_TISEL_TI3SEL_3 (0x8U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
+
+#define TIM1_TISEL_TI4SEL_Pos (24U)
+#define TIM1_TISEL_TI4SEL_Msk (0xFU << TIM1_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
+#define TIM1_TISEL_TI4SEL TIM1_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
+#define TIM1_TISEL_TI4SEL_0 (0x1U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
+#define TIM1_TISEL_TI4SEL_1 (0x2U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
+#define TIM1_TISEL_TI4SEL_2 (0x4U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
+#define TIM1_TISEL_TI4SEL_3 (0x8U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
+
+/******************* Bit definition for TIM8_AF1 register *********************/
+#define TIM8_AF1_BKINE_Pos (0U)
+#define TIM8_AF1_BKINE_Msk (0x1U << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
+#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
+#define TIM8_AF1_BKDFBK2E_Pos (8U)
+#define TIM8_AF1_BKDFBK2E_Msk (0x1U << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
+#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
+#define TIM8_AF1_BKINP_Pos (9U)
+#define TIM8_AF1_BKINP_Msk (0x1U << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
+#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
+
+#define TIM8_AF1_ETRSEL_Pos (14U)
+#define TIM8_AF1_ETRSEL_Msk (0xFU << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
+#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETR SEL) */
+#define TIM8_AF1_ETRSEL_0 (0x1U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM8_AF1_ETRSEL_1 (0x2U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM8_AF1_ETRSEL_2 (0x4U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
+#define TIM8_AF1_ETRSEL_3 (0x8U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
+/******************* Bit definition for TIM8_AF2 register *********************/
+#define TIM8_AF2_BK2INE_Pos (0U)
+#define TIM8_AF2_BK2INE_Msk (0x1U << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
+#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
+#define TIM8_AF2_BK2DFBK3E_Pos (8U)
+#define TIM8_AF2_BK2DFBK3E_Msk (0x1U << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
+#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
+#define TIM8_AF2_BK2INP_Pos (9U)
+#define TIM8_AF2_BK2INP_Msk (0x1U << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
+#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
+
+/******************* Bit definition for TIM8_TISEL register *********************/
+#define TIM8_TISEL_TI1SEL_Pos (0U)
+#define TIM8_TISEL_TI1SEL_Msk (0xFU << TIM8_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM8_TISEL_TI1SEL TIM8_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM8 TI1 SEL)*/
+#define TIM8_TISEL_TI1SEL_0 (0x1U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM8_TISEL_TI1SEL_1 (0x2U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM8_TISEL_TI1SEL_2 (0x4U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM8_TISEL_TI1SEL_3 (0x8U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM8_TISEL_TI2SEL_Pos (8U)
+#define TIM8_TISEL_TI2SEL_Msk (0xFU << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM8_TISEL_TI2SEL TIM8_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM8 TI2 SEL)*/
+#define TIM8_TISEL_TI2SEL_0 (0x1U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM8_TISEL_TI2SEL_1 (0x2U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM8_TISEL_TI2SEL_2 (0x4U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM8_TISEL_TI2SEL_3 (0x8U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+#define TIM8_TISEL_TI3SEL_Pos (16U)
+#define TIM8_TISEL_TI3SEL_Msk (0xFU << TIM8_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
+#define TIM8_TISEL_TI3SEL TIM8_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM8 TI3 SEL)*/
+#define TIM8_TISEL_TI3SEL_0 (0x1U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
+#define TIM8_TISEL_TI3SEL_1 (0x2U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
+#define TIM8_TISEL_TI3SEL_2 (0x4U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
+#define TIM8_TISEL_TI3SEL_3 (0x8U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
+
+#define TIM8_TISEL_TI4SEL_Pos (24U)
+#define TIM8_TISEL_TI4SEL_Msk (0xFU << TIM8_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
+#define TIM8_TISEL_TI4SEL TIM8_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM8 TI4 SEL)*/
+#define TIM8_TISEL_TI4SEL_0 (0x1U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
+#define TIM8_TISEL_TI4SEL_1 (0x2U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
+#define TIM8_TISEL_TI4SEL_2 (0x4U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
+#define TIM8_TISEL_TI4SEL_3 (0x8U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
+
+/******************* Bit definition for TIM2_AF1 register *********************/
+#define TIM2_AF1_ETRSEL_Pos (14U)
+#define TIM2_AF1_ETRSEL_Msk (0xFU << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
+#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETR SEL) */
+#define TIM2_AF1_ETRSEL_0 (0x1U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM2_AF1_ETRSEL_1 (0x2U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM2_AF1_ETRSEL_2 (0x4U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
+#define TIM2_AF1_ETRSEL_3 (0x8U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
+
+/******************* Bit definition for TIM2_TISEL register *********************/
+#define TIM2_TISEL_TI1SEL_Pos (0U)
+#define TIM2_TISEL_TI1SEL_Msk (0xFU << TIM2_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM2_TISEL_TI1SEL TIM2_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
+#define TIM2_TISEL_TI1SEL_0 (0x1U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM2_TISEL_TI1SEL_1 (0x2U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM2_TISEL_TI1SEL_2 (0x4U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM2_TISEL_TI1SEL_3 (0x8U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM2_TISEL_TI2SEL_Pos (8U)
+#define TIM2_TISEL_TI2SEL_Msk (0xFU << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM2_TISEL_TI2SEL TIM2_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM2 TI2 SEL)*/
+#define TIM2_TISEL_TI2SEL_0 (0x1U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM2_TISEL_TI2SEL_1 (0x2U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM2_TISEL_TI2SEL_2 (0x4U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM2_TISEL_TI2SEL_3 (0x8U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+#define TIM2_TISEL_TI3SEL_Pos (16U)
+#define TIM2_TISEL_TI3SEL_Msk (0xFU << TIM2_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
+#define TIM2_TISEL_TI3SEL TIM2_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM2 TI3 SEL)*/
+#define TIM2_TISEL_TI3SEL_0 (0x1U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
+#define TIM2_TISEL_TI3SEL_1 (0x2U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
+#define TIM2_TISEL_TI3SEL_2 (0x4U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
+#define TIM2_TISEL_TI3SEL_3 (0x8U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
+
+#define TIM2_TISEL_TI4SEL_Pos (24U)
+#define TIM2_TISEL_TI4SEL_Msk (0xFU << TIM2_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
+#define TIM2_TISEL_TI4SEL TIM2_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM2 TI4 SEL)*/
+#define TIM2_TISEL_TI4SEL_0 (0x1U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
+#define TIM2_TISEL_TI4SEL_1 (0x2U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
+#define TIM2_TISEL_TI4SEL_2 (0x4U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
+#define TIM2_TISEL_TI4SEL_3 (0x8U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
+
+/******************* Bit definition for TIM3_AF1 register *********************/
+#define TIM3_AF1_ETRSEL_Pos (14U)
+#define TIM3_AF1_ETRSEL_Msk (0xFU << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
+#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR SEL) */
+#define TIM3_AF1_ETRSEL_0 (0x1U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM3_AF1_ETRSEL_1 (0x2U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM3_AF1_ETRSEL_2 (0x4U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
+#define TIM3_AF1_ETRSEL_3 (0x8U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
+
+/******************* Bit definition for TIM3_TISEL register *********************/
+#define TIM3_TISEL_TI1SEL_Pos (0U)
+#define TIM3_TISEL_TI1SEL_Msk (0xFU << TIM3_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM3_TISEL_TI1SEL TIM3_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
+#define TIM3_TISEL_TI1SEL_0 (0x1U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM3_TISEL_TI1SEL_1 (0x2U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM3_TISEL_TI1SEL_2 (0x4U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM3_TISEL_TI1SEL_3 (0x8U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM3_TISEL_TI2SEL_Pos (8U)
+#define TIM3_TISEL_TI2SEL_Msk (0xFU << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM3_TISEL_TI2SEL TIM3_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
+#define TIM3_TISEL_TI2SEL_0 (0x1U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM3_TISEL_TI2SEL_1 (0x2U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM3_TISEL_TI2SEL_2 (0x4U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM3_TISEL_TI2SEL_3 (0x8U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+#define TIM3_TISEL_TI3SEL_Pos (16U)
+#define TIM3_TISEL_TI3SEL_Msk (0xFU << TIM3_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
+#define TIM3_TISEL_TI3SEL TIM3_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
+#define TIM3_TISEL_TI3SEL_0 (0x1U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
+#define TIM3_TISEL_TI3SEL_1 (0x2U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
+#define TIM3_TISEL_TI3SEL_2 (0x4U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
+#define TIM3_TISEL_TI3SEL_3 (0x8U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
+
+#define TIM3_TISEL_TI4SEL_Pos (24U)
+#define TIM3_TISEL_TI4SEL_Msk (0xFU << TIM3_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
+#define TIM3_TISEL_TI4SEL TIM3_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
+#define TIM3_TISEL_TI4SEL_0 (0x1U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
+#define TIM3_TISEL_TI4SEL_1 (0x2U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
+#define TIM3_TISEL_TI4SEL_2 (0x4U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
+#define TIM3_TISEL_TI4SEL_3 (0x8U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
+
+/******************* Bit definition for TIM4_AF1 register *********************/
+#define TIM4_AF1_ETRSEL_Pos (14U)
+#define TIM4_AF1_ETRSEL_Msk (0xFU << TIM4_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
+#define TIM4_AF1_ETRSEL TIM4_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM4 ETR SEL) */
+#define TIM4_AF1_ETRSEL_0 (0x1U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM4_AF1_ETRSEL_1 (0x2U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM4_AF1_ETRSEL_2 (0x4U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00010000 */
+#define TIM4_AF1_ETRSEL_3 (0x8U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00020000 */
+
+/******************* Bit definition for TIM4_TISEL register *********************/
+#define TIM4_TISEL_TI1SEL_Pos (0U)
+#define TIM4_TISEL_TI1SEL_Msk (0xFU << TIM4_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM4_TISEL_TI1SEL TIM4_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM4 TI1 SEL)*/
+#define TIM4_TISEL_TI1SEL_0 (0x1U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM4_TISEL_TI1SEL_1 (0x2U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM4_TISEL_TI1SEL_2 (0x4U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM4_TISEL_TI1SEL_3 (0x8U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM4_TISEL_TI2SEL_Pos (8U)
+#define TIM4_TISEL_TI2SEL_Msk (0xFU << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM4_TISEL_TI2SEL TIM4_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM4 TI2 SEL)*/
+#define TIM4_TISEL_TI2SEL_0 (0x1U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM4_TISEL_TI2SEL_1 (0x2U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM4_TISEL_TI2SEL_2 (0x4U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM4_TISEL_TI2SEL_3 (0x8U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+#define TIM4_TISEL_TI3SEL_Pos (16U)
+#define TIM4_TISEL_TI3SEL_Msk (0xFU << TIM4_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
+#define TIM4_TISEL_TI3SEL TIM4_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM4 TI3 SEL)*/
+#define TIM4_TISEL_TI3SEL_0 (0x1U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
+#define TIM4_TISEL_TI3SEL_1 (0x2U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
+#define TIM4_TISEL_TI3SEL_2 (0x4U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
+#define TIM4_TISEL_TI3SEL_3 (0x8U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
+
+#define TIM4_TISEL_TI4SEL_Pos (24U)
+#define TIM4_TISEL_TI4SEL_Msk (0xFU << TIM4_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
+#define TIM4_TISEL_TI4SEL TIM4_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM4 TI4 SEL)*/
+#define TIM4_TISEL_TI4SEL_0 (0x1U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
+#define TIM4_TISEL_TI4SEL_1 (0x2U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
+#define TIM4_TISEL_TI4SEL_2 (0x4U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
+#define TIM4_TISEL_TI4SEL_3 (0x8U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
+
+/******************* Bit definition for TIM5_AF1 register *********************/
+#define TIM5_AF1_ETRSEL_Pos (14U)
+#define TIM5_AF1_ETRSEL_Msk (0xFU << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
+#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETR SEL) */
+#define TIM5_AF1_ETRSEL_0 (0x1U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
+#define TIM5_AF1_ETRSEL_1 (0x2U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
+#define TIM5_AF1_ETRSEL_2 (0x4U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
+#define TIM5_AF1_ETRSEL_3 (0x8U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
+
+/******************* Bit definition for TIM5_TISEL register *********************/
+#define TIM5_TISEL_TI1SEL_Pos (0U)
+#define TIM5_TISEL_TI1SEL_Msk (0xFU << TIM5_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM5_TISEL_TI1SEL TIM5_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
+#define TIM5_TISEL_TI1SEL_0 (0x1U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM5_TISEL_TI1SEL_1 (0x2U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM5_TISEL_TI1SEL_2 (0x4U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM5_TISEL_TI1SEL_3 (0x8U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM5_TISEL_TI2SEL_Pos (8U)
+#define TIM5_TISEL_TI2SEL_Msk (0xFU << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM5_TISEL_TI2SEL TIM5_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
+#define TIM5_TISEL_TI2SEL_0 (0x1U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM5_TISEL_TI2SEL_1 (0x2U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM5_TISEL_TI2SEL_2 (0x4U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM5_TISEL_TI2SEL_3 (0x8U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+#define TIM5_TISEL_TI3SEL_Pos (16U)
+#define TIM5_TISEL_TI3SEL_Msk (0xFU << TIM5_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
+#define TIM5_TISEL_TI3SEL TIM5_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
+#define TIM5_TISEL_TI3SEL_0 (0x1U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
+#define TIM5_TISEL_TI3SEL_1 (0x2U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
+#define TIM5_TISEL_TI3SEL_2 (0x4U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
+#define TIM5_TISEL_TI3SEL_3 (0x8U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
+
+#define TIM5_TISEL_TI4SEL_Pos (24U)
+#define TIM5_TISEL_TI4SEL_Msk (0xFU << TIM5_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
+#define TIM5_TISEL_TI4SEL TIM5_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
+#define TIM5_TISEL_TI4SEL_0 (0x1U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
+#define TIM5_TISEL_TI4SEL_1 (0x2U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
+#define TIM5_TISEL_TI4SEL_2 (0x4U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
+#define TIM5_TISEL_TI4SEL_3 (0x8U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
+
+/******************* Bit definition for TIM15_AF1 register *********************/
+#define TIM15_AF1_BKINE_Pos (0U)
+#define TIM15_AF1_BKINE_Msk (0x1U << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
+#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
+#define TIM15_AF1_BKCMP1E_Pos (1U)
+#define TIM15_AF1_BKCMP1E_Msk (0x1U << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
+#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM15_AF1_BKCMP2E_Pos (2U)
+#define TIM15_AF1_BKCMP2E_Msk (0x1U << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
+#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
+#define TIM15_AF1_BKDF1BK2E_Pos (8U)
+#define TIM15_AF1_BKDF1BK2E_Msk (0x1U << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
+#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
+#define TIM15_AF1_BKINP_Pos (9U)
+#define TIM15_AF1_BKINP_Msk (0x1U << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
+#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
+#define TIM15_AF1_BKCMP1P_Pos (10U)
+#define TIM15_AF1_BKCMP1P_Msk (0x1U << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
+#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM15_AF1_BKCMP2P_Pos (11U)
+#define TIM15_AF1_BKCMP2P_Msk (0x1U << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
+#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
+
+/******************* Bit definition for TIM15_TISEL register *********************/
+#define TIM15_TISEL_TI1SEL_Pos (0U)
+#define TIM15_TISEL_TI1SEL_Msk (0xFU << TIM15_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM15_TISEL_TI1SEL TIM15_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM15 TI1 SEL)*/
+#define TIM15_TISEL_TI1SEL_0 (0x1U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM15_TISEL_TI1SEL_1 (0x2U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM15_TISEL_TI1SEL_2 (0x4U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM15_TISEL_TI1SEL_3 (0x8U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM15_TISEL_TI2SEL_Pos (8U)
+#define TIM15_TISEL_TI2SEL_Msk (0xFU << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM15_TISEL_TI2SEL TIM15_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM15 TI2 SEL)*/
+#define TIM15_TISEL_TI2SEL_0 (0x1U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM15_TISEL_TI2SEL_1 (0x2U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM15_TISEL_TI2SEL_2 (0x4U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM15_TISEL_TI2SEL_3 (0x8U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+/******************* Bit definition for TIM12_TISEL register *********************/
+#define TIM12_TISEL_TI1SEL_Pos (0U)
+#define TIM12_TISEL_TI1SEL_Msk (0xFU << TIM12_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM12_TISEL_TI1SEL TIM12_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM12 TI1 SEL)*/
+#define TIM12_TISEL_TI1SEL_0 (0x1U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM12_TISEL_TI1SEL_1 (0x2U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM12_TISEL_TI1SEL_2 (0x4U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM12_TISEL_TI1SEL_3 (0x8U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM12_TISEL_TI2SEL_Pos (8U)
+#define TIM12_TISEL_TI2SEL_Msk (0xFU << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM12_TISEL_TI2SEL TIM12_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM15 TI2 SEL)*/
+#define TIM12_TISEL_TI2SEL_0 (0x1U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM12_TISEL_TI2SEL_1 (0x2U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM12_TISEL_TI2SEL_2 (0x4U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM12_TISEL_TI2SEL_3 (0x8U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+/******************* Bit definition for TIM16_ register *********************/
+#define TIM16_AF1_BKINE_Pos (0U)
+#define TIM16_AF1_BKINE_Msk (0x1U << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
+#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
+#define TIM16_AF1_BKDF1BK2E_Pos (8U)
+#define TIM16_AF1_BKDF1BK2E_Msk (0x1U << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
+#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
+#define TIM16_AF1_BKINP_Pos (9U)
+#define TIM16_AF1_BKINP_Msk (0x1U << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
+#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
+
+/******************* Bit definition for TIM16_TISEL register *********************/
+#define TIM16_TISEL_TI1SEL_Pos (0U)
+#define TIM16_TISEL_TI1SEL_Msk (0xFU << TIM16_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM16_TISEL_TI1SEL TIM16_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM16 TI1 SEL) */
+#define TIM16_TISEL_TI1SEL_0 (0x1U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM16_TISEL_TI1SEL_1 (0x2U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM16_TISEL_TI1SEL_2 (0x4U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM16_TISEL_TI1SEL_3 (0x8U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+/******************* Bit definition for TIM17_AF1 register *********************/
+#define TIM17_AF1_BKINE_Pos (0U)
+#define TIM17_AF1_BKINE_Msk (0x1U << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
+#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
+#define TIM17_AF1_BKDF1BK2E_Pos (8U)
+#define TIM17_AF1_BKDF1BK2E_Msk (0x1U << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
+#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
+#define TIM17_AF1_BKINP_Pos (9U)
+#define TIM17_AF1_BKINP_Msk (0x1U << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
+#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
+
+
+/******************* Bit definition for TIM17_TISEL register *********************/
+#define TIM17_TISEL_TI1SEL_Pos (0U)
+#define TIM17_TISEL_TI1SEL_Msk (0xFU << TIM17_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM17_TISEL_TI1SEL TIM17_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM17 TI1 SEL) */
+#define TIM17_TISEL_TI1SEL_0 (0x1U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM17_TISEL_TI1SEL_1 (0x2U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM17_TISEL_TI1SEL_2 (0x4U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM17_TISEL_TI1SEL_3 (0x8U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+/******************* Bit definition for TIM_TISEL register *********************/
+#define TIM_TISEL_TI1SEL_Pos (0U)
+#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos (8U)
+#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos (16U)
+#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos (24U)
+#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos (3U)
+#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
+#define LPTIM_CR_RSTARE_Pos (4U)
+#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
+
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/****************** Bit definition for LPTIM_CFGR2 register *******************/
+#define LPTIM_CFGR2_IN1SEL_Pos (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */
+#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits (INPUT1 selection) */
+#define LPTIM_CFGR2_IN1SEL_0_Pos (LPTIM_CFGR2_IN1SEL_Pos)
+#define LPTIM_CFGR2_IN1SEL_0_Msk (0x1U << LPTIM_CFGR2_IN1SEL_0_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_0 LPTIM_CFGR2_IN1SEL_0_Msk /*!< Bit 0 */
+#define LPTIM_CFGR2_IN1SEL_1_Pos (1U)
+#define LPTIM_CFGR2_IN1SEL_1_Msk (0x1U << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
+#define LPTIM_CFGR2_IN1SEL_2_Pos (2U)
+#define LPTIM_CFGR2_IN1SEL_2_Msk (0x1U << LPTIM_CFGR2_IN1SEL_2_Pos) /*!< 0x00000004 */
+#define LPTIM_CFGR2_IN1SEL_2 LPTIM_CFGR2_IN1SEL_2_Msk /*!< Bit 2 */
+#define LPTIM_CFGR2_IN1SEL_3_Pos (3U)
+#define LPTIM_CFGR2_IN1SEL_3_Msk (0x1U << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
+
+#define LPTIM_CFGR2_IN2SEL_Pos (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
+#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< CFGR2[7:4] bits (INPUT2 selection) */
+#define LPTIM_CFGR2_IN2SEL_0_Pos (LPTIM_CFGR2_IN2SEL_Pos)
+#define LPTIM_CFGR2_IN2SEL_0_Msk (0x1U << LPTIM_CFGR2_IN2SEL_0_Pos) /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_0 LPTIM_CFGR2_IN2SEL_0_Msk /*!< Bit 4 */
+#define LPTIM_CFGR2_IN2SEL_1_Pos (5U)
+#define LPTIM_CFGR2_IN2SEL_1_Msk (0x1U << LPTIM_CFGR2_IN2SEL_1_Pos) /*!< 0x00000020 */
+#define LPTIM_CFGR2_IN2SEL_1 LPTIM_CFGR2_IN2SEL_1_Msk /*!< Bit 5 */
+#define LPTIM_CFGR2_IN2SEL_2_Pos (6U)
+#define LPTIM_CFGR2_IN2SEL_2_Msk (0x1U << LPTIM_CFGR2_IN2SEL_2_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR2_IN2SEL_2 LPTIM_CFGR2_IN2SEL_2_Msk /*!< Bit 6 */
+#define LPTIM_CFGR2_IN2SEL_3_Pos (7U)
+#define LPTIM_CFGR2_IN2SEL_3_Msk (0x1U << LPTIM_CFGR2_IN2SEL_3_Pos) /*!< 0x00000080 */
+#define LPTIM_CFGR2_IN2SEL_3 LPTIM_CFGR2_IN2SEL_3_Msk /*!< Bit 7 */
+
+/********************** Bit definition for LPTIM_HWCFGR register ***************/
+#define LPTIM_HWCFGR_CFG1_Pos (0U)
+#define LPTIM_HWCFGR_CFG1_Msk (0xFFU << LPTIM_HWCFGR_CFG1_Pos) /*!< 0x000000FF */
+#define LPTIM_HWCFGR_CFG1 LPTIM_HWCFGR_CFG1_Msk /*!< HW CFG1 */
+#define LPTIM_HWCFGR_CFG2_Pos (8U)
+#define LPTIM_HWCFGR_CFG2_Msk (0xFFU << LPTIM_HWCFGR_CFG2_Pos) /*!< 0x0000FF00 */
+#define LPTIM_HWCFGR_CFG2 LPTIM_HWCFGR_CFG2_Msk /*!< HW CFG2 */
+#define LPTIM_HWCFGR_CFG3_Pos (16U)
+#define LPTIM_HWCFGR_CFG3_Msk (0xFU << LPTIM_HWCFGR_CFG3_Pos) /*!< 0x000F0000 */
+#define LPTIM_HWCFGR_CFG3 LPTIM_HWCFGR_CFG3_Msk /*!< HW CFG3 */
+#define LPTIM_HWCFGR_CFG4_Pos (24U)
+#define LPTIM_HWCFGR_CFG4_Msk (0xFFU << LPTIM_HWCFGR_CFG4_Pos) /*!< 0xFF000000 */
+#define LPTIM_HWCFGR_CFG4 LPTIM_HWCFGR_CFG4_Msk /*!< HW CFG4 */
+
+/********************** Bit definition for LPTIM_VERR register *****************/
+#define LPTIM_VERR_MINREV_Pos (0U)
+#define LPTIM_VERR_MINREV_Msk (0xFU << LPTIM_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define LPTIM_VERR_MINREV LPTIM_VERR_MINREV_Msk /*!< Minor Revision number */
+#define LPTIM_VERR_MAJREV_Pos (4U)
+#define LPTIM_VERR_MAJREV_Msk (0xFU << LPTIM_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define LPTIM_VERR_MAJREV LPTIM_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for LPTIM_PIDR register ****************/
+#define LPTIM_PIDR_IPID_Pos (0U)
+#define LPTIM_PIDR_IPID_Msk (0xFFFFFFFFU << LPTIM_PIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define LPTIM_PIDR_IPID LPTIM_PIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for LPTIM_SIDR register *****************/
+#define LPTIM_SIDR_SID_Pos (0U)
+#define LPTIM_SIDR_SID_Msk (0xFFFFFFFFU << LPTIM_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define LPTIM_SIDR_SID LPTIM_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for COMP_SR register ********************/
+#define COMP_SR_C1VAL_Pos (0U)
+#define COMP_SR_C1VAL_Msk (0x1U << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
+#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
+#define COMP_SR_C2VAL_Pos (1U)
+#define COMP_SR_C2VAL_Msk (0x1U << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
+#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
+#define COMP_SR_C1IF_Pos (16U)
+#define COMP_SR_C1IF_Msk (0x1U << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
+#define COMP_SR_C1IF COMP_SR_C1IF_Msk
+#define COMP_SR_C2IF_Pos (17U)
+#define COMP_SR_C2IF_Msk (0x1U << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
+#define COMP_SR_C2IF COMP_SR_C2IF_Msk
+/******************* Bit definition for COMP_ICFR register ********************/
+#define COMP_ICFR_C1IF_Pos (16U)
+#define COMP_ICFR_C1IF_Msk (0x1U << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
+#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
+#define COMP_ICFR_C2IF_Pos (17U)
+#define COMP_ICFR_C2IF_Msk (0x1U << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
+#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
+/******************* Bit definition for COMP_OR register ********************/
+#define COMP_OR_AFOPA6_Pos (0U)
+#define COMP_OR_AFOPA6_Msk (0x1U << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
+#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
+#define COMP_OR_AFOPA8_Pos (1U)
+#define COMP_OR_AFOPA8_Msk (0x1U << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
+#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
+#define COMP_OR_AFOPB12_Pos (2U)
+#define COMP_OR_AFOPB12_Msk (0x1U << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
+#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
+#define COMP_OR_AFOPE6_Pos (3U)
+#define COMP_OR_AFOPE6_Msk (0x1U << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
+#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
+#define COMP_OR_AFOPE15_Pos (4U)
+#define COMP_OR_AFOPE15_Msk (0x1U << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
+#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
+#define COMP_OR_AFOPG2_Pos (5U)
+#define COMP_OR_AFOPG2_Msk (0x1U << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
+#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
+#define COMP_OR_AFOPG3_Pos (6U)
+#define COMP_OR_AFOPG3_Msk (0x1U << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
+#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
+#define COMP_OR_AFOPG4_Pos (7U)
+#define COMP_OR_AFOPG4_Msk (0x1U << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
+#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
+#define COMP_OR_AFOPI1_Pos (8U)
+#define COMP_OR_AFOPI1_Msk (0x1U << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
+#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
+#define COMP_OR_AFOPI4_Pos (9U)
+#define COMP_OR_AFOPI4_Msk (0x1U << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
+#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
+#define COMP_OR_AFOPK2_Pos (10U)
+#define COMP_OR_AFOPK2_Msk (0x1U << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
+#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
+
+/*!< ****************** Bit definition for COMP_CFGRx register ********************/
+#define COMP_CFGRx_EN_Pos (0U)
+#define COMP_CFGRx_EN_Msk (0x1U << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
+#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
+#define COMP_CFGRx_BRGEN_Pos (1U)
+#define COMP_CFGRx_BRGEN_Msk (0x1U << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
+#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
+#define COMP_CFGRx_SCALEN_Pos (2U)
+#define COMP_CFGRx_SCALEN_Msk (0x1U << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
+#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
+#define COMP_CFGRx_POLARITY_Pos (3U)
+#define COMP_CFGRx_POLARITY_Msk (0x1U << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
+#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
+#define COMP_CFGRx_WINMODE_Pos (4U)
+#define COMP_CFGRx_WINMODE_Msk (0x1U << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
+#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
+#define COMP_CFGRx_ITEN_Pos (6U)
+#define COMP_CFGRx_ITEN_Msk (0x1U << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
+#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
+#define COMP_CFGRx_HYST_Pos (8U)
+#define COMP_CFGRx_HYST_Msk (0x3U << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
+#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
+#define COMP_CFGRx_HYST_0 (0x1U << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
+#define COMP_CFGRx_HYST_1 (0x2U << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
+#define COMP_CFGRx_PWRMODE_Pos (12U)
+#define COMP_CFGRx_PWRMODE_Msk (0x3U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
+#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
+#define COMP_CFGRx_PWRMODE_0 (0x1U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
+#define COMP_CFGRx_PWRMODE_1 (0x2U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
+#define COMP_CFGRx_INMSEL_Pos (16U)
+#define COMP_CFGRx_INMSEL_Msk (0x7U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
+#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
+#define COMP_CFGRx_INMSEL_0 (0x1U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
+#define COMP_CFGRx_INMSEL_1 (0x2U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
+#define COMP_CFGRx_INMSEL_2 (0x4U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
+#define COMP_CFGRx_INPSEL_Pos (20U)
+#define COMP_CFGRx_INPSEL_Msk (0x1U << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
+#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
+#define COMP_CFGRx_BLANKING_Pos (24U)
+#define COMP_CFGRx_BLANKING_Msk (0xFU << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
+#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
+#define COMP_CFGRx_BLANKING_0 (0x1U << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
+#define COMP_CFGRx_BLANKING_1 (0x2U << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
+#define COMP_CFGRx_BLANKING_2 (0x4U << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
+#define COMP_CFGRx_LOCK_Pos (31U)
+#define COMP_CFGRx_LOCK_Msk (0x1U << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
+#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
+#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos (29U)
+#define USART_CR1_FIFOEN_Msk (0x1U << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
+#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos (30U)
+#define USART_CR1_TXFEIE_Msk (0x1U << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
+#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos (31U)
+#define USART_CR1_RXFFIE_Msk (0x1U << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
+#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_SLVEN_Pos (0U)
+#define USART_CR2_SLVEN_Msk (0x1U << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
+#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
+#define USART_CR2_DIS_NSS_Pos (3U)
+#define USART_CR2_DIS_NSS_Msk (0x1U << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos (23U)
+#define USART_CR3_TXFTIE_Msk (0x1U << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
+#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos (24U)
+#define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
+#define USART_CR3_RXFTCFG_Pos (25U)
+#define USART_CR3_RXFTCFG_Msk (0x7U << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0 (0x1U << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1 (0x2U << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2 (0x4U << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos (28U)
+#define USART_CR3_RXFTIE_Msk (0x1U << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
+#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos (29U)
+#define USART_CR3_TXFTCFG_Msk (0x7U << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
+#define USART_CR3_TXFTCFG_0 (0x1U << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1 (0x2U << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2 (0x4U << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_LPUART_Pos (0U)
+#define USART_BRR_LPUART_Msk (0xFFFFFU << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
+#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
+#define USART_BRR_BRR_Pos (0U)
+#define USART_BRR_BRR_Msk (0xFFFFU << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
+#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
+#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
+#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos (13U)
+#define USART_ISR_UDR_Msk (0x1U << USART_ISR_UDR_Pos) /*!< 0x00002000 */
+#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos (23U)
+#define USART_ISR_TXFE_Msk (0x1U << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
+#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos (24U)
+#define USART_ISR_RXFF_Msk (0x1U << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
+#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
+#define USART_ISR_TCBGT_Pos (25U)
+#define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
+#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
+#define USART_ISR_RXFT_Pos (26U)
+#define USART_ISR_RXFT_Msk (0x1U << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
+#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
+#define USART_ISR_TXFT_Pos (27U)
+#define USART_ISR_TXFT_Msk (0x1U << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
+#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos (2U)
+#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos (5U)
+#define USART_ICR_TXFECF_Msk (0x1U << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
+#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos (7U)
+#define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos (13U)
+#define USART_ICR_UDRCF_Msk (0x1U << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
+#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FF << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FF << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************* Bit definition for USART_PRESC register ****************/
+#define USART_PRESC_PRESCALER_Pos (0U)
+#define USART_PRESC_PRESCALER_Msk (0xFU << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0 (0x1U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1 (0x2U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
+
+/********************** Bit definition for USART_HWCFGR2 register ***************/
+#define USART_HWCFGR2_CFG1_Pos (0U)
+#define USART_HWCFGR2_CFG1_Msk (0xFU << USART_HWCFGR2_CFG1_Pos) /*!< 0x0000000F */
+#define USART_HWCFGR2_CFG1 USART_HWCFGR2_CFG1_Msk /*!< HW CFG1 */
+#define USART_HWCFGR2_CFG2_Pos (4U)
+#define USART_HWCFGR2_CFG2_Msk (0xFU << USART_HWCFGR2_CFG2_Pos) /*!< 0x000000F0 */
+#define USART_HWCFGR2_CFG2 USART_HWCFGR2_CFG2_Msk /*!< HW CFG2 */
+
+/********************** Bit definition for USART_HWCFGR1 register ***************/
+#define USART_HWCFGR1_CFG1_Pos (0U)
+#define USART_HWCFGR1_CFG1_Msk (0xFU << USART_HWCFGR1_CFG1_Pos) /*!< 0x0000000F */
+#define USART_HWCFGR1_CFG1 USART_HWCFGR1_CFG1_Msk /*!< HW CFG1 */
+#define USART_HWCFGR1_CFG2_Pos (4U)
+#define USART_HWCFGR1_CFG2_Msk (0xFU << USART_HWCFGR1_CFG2_Pos) /*!< 0x000000F0 */
+#define USART_HWCFGR1_CFG2 USART_HWCFGR1_CFG2_Msk /*!< HW CFG2 */
+#define USART_HWCFGR1_CFG3_Pos (8U)
+#define USART_HWCFGR1_CFG3_Msk (0xFU << USART_HWCFGR1_CFG3_Pos) /*!< 0x00000F00 */
+#define USART_HWCFGR1_CFG3 USART_HWCFGR1_CFG3_Msk /*!< HW CFG3 */
+#define USART_HWCFGR1_CFG4_Pos (12U)
+#define USART_HWCFGR1_CFG4_Msk (0xFU << USART_HWCFGR1_CFG4_Pos) /*!< 0x0000F000 */
+#define USART_HWCFGR1_CFG4 USART_HWCFGR1_CFG4_Msk /*!< HW CFG4 */
+#define USART_HWCFGR1_CFG5_Pos (16U)
+#define USART_HWCFGR1_CFG5_Msk (0xFU << USART_HWCFGR1_CFG5_Pos) /*!< 0x000F0000 */
+#define USART_HWCFGR1_CFG5 USART_HWCFGR1_CFG5_Msk /*!< HW CFG5 */
+#define USART_HWCFGR1_CFG6_Pos (20U)
+#define USART_HWCFGR1_CFG6_Msk (0xFU << USART_HWCFGR1_CFG6_Pos) /*!< 0x00F00000 */
+#define USART_HWCFGR1_CFG6 USART_HWCFGR1_CFG6_Msk /*!< HW CFG6 */
+#define USART_HWCFGR1_CFG7_Pos (24U)
+#define USART_HWCFGR1_CFG7_Msk (0xFU << USART_HWCFGR1_CFG7_Pos) /*!< 0x0F000000 */
+#define USART_HWCFGR1_CFG7 USART_HWCFGR1_CFG7_Msk /*!< HW CFG7 */
+#define USART_HWCFGR1_CFG8_Pos (28U)
+#define USART_HWCFGR1_CFG8_Msk (0xFU << USART_HWCFGR1_CFG8_Pos) /*!< 0xF0000000 */
+#define USART_HWCFGR1_CFG8 USART_HWCFGR1_CFG8_Msk /*!< HW CFG8 */
+
+/********************** Bit definition for USART_VERR register *****************/
+#define USART_VERR_MINREV_Pos (0U)
+#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< Minor Revision number */
+#define USART_VERR_MAJREV_Pos (4U)
+#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for USART_IPIDR register ****************/
+#define USART_IPIDR_IPID_Pos (0U)
+#define USART_IPIDR_IPID_Msk (0xFFFFFFFFU << USART_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define USART_IPIDR_IPID USART_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for USART_SIDR register *****************/
+#define USART_SIDR_SID_Pos (0U)
+#define USART_SIDR_SID_Msk (0xFFFFFFFFU << USART_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define USART_SIDR_SID USART_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* Single Wire Protocol Master Interface (SWPMI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SWPMI_CR register ********************/
+#define SWPMI_CR_RXDMA ((uint16_t)0x0001) /*!<Reception DMA enable */
+#define SWPMI_CR_TXDMA ((uint16_t)0x0002) /*!<Transmission DMA enable */
+#define SWPMI_CR_RXMODE ((uint16_t)0x0004) /*!<Reception buffering mode */
+#define SWPMI_CR_TXMODE ((uint16_t)0x0008) /*!<Transmission buffering mode */
+#define SWPMI_CR_LPBK ((uint16_t)0x0010) /*!<Loopback mode enable */
+#define SWPMI_CR_SWPACT ((uint16_t)0x0020) /*!<Single wire protocol master interface activate */
+#define SWPMI_CR_DEACT ((uint16_t)0x0400) /*!<Single wire protocol master interface deactivate */
+#define SWPMI_CR_SWPEN ((uint16_t)0x0800) /*!<Single wire protocol master transceiver enable */
+
+/******************* Bit definition for SWPMI_BRR register ********************/
+#define SWPMI_BRR_BR ((uint16_t)0x003F) /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/******************* Bit definition for SWPMI_ISR register ********************/
+#define SWPMI_ISR_RXBFF ((uint16_t)0x0001) /*!<Receive buffer full flag */
+#define SWPMI_ISR_TXBEF ((uint16_t)0x0002) /*!<Transmit buffer empty flag */
+#define SWPMI_ISR_RXBERF ((uint16_t)0x0004) /*!<Receive CRC error flag */
+#define SWPMI_ISR_RXOVRF ((uint16_t)0x0008) /*!<Receive overrun error flag */
+#define SWPMI_ISR_TXUNRF ((uint16_t)0x0010) /*!<Transmit underrun error flag */
+#define SWPMI_ISR_RXNE ((uint16_t)0x0020) /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE ((uint16_t)0x0040) /*!<Transmit data register empty */
+#define SWPMI_ISR_TCF ((uint16_t)0x0080) /*!<Transfer complete flag */
+#define SWPMI_ISR_SRF ((uint16_t)0x0100) /*!<Slave resume flag */
+#define SWPMI_ISR_SUSP ((uint16_t)0x0200) /*!<SUSPEND flag */
+#define SWPMI_ISR_DEACTF ((uint16_t)0x0400) /*!<DEACTIVATED flag */
+#define SWPMI_ISR_RDYF ((uint16_t)0x0800) /*!<Transceiver ready flag */
+
+/******************* Bit definition for SWPMI_ICR register ********************/
+#define SWPMI_ICR_CRXBFF ((uint16_t)0x0001) /*!<Clear receive buffer full flag */
+#define SWPMI_ICR_CTXBEF ((uint16_t)0x0002) /*!<Clear transmit buffer empty flag */
+#define SWPMI_ICR_CRXBERF ((uint16_t)0x0004) /*!<Clear receive CRC error flag */
+#define SWPMI_ICR_CRXOVRF ((uint16_t)0x0008) /*!<Clear receive overrun error flag */
+#define SWPMI_ICR_CTXUNRF ((uint16_t)0x0010) /*!<Clear transmit underrun error flag */
+#define SWPMI_ICR_CTCF ((uint16_t)0x0080) /*!<Clear transfer complete flag */
+#define SWPMI_ICR_CSRF ((uint16_t)0x0100) /*!<Clear slave resume flag */
+#define SWPMI_ICR_CRDYF ((uint16_t)0x0800) /*!<Clear transceiver ready flag */
+
+/******************* Bit definition for SWPMI_IER register ********************/
+#define SWPMI_IER_RXBFIE ((uint16_t)0x0001) /*!<Receive buffer full interrupt enable */
+#define SWPMI_IER_TXBEIE ((uint16_t)0x0002) /*!<Transmit buffer empty interrupt enable */
+#define SWPMI_IER_RXBERIE ((uint16_t)0x0004) /*!<Receive CRC error interrupt enable */
+#define SWPMI_IER_RXOVRIE ((uint16_t)0x0008) /*!<Receive overrun error interrupt enable */
+#define SWPMI_IER_TXUNRIE ((uint16_t)0x0010) /*!<Transmit underrun error interrupt enable */
+#define SWPMI_IER_RIE ((uint16_t)0x0020) /*!<Receive interrupt enable */
+#define SWPMI_IER_TIE ((uint16_t)0x0040) /*!<Transmit interrupt enable */
+#define SWPMI_IER_TCIE ((uint16_t)0x0080) /*!<Transmit complete interrupt enable */
+#define SWPMI_IER_SRIE ((uint16_t)0x0100) /*!<Slave resume interrupt enable */
+#define SWPMI_IER_RDYIE ((uint16_t)0x0800) /*!<Transceiver ready interrupt enable */
+
+/******************* Bit definition for SWPMI_RFL register ********************/
+#define SWPMI_RFL_RFL ((uint16_t)0x001F) /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1 ((uint16_t)0x0003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/******************* Bit definition for SWPMI_TDR register ********************/
+#define SWPMI_TDR_TD_Pos (0U)
+#define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
+
+/******************* Bit definition for SWPMI_RDR register ********************/
+#define SWPMI_RDR_RD_Pos (0U)
+#define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+
+
+/******************* Bit definition for SWPMI_OR register ********************/
+#define SWPMI_OR_TBYP ((uint16_t)0x0001) /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS ((uint16_t)0x0002) /*!<SWP CLASS selection */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos (11U)
+#define WWDG_CFR_WDGTB_Msk (0x7U << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2 (0x4U << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
+
+/******************* Bit definition for WWDG_HWCFGR register ***************/
+#define WWDG_HWCFGR_PREDIV_Pos (0U)
+#define WWDG_HWCFGR_PREDIV_Msk (0xFFFFU << WWDG_HWCFGR_PREDIV_Pos) /*!< 0x0000FFFF */
+#define WWDG_HWCFGR_PREDIV WWDG_HWCFGR_PREDIV_Msk /*!< Watchdog clock prescaler */
+
+/******************* Bit definition for WWDG_VERR register *****************/
+#define WWDG_VERR_MINREV_Pos (0U)
+#define WWDG_VERR_MINREV_Msk (0xFU << WWDG_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define WWDG_VERR_MINREV WWDG_VERR_MINREV_Msk /*!< Minor Revision number */
+#define WWDG_VERR_MAJREV_Pos (4U)
+#define WWDG_VERR_MAJREV_Msk (0xFU << WWDG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define WWDG_VERR_MAJREV WWDG_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/******************* Bit definition for WWDG_IPIDR register ****************/
+#define WWDG_IPIDR_ID_Pos (0U)
+#define WWDG_IPIDR_ID_Msk (0xFFFFFFFFU << WWDG_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
+#define WWDG_IPIDR_ID WWDG_IPIDR_ID_Msk /*!< IP Identification */
+
+/********************** Bit definition for WWDG_SIDR register *****************/
+#define WWDG_SIDR_SID_Pos (0U)
+#define WWDG_SIDR_SID_Msk (0xFFFFFFFFU << WWDG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define WWDG_SIDR_SID WWDG_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* MDIOS */
+/* */
+/******************************************************************************/
+/******************** Bit definition for MDIOS_CR register *******************/
+#define MDIOS_CR_EN_Pos (0U)
+#define MDIOS_CR_EN_Msk (0x1U << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
+#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos (1U)
+#define MDIOS_CR_WRIE_Msk (0x1U << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
+#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos (2U)
+#define MDIOS_CR_RDIE_Msk (0x1U << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
+#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos (3U)
+#define MDIOS_CR_EIE_Msk (0x1U << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
+#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos (7U)
+#define MDIOS_CR_DPC_Msk (0x1U << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
+#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FU << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0 (0x01U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1 (0x02U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2 (0x04U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3 (0x08U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4 (0x10U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
+
+/******************** Bit definition for MDIOS_SR register *******************/
+#define MDIOS_SR_PERF_Pos (0U)
+#define MDIOS_SR_PERF_Msk (0x1U << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
+#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos (1U)
+#define MDIOS_SR_SERF_Msk (0x1U << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
+#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos (2U)
+#define MDIOS_SR_TERF_Msk (0x1U << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
+#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
+
+/******************** Bit definition for MDIOS_CLRFR register *******************/
+#define MDIOS_SR_CPERF_Pos (0U)
+#define MDIOS_SR_CPERF_Msk (0x1U << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
+#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos (1U)
+#define MDIOS_SR_CSERF_Msk (0x1U << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
+#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos (2U)
+#define MDIOS_SR_CTERF_Msk (0x1U << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
+#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
+
+/********************** Bit definition for MDIOS_HWCFGR register ***************/
+#define MDIOS_HWCFGR_NBREG_Pos (0U)
+#define MDIOS_HWCFGR_NBREG_Msk (0xFFU << MDIOS_HWCFGR_NBREG_Pos) /*!< 0x000000FF */
+#define MDIOS_HWCFGR_NBREG MDIOS_HWCFGR_NBREG_Msk /*!< IP configuration number of registers */
+
+/********************** Bit definition for MDIOS_VERR register *****************/
+#define MDIOS_VERR_MINREV_Pos (0U)
+#define MDIOS_VERR_MINREV_Msk (0xFU << MDIOS_VERR_MINREV_Pos) /*!< 0x0000000F */
+#define MDIOS_VERR_MINREV MDIOS_VERR_MINREV_Msk /*!< Minor Revision number */
+#define MDIOS_VERR_MAJREV_Pos (4U)
+#define MDIOS_VERR_MAJREV_Msk (0xFU << MDIOS_VERR_MAJREV_Pos) /*!< 0x000000F0 */
+#define MDIOS_VERR_MAJREV MDIOS_VERR_MAJREV_Msk /*!< Major Revision number */
+
+/********************** Bit definition for MDIOS_IPIDR register ****************/
+#define MDIOS_IPIDR_IPID_Pos (0U)
+#define MDIOS_IPIDR_IPID_Msk (0xFFFFFFFFU << MDIOS_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
+#define MDIOS_IPIDR_IPID MDIOS_IPIDR_IPID_Msk /*!< IP Identification */
+
+/********************** Bit definition for MDIOS_SIDR register *****************/
+#define MDIOS_SIDR_SID_Pos (0U)
+#define MDIOS_SIDR_SID_Msk (0xFFFFFFFFU << MDIOS_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
+#define MDIOS_SIDR_SID MDIOS_SIDR_SID_Msk /*!< IP size identification */
+
+/******************************************************************************/
+/* */
+/* USB_OTG */
+/* */
+/******************************************************************************/
+/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
+
+/******************** Bit definition forUSB_OTG_HCFG register ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos (2U)
+#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
+
+/******************** Bit definition forUSB_OTG_DCFG register ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos (0U)
+#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos (4U)
+#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
+#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos (11U)
+#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/******************** Bit definition forUSB_OTG_PCGCR register ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
+
+/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
+
+/******************** Bit definition forUSB_OTG_DCTL register ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos (1U)
+#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos (2U)
+#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos (3U)
+#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos (4U)
+#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos (7U)
+#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos (8U)
+#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos (9U)
+#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos (10U)
+#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
+
+/******************** Bit definition forUSB_OTG_HFIR register ********************/
+#define USB_OTG_HFIR_FRIVL_Pos (0U)
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
+
+/******************** Bit definition forUSB_OTG_HFNUM register ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos (16U)
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
+
+/******************** Bit definition forUSB_OTG_DSTS register ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos (3U)
+#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos (8U)
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
+
+/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
+
+/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYIF_Pos (3U)
+#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1U << USB_OTG_GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */
+#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
+#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1U << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
+
+/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
+
+/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/******************** Bit definition forUSB_OTG_HAINT register ********************/
+#define USB_OTG_HAINT_HAINT_Pos (0U)
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
+
+/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
+
+/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos (3U)
+#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
+
+/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
+
+/******************** Bit definition forUSB_OTG_DAINT register ********************/
+#define USB_OTG_DAINT_IEPINT_Pos (0U)
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos (16U)
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
+
+/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
+
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition for OTG register ********************/
+
+#define USB_OTG_CHNUM_Pos (0U)
+#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
+#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos (4U)
+#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
+
+#define USB_OTG_DPID_Pos (15U)
+#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
+#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
+#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos (17U)
+#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
+#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos (0U)
+#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos (21U)
+#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
+#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
+
+/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
+
+/******************** Bit definition for OTG register ********************/
+#define USB_OTG_NPTXFSA_Pos (0U)
+#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos (16U)
+#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos (0U)
+#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos (16U)
+#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
+
+/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
+
+/******************** Bit definition forUSB_OTG_GCCFG register ********************/
+#define USB_OTG_GCCFG_DCDET_Pos (0U)
+#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos (1U)
+#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos (2U)
+#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos (19U)
+#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos (20U)
+#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_OTGIDEN_Pos (22U)
+#define USB_OTG_GCCFG_OTGIDEN_Msk (0x1U << USB_OTG_GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_GCCFG_OTGIDEN USB_OTG_GCCFG_OTGIDEN_Msk /*!< OTG Id enable */
+#define USB_OTG_GCCFG_PHYHSEN_Pos (23U)
+#define USB_OTG_GCCFG_PHYHSEN_Msk (0x1U << USB_OTG_GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_GCCFG_PHYHSEN USB_OTG_GCCFG_PHYHSEN_Msk /*!< HS PHY enable */
+
+/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
+
+/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/******************** Bit definition forUSB_OTG_CID register ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
+
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
+
+/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPRT register ********************/
+#define USB_OTG_HPRT_PCSTS_Pos (0U)
+#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos (1U)
+#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos (2U)
+#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos (4U)
+#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos (6U)
+#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos (7U)
+#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos (8U)
+#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos (10U)
+#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos (12U)
+#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos (13U)
+#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos (17U)
+#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos (20U)
+#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos (22U)
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
+
+/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
+
+/******************** Bit definition forUSB_OTG_HCINT register ********************/
+#define USB_OTG_HCINT_XFRC_Pos (0U)
+#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos (1U)
+#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos (2U)
+#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos (3U)
+#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos (4U)
+#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos (5U)
+#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos (6U)
+#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos (7U)
+#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos (8U)
+#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos (9U)
+#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos (10U)
+#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
+
+/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos (3U)
+#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos (9U)
+#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos (12U)
+#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos (13U)
+#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
+
+/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
+
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
+/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_HCDMA register ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
+
+/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
+
+/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
+
+/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos (3U)
+#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos (14U)
+#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
+
+/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for PCGCCTL register ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
+
+/******************************** DTS Instances ******************************/
+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS1)
+
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC1) || \
+ ((INSTANCE) == CRC2))
+
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+ ((INSTANCE) == DFSDM1_Filter1) || \
+ ((INSTANCE) == DFSDM1_Filter2) || \
+ ((INSTANCE) == DFSDM1_Filter3) || \
+ ((INSTANCE) == DFSDM1_Filter4) || \
+ ((INSTANCE) == DFSDM1_Filter5))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+ ((INSTANCE) == DFSDM1_Channel1) || \
+ ((INSTANCE) == DFSDM1_Channel2) || \
+ ((INSTANCE) == DFSDM1_Channel3) || \
+ ((INSTANCE) == DFSDM1_Channel4) || \
+ ((INSTANCE) == DFSDM1_Channel5) || \
+ ((INSTANCE) == DFSDM1_Channel6) || \
+ ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+ ((INSTANCE) == DMA1_Stream1) || \
+ ((INSTANCE) == DMA1_Stream2) || \
+ ((INSTANCE) == DMA1_Stream3) || \
+ ((INSTANCE) == DMA1_Stream4) || \
+ ((INSTANCE) == DMA1_Stream5) || \
+ ((INSTANCE) == DMA1_Stream6) || \
+ ((INSTANCE) == DMA1_Stream7) || \
+ ((INSTANCE) == DMA2_Stream0) || \
+ ((INSTANCE) == DMA2_Stream1) || \
+ ((INSTANCE) == DMA2_Stream2) || \
+ ((INSTANCE) == DMA2_Stream3) || \
+ ((INSTANCE) == DMA2_Stream4) || \
+ ((INSTANCE) == DMA2_Stream5) || \
+ ((INSTANCE) == DMA2_Stream6) || \
+ ((INSTANCE) == DMA2_Stream7))
+
+/******************************** DMA Request Generator Instances **************/
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+ ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+ ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+ ((INSTANCE) == DMAMUX1_RequestGenerator3))
+
+/******************************** MDMA Request Generator Instances **************/
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
+ ((INSTANCE) == MDMA_Channel1) || \
+ ((INSTANCE) == MDMA_Channel2) || \
+ ((INSTANCE) == MDMA_Channel3) || \
+ ((INSTANCE) == MDMA_Channel4) || \
+ ((INSTANCE) == MDMA_Channel5) || \
+ ((INSTANCE) == MDMA_Channel6) || \
+ ((INSTANCE) == MDMA_Channel7) || \
+ ((INSTANCE) == MDMA_Channel8) || \
+ ((INSTANCE) == MDMA_Channel9) || \
+ ((INSTANCE) == MDMA_Channel10) || \
+ ((INSTANCE) == MDMA_Channel11) || \
+ ((INSTANCE) == MDMA_Channel12) || \
+ ((INSTANCE) == MDMA_Channel13) || \
+ ((INSTANCE) == MDMA_Channel14) || \
+ ((INSTANCE) == MDMA_Channel15) || \
+ ((INSTANCE) == MDMA_Channel16))
+/******************************* QUADSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
+
+/******************************* FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
+ ((INSTANCE) == FDCAN2))
+
+#define IS_FDCAN_TT_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH) || \
+ ((INSTANCE) == GPIOI) || \
+ ((INSTANCE) == GPIOJ) || \
+ ((INSTANCE) == GPIOK) || \
+ ((INSTANCE) == GPIOZ))
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** HSEM Instances *******************************/
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
+/******************** Bit definition for HSEM_CR register *****************/
+#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CA7 ID */
+#define HSEM_CPU2_COREID (0x00000002U) /* Semaphore Core CM4 ID */
+#define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
+
+#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
+#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
+
+#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
+#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
+
+#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3) || \
+ ((INSTANCE) == I2C4) || \
+ ((INSTANCE) == I2C5) || \
+ ((INSTANCE) == I2C6) )
+/************** I2C Instances : wakeup capability from stop modes *************/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3) || \
+ ((INSTANCE) == I2C4) || \
+ ((INSTANCE) == I2C5) || \
+ ((INSTANCE) == I2C6) )
+
+/******************************* IPCC Instances ********************************/
+#define IS_IPCC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IPCC)
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG1) || \
+ ((INSTANCE) == RNG2))
+
+/******************************* HASH Instances ********************************/
+#define IS_HASH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HASH1) || \
+ ((INSTANCE) == HASH2))
+
+/******************************* HASH Instances ********************************/
+#define IS_HASH_DIGEST_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HASH1_DIGEST) || \
+ ((INSTANCE) == HASH2_DIGEST))
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SDMMC Instances *****************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1) || \
+ ((INSTANCE) == SDMMC2) || \
+ ((INSTANCE) == SDMMC3))
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4) || \
+ ((INSTANCE) == SPI5) || \
+ ((INSTANCE) == SPI6))
+
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
+ ((INSTANCE) == LPTIM2) || \
+ ((INSTANCE) == LPTIM3) ||\
+ ((INSTANCE) == LPTIM4) ||\
+ ((INSTANCE) == LPTIM5))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
+ ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM13) || \
+ ((INSTANCE) == TIM14) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 5 capture/compare channels *************/
+#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 6 capture/compare channels *************/
+#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/***************** TIM Instances : external trigger reamp input availabe *******/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/***************** TIM Instances : external trigger reamp input availabe *******/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event *************/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1)|| \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM5) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM12) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM13) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM14) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : TIM_BKIN2 ***************************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/************ TIM Instances : Advanced timers ********************************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+ ((__INSTANCE__) == TIM2) || \
+ ((__INSTANCE__) == TIM3) || \
+ ((__INSTANCE__) == TIM4) || \
+ ((__INSTANCE__) == TIM5) || \
+ ((__INSTANCE__) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** USART Instances : SPI slave mode ************************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/******************** UART Instances : FIFO mode.******************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/*********************** UART Instances : Driver Enable ***********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/********************* UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/******************* UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/************************* UART Instances : LIN mode **************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/****************** UART Instances : Wake-up from Stop mode *******************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+/************************* UART Instances : IRDA mode *************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5) || \
+ ((INSTANCE) == USART6) || \
+ ((INSTANCE) == UART7) || \
+ ((INSTANCE) == UART8))
+
+
+/********************* USART Instances : Smard card mode **********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == USART6))
+
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
+
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
+
+/****************************** SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+ ((INSTANCE) == SAI1_Block_B) || \
+ ((INSTANCE) == SAI2_Block_A) || \
+ ((INSTANCE) == SAI2_Block_B) || \
+ ((INSTANCE) == SAI3_Block_A) || \
+ ((INSTANCE) == SAI3_Block_B) || \
+ ((INSTANCE) == SAI4_Block_A) || \
+ ((INSTANCE) == SAI4_Block_B))
+
+/****************************** SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/******************************* BSEC VERSION ********************************/
+#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VER)
+
+/******************************* TZPC VERSION ********************************/
+#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
+
+/******************************* FMC VERSION ********************************/
+#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* SYSCFG VERSION ********************************/
+#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* ETHERNET VERSION ********************************/
+#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
+
+
+/******************************* SYSCFG VERSION ********************************/
+#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* PWR VERSION ********************************/
+#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
+
+/******************************* RCC VERSION ********************************/
+#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* HDP VERSION ********************************/
+#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* IPCC VERSION ********************************/
+#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
+
+/******************************* HSEM VERSION ********************************/
+#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* GPIO VERSION ********************************/
+#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* DMA VERSION ********************************/
+#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* DMAMUX VERSION ********************************/
+#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* MDMA VERSION ********************************/
+#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* TAMP VERSION ********************************/
+#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* RTC VERSION ********************************/
+#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* SDMMC VERSION ********************************/
+#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* QUADSPI VERSION ********************************/
+#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* CRC VERSION ********************************/
+#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* RNG VERSION ********************************/
+#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER)
+
+/******************************* HASH VERSION ********************************/
+#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER)
+
+/******************************* CRYP VERSION ********************************/
+#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER)
+
+/******************************* DCMI VERSION ********************************/
+#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* CEC VERSION ********************************/
+#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* LPTIM VERSION ********************************/
+#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* TIM VERSION ********************************/
+#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* IWDG VERSION ********************************/
+#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* WWDG VERSION ********************************/
+#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* DFSDM VERSION ********************************/
+#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* SAI VERSION ********************************/
+#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* MDIOS VERSION ********************************/
+#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* I2C VERSION ********************************/
+#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* USART VERSION ********************************/
+#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* SPDIFRX VERSION ********************************/
+#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* SPI VERSION ********************************/
+#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* ADC VERSION ********************************/
+#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* DLYB VERSION ********************************/
+#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* DAC VERSION ********************************/
+#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
+
+/******************************* DSI VERSION ********************************/
+#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* USBPHYC VERSION ********************************/
+#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
+
+/******************************* DEVICE VERSION ********************************/
+#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos)
+#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000)
+
+/******************************* DEVICE ID ************************************/
+#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
+
+/**
+ * @brief Check whether platform is engineering boot mode
+ * @param None
+ * @retval TRUE or FALSE
+ */
+#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2))
+
+
+ /**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32MP157Cxx_CM4_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h
new file mode 100644
index 0000000..6b22524
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h
@@ -0,0 +1,228 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32MP1xx Device Peripheral Access Layer Header File.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The STM32MP1xx device used in the target application
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_HAL_DRIVER"
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32mp1xx
+ * @{
+ */
+
+#ifndef __STM32MP1xx_H
+#define __STM32MP1xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32MP1 device used in your
+ application
+ */
+
+#if !defined (STM32MP1)
+#define STM32MP1
+#endif /* STM32MP1 */
+
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+ * @brief CMSIS Device version number
+ */
+#define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+ |(__CMSIS_DEVICE_HAL_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Device_Included
+ * @{
+ */
+#if defined(CORE_CM4)
+#if defined(STM32MP15xx) /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
+ #include "stm32mp157cxx_cm4.h"
+#elif defined(STM32MP157Axx)
+ #include "stm32mp157axx_cm4.h"
+#elif defined(STM32MP157Cxx)
+ #include "stm32mp157cxx_cm4.h"
+#elif defined(STM32MP157Dxx)
+ #include "stm32mp157dxx_cm4.h"
+#elif defined(STM32MP157Fxx)
+ #include "stm32mp157fxx_cm4.h"
+#elif defined(STM32MP153Axx)
+ #include "stm32mp153axx_cm4.h"
+#elif defined(STM32MP153Cxx)
+ #include "stm32mp153cxx_cm4.h"
+#elif defined(STM32MP153Dxx)
+ #include "stm32mp153dxx_cm4.h"
+#elif defined(STM32MP153Fxx)
+ #include "stm32mp153fxx_cm4.h"
+#elif defined(STM32MP151Axx)
+ #include "stm32mp151axx_cm4.h"
+#elif defined(STM32MP151Cxx)
+ #include "stm32mp151cxx_cm4.h"
+#elif defined(STM32MP151Dxx)
+ #include "stm32mp151dxx_cm4.h"
+#elif defined(STM32MP151Fxx)
+ #include "stm32mp151fxx_cm4.h"
+#else
+ #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
+#endif
+#endif
+
+#if defined(CORE_CA7)
+#if defined(STM32MP15xx) /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
+ #include "stm32mp157cxx_ca7.h"
+#elif defined(STM32MP157Axx)
+ #include "stm32mp157axx_ca7.h"
+#elif defined(STM32MP157Cxx)
+ #include "stm32mp157cxx_ca7.h"
+#elif defined(STM32MP157Dxx)
+ #include "stm32mp157dxx_ca7.h"
+#elif defined(STM32MP157Fxx)
+ #include "stm32mp157fxx_ca7.h"
+#elif defined(STM32MP153Axx)
+ #include "stm32mp153axx_ca7.h"
+#elif defined(STM32MP153Cxx)
+ #include "stm32mp153cxx_ca7.h"
+#elif defined(STM32MP153Dxx)
+ #include "stm32mp153dxx_ca7.h"
+#elif defined(STM32MP153Fxx)
+ #include "stm32mp153fxx_ca7.h"
+#elif defined(STM32MP151Axx)
+ #include "stm32mp151axx_ca7.h"
+#elif defined(STM32MP151Cxx)
+ #include "stm32mp151cxx_ca7.h"
+#elif defined(STM32MP151Dxx)
+ #include "stm32mp151dxx_ca7.h"
+#elif defined(STM32MP151Fxx)
+ #include "stm32mp151fxx_ca7.h"
+#else
+ #error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
+#endif
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+
+/**
+ * @}
+ */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32mp1xx_hal_conf.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32MP1xx_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h
new file mode 100644
index 0000000..9f8b1a5
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Device/ST/STM32MP1xx/Include/system_stm32mp1xx.h
@@ -0,0 +1,106 @@
+/**
+ ******************************************************************************
+ * @file system_stm32mp1xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device System Source File for STM32MP1xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32mp1xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32MP1XX_H
+#define __SYSTEM_STM32MP1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup STM32MP1xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32MP1xx_System_Exported_types
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+extern uint32_t SystemCoreClock; /*!< System Core1 Clock Frequency */
+extern uint32_t SystemCore1Clock; /*!< System Core1 Clock Frequency */
+extern uint32_t SystemCore2Clock; /*!< System Core2 Clock Frequency */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32MP1xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32MP1XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armcc.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 0000000..7d751fb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armclang.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 0000000..d8031b0
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1869 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_compiler.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 0000000..79a2cac
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,266 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include <cmsis_ccs.h>
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_gcc.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 0000000..1bd41a4
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,2085 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.0.4
+ * @date 09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_iccarm.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_iccarm.h
new file mode 100644
index 0000000..3c90a2c
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_iccarm.h
@@ -0,0 +1,935 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.0.7
+ * @date 19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include <intrinsics.h>
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_version.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_version.h
new file mode 100644
index 0000000..ae3f2e3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.2
+ * @date 19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mbl.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 0000000..ec76ab2
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1918 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MBL_REV
+ #define __ARMv8MBL_REV 0x0000U
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mml.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 0000000..2d0f106
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2927 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000..6f82227
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0.h
@@ -0,0 +1,949 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0plus.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000..b9377e8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1083 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.6
+ * @date 28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm1.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm1.h
new file mode 100644
index 0000000..fd1c407
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm1.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file core_cm1.h
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M1
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (1U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM1_REV
+ #define __CM1_REV 0x0100U
+ #warning "__CM1_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm23.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm23.h
new file mode 100644
index 0000000..8202a8d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1993 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm3.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000..b0dfbd3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1941 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm33.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm33.h
new file mode 100644
index 0000000..02f82e2
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm33.h
@@ -0,0 +1,3002 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_PCS_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm4.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000..308b868
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm7.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000..ada6c2a
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2671 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += (uint32_t)linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc000.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000..9086c64
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1022 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.5
+ * @date 28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc300.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000..665822d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1915 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.6
+ * @date 04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv7.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 0000000..7d4b600
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if non-shareable) or 010b (if shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv8.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv8.h
new file mode 100644
index 0000000..99ee9f9
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/mpu_armv8.h
@@ -0,0 +1,333 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M MPU
+ * @version V5.0.4
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ ((BASE & MPU_RBAR_BASE_Msk) | \
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DSB();
+ __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/tz_context.h b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/tz_context.h
new file mode 100644
index 0000000..d4c1474
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/CMSIS/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file tz_context.h
+ * @brief Context Management for Armv8-M TrustZone
+ * @version V1.0.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000..dfbdde7
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3780 @@
+/**
+ ******************************************************************************
+ * @file stm32_hal_legacy.h
+ * @author MCD Application Team
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * macros and functions maintained for legacy purpose.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define AES_FLAG_RDERR CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP ADC_REGULAR_GROUP
+#define INJECTED_GROUP ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT ADC_AWD_EVENT
+#define AWD1_EVENT ADC_AWD1_EVENT
+#define AWD2_EVENT ADC_AWD2_EVENT
+#define AWD3_EVENT ADC_AWD3_EVENT
+#define OVR_EVENT ADC_OVR_EVENT
+#define JQOVF_EVENT ADC_JQOVF_EVENT
+#define ALL_CHANNELS ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
+/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define DAC1_CHANNEL_1 DAC_CHANNEL_1
+#define DAC1_CHANNEL_2 DAC_CHANNEL_2
+#define DAC2_CHANNEL_1 DAC_CHANNEL_1
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW OB_IWDG_SW
+#define OB_WDG_HW OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+#if defined(STM32G0)
+#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+ * @{
+ */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define GET_GPIO_SOURCE GPIO_GET_INDEX
+#define GET_GPIO_INDEX GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
+ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+ */
+#define HRTIM_EVENTSRC_1 (0x00000000U)
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+ * set/reset crossbar of a timer output
+ */
+#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+ * by a timer
+ */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+ */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define KR_KEY_RELOAD IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE IWDG_KEY_ENABLE
+#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE NOR_WRITE
+#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+ #define I2S_IT_TXE I2S_IT_TXP
+ #define I2S_IT_RXNE I2S_IT_RXP
+
+ #define I2S_FLAG_TXE I2S_FLAG_TXP
+ #define I2S_FLAG_RXNE I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+ #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define FORMAT_BIN RTC_FORMAT_BIN
+#define FORMAT_BCD RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+ #define SPI_FLAG_TXE SPI_FLAG_TXP
+ #define SPI_FLAG_RXNE SPI_FLAG_RXP
+
+ #define SPI_IT_TXE SPI_IT_TXP
+ #define SPI_IT_RXNE SPI_IT_RXP
+
+ #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
+ #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
+ #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
+ #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1 TIM_DMABASE_CR1
+#define TIM_DMABase_CR2 TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER TIM_DMABASE_DIER
+#define TIM_DMABase_SR TIM_DMABASE_SR
+#define TIM_DMABase_EGR TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER TIM_DMABASE_CCER
+#define TIM_DMABase_CNT TIM_DMABASE_CNT
+#define TIM_DMABase_PSC TIM_DMABASE_PSC
+#define TIM_DMABase_ARR TIM_DMABASE_ARR
+#define TIM_DMABase_RCR TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1 TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2 TIM_DMABASE_OR2
+#define TIM_DMABase_OR3 TIM_DMABASE_OR3
+#define TIM_DMABase_OR TIM_DMABASE_OR
+
+#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+
+#define __DIV_LPUART UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED USART_NACK_ENABLE
+#define USARTNACK_DISABLED USART_NACK_DISABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CFR_BASE WWDG_CFR_BASE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+#define VLAN_TAG ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
+
+/**
+ * @}
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
+/**
+ * @}
+ */
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
+
+#define DBP_BitNumber DBP_BIT_NUMBER
+#define PVDE_BitNumber PVDE_BIT_NUMBER
+#define PMODE_BitNumber PMODE_BIT_NUMBER
+#define EWUP_BitNumber EWUP_BIT_NUMBER
+#define FPDS_BitNumber FPDS_BIT_NUMBER
+#define ODEN_BitNumber ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
+#define BRE_BitNumber BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+
+ /**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#ifdef HAL_DMA_MODULE_ENABLED
+#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError TIM_DMAError
+#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#endif
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#ifdef HAL_DMA_MODULE_ENABLED
+#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define AES_IT_CC CRYP_IT_CC
+#define AES_IT_ERR CRYP_IT_ERR
+#define AES_FLAG_CCF CRYP_FLAG_CCF
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __ADC_ENABLE __HAL_ADC_ENABLE
+#define __ADC_DISABLE __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
+#define __ADC_IS_ENABLED ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1 ADC_SQR1
+#define __HAL_ADC_SMPR1 ADC_SMPR1
+#define __HAL_ADC_SMPR2 ADC_SMPR2
+#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+ #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+ #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+ #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+ #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32F3)
+#define COMP_START __HAL_COMP_ENABLE
+#define COMP_STOP __HAL_COMP_DISABLE
+#define COMP_LOCK __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+ __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro */
+/* is COMP_FLAG_LOCK. */
+/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
+/* argument. */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+ * @}
+ */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+ * @}
+ */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+ ((WAVE) == DAC_WAVE_NOISE)|| \
+ ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_WRPAREA IS_OB_WRPAREA
+#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE IS_FLASH_TYPEERASE
+#define IS_NBSECTORS IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
+#define __HAL_I2C_SPEED I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+ #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __IRDA_DISABLE __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+ * @{
+ */
+
+#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14 RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV RCC_MCODIV_1
+#define RCC_MCO_DIV1 RCC_MCODIV_1
+#define RCC_MCO_DIV2 RCC_MCODIV_2
+#define RCC_MCO_DIV4 RCC_MCODIV_4
+#define RCC_MCO_DIV8 RCC_MCODIV_8
+#define RCC_MCO_DIV16 RCC_MCODIV_16
+#define RCC_MCO_DIV32 RCC_MCODIV_32
+#define RCC_MCO_DIV64 RCC_MCODIV_64
+#define RCC_MCO_DIV128 RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#else
+#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB RCC_CR_HSION_BB
+#define CR_CSSON_BB RCC_CR_CSSON_BB
+#define CR_PLLON_BB RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB RCC_CR_MSION_BB
+#define CSR_LSION_BB RCC_CSR_LSION_BB
+#define CSR_LSEON_BB RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB RCC_CR_HSEON_BB
+#define CSR_RMVF_BB RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#else
+#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif /* STM32F1 */
+
+#define IS_ALARM IS_RTC_ALARM
+#define IS_ALARM_MASK IS_RTC_ALARM_MASK
+#define IS_TAMPER IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
+
+#if defined(STM32F4) || defined(STM32F2)
+#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define SDMMC1_IRQn SDIO_IRQn
+#define SDMMC1_IRQHandler SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
+#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
+#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
+#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
+#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
+#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
+#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
+#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
+#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
+#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
+#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
+#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
+#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
+#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
+#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
+#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
+#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define SDIO_IRQn SDMMC1_IRQn
+#define SDIO_IRQHandler SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
+#define __USART_ENABLE __HAL_USART_ENABLE
+#define __USART_DISABLE __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
+/**
+ * @}
+ */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+ * @}
+ */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h
new file mode 100644
index 0000000..c742150
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h
@@ -0,0 +1,802 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal.h
+ * @author MCD Application Team
+ * @brief This file contains all the functions prototypes for the HAL
+ * module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_H
+#define STM32MP1xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_conf.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Types HAL Exported Types
+ * @{
+ */
+/** @defgroup HAL_Exported_Types_Group1 Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Types_Group2 HDP SW Signal
+ * @{
+ */
+
+ /**
+ * @brief HDP SW Signal SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ HDP_SW_SIGNAL_RESET = 0,
+ HDP_SW_SIGNAL_SET
+}HDP_SwSignalState;
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_Exported_Constants_Group1 SYSCFG VREFBUF Voltage Scale
+ * @{
+ */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */
+
+
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
+ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Constants_Group2 SYSCFG VREFBUF High Impedance
+ * @{
+ */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_Exported_Constants_Group3 SYSCFG Ethernet Config
+ * @{
+ */
+
+#define SYSCFG_ETH_MII SYSCFG_PMCSETR_ETH_SELMII_SEL /*!< Select the Media Independent Interface */
+#define SYSCFG_ETH_GMII ((uint32_t)0x00000000) /*!< Select the Gigabit Media Independent Interface */
+#define SYSCFG_ETH_RMII SYSCFG_PMCSETR_ETH_SEL_2 /*!< Select the Reduced Media Independent Interface */
+#define SYSCFG_ETH_RGMII SYSCFG_PMCSETR_ETH_SEL_0 /*!< Select the Reduced Gigabit Media Independent Interface */
+
+#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \
+ ((CONFIG) == SYSCFG_ETH_RMII) || \
+ ((CONFIG) == SYSCFG_ETH_GMII) || \
+ ((CONFIG) == SYSCFG_ETH_RGMII))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_Exported_Constants_Group4 SYSCFG Analog Switch Config
+ * @{
+ */
+#define SYSCFG_SWITCH_PA0 SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< Select PA0 analog switch */
+#define SYSCFG_SWITCH_PA1 SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< Select PA1 analog switch */
+
+
+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
+ (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1))
+
+
+#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 analog switch opened */
+#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */
+#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 analog switch opened */
+#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/
+
+#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
+ (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \
+ (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \
+ (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE))
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Constants_Group5 SYSCFG IOCompenstionCell Config
+ * @{
+ */
+#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
+#define SYSCFG_REGISTER_CODE SYSCFG_CMPCR_SW_CTRL /*!< Code from the SYSCFG compensation cell code register */
+
+#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
+ ((SELECT) == SYSCFG_REGISTER_CODE))
+
+#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10))
+
+/** @brief Check SYSCFG Compensation Cell Ready flag is set or not.
+ * @retval State of bit (1 or 0)
+ */
+#define __HAL_SYSCFG_CMP_CELL_GET_FLAG() ((READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)) ? 1U : 0U)
+
+/**
+ * @brief Get I/O compensation cell value for PMOS transistors
+ * @retval The I/O compensation cell value for PMOS transistors
+ */
+#define __HAL_SYSCFG_GET_PMOS_CMP() (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_APSRC))
+
+/**
+ * @brief Get I/O compensation cell value for NMOS transistors
+ * @retval Returned value is the I/O compensation cell value for NMOS transistors
+ */
+#define __HAL_SYSCFG_GET_NMOS_CMP() (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_ANSRC))
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Exported_Constants_Group6 SYSCFG IOControl HighSpeed Config
+ * @{
+ */
+
+#define SYSCFG_HIGHSPEED_TRACE_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_TRACE /*!< High Speed Low Voltage Pad mode Enable when a TRACEx signal is selected in AFMUX */
+#define SYSCFG_HIGHSPEED_QUADSPI_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI /*!< High Speed Low Voltage Pad mode Enable when a QUADSPI_x signal is selected in AFMUX */
+#define SYSCFG_HIGHSPEED_ETH_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_ETH /*!< High Speed Low Voltage Pad mode Enable when a ETH_x signal is selected in AFMUX */
+#define SYSCFG_HIGHSPEED_SDMMC_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_SDMMC /*!< High Speed Low Voltage Pad mode Enable when a SDMMCy_x signal is selected in AFMUX */
+#define SYSCFG_HIGHSPEED_SPI_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_SPI /*!< High Speed Low Voltage Pad mode Enable when a SPIy_x signal is selected in AFMUX */
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_Exported_Constants_Group7 HDP Software signal define
+ * @{
+ */
+#define HDP_SW_SIGNAL_0 ((uint8_t)0x01U) /* HDP Software signal 0 selected */
+#define HDP_SW_SIGNAL_1 ((uint8_t)0x02U) /* HDP Software signal 1 selected */
+#define HDP_SW_SIGNAL_2 ((uint8_t)0x04U) /* HDP Software signal 2 selected */
+#define HDP_SW_SIGNAL_3 ((uint8_t)0x08U) /* HDP Software signal 3 selected */
+#define HDP_SW_SIGNAL_4 ((uint8_t)0x10U) /* HDP Software signal 4 selected */
+#define HDP_SW_SIGNAL_5 ((uint8_t)0x20U) /* HDP Software signal 5 selected */
+#define HDP_SW_SIGNAL_6 ((uint8_t)0x40U) /* HDP Software signal 6 selected */
+#define HDP_SW_SIGNAL_7 ((uint8_t)0x80U) /* HDP Software signal 7 selected */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+ * @{
+ */
+
+/** @brief Freeze/Unfreeze Peripherals in Debug mode
+ */
+#if defined (CORE_CM4)
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C5_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
+#endif
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
+#endif
+
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
+#endif
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
+#endif
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
+#endif
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
+#endif
+
+#if defined(DBGMCU_APB5_FZ_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
+#endif
+#if defined(DBGMCU_APB5_FZ_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_RTC_STOP)
+#endif
+#if defined(DBGMCU_APB5_FZ_DBG_I2C6_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
+#endif
+#elif defined(CORE_CA7)
+
+#if defined(DBGMCU_APB4_FZ_DBG_IWDG2_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG2() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4_FZ_DBG_IWDG2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG2() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4_FZ_DBG_IWDG2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#endif
+#if defined(DBGMCU_APB1_FZ_DBG_I2C5_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
+#endif
+
+#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
+#endif
+#if defined(DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
+#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
+#endif
+
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
+#endif
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
+#endif
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
+#endif
+#if defined(DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
+#endif
+
+#if defined(DBGMCU_APB5_FZ_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
+#endif
+#if defined(DBGMCU_APB5_FZ_DBG_IWDG1_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG1() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_IWDG1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG1() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_IWDG1_STOP)
+#endif
+#if defined(DBGMCU_APB5_FZ_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_RTC_STOP)
+#endif
+#if defined(DBGMCU_APB5_FZ_DBG_I2C6_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
+#endif
+
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup HDP_Exported_Macros HDP Exported Macros
+ * @{
+ */
+
+/** @addtogroup HDP_Enable
+ * @{
+ */
+#define __HAL_HDP_ENABLE() SET_BIT(HDP->HDP_CTRL, HDP_CTRL_EN)
+/**
+ * @}
+ */
+
+
+
+/** @addtogroup HDP_Configure_SW_Programmable_Signals
+ * @{
+ */
+
+/** @brief This macros allows atomic write of HDP_GPOVAL register
+ It uses HDP_GPOSET and HDP_GPOCLR regsiters to toogle
+ *
+ * @param __HDP_SW_Signal__: specifies the sw signal bit to be written.
+ * This parameter can be one of HDP_SW_SIGNAL_x(s) where x can be (0..7).
+ * @param __HDP_SwSignalState__: specifies the value to be written to the selected bit.
+ * This parameter can be one of the HDP_SwSignalState enum values:
+ * @arg HDP_SW_SIGNAL_RESET: to clear the signal pin
+ * @arg HDP_SW_SIGNAL_SET: to set the signal pin
+ */
+#define __HAL_HDP_ATOMIC_WRITE_GPOVAL(__HDP_SW_Signal__, __HDP_SwSignalState__) \
+ do { \
+ if ((__HDP_SwSignalState__) != HDP_SW_SIGNAL_RESET) \
+ { \
+ WRITE_REG(HDP->HDP_GPOSET, (uint8_t)(__HDP_SW_Signal__)); \
+ } \
+ else \
+ { \
+ WRITE_REG(HDP->HDP_GPOCLR, (uint8_t)(__HDP_SW_Signal__)); \
+ } \
+ } while(0)
+
+/** @brief This macros allows non-atomic write of HDP_GPOVAL register
+ *
+ * @param __GPOValue__: specifies the value to set in HDP_GPOVAL register
+ *
+ */
+#define __HAL_HDP_NON_ATOMIC_WRITE_GPOVAL(__GPOValue__) WRITE_REG(HDP->HDP_GPOVAL, (uint8_t)(__GPOValue__))
+
+/** @brief This macros returns value of HDP_GPOVAL register
+ *
+ * @retval the value to set in HDP_GPOVAL register
+ */
+#define __HAL_HDP_READ_GPOVAL() READ_REG(HDP->HDP_GPOVAL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup HDP0_MUX0_Config
+ * @{
+ */
+#define __HAL_HDP0_SELECT_PWR_PWRWAKE_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) 0x00000000))
+#define __HAL_HDP0_SELECT_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_0))
+#define __HAL_HDP0_SELECT_PWR_STDBY_WKUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_1))
+#define __HAL_HDP0_SELECT_PWR_ENCOMP_VDDCORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0))
+#define __HAL_HDP0_SELECT_BSEC_OUT_SEC_NIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2))
+#define __HAL_HDP0_SELECT_RCC_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1))
+#define __HAL_HDP0_SELECT_GPU_DBG7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0))
+#define __HAL_HDP0_SELECT_DDRCTRL_IP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3))
+#define __HAL_HDP0_SELECT_PWR_DDR_RET_ENABLE_N() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3 | HDP_MUX_MUX0_0))
+#define __HAL_HDP0_SELECT_GPOVAL_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3 | HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HDP1_MUX1_Config
+ * @{
+ */
+#define __HAL_HDP1_SELECT_PWR_PWRWAKE_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) 0x00000000))
+#define __HAL_HDP1_SELECT_CM4_HALTED() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_0))
+#define __HAL_HDP1_SELECT_CA7_nAXIERRIRQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_1))
+#define __HAL_HDP1_SELECT_PWR_OKIN_MR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0))
+#define __HAL_HDP1_SELECT_BSEC_OUT_SEC_DBGEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2))
+#define __HAL_HDP1_SELECT_EXTI_SYS_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_0))
+#define __HAL_HDP1_SELECT_RCC_PWRDS_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1))
+#define __HAL_HDP1_SELECT_GPU_DBG6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0))
+#define __HAL_HDP1_SELECT_DDRCTRL_DFI_CTRLUPD_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3))
+#define __HAL_HDP1_SELECT_DDRCTRL_CACTIVE_DDRC_ASR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3 | HDP_MUX_MUX1_0))
+#define __HAL_HDP1_SELECT_GPOVAL_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3 | HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HDP2_MUX2_Config
+ * @{
+ */
+#define __HAL_HDP2_SELECT_PWR_PWRWAKE_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) 0x00000000))
+#define __HAL_HDP2_SELECT_CM4_RXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_0))
+#define __HAL_HDP2_SELECT_CA7_nPMUIRQ1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_1))
+#define __HAL_HDP2_SELECT_CA7_nFIQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0))
+#define __HAL_HDP2_SELECT_BSEC_IN_RSTCORE_n() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2))
+#define __HAL_HDP2_SELECT_EXTI_C2_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_0))
+#define __HAL_HDP2_SELECT_RCC_PWRDS_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1))
+#define __HAL_HDP2_SELECT_GPU_DBG5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0))
+#define __HAL_HDP2_SELECT_DDRCTRL_DFI_INIT_COMPLETE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3))
+#define __HAL_HDP2_SELECT_DDRCTRL_PERF_OP_IS_REFRESH() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_0))
+#define __HAL_HDP2_SELECT_DDRCTRL_GSKP_DFI_LP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_1))
+#define __HAL_HDP2_SELECT_GPOVAL_2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HDP3_MUX3_Config
+ * @{
+ */
+#define __HAL_HDP3_SELECT_PWR_SEL_VTH_VDD_CORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) 0x00000000))
+#define __HAL_HDP3_SELECT_CM4_TXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_0))
+#define __HAL_HDP3_SELECT_CA7_nPMUIRQ0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_1))
+#define __HAL_HDP3_SELECT_CA7_nFIQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0))
+#define __HAL_HDP3_SELECT_BSEC_OUT_SEC_DFTLOCK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2))
+#define __HAL_HDP3_SELECT_EXTI_C1_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_0))
+#define __HAL_HDP3_SELECT_RCC_PWRDS_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1))
+#define __HAL_HDP3_SELECT_GPU_DBG4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0))
+#define __HAL_HDP3_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3))
+#define __HAL_HDP3_SELECT_DDRCTRL_CACTIVE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3 | HDP_MUX_MUX3_0))
+#define __HAL_HDP3_SELECT_GPOVAL_3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3 | HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HDP4_MUX4_Config
+ * @{
+ */
+#define __HAL_HDP4_SELECT_PWR_MPUCR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) 0x00000000))
+#define __HAL_HDP4_SELECT_CM4_SLEEPING() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_0))
+#define __HAL_HDP4_SELECT_CA7_nRESET1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_1))
+#define __HAL_HDP4_SELECT_CA7_nIRQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0))
+#define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DFTEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2))
+#define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DBGSWENABLE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_0))
+#define __HAL_HDP4_SELECT_ETH_OUT_PMT_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1))
+#define __HAL_HDP4_SELECT_GPU_DBG3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0))
+#define __HAL_HDP4_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3))
+#define __HAL_HDP4_SELECT_DDRCTRL_CACTIVE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3 | HDP_MUX_MUX4_0))
+#define __HAL_HDP4_SELECT_GPOVAL_4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3 | HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HDP5_MUX5_Config
+ * @{
+ */
+#define __HAL_HDP5_SELECT_CA7_STANDBYWFIL2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) 0x00000000))
+#define __HAL_HDP5_SELECT_PWR_VTH_VDDCORE_ACK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_0))
+#define __HAL_HDP5_SELECT_CA7_nRESET0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_1))
+#define __HAL_HDP5_SELECT_CA7_nIRQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0))
+#define __HAL_HDP5_SELECT_BSEC_IN_PWROK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2))
+#define __HAL_HDP5_SELECT_BSEC_OUT_SEC_DEVICEEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_0))
+#define __HAL_HDP5_SELECT_ETH_OUT_LPI_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1))
+#define __HAL_HDP5_SELECT_GPU_DBG2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0))
+#define __HAL_HDP5_SELECT_DDRCTRL_CACTIVE_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3))
+#define __HAL_HDP5_SELECT_DDRCTRL_WR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3 | HDP_MUX_MUX5_0)))
+#define __HAL_HDP5_SELECT_GPOVAL_5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3 | HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0))
+/**
+ * @}
+ */
+
+/** @addtogroup HDP6_MUX6_Config
+ * @{
+ */
+#define __HAL_HDP6_SELECT_CA7_STANDBYWFI1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) 0x00000000))
+#define __HAL_HDP6_SELECT_CA7_STANDBYWFE1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_0))
+#define __HAL_HDP6_SELECT_CA7_EVENTO() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_1))
+#define __HAL_HDP6_SELECT_CA7_DBGACK1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0))
+#define __HAL_HDP6_SELECT_BSEC_OUT_SEC_SPNIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_0))
+#define __HAL_HDP6_SELECT_ETH_OUT_MAC_SPEED_O1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1))
+#define __HAL_HDP6_SELECT_GPU_DBG1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0))
+#define __HAL_HDP6_SELECT_DDRCTRL_CSYSACK_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3))
+#define __HAL_HDP6_SELECT_DDRCTRL_LPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3 | HDP_MUX_MUX6_0))
+#define __HAL_HDP6_SELECT_GPOVAL_6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3 | HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0))
+
+/**
+ * @}
+ */
+
+/** @addtogroup HDP7_MUX7_Config
+ * @{
+ */
+#define __HAL_HDP7_SELECT_CA7_STANDBYWFI0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) 0x00000000))
+#define __HAL_HDP7_SELECT_CA7_STANDBYWFE0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_0))
+#define __HAL_HDP7_SELECT_CA7_DBGACK0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0))
+#define __HAL_HDP7_SELECT_BSEC_OUT_FUSE_OK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2))
+#define __HAL_HDP7_SELECT_BSEC_OUT_SEC_SPIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_0))
+#define __HAL_HDP7_SELECT_ETH_OUT_MAC_SPEED_O0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1))
+#define __HAL_HDP7_SELECT_GPU_DBG0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0))
+#define __HAL_HDP7_SELECT_DDRCTRL_CSYSREQ_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3))
+#define __HAL_HDP7_SELECT_DDRCTRL_HPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3 | HDP_MUX_MUX7_0))
+#define __HAL_HDP7_SELECT_GPOVAL_7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3 | HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ******************************/
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+void HAL_EnableDBGWakeUp(void);
+void HAL_DisableDBGWakeUp(void);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions ************************************************/
+/** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
+void HAL_SYSCFG_EnableBOOST(void);
+void HAL_SYSCFG_DisableBOOST(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+void HAL_SYSCFG_EnableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal);
+void HAL_SYSCFG_DisableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal);
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+HAL_StatusTypeDef HAL_SYSCFG_EnableIOCompensation(void);
+void HAL_SYSCFG_DisableIOCompensation(void);
+void HAL_EnableDBGSleepMode(void);
+void HAL_DisableDBGSleepMode(void);
+void HAL_EnableDBGStopMode(void);
+void HAL_DisableDBGStopMode(void);
+void HAL_EnableDBGStandbyMode(void);
+void HAL_DisableDBGStandbyMode(void);
+void HAL_EnableDBGWakeUp(void);
+void HAL_DisableDBGWakeUp(void);
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
new file mode 100644
index 0000000..54a9c76
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
@@ -0,0 +1,1814 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_ADC_H
+#define STM32MP1xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32mp1xx_ll_adc.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC group regular oversampling structure definition
+ */
+typedef struct
+{
+ uint32_t Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value between 1 and 1024 */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
+ The oversampling is either temporary stopped or reset upon an injected
+ sequence interruption.
+ If oversampling is enabled on both regular and injected groups, this parameter
+ is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
+ (the oversampling buffer is zeroed during injection sequence).
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
+
+} ADC_OversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC instance and ADC group regular.
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+ * ScanConvMode, EOCSelection, LowPowerAutoWait.
+ * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
+ * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
+ * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled
+ * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
+ * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
+ * (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
+ This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
+ Note: The ADC clock configuration is common to all ADC instances.
+ Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
+ AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
+ Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
+ if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
+ must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
+ Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
+ Note: This parameter can be modified only if all ADC instances are disabled. */
+
+ uint32_t Resolution; /*!< Configure the ADC resolution.
+ This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
+ This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
+ Scan direction is upward: from rank 1 to rank 'n'.
+ This parameter can be a value of @ref ADC_Scan_mode */
+
+ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
+ This parameter can be a value of @ref ADC_EOCSelection. */
+
+ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
+ conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
+ using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
+ This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
+ for low frequency applications.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
+ to free the IRQ vector sequencer.
+ Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
+ use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
+ (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+
+ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
+ after the first ADC conversion start trigger occurred (software start or external trigger).
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
+ To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+ Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
+ continuous mode or external trigger that could launch a conversion). */
+
+ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
+ (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
+ If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+
+ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
+ If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+ This parameter can be a value of @ref ADC_regular_external_trigger_source.
+ Caution: external trigger source is common to all ADC instances. */
+
+ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
+ If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+ This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+ uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
+ Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
+ This parameter can be a value of @ref ADC_ConversionDataManagement.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups
+ (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
+
+ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+ This parameter applies to ADC group regular only.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+ Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
+ end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
+ HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
+ Note: Error reporting with respect to the conversion mode:
+ - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
+ overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
+ - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
+
+ uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
+ This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
+ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
+
+ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
+ Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
+
+} ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of ADC channel for regular group
+ * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+ * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
+ * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
+ * on the fly).
+ */
+typedef struct
+{
+ uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+ uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
+ This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
+ Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
+ the new channel setting (or parameter number of conversions adjusted) */
+
+ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+ Caution: This parameter applies to a channel that can be used into regular and/or injected group.
+ It overwrites the last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values. */
+
+ uint32_t SingleDiff; /*!< Select single-ended or differential input.
+ In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+ This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
+ Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+ It overwrites the last setting.
+ Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
+ of another parameter update on the fly) */
+
+ uint32_t OffsetNumber; /*!< Select the offset number
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
+ Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
+
+ uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,
+ 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch a conversion). */
+
+ FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.
+ This parameter is applied only for 16-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE.*/
+
+ FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
+ This parameter is applied only for 16-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} ADC_ChannelConfTypeDef;
+
+/**
+ * @brief Structure definition of ADC analog watchdog
+ * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
+ */
+typedef struct
+{
+ uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
+ For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
+ For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+ This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+ For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
+ For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
+ This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
+ For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
+ For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
+ Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
+ between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ impacted: the comparison of analog watchdog thresholds is done
+ on oversampling intermediate computation (after ratio, before shift
+ application): intermediate register bitfield [32:7] (26 most significant bits). */
+
+ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
+ Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
+ between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
+ Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
+ the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
+ Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ impacted: the comparison of analog watchdog thresholds is done
+ on oversampling intermediate computation (after ratio, before shift
+ application): intermediate register bitfield [32:7] (26 most significant bits). */
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+ * @brief ADC group injected contexts queue configuration
+ * @note Structure intended to be used only through structure "ADC_HandleTypeDef"
+ */
+typedef struct
+{
+ uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
+ HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+ JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
+} ADC_InjectionConfigTypeDef;
+
+/** @defgroup ADC_States ADC States
+ * @{
+ */
+
+/**
+ * @brief HAL ADC state machine: ADC states definition (bitfields)
+ * @note ADC state machine is managed by bitfields, state must be compared
+ * with bit by bit.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief ADC handle Structure definition
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+ ADC_TypeDef *Instance; /*!< Register base address */
+ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
+#ifdef HAL_DMA_MODULE_ENABLED
+ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+#endif
+ HAL_LockTypeDef Lock; /*!< ADC locking object */
+ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
+ __IO uint32_t ErrorCode; /*!< ADC Error code */
+ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
+ void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
+ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
+ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
+ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
+ HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
+ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+ * @{
+ */
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
+ enable/disable, erroneous state, ...) */
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+
+#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
+#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
+#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
+#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
+#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
+#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
+#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
+#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
+#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
+#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
+#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits */
+#define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */
+#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+ * @{
+ */
+#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
+#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
+#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+ * @{
+ */
+#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
+#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+ * @{
+ */
+#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
+#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
+#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
+#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
+#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
+#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
+#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
+#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles */
+#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles */
+#define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles */
+#define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles */
+#define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles */
+#define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles */
+#define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode
+ * @{
+ */
+#define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)
+#define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
+/* all ADC instances (refer to Reference Manual). */
+#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
+#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC2. */
+#define ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_VCORE) /*!< ADC internal channel connected to VddCore, channel specific to ADC2. */
+#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC2. */
+#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC2. */
+#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
+#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
+ * @{
+ */
+#define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register only */
+#define ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
+#define ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
+#define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1) /*!< DMA circular mode selected */
+/**
+ * @}
+ */
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
+ * @{
+ */
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
+ * @{
+ */
+#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
+#define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift
+ * @{
+ */
+#define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */
+#define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */
+#define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */
+#define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */
+#define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */
+#define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */
+#define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */
+#define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */
+#define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */
+#define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */
+#define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */
+#define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */
+#define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */
+#define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */
+#define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */
+#define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
+ * @{
+ */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_Event_type ADC Event type
+ * @{
+ */
+#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
+#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
+#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+/**
+ * @}
+ */
+#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+ * @{
+ */
+#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
+#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
+#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
+#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
+
+#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+ * @{
+ */
+#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Verify the ADC data conversion setting.
+ * @param DATA : programmed DATA conversion mode.
+ * @retval SET (DATA is a valid value) or RESET (DATA is invalid)
+ */
+#define IS_ADC_CONVERSIONDATAMGT(DATA) \
+ ((((DATA) == ADC_CONVERSIONDATA_DR)) || \
+ (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \
+ (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
+ (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
+
+/**
+ * @brief Return resolution bits in CFGR register RES[1:0] field.
+ * @param __HANDLE__ ADC handle
+ * @retval Value of bitfield RES in CFGR register.
+ */
+#define ADC_GET_RESOLUTION(__HANDLE__) \
+ (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+ * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+ * @brief Verification of ADC state: enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @retval SET (ADC enabled) or RESET (ADC disabled)
+ */
+#define ADC_IS_ENABLE(__HANDLE__) \
+ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
+ ) ? SET : RESET)
+
+/**
+ * @brief Check if conversion is on going on regular group.
+ * @param __HANDLE__ ADC handle
+ * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)
+ */
+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
+ (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))
+
+/**
+ * @brief Check if ADC clock mode is synchronous
+ * @param __HANDLE__: ADC handle
+ * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous)
+ */
+#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \
+ (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \
+ ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL): RESET)
+
+/**
+ * @brief Simultaneously clear and set specific bits of the handle State.
+ * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+ * the first parameter is the ADC handle State, the second parameter is the
+ * bit field to clear, the third and last parameter is the bit field to set.
+ * @retval None
+ */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+ * @brief Verify that a given value is aligned with the ADC resolution range.
+ * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits).
+ * @param __ADC_VALUE__ value checked against the resolution.
+ * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+ */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/**
+ * @brief Verify the length of the scheduled regular conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+
+
+/**
+ * @brief Verify the number of scheduled regular conversions in discontinuous mode.
+ * @param NUMBER number of scheduled regular conversions in discontinuous mode.
+ * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
+ */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
+
+
+/**
+ * @brief Verify the ADC clock setting.
+ * @param __ADC_CLOCK__ programmed ADC clock.
+ * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
+ */
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
+ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
+
+/**
+ * @brief Verify the ADC resolution setting.
+ * @param __RESOLUTION__ programmed ADC resolution.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+ */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+ ((__RESOLUTION__) == ADC_RESOLUTION_8B) )
+/**
+ * @brief Verify the ADC resolution setting when limited to 8 bits.
+ * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits.
+ * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+ */
+#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
+
+/**
+ * @brief Verify the ADC scan mode.
+ * @param __SCAN_MODE__ programmed ADC scan mode.
+ * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+ */
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+ ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
+
+/**
+ * @brief Verify the ADC edge trigger setting for regular group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
+
+/**
+ * @brief Verify the ADC regular conversions external trigger.
+ * @param __REGTRIG__ programmed ADC regular conversions external trigger.
+ * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
+ */
+#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START) )
+
+/**
+ * @brief Verify the ADC regular conversions check for converted data availability.
+ * @param __EOC_SELECTION__ converted data availability check.
+ * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
+ */
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
+ ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
+
+/**
+ * @brief Verify the ADC regular conversions overrun handling.
+ * @param __OVR__ ADC regular conversions overrun handling.
+ * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+ */
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
+ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
+
+/**
+ * @brief Verify the ADC conversions sampling time.
+ * @param __TIME__ ADC conversions sampling time.
+ * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
+ */
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \
+ ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) )
+
+/**
+ * @brief Verify the ADC regular channel setting.
+ * @param __CHANNEL__ programmed ADC regular channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+ ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Fixed timeout values for ADC conversion (including sampling time) */
+/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
+/* Maximum conversion time is 12.5 + Maximum sampling time */
+/* or 12.5 + 640.5 = 653 ADC clock cycles */
+/* Minimum ADC Clock frequency is 0.14 MHz */
+/* Maximum conversion time is */
+/* 653 / 0.14 MHz = 4.66 ms */
+#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */
+
+/* Delay for temperature sensor stabilization time. */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
+/* Unit: us */
+#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+
+/* Delay for ADC voltage regulator startup time */
+/* Maximum delay is 10 microseconds */
+/* (refer device RM, parameter Tadcvreg_stup). */
+#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+ * @{
+ */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user. */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+ * @{
+ */
+
+/** @brief Reset ADC handle state.
+ * @param __HANDLE__ ADC handle
+ * @retval None
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
+
+/**
+ * @brief Enable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ * @retval None
+ */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable ADC interrupt.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC Interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ * @retval None
+ */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
+ * @param __HANDLE__ ADC handle
+ * @param __INTERRUPT__ ADC interrupt source to check
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_IT_RDY ADC Ready interrupt source
+ * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
+ * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
+ * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_OVR ADC overrun interrupt source
+ * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
+ * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
+ * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
+ * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+ * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
+ * @retval State of interruption (SET or RESET)
+ */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified ADC flag is set or not.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
+ * @retval State of flag (TRUE or FALSE).
+ */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
+ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+ * @brief Clear the specified ADC flag.
+ * @param __HANDLE__ ADC handle
+ * @param __FLAG__ ADC flag
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_FLAG_RDY ADC Ready flag
+ * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
+ * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
+ * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
+ * @arg @ref ADC_FLAG_OVR ADC overrun flag
+ * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
+ * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
+ * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
+ * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
+ * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
+ * @retval None
+ */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals ADC_CHANNEL_x.
+ * @note Example:
+ * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_19
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_VCORE (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+ * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_19
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_VCORE (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_19
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_VCORE (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0 (3)
+ * @arg @ref ADC_CHANNEL_1 (3)
+ * @arg @ref ADC_CHANNEL_2 (3)
+ * @arg @ref ADC_CHANNEL_3 (3)
+ * @arg @ref ADC_CHANNEL_4 (3)
+ * @arg @ref ADC_CHANNEL_5 (3)
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ * @arg @ref ADC_CHANNEL_19
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_VCORE (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref ADC_CHANNEL_0
+ * @arg @ref ADC_CHANNEL_1
+ * @arg @ref ADC_CHANNEL_2
+ * @arg @ref ADC_CHANNEL_3
+ * @arg @ref ADC_CHANNEL_4
+ * @arg @ref ADC_CHANNEL_5
+ * @arg @ref ADC_CHANNEL_6
+ * @arg @ref ADC_CHANNEL_7
+ * @arg @ref ADC_CHANNEL_8
+ * @arg @ref ADC_CHANNEL_9
+ * @arg @ref ADC_CHANNEL_10
+ * @arg @ref ADC_CHANNEL_11
+ * @arg @ref ADC_CHANNEL_12
+ * @arg @ref ADC_CHANNEL_13
+ * @arg @ref ADC_CHANNEL_14
+ * @arg @ref ADC_CHANNEL_15
+ * @arg @ref ADC_CHANNEL_16
+ * @arg @ref ADC_CHANNEL_17
+ * @arg @ref ADC_CHANNEL_18
+ */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+ * ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref ADC_CHANNEL_VREFINT (1)
+ * @arg @ref ADC_CHANNEL_VCORE (1)
+ * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref ADC_CHANNEL_VBAT (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+#endif
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
+ __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_16B
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @retval ADC conversion data full-scale digital value
+ */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_16B
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_16B
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
+ (__ADC_RESOLUTION_CURRENT__), \
+ (__ADC_RESOLUTION_TARGET__))
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_16B
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
+ (__ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 serie, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_16B
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_16B
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
+ (__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32MP1, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32MP1, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_RESOLUTION_16B
+ * @arg @ref ADC_RESOLUTION_14B
+ * @arg @ref ADC_RESOLUTION_12B
+ * @arg @ref ADC_RESOLUTION_10B
+ * @arg @ref ADC_RESOLUTION_8B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
+ (__TEMPSENSOR_TYP_CALX_V__), \
+ (__TEMPSENSOR_CALX_TEMP__), \
+ (__VREFANALOG_VOLTAGE__), \
+ (__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Include ADC HAL Extended module */
+#include "stm32mp1xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+ * @}
+ */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
+
+/**
+ * @}
+ */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+ * @{
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+#if defined(HAL_DMA_MODULE_ENABLED)
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+#endif
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32MP1xx_HAL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h
new file mode 100644
index 0000000..3e46cbe
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h
@@ -0,0 +1,1113 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_adc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of ADC HAL extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_ADC_EX_H
+#define STM32MP1xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ADCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief ADC Injected Conversion Oversampling structure definition
+ */
+typedef struct
+{
+ uint32_t Ratio; /*!< Configures the oversampling ratio.
+ This parameter can be a value between 1 and 1024 */
+
+ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
+ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+} ADC_InjOversamplingTypeDef;
+
+/**
+ * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
+ * @note Parameters of this structure are shared within 2 scopes:
+ * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
+ * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
+ * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
+ * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+ * ADC state can be either:
+ * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
+ * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
+ * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
+ * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
+ * on ADC groups regular and injected.
+ * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+ * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
+ */
+typedef struct
+{
+ uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+ Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
+ This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
+ Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
+ the new channel setting (or parameter number of conversions adjusted) */
+
+ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
+ Unit: ADC clock cycles.
+ Conversion time is the addition of sampling time and processing time
+ (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+ This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
+ Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+ It overwrites the last setting.
+ Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
+ sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
+ Refer to device datasheet for timings values. */
+
+ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
+ In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
+ Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
+ This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
+ Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
+ It overwrites the last setting.
+ Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
+ Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
+ of another parameter update on the fly) */
+
+ uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
+ This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
+ Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
+
+ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
+ Offset value must be a positive number.
+ Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
+ between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
+ without continuous mode or external trigger that could launch a conversion). */
+
+ uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not.
+ This parameter is applied only for 16-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
+ This parameter is applied only for 16-bit or 8-bit resolution.
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
+ This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
+
+ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
+ To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+
+ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
+ (main sequence subdivided in successive parts).
+ Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+ Discontinuous mode can be enabled only if continuous mode is disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
+ Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+
+ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
+ This parameter can be set to ENABLE or DISABLE.
+ Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
+ Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
+ Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
+ To maintain JAUTO always enabled, DMA must be configured in circular mode.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+
+ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
+ This parameter can be set to ENABLE or DISABLE.
+ If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
+ new injected context is set when queue is full, error is triggered by interruption and through function
+ 'HAL_ADCEx_InjectedQueueOverflowCallback'.
+ Caution: This feature request that the sequence is fully configured before injected conversion start.
+ Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set.
+ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
+
+ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
+ If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
+ This parameter can be a value of @ref ADC_injected_external_trigger_source.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+
+ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
+ This parameter can be a value of @ref ADC_injected_external_trigger_edge.
+ If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
+ Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
+ configure a channel on injected group can impact the configuration of other channels previously set. */
+
+ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
+ This parameter can be set to ENABLE or DISABLE.
+ Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
+
+ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
+ Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
+ Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
+} ADC_InjectionConfTypeDef;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Structure definition of ADC multimode
+ * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
+ * Both Master and Slave ADCs must be disabled.
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
+
+ uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format:
+ This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
+
+ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
+ Delay range depends on selected resolution:
+ from 1 to 9 clock cycles for 16 bits,
+ from 1 to 9 clock cycles for 14 bits
+ from 1 to 8 clock cycles for 12 bits
+ from 1 to 6 clock cycles for 10 bits
+ from 1 to 6 clock cycles for 8 bits */
+} ADC_MultiModeTypeDef;
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
+ * @{
+ */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
+ * @{
+ */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
+ * @{
+ */
+#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
+#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
+#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
+#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
+#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
+#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
+#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+
+/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
+ * @{
+ */
+#define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */
+#define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */
+#define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
+#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
+#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
+#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CFGR_fields ADCx CFGR fields
+ * @{
+ */
+#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
+ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
+ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | |\
+ ADC_CFGR_RES | ADC_CFGR_DMNGT )
+/**
+ * @}
+ */
+
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+ * @{
+ */
+#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+ ADC_SMPR1_SMP0)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
+ * @{
+ */
+/* ADC_CFGR fields of parameters that can be updated when no conversion
+ (neither regular nor injected) is on-going */
+#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+ * @{
+ */
+
+/** @brief Force ADC instance in multimode mode independent (multimode disable).
+ * @note This macro must be used only in case of transition from multimode
+ * to mode independent and in case of unknown previous state,
+ * to ensure ADC configuration is in mode independent.
+ * @note Standard way of multimode configuration change is done from
+ * HAL ADC handle of ADC master using function
+ * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+ * Usage of this macro is not the Standard way of multimode
+ * configuration and can lead to have HAL ADC handles status
+ * misaligned. Usage of this macro must be limited to cases
+ * mentionned above.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
+ LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
+
+/**
+ * @}
+ */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+ * @{
+ */
+/* Macro reserved for internal HAL driver usage, not intended to be used in */
+/* code of final user. */
+
+/**
+ * @brief Test if conversion trigger of injected group is software start
+ * or external trigger.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (software start) or RESET (external trigger).
+ */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
+ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
+
+/**
+ * @brief Check whether or not ADC is independent.
+ * @param __HANDLE__ ADC handle.
+ * @note When multimode feature is not available, the macro always returns SET.
+ * @retval SET (ADC is independent) or RESET (ADC is not).
+ */
+#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
+
+/**
+ * @brief Set the selected injected Channel rank.
+ * @param __CHANNELNB__ Channel number.
+ * @param __RANKNB__ Rank number.
+ * @retval None
+ */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+
+/**
+ * @brief Configure ADC injected context queue
+ * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for injected group
+ * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
+
+/**
+ * @brief Configure ADC discontinuous conversion mode for regular group
+ * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
+
+/**
+ * @brief Configure the number of discontinuous conversions for regular group.
+ * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
+ * @retval None
+ */
+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
+
+/**
+ * @brief Configure the ADC auto delay mode.
+ * @param __AUTOWAIT__ Auto delay bit enable or disable.
+ * @retval None
+ */
+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
+
+/**
+ * @brief Configure ADC continuous conversion mode.
+ * @param __CONTINUOUS_MODE__ Continuous mode.
+ * @retval None
+ */
+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
+
+/**
+ * @brief Enable the ADC DMA continuous request.
+ * @param __DMACONTREQ_MODE__: DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
+
+/**
+ * @brief Configure the channel number into offset OFRx register.
+ * @param __CHANNEL__ ADC Channel.
+ * @retval None
+ */
+#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
+
+/**
+ * @brief Configure the channel number into differential mode selection register.
+ * @param __CHANNEL__ ADC Channel.
+ * @retval None
+ */
+#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))
+
+/**
+ * @brief Configure calibration factor in differential mode to be set into calibration register.
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+ * @brief Calibration factor in differential mode to be retrieved from calibration register.
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval None
+ */
+#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
+
+/**
+ * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
+ * @param __THRESHOLD__ Threshold value.
+ * @retval None
+ */
+#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Configure the ADC DMA continuous request for ADC multimode.
+ * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+ * @retval None
+ */
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Shift the offset in function of the selected ADC resolution.
+ * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0
+ * If resolution 16 bits, no shift.
+ * If resolution 14 bits, shift of 2 ranks on the left.
+ * If resolution 12 bits, shift of 4 ranks on the left.
+ * If resolution 10 bits, shift of 6 ranks on the left.
+ * If resolution 8 bits, shift of 8 ranks on the left.
+ * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))
+ * @param __HANDLE__: ADC handle
+ * @param __OFFSET__: Value to be shifted
+ * @retval None
+ */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+ ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
+ ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
+ : \
+ ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
+ )
+
+/**
+ * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
+ * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
+ * If resolution 16 bits, no shift.
+ * If resolution 14 bits, shift of 2 ranks on the left.
+ * If resolution 12 bits, shift of 4 ranks on the left.
+ * If resolution 10 bits, shift of 6 ranks on the left.
+ * If resolution 8 bits, shift of 8 ranks on the left.
+ * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
+ * @param __HANDLE__: ADC handle
+ * @param __THRESHOLD__: Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
+ ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
+ : \
+ ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
+ )
+
+/**
+ * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
+ * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.
+ * If resolution 16 bits, no shift.
+ * If resolution 14 bits, shift of 2 ranks on the left.
+ * If resolution 12 bits, shift of 4 ranks on the left.
+ * If resolution 10 bits, shift of 6 ranks on the left.
+ * If resolution 8 bits, shift of 8 ranks on the left.
+ * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))
+ * @param __HANDLE__: ADC handle
+ * @param __THRESHOLD__: Value to be shifted
+ * @retval None
+ */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+ ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
+ ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
+ : \
+ ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
+ )
+/**
+ * @brief Clear Common Control Register.
+ * @param __HANDLE__ ADC handle.
+ * @retval None
+ */
+/**
+ * @brief Report common register to ADC1 and ADC2
+ * @param __HANDLE__: ADC handle
+ * @retval Common control register
+ */
+#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
+
+/**
+ * @brief Report Master Instance
+ * @param __HANDLE__: ADC handle
+ * @note return same instance if ADC of input handle is independent ADC
+ * @retval Master Instance
+ */
+#define ADC_MASTER_REGISTER(__HANDLE__) \
+ ( ( (((__HANDLE__)->Instance) == ADC1) \
+ )? \
+ ((__HANDLE__)->Instance) \
+ : \
+ (ADC1) \
+ )
+
+/**
+ * @brief Check whether or not dual regular conversions are enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
+ */
+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
+ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
+ )? \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
+ : \
+ RESET \
+ )
+
+/**
+ * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
+ * @param __HANDLE__: ADC handle
+ * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)
+ */
+#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \
+ )? \
+ SET \
+ : \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
+ )
+
+/**
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
+ */
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) \
+ )? \
+ SET \
+ : \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
+
+/**
+ * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
+ * @param __HANDLE__: ADC handle
+ * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
+ */
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
+ ( ( ((__HANDLE__)->Instance == ADC1) \
+ )? \
+ SET \
+ : \
+ ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
+ ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
+
+
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
+ ADC_CCR_PRESC | \
+ ADC_CCR_VBATEN | \
+ ADC_CCR_VSENSEEN | \
+ ADC_CCR_VREFEN | \
+ ADC_CCR_DAMDF | \
+ ADC_CCR_DELAY | \
+ ADC_CCR_DUAL )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Set handle instance of the ADC slave associated to the ADC master.
+ * @param __HANDLE_MASTER__ ADC master handle.
+ * @param __HANDLE_SLAVE__ ADC slave handle.
+ * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
+ * @retval None
+ */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
+ ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \
+ ((__HANDLE_SLAVE__)->Instance = ADC2) \
+ : \
+ ((__HANDLE_SLAVE__)->Instance = NULL) \
+ )
+
+
+/**
+ * @brief Verify the ADC instance connected to the temperature sensor.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
+
+/**
+ * @brief Verify the ADC instance connected to the battery voltage VBAT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
+
+/**
+ * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
+
+/**
+ * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE.
+ * @param __HANDLE__ ADC handle.
+ * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+ */
+/* The internal voltage reference VDDCORE measurement path (channel 0) is available on ADC2 */
+#define ADC_VDDCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2)
+
+/**
+ * @brief Verify the length of scheduled injected conversions group.
+ * @param __LENGTH__ number of programmed conversions.
+ * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
+ */
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+
+/**
+ * @brief Calibration factor size verification (7 bits maximum).
+ * @param __CALIBRATION_FACTOR__ Calibration factor value.
+ * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+ */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+
+/**
+ * @brief Verify the ADC channel setting.
+ * @param __CHANNEL__ programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \
+ ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_18) || \
+ ((__CHANNEL__) == ADC_CHANNEL_19) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \
+ ((__CHANNEL__) == ADC_CHANNEL_VCORE) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) )
+
+/**
+ * @brief Verify the ADC channel setting in differential mode for ADC1.
+ * @param __CHANNEL__: programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_3) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_4) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_5) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_10) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_11) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_12) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_16) ||\
+ ((__CHANNEL__) == ADC_CHANNEL_18) )
+
+/**
+ * @brief Verify the ADC channel setting in differential mode for ADC2.
+ * @param __CHANNEL__: programmed ADC channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_18) )
+
+/**
+ * @brief Verify the ADC single-ended input or differential mode setting.
+ * @param __SING_DIFF__ programmed channel setting.
+ * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+ */
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
+ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
+
+/**
+ * @brief Verify the ADC offset management setting.
+ * @param __OFFSET_NUMBER__ ADC offset management.
+ * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
+ */
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
+ ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
+
+/**
+ * @brief Verify the ADC injected channel setting.
+ * @param __CHANNEL__ programmed ADC injected channel.
+ * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+ */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+ ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
+
+/**
+ * @brief Verify the ADC injected conversions external trigger.
+ * @param __INJTRIG__ programmed ADC injected conversions external trigger.
+ * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
+ */
+#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \
+ \
+ ((__INJTRIG__) == ADC_SOFTWARE_START) )
+
+/**
+ * @brief Verify the ADC edge trigger setting for injected group.
+ * @param __EDGE__ programmed ADC edge trigger setting.
+ * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+ */
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
+ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Verify the ADC multimode setting.
+ * @param __MODE__ programmed ADC multimode setting.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
+ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
+ ((__MODE__) == ADC_DUALMODE_INTERL) || \
+ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
+
+/**
+ * @brief Verify the ADC dual data mode setting.
+ * @param MODE: programmed ADC dual mode setting.
+ * @retval SET (MODE is valid) or RESET (MODE is invalid)
+ */
+#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \
+ ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
+ ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) )
+
+/**
+ * @brief Verify the ADC multimode delay setting.
+ * @param __DELAY__ programmed ADC multimode delay setting.
+ * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+ */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
+ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Verify the ADC analog watchdog setting.
+ * @param __WATCHDOG__ programmed ADC analog watchdog setting.
+ * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
+
+/**
+ * @brief Verify the ADC analog watchdog mode setting.
+ * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
+ * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
+ */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
+ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
+
+/**
+ * @brief Verify the ADC conversion (regular or injected or both).
+ * @param __CONVERSION__ ADC conversion group.
+ * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+ */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
+ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
+ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
+
+/**
+ * @brief Verify the ADC event type.
+ * @param __EVENT__ ADC event.
+ * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+ */
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
+ ((__EVENT__) == ADC_AWD_EVENT) || \
+ ((__EVENT__) == ADC_AWD2_EVENT) || \
+ ((__EVENT__) == ADC_AWD3_EVENT) || \
+ ((__EVENT__) == ADC_OVR_EVENT) || \
+ ((__EVENT__) == ADC_JQOVF_EVENT) )
+
+/**
+ * @brief Verify the ADC oversampling ratio.
+ * @param RATIO: programmed ADC oversampling ratio.
+ * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
+ */
+#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
+
+/**
+ * @brief Verify the ADC oversampling shift.
+ * @param __SHIFT__ programmed ADC oversampling shift.
+ * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+ */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
+ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
+
+/**
+ * @brief Verify the ADC oversampling triggered mode.
+ * @param __MODE__ programmed ADC oversampling triggered mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+/**
+ * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
+ * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
+
+/**
+ * @brief Verify the DFSDM mode configuration.
+ * @param __HANDLE__ ADC handle.
+ * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
+ * this reason, the input parameter is the ADC handle and not the configuration parameter
+ * directly.
+ * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
+ */
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
+
+/**
+ * @brief Return the DFSDM configuration mode.
+ * @param __HANDLE__ ADC handle.
+ * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
+ * For this reason, the input parameter is the ADC handle and not the configuration parameter
+ * directly.
+ * @retval DFSDM configuration mode
+ */
+#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+ * @{
+ */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff);
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* ADC multimode */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+
+/* ADC group regular conversions stop */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
+#endif /* ADC_MULTIMODE_SUPPORT */
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_ADC_EX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cortex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cortex.h
new file mode 100644
index 0000000..657456d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cortex.h
@@ -0,0 +1,441 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_cortex.h
+ * @author MCD Application Team
+ * @brief Header file of CORTEX HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_CORTEX_H
+#define __STM32MP1xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CORTEX
+ * @{
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+ * @brief MPU Region initialization structure
+ * @{
+ */
+typedef struct
+{
+ uint8_t Enable; /*!< Specifies the status of the region.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
+ uint8_t Number; /*!< Specifies the number of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
+ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
+ uint8_t Size; /*!< Specifies the size of the region to protect.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
+ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint8_t TypeExtField; /*!< Specifies the TEX field level.
+ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
+ uint8_t AccessPermission; /*!< Specifies the region access permission type.
+ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
+ uint8_t DisableExec; /*!< Specifies the instruction access status.
+ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
+ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
+ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
+ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
+ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
+}MPU_Region_InitTypeDef;
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+ * @{
+ */
+#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+/**
+ * @}
+ */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+ * @{
+ */
+#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
+#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
+#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
+#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+ * @{
+ */
+#define MPU_REGION_ENABLE ((uint8_t)0x01)
+#define MPU_REGION_DISABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+ * @{
+ */
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+ * @{
+ */
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+ * @{
+ */
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+ * @{
+ */
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+ * @{
+ */
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+ * @{
+ */
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+ * @{
+ */
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+ * @{
+ */
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+ * @{
+ */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+ ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+ ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
+ ((TYPE) == MPU_TEX_LEVEL1) || \
+ ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RW) || \
+ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+ ((TYPE) == MPU_REGION_PRIV_RO) || \
+ ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
+ ((NUMBER) == MPU_REGION_NUMBER1) || \
+ ((NUMBER) == MPU_REGION_NUMBER2) || \
+ ((NUMBER) == MPU_REGION_NUMBER3) || \
+ ((NUMBER) == MPU_REGION_NUMBER4) || \
+ ((NUMBER) == MPU_REGION_NUMBER5) || \
+ ((NUMBER) == MPU_REGION_NUMBER6) || \
+ ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
+ ((SIZE) == MPU_REGION_SIZE_64B) || \
+ ((SIZE) == MPU_REGION_SIZE_128B) || \
+ ((SIZE) == MPU_REGION_SIZE_256B) || \
+ ((SIZE) == MPU_REGION_SIZE_512B) || \
+ ((SIZE) == MPU_REGION_SIZE_1KB) || \
+ ((SIZE) == MPU_REGION_SIZE_2KB) || \
+ ((SIZE) == MPU_REGION_SIZE_4KB) || \
+ ((SIZE) == MPU_REGION_SIZE_8KB) || \
+ ((SIZE) == MPU_REGION_SIZE_16KB) || \
+ ((SIZE) == MPU_REGION_SIZE_32KB) || \
+ ((SIZE) == MPU_REGION_SIZE_64KB) || \
+ ((SIZE) == MPU_REGION_SIZE_128KB) || \
+ ((SIZE) == MPU_REGION_SIZE_256KB) || \
+ ((SIZE) == MPU_REGION_SIZE_512KB) || \
+ ((SIZE) == MPU_REGION_SIZE_1MB) || \
+ ((SIZE) == MPU_REGION_SIZE_2MB) || \
+ ((SIZE) == MPU_REGION_SIZE_4MB) || \
+ ((SIZE) == MPU_REGION_SIZE_8MB) || \
+ ((SIZE) == MPU_REGION_SIZE_16MB) || \
+ ((SIZE) == MPU_REGION_SIZE_32MB) || \
+ ((SIZE) == MPU_REGION_SIZE_64MB) || \
+ ((SIZE) == MPU_REGION_SIZE_128MB) || \
+ ((SIZE) == MPU_REGION_SIZE_256MB) || \
+ ((SIZE) == MPU_REGION_SIZE_512MB) || \
+ ((SIZE) == MPU_REGION_SIZE_1GB) || \
+ ((SIZE) == MPU_REGION_SIZE_2GB) || \
+ ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
+ * @brief CORTEX private functions
+ * @{
+ */
+
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU */
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h
new file mode 100644
index 0000000..5cd3811
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h
@@ -0,0 +1,199 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_def.h
+ * @author MCD Application Team
+ * @brief This file contains HAL common defines, enumeration, macros and
+ * structures definitions.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_DEF
+#define STM32MP1xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx.h"
+#if defined(USE_HAL_LEGACY)
+ #include "Legacy/stm32_hal_legacy.h"
+#endif
+#include <stdio.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HAL Status structures definition
+ */
+typedef enum
+{
+ HAL_OK = 0x00U,
+ HAL_ERROR = 0x01U,
+ HAL_BUSY = 0x02U,
+ HAL_TIMEOUT = 0x03U
+} HAL_StatusTypeDef;
+
+/**
+ * @brief HAL Lock structures definition
+ */
+typedef enum
+{
+ HAL_UNLOCKED = 0x00U,
+ HAL_LOCKED = 0x01U
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0U)
+
+/** @brief Reset the Handle's State field.
+ * @param __HANDLE__ specifies the Peripheral Handle.
+ * @note This macro can be used for the following purpose:
+ * - When the Handle is declared as local variable; before passing it as parameter
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to set to 0 the Handle's "State" field.
+ * Otherwise, "State" field may have any random value and the first time the function
+ * HAL_PPP_Init() is called, the low level hardware initialization will be missed
+ * (i.e. HAL_PPP_MspInit() will not be executed).
+ * - When there is a need to reconfigure the low level hardware: instead of calling
+ * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+ * In this later function, when the Handle's "State" field is set to 0, it will execute the function
+ * HAL_PPP_MspInit() which will reconfigure the low level hardware.
+ * @retval None
+ */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+/* Reserved for future use */
+ #error " USE_RTOS should be 0 in the current HAL release "
+#else
+ #define __HAL_LOCK(__HANDLE__) \
+ do{ \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ }while (0U)
+
+ #define __HAL_UNLOCK(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0U)
+#endif /* USE_RTOS */
+
+#if defined ( __GNUC__ )
+ #ifndef __weak
+ #define __weak __attribute__((weak))
+ #endif /* __weak */
+ #ifndef __packed
+ #define __packed __attribute__((__packed__))
+ #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__GNUC__) /* GNU Compiler */
+ #ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4U)))
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #define __ALIGN_BEGIN
+ #endif /* __ALIGN_BEGIN */
+#else
+ #ifndef __ALIGN_END
+ #define __ALIGN_END
+ #endif /* __ALIGN_END */
+ #ifndef __ALIGN_BEGIN
+ #if defined (__CC_ARM) /* ARM Compiler */
+#define __ALIGN_BEGIN __align(4U)
+ #elif defined (__ICCARM__) /* IAR Compiler */
+ #define __ALIGN_BEGIN
+ #endif /* __CC_ARM */
+ #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM )
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source module.
+ Using the 'Options for File' dialog you can simply change the 'Code / Const'
+ area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+ dialog.
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/**
+ * @brief __NOINLINE definition
+ */
+#if defined ( __CC_ARM ) || defined ( __GNUC__ )
+/* ARM & GNUCompiler
+ ----------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h
new file mode 100644
index 0000000..e149255
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma.h
@@ -0,0 +1,952 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_dma.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_DMA_H
+#define __STM32MP1xx_HAL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+ * @brief DMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief DMA Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Request; /*!< Specifies the request selected for the specified stream.
+ This parameter can be a value of @ref DMA_Request_selection */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
+ This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+ uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_Memory_data_size */
+
+ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
+ This parameter can be a value of @ref DMA_mode
+ @note The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Stream */
+
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
+ This parameter can be a value of @ref DMA_Priority_level */
+
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+ This parameter can be a value of @ref DMA_FIFO_direct_mode
+ @note The Direct mode (FIFO mode disabled) cannot be used if the
+ memory-to-memory data transfer is configured on the selected stream */
+
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref DMA_FIFO_threshold_level */
+
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_Memory_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_Peripheral_burst
+ @note The burst mode is possible only if the address Increment mode is enabled. */
+} DMA_InitTypeDef;
+
+/**
+ * @brief HAL DMA State structures definition
+ */
+typedef enum
+{
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */
+ HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
+} HAL_DMA_StateTypeDef;
+
+/**
+ * @brief HAL DMA Transfer complete level structure definition
+ */
+typedef enum
+{
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
+} HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL DMA Callbacks IDs structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
+ HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
+ HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
+} HAL_DMA_CallbackIDTypeDef;
+
+/**
+ * @brief DMA handle Structure definition
+ */
+typedef struct __DMA_HandleTypeDef
+{
+ DMA_Stream_TypeDef *Instance; /*!< Register base address */
+
+ DMA_InitTypeDef Init; /*!< DMA communication parameters */
+
+ HAL_LockTypeDef Lock; /*!< DMA locking object */
+
+ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
+
+ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
+
+ void (* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete Memory1 callback */
+
+ void (* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Half complete Memory1 callback */
+
+ void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
+
+ void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */
+
+ __IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
+
+ uint32_t StreamIndex; /*!< DMA Stream Index */
+
+ DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */
+
+ DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
+
+ uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
+
+
+ DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
+
+ DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */
+
+ uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
+
+} DMA_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+ * @brief DMA Exported constants
+ * @{
+ */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+ * @brief DMA Error Code
+ * @{
+ */
+#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
+#define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */
+#define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */
+#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */
+#define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
+#define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */
+#define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */
+#define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Request_selection DMA Request selection
+ * @brief DMA Request selection
+ * @{
+ */
+/* D2 Domain : DMAMUX1 requests */
+#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
+
+#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
+#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
+#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
+#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
+#define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
+#define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
+#define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
+#define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
+
+#define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */
+#define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */
+
+#define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
+#define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
+#define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
+#define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
+#define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
+#define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
+#define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
+
+#define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
+#define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
+#define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
+#define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
+#define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
+
+#define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
+#define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
+#define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
+#define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
+#define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
+#define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
+
+#define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
+#define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
+#define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
+#define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
+
+#define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
+#define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
+#define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
+#define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
+
+#define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
+#define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
+#define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
+#define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
+
+#define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
+#define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
+#define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
+#define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
+
+#define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
+#define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
+#define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
+#define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
+#define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
+#define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
+#define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
+
+#define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
+#define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
+#define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
+#define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
+#define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
+#define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
+
+#define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
+#define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
+
+#define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
+#define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
+#define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
+#define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
+
+#define DMA_REQUEST_DAC1 67U /*!< DMAMUX1 DAC1 request */
+#define DMA_REQUEST_DAC2 68U /*!< DMAMUX1 DAC2 request */
+
+#define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
+#define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
+
+#define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
+#define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
+
+#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
+#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
+
+#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */
+
+#if defined(CRYP2)
+#define DMA_REQUEST_CRYP2_IN 76U /*!< DMAMUX1 CRYP2 IN request */
+#define DMA_REQUEST_CRYP2_OUT 77U /*!< DMAMUX1 CRYP2 OUT request */
+#endif
+
+#define DMA_REQUEST_HASH2_IN 78U /*!< DMAMUX1 HASH2 IN request */
+
+#define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
+#define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
+#define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
+#define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
+
+#define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
+#define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
+#define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
+#define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
+
+#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
+#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
+#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
+#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
+
+#define DMA_REQUEST_DFSDM1_FLT4 91U /*!< DMAMUX1 DFSDM1 Filter4 request */
+#define DMA_REQUEST_DFSDM1_FLT5 92U /*!< DMAMUX1 DFSDM1 Filter5 request */
+
+#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/
+#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/
+
+#define DMA_REQUEST_SAI4_A 99U /*!< DMAMUX1 SAI4 A request */
+#define DMA_REQUEST_SAI4_B 100U /*!< DMAMUX1 SAI4 B request */
+
+#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
+#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */
+#define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */
+#define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */
+
+#define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
+#define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
+#define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
+#define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
+
+#define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
+#define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
+
+#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
+#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
+
+#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
+#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
+
+#define DMA_REQUEST_I2C5_RX 115U /*!< DMAMUX1 I2C5 RX request */
+#define DMA_REQUEST_I2C5_TX 116U /*!< DMAMUX1 I2C5 TX request */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+ * @brief DMA data transfer direction
+ * @{
+ */
+#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+ * @brief DMA peripheral incremented mode
+ * @{
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
+#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+ * @brief DMA memory incremented mode
+ * @{
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
+#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+ * @brief DMA peripheral data size
+ * @{
+ */
+#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+ * @brief DMA memory data size
+ * @{
+ */
+#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_mode DMA mode
+ * @brief DMA mode
+ * @{
+ */
+#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
+#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+ * @brief DMA priority levels
+ * @{
+ */
+#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+ * @brief DMA FIFO direct mode
+ * @{
+ */
+#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+ * @brief DMA FIFO level
+ * @{
+ */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
+#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+ * @brief DMA memory burst
+ * @{
+ */
+#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
+#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
+#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
+#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+ * @brief DMA peripheral burst
+ * @{
+ */
+#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
+#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+ * @brief DMA interrupts definition
+ * @{
+ */
+#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE ((uint32_t)0x00000080U)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+ * @brief DMA flag definitions
+ * @{
+ */
+#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)
+#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)
+#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
+#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
+#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
+#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
+#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
+#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
+#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
+#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
+#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
+#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
+#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
+#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
+#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
+#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
+#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
+#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
+#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
+#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @brief Reset DMA handle state
+ * @param __HANDLE__: specifies the DMA handle.
+ * @retval None
+ */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+ * @brief Return the current DMA Stream FIFO filled level.
+ * @param __HANDLE__: DMA handle
+ * @retval The FIFO filling state.
+ * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
+ * and not empty.
+ * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+ * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+ * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+ * - DMA_FIFOStatus_Empty: when FIFO is empty
+ * - DMA_FIFOStatus_Full: when FIFO is full
+ */
+#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
+
+/**
+ * @brief Enable the specified DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_ENABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN)
+
+/**
+ * @brief Disable the specified DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+ * @brief Return the current DMA Stream transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer complete flag index.
+ */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ (uint32_t)0x00000000)
+
+/**
+ * @brief Return the current DMA Stream half transfer complete flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified half transfer complete flag index.
+ */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ (uint32_t)0x00000000)
+
+/**
+ * @brief Return the current DMA Stream transfer error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ (uint32_t)0x00000000)
+
+/**
+ * @brief Return the current DMA Stream FIFO error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified FIFO error flag index.
+ */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
+ (uint32_t)0x00000000)
+
+/**
+ * @brief Return the current DMA Stream direct mode error flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified direct mode error flag index.
+ */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
+ (uint32_t)0x00000000)
+
+
+/**
+ * @brief Get the DMA Stream pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+ * @brief Clear the DMA Stream pending flags.
+ * @param __HANDLE__: DMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_FLAG_TCIFx: Transfer complete flag.
+ * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+ * @arg DMA_FLAG_TEIFx: Transfer error flag.
+ * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+ * @arg DMA_FLAG_FEIFx: FIFO error flag.
+ * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
+ * @retval None
+ */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+
+/**
+ * @brief Enable the specified DMA Stream interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
+
+/**
+ * @brief Disable the specified DMA Stream interrupts.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval None
+ */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
+
+/**
+ * @brief Check whether the specified DMA Stream interrupt is enabled or not.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask.
+ * @arg DMA_IT_HT: Half transfer complete interrupt mask.
+ * @arg DMA_IT_TE: Transfer error interrupt mask.
+ * @arg DMA_IT_FE: FIFO error interrupt mask.
+ * @arg DMA_IT_DME: Direct mode error interrupt.
+ * @retval The state of DMA_IT.
+ */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
+ (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
+ (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
+
+/**
+ * @brief Writes the number of data units to be transferred on the DMA Stream.
+ * @param __HANDLE__: DMA handle
+ * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+ * Number of data items depends only on the Peripheral data format.
+ *
+ * @note If Peripheral data format is Bytes: number of data units is equal
+ * to total number of bytes to be transferred.
+ *
+ * @note If Peripheral data format is Half-Word: number of data units is
+ * equal to total number of bytes to be transferred / 2.
+ *
+ * @note If Peripheral data format is Word: number of data units is equal
+ * to total number of bytes to be transferred / 4.
+ *
+ * @retval The number of remaining data units in the current DMAy Streamx transfer.
+ */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+ * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
+ * @param __HANDLE__: DMA handle
+ *
+ * @retval The number of remaining data units in the current DMA Stream transfer.
+ */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR)
+/**
+ * @}
+ */
+
+/* Include DMA HAL Extension module */
+#include "stm32mp1xx_hal_dma_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+ * @brief DMA Exported functions
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+ * @brief I/O operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+ * @brief DMA private defines and constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+ * @brief DMA private macros
+ * @{
+ */
+#define IS_DMA_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_I2C5_TX)
+
+
+#define IS_DMA_INSTANCE(__HANDLE__) (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7)))
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+ ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
+ ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
+ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+ ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
+ ((MODE) == DMA_CIRCULAR) || \
+ ((MODE) == DMA_PFCTRL))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
+ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+ ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+ ((BURST) == DMA_MBURST_INC4) || \
+ ((BURST) == DMA_MBURST_INC8) || \
+ ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+ ((BURST) == DMA_PBURST_INC4) || \
+ ((BURST) == DMA_PBURST_INC8) || \
+ ((BURST) == DMA_PBURST_INC16))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+ * @brief DMA private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h
new file mode 100644
index 0000000..5391d5b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dma_ex.h
@@ -0,0 +1,256 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_dma_ex.h
+ * @author MCD Application Team
+ * @brief Header file of DMA HAL extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_DMA_EX_H
+#define STM32MP1xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup DMAEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+ * @brief DMAEx Exported types
+ * @{
+ */
+
+/**
+ * @brief HAL DMA Memory definition
+ */
+typedef enum
+{
+ MEMORY0 = 0x00U, /*!< Memory 0 */
+ MEMORY1 = 0x01U, /*!< Memory 1 */
+
+} HAL_DMA_MemoryTypeDef;
+
+/**
+ * @brief HAL DMAMUX Synchronization configuration structure definition
+ */
+typedef struct
+{
+ uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
+ This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
+
+ uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
+ This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
+
+ FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
+ This parameter can take the value ENABLE or DISABLE*/
+
+
+ FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
+ This parameter can take the value ENABLE or DISABLE */
+
+ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
+ This parameters can be in the range 1 to 32 */
+
+} HAL_DMA_MuxSyncConfigTypeDef;
+
+
+/**
+ * @brief HAL DMAMUX request generator parameters structure definition
+ */
+typedef struct
+{
+ uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
+ This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
+
+ uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
+ This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
+
+ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event.
+ This parameters can be in the range 1 to 32 */
+
+} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
+ * @brief DMAEx Exported constants
+ * @{
+ */
+
+/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
+ * @brief DMAEx MUX SyncSignalID selection
+ * @{
+ */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< Domain synchronization Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< Domain synchronization Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< Domain synchronization Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< Domain synchronization Signal is LPTIM1 OUT */
+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< Domain synchronization Signal is LPTIM2 OUT */
+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< Domain synchronization Signal is LPTIM3 OUT */
+#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< Domain synchronization Signal is EXTI0 IT */
+#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< Domain synchronization Signal is TIM12 TRGO */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
+ * @brief DMAEx MUX SyncPolarity selection
+ * @{
+ */
+#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */
+#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
+#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
+#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
+ * @brief DMAEx MUX SignalGeneratorID selection
+ * @{
+ */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< Domain Request generator Signal is DMAMUX1 Channel0 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< Domain Request generator Signal is DMAMUX1 Channel1 Event */
+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< Domain Request generator Signal is DMAMUX1 Channel2 Event */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< Domain Request generator Signal is LPTIM1 OUT */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< Domain Request generator Signal is LPTIM2 OUT */
+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< Domain Request generator Signal is LPTIM3 OUT */
+#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< Domain Request generator Signal is EXTI0 IT */
+#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< Domain Request generator Signal is TIM12 TRGO */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
+ * @brief DMAEx MUX RequestGeneneratorPolarity selection
+ * @{
+ */
+#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */
+#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
+#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+ * @brief DMAEx Exported functions
+ * @{
+ */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+ * @brief Extended features functions
+ * @{
+ */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
+
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Macros DMA Private Macros
+ * @brief DMAEx private macros
+ * @{
+ */
+
+#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
+
+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
+
+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
+ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
+ ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
+ ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
+
+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
+
+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
+ ((EVENT) == ENABLE))
+
+#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
+
+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
+
+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
+ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+ * @brief DMAEx Private functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h
new file mode 100644
index 0000000..512cfb0
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h
@@ -0,0 +1,371 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_EXTI_H
+#define STM32MP1xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup EXTI EXTI
+ * @brief EXTI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+ * @{
+ */
+typedef enum
+{
+ HAL_EXTI_COMMON_CB_ID = 0x00U,
+ HAL_EXTI_RISING_CB_ID = 0x01U,
+ HAL_EXTI_FALLING_CB_ID = 0x02U,
+} EXTI_CallbackIDTypeDef;
+
+
+/**
+ * @brief EXTI Handle structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< Exti line number */
+ void (* RisingCallback)(void); /*!< Exti rising callback */
+ void (* FallingCallback)(void); /*!< Exti falling callback */
+} EXTI_HandleTypeDef;
+
+/**
+ * @brief EXTI Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< The Exti line to be configured. This parameter
+ can be a value of @ref EXTI_Line */
+ uint32_t Mode; /*!< The Exit Mode to be configured for a core.
+ This parameter can be a combination of @ref EXTI_Mode */
+ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
+ can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Line EXTI Line
+ * @{
+ */
+#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u) /* EXTI_GPIO */
+#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u) /* EXTI_GPIO */
+#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u) /* EXTI_GPIO */
+#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u) /* EXTI_GPIO */
+#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u) /* EXTI_GPIO */
+#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u) /* EXTI_GPIO */
+#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u) /* EXTI_GPIO */
+#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u) /* EXTI_GPIO */
+#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u) /* EXTI_GPIO */
+#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u) /* EXTI_GPIO */
+#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au) /* EXTI_GPIO */
+#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu) /* EXTI_GPIO */
+#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu) /* EXTI_GPIO */
+#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du) /* EXTI_GPIO */
+#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu) /* EXTI_GPIO */
+#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu) /* EXTI_GPIO */
+#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) /* PVD and AVD */
+#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u) /* RTC timestamp and SecureError wakeup */
+#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u) /* TAMP tamper and SecureError wakeup */
+#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u) /* RTC Wakeup timer and Alarms (A and B) and SecureError wakeup */
+#define EXTI_LINE_20 (EXTI_RESERVED | | EXTI_REG1 | 0x14u) /* RESERVED */
+#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u) /* I2C1 wakeup */
+#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) /* I2C2 wakeup */
+#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) /* I2C3 wakeup */
+#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) /* I2C4 wakeup */
+#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) /* I2C5 wakeup */
+#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) /* USART1 wakeup */
+#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) /* USART2 wakeup */
+#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) /* USART3 wakeup */
+#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) /* USART6 wakeup */
+#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) /* UART4 wakeup */
+#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu) /* UART5 wakeup */
+#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u) /* UART7 wakeup */
+#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u) /* UART8 wakeup */
+#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) /* RESERVED */
+#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) /* RESERVED */
+#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) /* SPI1 wakeup */
+#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u) /* SPI2 wakeup */
+#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u) /* SPI3 wakeup */
+#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u) /* SPI4 wakeup */
+#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | 0x08u) /* SPI5 wakeup */
+#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | 0x09u) /* SPI6 wakeup */
+#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) /* MDIOS wakeup */
+#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) /* USBH wakeup */
+#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu) /* OTG wakeup */
+#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du) /* IWDG1 early wake */
+#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu) /* IWDG1 early wake */
+#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | 0x0Fu) /* LPTIM1 wakeup */
+#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u) /* LPTIM2 wakeup */
+#define EXTI_LINE_49 (EXTI_RESERVED | EXTI_REG2 | 0x11u) /* RESERVED */
+#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_REG2 | 0x12u) /* LPTIM3 wakeup */
+#define EXTI_LINE_51 (EXTI_RESERVED | EXTI_REG2 | 0x13u) /* RESERVED */
+#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | 0x14u) /* LPTIM4 wakeup */
+#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_REG2 | 0x15u) /* LPTIM5 wakeup */
+#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_REG2 | 0x16u) /* I2C6 wakeup */
+#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | 0x17u) /* WKUP1 wakeup */
+#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | 0x18u) /* WKUP2 wakeup */
+#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19u) /* WKUP3 wakeup */
+#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | 0x1Au) /* WKUP4 wakeup */
+#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_REG2 | 0x1Bu) /* WKUP5 wakeup */
+#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_REG2 | 0x1Cu) /* WKUP6 wakeup */
+#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_REG2 | 0x1Du) /* IPCC interrupt CPU1 */
+#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_REG2 | 0x1Eu) /* IPCC interrupt CPU2 */
+#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_REG2 | 0x1Fu) /* HSEM_IT1 interrupt */
+#define EXTI_LINE_64 (EXTI_DIRECT | EXTI_REG3 | 0x00u) /* HSEM_IT2 interrupt */
+#define EXTI_LINE_65 (EXTI_CONFIG | EXTI_REG3 | 0x01u) /* CPU2 SEV interrupt */
+#define EXTI_LINE_66 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | 0x02u) /* CPU1 SEV interrupt */
+#define EXTI_LINE_67 (EXTI_RESERVED | EXTI_REG3 | 0x03u) /* RESERVED */
+#define EXTI_LINE_68 (EXTI_CONFIG | EXTI_REG3 | 0x04u) /* WWDG1 reset */
+#define EXTI_LINE_69 (EXTI_DIRECT | EXTI_REG3 | 0x05u) /* HDMI CEC wakeup */
+#define EXTI_LINE_70 (EXTI_DIRECT | EXTI_REG3 | 0x06u) /* ETH1 pmt_intr_o wakeup */
+#define EXTI_LINE_71 (EXTI_DIRECT | EXTI_REG3 | 0x07u) /* ETH1 lpi_intr_o wakeup */
+#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_REG3 | 0x08u) /* DTS wakeup */
+#define EXTI_LINE_73 (EXTI_CONFIG | EXTI_REG3 | 0x09u) /* CPU2 SYSRESETREQ local CPU2 reset */
+#define EXTI_LINE_74 (EXTI_RESERVED | EXTI_REG3 | 0x0Au) /* RESERVED */
+#define EXTI_LINE_75 (EXTI_DIRECT | EXTI_REG3 | 0x0Bu) /* CDBGPWRUPREQ event */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Mode EXTI Mode
+ * @{
+ */
+#define EXTI_MODE_C1_NONE 0x00000010u
+#define EXTI_MODE_C1_INTERRUPT 0x00000011u
+#define EXTI_MODE_C1_EVENT 0x00000012u
+#define EXTI_MODE_C2_NONE 0x00000020u
+#define EXTI_MODE_C2_INTERRUPT 0x00000021u
+#define EXTI_MODE_C2_EVENT 0x00000022u
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Trigger EXTI Trigger
+ * @{
+ */
+#define EXTI_TRIGGER_NONE 0x00000000u
+#define EXTI_TRIGGER_RISING 0x00000001u
+#define EXTI_TRIGGER_FALLING 0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000u
+#define EXTI_GPIOB 0x00000001u
+#define EXTI_GPIOC 0x00000002u
+#define EXTI_GPIOD 0x00000003u
+#define EXTI_GPIOE 0x00000004u
+#define EXTI_GPIOF 0x00000005u
+#define EXTI_GPIOG 0x00000006u
+#define EXTI_GPIOH 0x00000007u
+#define EXTI_GPIOI 0x00000008u
+#define EXTI_GPIOJ 0x00000009u
+#define EXTI_GPIOK 0x0000000Au
+#define EXTI_GPIOZ 0x0000000Bu
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24u
+#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI Event presence definition
+ */
+#define EXTI_EVENT_PRESENCE_SHIFT 28u
+#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
+#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
+
+/**
+ * @brief EXTI Register and bit usage
+ */
+#define EXTI_REG_SHIFT 16u
+#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
+#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
+#define EXTI_PIN_MASK 0x0000001Fu
+
+/**
+ * @brief EXTI Mask for interrupt & event mode
+ */
+#define EXTI_MODE_MASK (EXTI_MODE_C1 | EXTI_MODE_C2 | EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+ * @brief EXTI Mask for trigger possibilities
+ */
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+ * @brief EXTI Line number
+ */
+#define EXTI_LINE_NB 76uL
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
+
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \
+ ((__LINE__) == EXTI_TRIGGER_FALLING))
+
+#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
+
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF) || \
+ ((__PORT__) == EXTI_GPIOG) || \
+ ((__PORT__) == EXTI_GPIOH) || \
+ ((__PORT__) == EXTI_GPIOI) || \
+ ((__PORT__) == EXTI_GPIOK) || \
+ ((__PORT__) == EXTI_GPIOZ))
+
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+ * @brief EXTI Exported Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_fdcan.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_fdcan.h
new file mode 100644
index 0000000..54f901b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_fdcan.h
@@ -0,0 +1,2319 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_fdcan.h
+ * @author MCD Application Team
+ * @brief Header file of FDCAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_FDCAN_H
+#define STM32MP1xx_HAL_FDCAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup FDCAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
+ HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
+ HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
+ HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
+} HAL_FDCAN_StateTypeDef;
+
+/**
+ * @brief FDCAN Init structure definition
+ */
+typedef struct
+{
+ uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
+ This parameter can be a value of @ref FDCAN_frame_format */
+
+ uint32_t Mode; /*!< Specifies the FDCAN mode.
+ This parameter can be a value of @ref FDCAN_operating_mode */
+
+ FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is
+ divided for generating the nominal bit time quanta.
+ This parameter must be a number between 1 and 512 */
+
+ uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
+ hardware is allowed to lengthen or shorten a bit to perform
+ resynchronization.
+ This parameter must be a number between 1 and 128 */
+
+ uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter must be a number between 2 and 256 */
+
+ uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter must be a number between 2 and 128 */
+
+ uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is
+ divided for generating the data bit time quanta.
+ This parameter must be a number between 1 and 32 */
+
+ uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
+ hardware is allowed to lengthen or shorten a data bit to
+ perform resynchronization.
+ This parameter must be a number between 1 and 16 */
+
+ uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1.
+ This parameter must be a number between 1 and 32 */
+
+ uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2.
+ This parameter must be a number between 1 and 16 */
+
+ uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address.
+ This parameter must be a number between 0 and 2560 */
+
+ uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
+ This parameter must be a number between 0 and 128 */
+
+ uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
+ This parameter must be a number between 0 and 64 */
+
+ uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements.
+ This parameter must be a number between 0 and 64 */
+
+ uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
+ This parameter can be a value of @ref FDCAN_data_field_size */
+
+ uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements.
+ This parameter must be a number between 0 and 64 */
+
+ uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
+ This parameter can be a value of @ref FDCAN_data_field_size */
+
+ uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements.
+ This parameter must be a number between 0 and 64 */
+
+ uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element.
+ This parameter can be a value of @ref FDCAN_data_field_size */
+
+ uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements.
+ This parameter must be a number between 0 and 32 */
+
+ uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers.
+ This parameter must be a number between 0 and 32 */
+
+ uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
+ This parameter must be a number between 0 and 32 */
+
+ uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
+ This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
+
+ uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element.
+ This parameter can be a value of @ref FDCAN_data_field_size */
+
+} FDCAN_InitTypeDef;
+
+/**
+ * @brief FDCAN clock calibration unit structure definition
+ */
+typedef struct
+{
+ uint32_t ClockCalibration; /*!< Enable or disable the clock calibration.
+ This parameter can be a value of @ref FDCAN_clock_calibration. */
+
+ uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration
+ is bypassed.
+ This parameter can be a value of @ref FDCAN_clock_divider */
+
+ uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The
+ actual configured number of periods is MinOscClkPeriods x 32.
+ This parameter must be a number between 0x00 and 0xFF */
+
+ uint32_t CalFieldLength; /*!< Specifies the calibration field length.
+ This parameter can be a value of @ref FDCAN_calibration_field_length */
+
+ uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
+ This parameter must be a number between 4 and 25 */
+
+ uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter.
+ If set to zero the counter is disabled.
+ This parameter must be a number between 0x0000 and 0xFFFF */
+
+} FDCAN_ClkCalUnitTypeDef;
+
+/**
+ * @brief FDCAN filter structure definition
+ */
+typedef struct
+{
+ uint32_t IdType; /*!< Specifies the identifier type.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between:
+ - 0 and 127, if IdType is FDCAN_STANDARD_ID
+ - 0 and 63, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t FilterType; /*!< Specifies the filter type.
+ This parameter can be a value of @ref FDCAN_filter_type.
+ The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
+ only when IdType is FDCAN_EXTENDED_ID.
+ This parameter is ignored if FilterConfig is set to
+ FDCAN_FILTER_TO_RXBUFFER */
+
+ uint32_t FilterConfig; /*!< Specifies the filter configuration.
+ This parameter can be a value of @ref FDCAN_filter_config */
+
+ uint32_t FilterID1; /*!< Specifies the filter identification 1.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t FilterID2; /*!< Specifies the filter identification 2.
+ This parameter is ignored if FilterConfig is set to
+ FDCAN_FILTER_TO_RXBUFFER.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the
+ matching message will be stored.
+ This parameter must be a number between 0 and 63.
+ This parameter is ignored if FilterConfig is different
+ from FDCAN_FILTER_TO_RXBUFFER */
+
+ uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
+ calibration messages.
+ This parameter is ignored if FilterConfig is different
+ from FDCAN_FILTER_TO_RXBUFFER.
+ This parameter can be:
+ - 0 : ordinary message
+ - 1 : calibration message */
+
+} FDCAN_FilterTypeDef;
+
+/**
+ * @brief FDCAN Tx header structure definition
+ */
+typedef struct
+{
+ uint32_t Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IdType; /*!< Specifies the identifier type for the message that will be
+ transmitted.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted.
+ This parameter can be a value of @ref FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter can be a value of @ref FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without
+ bit rate switching.
+ This parameter can be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or
+ FD format.
+ This parameter can be a value of @ref FDCAN_format */
+
+ uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
+ This parameter can be a value of @ref FDCAN_EFC */
+
+ uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO
+ element for identification of Tx message status.
+ This parameter must be a number between 0 and 0xFF */
+
+} FDCAN_TxHeaderTypeDef;
+
+/**
+ * @brief FDCAN Rx header structure definition
+ */
+typedef struct
+{
+ uint32_t Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IdType; /*!< Specifies the identifier type of the received message.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t RxFrameType; /*!< Specifies the the received message frame type.
+ This parameter can be a value of @ref FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the received frame length.
+ This parameter can be a value of @ref FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit
+ rate switching.
+ This parameter can be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
+ format.
+ This parameter can be a value of @ref FDCAN_format */
+
+ uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
+ reception.
+ This parameter must be a number between 0 and 0xFFFF */
+
+ uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
+ This parameter must be a number between:
+ - 0 and 127, if IdType is FDCAN_STANDARD_ID
+ - 0 and 63, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
+ Acceptance of non-matching frames may be enabled via
+ HAL_FDCAN_ConfigGlobalFilter().
+ This parameter can be 0 or 1 */
+
+} FDCAN_RxHeaderTypeDef;
+
+/**
+ * @brief FDCAN Tx event FIFO structure definition
+ */
+typedef struct
+{
+ uint32_t Identifier; /*!< Specifies the identifier.
+ This parameter must be a number between:
+ - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
+
+ uint32_t IdType; /*!< Specifies the identifier type for the transmitted message.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message.
+ This parameter can be a value of @ref FDCAN_frame_type */
+
+ uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
+ This parameter can be a value of @ref FDCAN_data_length_code */
+
+ uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
+ This parameter can be a value of @ref FDCAN_error_state_indicator */
+
+ uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit
+ rate switching.
+ This parameter can be a value of @ref FDCAN_bit_rate_switching */
+
+ uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD
+ format.
+ This parameter can be a value of @ref FDCAN_format */
+
+ uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
+ transmission.
+ This parameter must be a number between 0 and 0xFFFF */
+
+ uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element
+ for identification of Tx message status.
+ This parameter must be a number between 0 and 0xFF */
+
+ uint32_t EventType; /*!< Specifies the event type.
+ This parameter can be a value of @ref FDCAN_event_type */
+
+} FDCAN_TxEventFifoTypeDef;
+
+/**
+ * @brief FDCAN High Priority Message Status structure definition
+ */
+typedef struct
+{
+ uint32_t FilterList; /*!< Specifies the filter list of the matching filter element.
+ This parameter can be:
+ - 0 : Standard Filter List
+ - 1 : Extended Filter List */
+
+ uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
+ This parameter can be a number between:
+ - 0 and 127, if FilterList is 0 (Standard)
+ - 0 and 63, if FilterList is 1 (Extended) */
+
+ uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
+ This parameter can be a value of @ref FDCAN_hp_msg_storage */
+
+ uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the
+ message was stored.
+ This parameter is valid only when MessageStorage is:
+ FDCAN_HP_STORAGE_RXFIFO0
+ or
+ FDCAN_HP_STORAGE_RXFIFO1 */
+
+} FDCAN_HpMsgStatusTypeDef;
+
+/**
+ * @brief FDCAN Protocol Status structure definition
+ */
+typedef struct
+{
+ uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
+
+ uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
+ frame with its BRS flag set.
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
+
+ uint32_t Activity; /*!< Specifies the FDCAN module communication state.
+ This parameter can be a value of @ref FDCAN_communication_state */
+
+ uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
+ This parameter can be:
+ - 0 : The FDCAN is in Error_Active state
+ - 1 : The FDCAN is in Error_Passive state */
+
+ uint32_t Warning; /*!< Specifies the FDCAN module warning status.
+ This parameter can be:
+ - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
+ - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
+
+ uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
+ This parameter can be:
+ - 0 : The FDCAN is not in Bus_Off state
+ - 1 : The FDCAN is in Bus_Off state */
+
+ uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
+ This parameter can be:
+ - 0 : Last received CAN FD message did not have its ESI flag set
+ - 1 : Last received CAN FD message had its ESI flag set */
+
+ uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
+ This parameter can be:
+ - 0 : Last received CAN FD message did not have its BRS flag set
+ - 1 : Last received CAN FD message had its BRS flag set */
+
+ uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
+ This parameter can be:
+ - 0 : no CAN FD message received
+ - 1 : CAN FD message received */
+
+ uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
+ This parameter can be:
+ - 0 : No protocol exception event occurred since last read access
+ - 1 : Protocol exception event occurred */
+
+ uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
+ This parameter can be a number between 0 and 127 */
+
+} FDCAN_ProtocolStatusTypeDef;
+
+/**
+ * @brief FDCAN Error Counters structure definition
+ */
+typedef struct
+{
+ uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
+ This parameter can be a number between 0 and 255 */
+
+ uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
+ This parameter can be a number between 0 and 127 */
+
+ uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
+ This parameter can be:
+ - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
+ - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+
+ uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
+ This parameter can be a number between 0 and 255.
+ This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
+ or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
+ TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
+
+} FDCAN_ErrorCountersTypeDef;
+
+/**
+ * @brief FDCAN TT Init structure definition
+ */
+typedef struct
+{
+ uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode.
+ This parameter can be a value of @ref FDCAN_operation_mode */
+
+ uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation.
+ This parameter can be a value of @ref FDCAN_TT_operation.
+ This parameter is ignored if OperationMode is set to
+ FDCAN_TT_COMMUNICATION_LEVEL0 */
+
+ uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master.
+ This parameter can be a value of @ref FDCAN_TT_time_master */
+
+ uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
+ numerator : TUR = (Numerator ± SDL) / Denominator.
+ With : SDL = 2^(SyncDevLimit+5).
+ This parameter must be a number between 0 and 7 */
+
+ uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
+ This parameter must be a number between 0 and 127 */
+
+ uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization.
+ This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
+ This parameter is ignored if OperationMode is set to
+ FDCAN_TT_COMMUNICATION_LEVEL1 */
+
+ uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after
+ which the application has to serve the application watchdog.
+ The application watchdog is incremented once each 256 NTUs.
+ The application watchdog can be disabled by setting AppWdgLimit to 0.
+ This parameter must be a number between 0 and 255.
+ This parameter is ignored if OperationMode is set to
+ FDCAN_TT_COMMUNICATION_LEVEL0 */
+
+ uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering.
+ This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
+ This parameter is ignored if OperationMode is set to
+ FDCAN_TT_COMMUNICATION_LEVEL1 */
+
+ uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration.
+ This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
+ This parameter is ignored if OperationMode is set to
+ FDCAN_TT_COMMUNICATION_LEVEL1 */
+
+ uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity.
+ This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
+ This parameter is ignored if OperationMode is set to
+ FDCAN_TT_COMMUNICATION_LEVEL0 */
+
+ uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix.
+ This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */
+
+ uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
+ This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */
+
+ uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs.
+ This parameter must be a number between 1 and 16 */
+
+ uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix.
+ This is the sum of Tx_Triggers for exclusive, single arbitrating and
+ merged arbitrating windows.
+ This parameter must be a number between 0 and 4095 */
+
+ uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator.
+ It is adviced to set this parameter to the largest applicable value.
+ This parameter must be a number between 0x10000 and 0x1FFFF */
+
+ uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator.
+ This parameter must be a number between 0x0001 and 0x3FFF */
+
+ uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements.
+ This parameter must be a number between 0 and 64 */
+
+ uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger.
+ This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
+
+ uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger.
+ This parameter can be a value of @ref FDCAN_TT_event_trig_selection */
+
+} FDCAN_TT_ConfigTypeDef;
+
+/**
+ * @brief FDCAN Trigger structure definition
+ */
+typedef struct
+{
+ uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured.
+ This parameter must be a number between 0 and 63 */
+
+ uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active.
+ This parameter must be a number between 0 and 0xFFFF */
+
+ uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor.
+ This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */
+
+ uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active.
+ This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+ This parameter must be a number between 0 and RepeatFactor */
+
+ uint32_t TmEventInt; /*!< Enable or disable the internal time mark event.
+ If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
+ becomes active.
+ This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */
+
+ uint32_t TmEventExt; /*!< Enable or disable the external time mark event.
+ If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
+ trigger memory element becomes active.
+ This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */
+
+ uint32_t TriggerType; /*!< Specifies the trigger type.
+ This parameter can be a value of @ref FDCAN_TT_Trigger_Type */
+
+ uint32_t FilterType; /*!< Specifies the filter identifier type.
+ This parameter can be a value of @ref FDCAN_id_type */
+
+ uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
+ This parameter can be a value of @ref FDCAN_Tx_location.
+ This parameter is taken in consideration only if the trigger is configured for
+ transmission. */
+
+ uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid.
+ This parameter is taken in consideration only if the trigger is configured for
+ reception.
+ This parameter must be a number between:
+ - 0 and 127, if FilterType is FDCAN_STANDARD_ID
+ - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */
+
+} FDCAN_TriggerTypeDef;
+
+/**
+ * @brief FDCAN TT Operation Status structure definition
+ */
+typedef struct
+{
+ uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level.
+ This parameter can be a value of @ref FDCAN_TT_error_level */
+
+ uint32_t MasterState; /*!< Specifies the type of the TT master state.
+ This parameter can be a value of @ref FDCAN_TT_master_state */
+
+ uint32_t SyncState; /*!< Specifies the type of the TT synchronization state.
+ This parameter can be a value of @ref FDCAN_TT_sync_state */
+
+ uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase.
+ This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
+ This parameter can be:
+ - 0 : Global time not valid
+ - 1 : Global time in phase with Time Master */
+
+ uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed.
+ This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
+ This parameter can be:
+ - 0 : Local clock speed not synchronized to Time Master clock speed
+ - 1 : Synchronization Deviation = SDL */
+
+ uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value.
+ This parameter can be a number between 0 and 0xFF */
+
+ uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
+ This parameter can be:
+ - 0 : No global time preset pending
+ - 1 : Node waits for the global time preset to take effect */
+
+ uint32_t GapFinished; /*!< Specifies whether a Gap is finished.
+ This parameter can be:
+ - 0 : Reset at the end of each reference message
+ - 1 : Gap finished */
+
+ uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master.
+ This parameter can be a number between 0 and 0x7 */
+
+ uint32_t GapStarted; /*!< Specifies whether a Gap is started.
+ This parameter can be:
+ - 0 : No Gap in schedule
+ - 1 : Gap time after Basic Cycle has started */
+
+ uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced.
+ This parameter can be:
+ - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
+ - 1 : Reference message with Next_is_Gap = 1 received */
+
+ uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State.
+ This parameter can be:
+ - 0 : Application Watchdog served in time
+ - 1 : Failed to serve Application Watchdog in time */
+
+ uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State.
+ This parameter can be:
+ - 0 : No external clock synchronization pending
+ - 1 : Node waits for external clock synchronization to take effect */
+
+ uint32_t PhaseLock; /*!< Specifies the Phase Lock State.
+ This parameter can be:
+ - 0 : Phase outside range
+ - 1 : Phase inside range */
+
+} FDCAN_TTOperationStatusTypeDef;
+
+/**
+ * @brief FDCAN Message RAM blocks
+ */
+typedef struct
+{
+ uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address.
+ This parameter must be a 32-bit word address */
+
+ uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM.
+ This parameter must be a 32-bit word address */
+
+} FDCAN_MsgRamAddressTypeDef;
+
+/**
+ * @brief FDCAN handle structure definition
+ */
+typedef struct
+{
+ FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
+
+ TTCAN_TypeDef *ttcan; /*!< TT register base address */
+
+ FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
+
+ FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
+
+ uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
+ of latest Tx FIFO/Queue request */
+
+ __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< FDCAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< FDCAN Error code */
+
+
+} FDCAN_HandleTypeDef;
+
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
+ * @{
+ */
+#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
+#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */
+#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */
+#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */
+#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
+#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
+#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */
+#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */
+#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
+#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
+#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
+#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */
+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */
+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */
+#define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */
+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */
+#define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */
+#define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */
+#define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_frame_format FDCAN Frame Format
+ * @{
+ */
+#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */
+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */
+#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode
+ * @{
+ */
+#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
+#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
+#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
+#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
+ * @{
+ */
+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
+#define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider
+ * @{
+ */
+#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
+#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */
+#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */
+#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */
+#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
+ * @{
+ */
+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */
+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_calibration_state FDCAN Calibration State
+ * @{
+ */
+#define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */
+#define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */
+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
+ * @{
+ */
+#define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */
+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
+#define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size
+ * @{
+ */
+#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */
+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
+ * @{
+ */
+#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_id_type FDCAN ID Type
+ * @{
+ */
+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_frame_type FDCAN Frame Type
+ * @{
+ */
+#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code
+ * @{
+ */
+#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
+#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
+#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
+#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
+#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
+#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
+#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
+#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
+#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
+ * @{
+ */
+#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
+ * @{
+ */
+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
+#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_format FDCAN format
+ * @{
+ */
+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
+#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_EFC FDCAN Event FIFO control
+ * @{
+ */
+#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */
+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_filter_type FDCAN Filter Type
+ * @{
+ */
+#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
+#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
+#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */
+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration
+ * @{
+ */
+#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */
+#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
+#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
+#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */
+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */
+#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Tx_location FDCAN Tx Location
+ * @{
+ */
+#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
+#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
+#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
+#define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */
+#define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */
+#define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */
+#define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */
+#define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */
+#define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */
+#define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */
+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_location FDCAN Rx Location
+ * @{
+ */
+#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
+#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
+#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */
+#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */
+#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */
+#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */
+#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */
+#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */
+#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */
+#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */
+#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */
+#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */
+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_event_type FDCAN Event Type
+ * @{
+ */
+#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */
+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
+ * @{
+ */
+#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */
+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */
+#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
+#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
+ * @{
+ */
+#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */
+#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */
+#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */
+#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */
+#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
+#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
+#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */
+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_communication_state FDCAN communication state
+ * @{
+ */
+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
+#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */
+#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
+ * @{
+ */
+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
+#define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */
+#define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
+ * @{
+ */
+#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
+ * @{
+ */
+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
+#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
+ * @{
+ */
+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
+ * @{
+ */
+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timestamp FDCAN timestamp
+ * @{
+ */
+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
+ * @{
+ */
+#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
+#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */
+#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */
+#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */
+#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */
+#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */
+#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */
+#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */
+#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
+ * @{
+ */
+#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
+#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
+#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
+ * @{
+ */
+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */
+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
+ * @{
+ */
+#define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */
+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */
+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */
+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */
+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
+ * @{
+ */
+#define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */
+#define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */
+#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */
+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */
+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */
+#define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */
+#define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */
+#define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */
+#define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */
+#define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */
+#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
+ * @{
+ */
+#define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */
+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
+ * @{
+ */
+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */
+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode
+ * @{
+ */
+#define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
+#define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
+#define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_operation FDCAN TT Operation
+ * @{
+ */
+#define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */
+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
+ * @{
+ */
+#define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */
+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
+ * @{
+ */
+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */
+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
+ * @{
+ */
+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */
+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
+ * @{
+ */
+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */
+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
+ * @{
+ */
+#define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */
+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
+ * @{
+ */
+#define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
+ * @{
+ */
+#define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */
+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
+#define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
+ * @{
+ */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */
+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
+ * @{
+ */
+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */
+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */
+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */
+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
+ * @{
+ */
+#define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */
+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */
+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */
+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
+ * @{
+ */
+#define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */
+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
+ * @{
+ */
+#define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */
+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */
+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */
+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
+ * @{
+ */
+#define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */
+#define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */
+#define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */
+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State
+ * @{
+ */
+#define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
+#define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */
+#define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */
+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
+ * @{
+ */
+#define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */
+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
+#define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */
+#define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */
+/**
+ * @}
+ */
+
+/** @defgroup Interrupt_Masks Interrupt masks
+ * @{
+ */
+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
+#define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_flags FDCAN Flags
+ * @{
+ */
+#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */
+#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
+#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */
+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */
+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */
+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
+#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */
+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
+#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
+#define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
+#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
+#define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
+#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */
+#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */
+#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */
+#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */
+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */
+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
+#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */
+#define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */
+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Interrupts FDCAN Interrupts
+ * @{
+ */
+
+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
+ * @{
+ */
+#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */
+#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
+#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */
+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
+ * @{
+ */
+#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
+#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
+ * @{
+ */
+#define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */
+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
+ * @{
+ */
+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
+#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
+#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
+#define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
+ * @{
+ */
+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
+#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
+#define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
+ * @{
+ */
+#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
+#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
+#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
+#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
+ * @{
+ */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TTflags FDCAN TT Flags
+ * @{
+ */
+#define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */
+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */
+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */
+#define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */
+#define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */
+#define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
+#define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */
+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */
+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */
+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */
+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */
+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */
+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */
+#define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */
+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */
+#define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
+ * @{
+ */
+
+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
+ * @{
+ */
+#define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */
+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */
+#define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
+#define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
+ * @{
+ */
+#define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */
+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
+ * @{
+ */
+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
+ * @{
+ */
+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */
+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
+ * @{
+ */
+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */
+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */
+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */
+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */
+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
+ * @{
+ */
+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
+#define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */
+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */
+#define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset FDCAN handle state.
+ * @param __HANDLE__ FDCAN handle.
+ * @retval None
+ */
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
+ do{ \
+ (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
+ FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
+ }while(0)
+
+
+/**
+ * @brief Disable the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
+ do{ \
+ ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
+ FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
+ }while(0)
+
+/**
+ * @brief Check whether the specified FDCAN interrupt is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN interrupt.
+ * This parameter can be one of @arg FDCAN_Interrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+
+/**
+ * @brief Clear the specified FDCAN interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the interrupts to clear.
+ * This parameter can be any combination of @arg FDCAN_Interrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
+do{ \
+ ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
+ FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
+ }while(0)
+
+/**
+ * @brief Check whether the specified FDCAN flag is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ FDCAN flag.
+ * This parameter can be one of @arg FDCAN_flags
+ * @retval FlagStatus
+ */
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+
+/**
+ * @brief Clear the specified FDCAN flags.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ specifies the flags to clear.
+ * This parameter can be any combination of @arg FDCAN_flags
+ * @retval None
+ */
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+do{ \
+ ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
+ FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \
+ }while(0)
+
+/** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the FDCAN interrupt source to check.
+ * This parameter can be a value of @arg FDCAN_Interrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
+
+/**
+ * @brief Enable the specified FDCAN TT interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN TT interrupt.
+ * This parameter can be any combination of @arg FDCAN_TTInterrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified FDCAN TT interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN TT interrupt.
+ * This parameter can be any combination of @arg FDCAN_TTInterrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified FDCAN TT interrupt is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ FDCAN TT interrupt.
+ * This parameter can be one of @arg FDCAN_TTInterrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
+
+/**
+ * @brief Clear the specified FDCAN TT interrupts.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the TT interrupts to clear.
+ * This parameter can be any combination of @arg FDCAN_TTInterrupts
+ * @retval None
+ */
+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified FDCAN TT flag is set or not.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ FDCAN TT flag.
+ * This parameter can be one of @arg FDCAN_TTflags
+ * @retval FlagStatus
+ */
+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
+
+/**
+ * @brief Clear the specified FDCAN TT flags.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __FLAG__ specifies the TT flags to clear.
+ * This parameter can be any combination of @arg FDCAN_TTflags
+ * @retval None
+ */
+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
+
+/** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled.
+ * @param __HANDLE__ FDCAN handle.
+ * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
+ * This parameter can be a value of @arg FDCAN_TTInterrupts
+ * @retval ITStatus
+ */
+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FDCAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group2
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group3
+ * @{
+ */
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group4
+ * @{
+ */
+/* TT Configuration and control functions**************************************/
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group5
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group6
+ * @{
+ */
+/* Callback functions *********************************************************/
+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Exported_Functions_Group7
+ * @{
+ */
+/* Peripheral State functions *************************************************/
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Types FDCAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros
+ * @{
+ */
+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \
+ ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
+ ((FORMAT) == FDCAN_FRAME_FD_BRS ))
+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \
+ ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
+ ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \
+ ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \
+ ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK ))
+
+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
+ ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
+
+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV10) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV12) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV14) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV16) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV18) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV20) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV22) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV24) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV26) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV28) || \
+ ((CKDIV) == FDCAN_CLOCK_DIV30))
+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
+#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
+#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
+ ((SIZE) == FDCAN_DATA_BYTES_12) || \
+ ((SIZE) == FDCAN_DATA_BYTES_16) || \
+ ((SIZE) == FDCAN_DATA_BYTES_20) || \
+ ((SIZE) == FDCAN_DATA_BYTES_24) || \
+ ((SIZE) == FDCAN_DATA_BYTES_32) || \
+ ((SIZE) == FDCAN_DATA_BYTES_48) || \
+ ((SIZE) == FDCAN_DATA_BYTES_64))
+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
+ ((MODE) == FDCAN_TX_QUEUE_OPERATION))
+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
+ ((ID_TYPE) == FDCAN_EXTENDED_ID))
+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \
+ ((CONFIG) == FDCAN_FILTER_REJECT ) || \
+ ((CONFIG) == FDCAN_FILTER_HP ) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
+ ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER ))
+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
+ ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
+ ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
+ ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
+ ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
+ ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
+ ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
+ ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
+ ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
+ ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
+ ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
+ ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
+ ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
+ ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
+ ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
+ ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
+ ((FIFO) == FDCAN_RX_FIFO1))
+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
+ ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
+ ((TYPE) == FDCAN_FILTER_DUAL ) || \
+ ((TYPE) == FDCAN_FILTER_MASK ))
+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \
+ ((TYPE) == FDCAN_FILTER_DUAL ) || \
+ ((TYPE) == FDCAN_FILTER_MASK ) || \
+ ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \
+ ((TYPE) == FDCAN_REMOTE_FRAME))
+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_1 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_2 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_3 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_4 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_5 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_6 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_7 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_8 ) || \
+ ((DLC) == FDCAN_DLC_BYTES_12) || \
+ ((DLC) == FDCAN_DLC_BYTES_16) || \
+ ((DLC) == FDCAN_DLC_BYTES_20) || \
+ ((DLC) == FDCAN_DLC_BYTES_24) || \
+ ((DLC) == FDCAN_DLC_BYTES_32) || \
+ ((DLC) == FDCAN_DLC_BYTES_48) || \
+ ((DLC) == FDCAN_DLC_BYTES_64))
+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
+ ((ESI) == FDCAN_ESI_PASSIVE))
+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
+ ((BRS) == FDCAN_BRS_ON ))
+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
+ ((FDF) == FDCAN_FD_CAN ))
+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \
+ ((EFC) == FDCAN_STORE_TX_EVENTS))
+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
+ ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \
+ ((FIFO) == FDCAN_CFG_RX_FIFO1 ))
+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
+ ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
+ ((DESTINATION) == FDCAN_REJECT ))
+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
+ ((DESTINATION) == FDCAN_REJECT_REMOTE))
+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
+ ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
+ ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
+ ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \
+ ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
+ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \
+ ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 ))
+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
+ ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
+ ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
+ ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER ))
+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
+ ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \
+ ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
+ ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
+ ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
+ ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
+ ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
+ ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \
+ ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \
+ ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \
+ ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
+ ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
+ ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \
+ ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \
+ ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \
+ ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \
+ ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \
+ ((TYPE) == FDCAN_TT_END_OF_LIST ))
+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
+ ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
+ ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
+ ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
+ ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \
+ ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \
+ ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
+ ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
+ ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
+ ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
+ ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
+ ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
+ ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
+ ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
+ ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
+ ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
+ ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \
+ ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
+ ((SYNC) == FDCAN_TT_SYNC_MATRIX_START ))
+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
+ ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
+ ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
+ ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
+ ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
+ ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
+ ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \
+ ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
+ ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
+ ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
+ ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
+ ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
+ ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
+ ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* FDCAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_FDCAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h
new file mode 100644
index 0000000..ddb0c77
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h
@@ -0,0 +1,362 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_gpio.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_GPIO_H
+#define __STM32MP1xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_mode_define */
+
+ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+ This parameter can be a value of @ref GPIO_pull_define */
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_speed_define */
+
+ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+ * @brief GPIO Bit SET and Bit RESET enumeration
+ */
+typedef enum
+{
+ GPIO_PIN_RESET = 0,
+ GPIO_PIN_SET
+}GPIO_PinState;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define GPIO pins define
+ * @{
+ */
+#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
+
+#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+ * @brief GPIO Configuration Mode
+ * Elements values convention: 0xX0yz00YZ
+ * - X : GPIO mode or EXTI Mode
+ * - y : External IT or Event trigger detection
+ * - z : IO configuration on External IT or Event
+ * - Y : Output type (Push Pull or Open Drain)
+ * - Z : IO Direction mode (Input, Output, Alternate or Analog)
+ * @{
+ */
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
+
+#define GPIO_MODE_AF GPIO_MODE_AF_PP /*!< Alternate Function for Input PIN */
+
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
+
+#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_speed_define GPIO speed define
+ * @brief GPIO Output Maximum frequency
+ * @{
+ */
+#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */
+#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */
+#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */
+#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */
+/**
+ * @}
+ */
+
+ /** @defgroup GPIO_pull_define GPIO pull define
+ * @brief GPIO Pull-Up or Pull-Down Activation
+ * @{
+ */
+#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
+#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) ((EXTI->RPR1 & (__EXTI_LINE__)) | (EXTI->FPR1 & (__EXTI_LINE__)))
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) do { \
+ EXTI->RPR1 = (__EXTI_LINE__); \
+ EXTI->FPR1 = (__EXTI_LINE__); \
+ } while (0);
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not for Rising edge.
+
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__))
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not for Falling edge.
+
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__))
+
+/**
+ * @brief Clears the EXTI's line pending bits for Risng edge.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) do { \
+ EXTI->RPR1 = (__EXTI_LINE__); \
+ } while (0);
+
+/**
+ * @brief Clears the EXTI's line pending bits for Falling edge.
+ * @param __EXTI_LINE__: specifies the EXTI lines to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) do { \
+ EXTI->FPR1 = (__EXTI_LINE__); \
+ } while (0);
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the EXTI line to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval None
+
+ */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
+
+/**
+ * @brief Check whether the specified EXTI line flag is set or not.
+ * @param __EXTI_LINE__ specifies the EXTI line flag to check.
+ * This parameter can be GPIO_PIN_x where x can be(0..15)
+ * @retval The new state of __EXTI_LINE__ (SET or RESET).
+ */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
+
+/**
+ * @brief Clear the EXTI line pending flags.
+ * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+ * @retval None
+ */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
+
+/**
+ * @}
+ */
+
+/* Include GPIO HAL Extension module */
+#include "stm32mp1xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
+/**
+ * @}
+ */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+ * @{
+ */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK ) != 0x00u) &&\
+ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+ ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio_ex.h
new file mode 100644
index 0000000..7acec09
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio_ex.h
@@ -0,0 +1,317 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_gpio_ex.h
+ * @author MCD Application Team
+ * @brief Header file of GPIO HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_GPIO_EX_H
+#define __STM32MP1xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup GPIOEx GPIOEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+ * @{
+ */
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO1 ((uint8_t)0x00) /* MCO1 Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_HDP ((uint8_t)0x00) /* HDP Alternate Function mapping */
+
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_MCO2 ((uint8_t)0x01) /* MCO2 Alternate Function mapping */
+#define GPIO_AF1_RTC ((uint8_t)0x01) /* RTC Alternate Function mapping */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
+#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
+#define GPIO_AF2_SAI4 ((uint8_t)0x02) /* SAI4 Alternate Function mapping */
+#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */
+#define GPIO_AF2_MCO1 ((uint8_t)0x02) /* MCO1 Alternate Function mapping */
+#define GPIO_AF2_MCO2 ((uint8_t)0x02) /* MCO2 Alternate Function mapping */
+#define GPIO_AF2_HDP ((uint8_t)0x02) /* HDP Alternate Function mapping */
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF3_I2C2 ((uint8_t)0x03) /* I2C6 Alternate Function mapping */
+#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
+#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
+#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
+#define GPIO_AF3_SAI4 ((uint8_t)0x03) /* SAI4 Alternate Function mapping */
+#define GPIO_AF3_SDIO1 ((uint8_t)0x03) /* SDIO1 Alternate Function mapping */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
+#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
+#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
+#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF4_SAI4 ((uint8_t)0x04) /* SAI4 Alternate Function mapping */
+#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
+#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
+#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
+#define GPIO_AF5_I2C1 ((uint8_t)0x05) /* I2C1 Alternate Function mapping */
+#define GPIO_AF5_SDIO1 ((uint8_t)0x05) /* SDIO1 Alternate Function mapping */
+#define GPIO_AF5_SDIO3 ((uint8_t)0x05) /* SDIO3 Alternate Function mapping */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
+#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
+#define GPIO_AF6_SAI4 ((uint8_t)0x06) /* SAI4 Alternate Function mapping */
+#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
+#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
+#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
+#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
+#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
+#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
+#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
+#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
+#define GPIO_AF8_SDIO1 ((uint8_t)0x08) /* SDIO1 Alternate Function mapping */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
+#if defined (FDCAN1)
+#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
+#endif
+#if defined (FDCAN2)
+#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
+#endif
+#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO2 Alternate Function mapping */
+#define GPIO_AF9_LCD ((uint8_t)0x09) /* LCD Alternate Function mapping */
+#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
+#define GPIO_AF9_SDIO3 ((uint8_t)0x09) /* SDIO3 Alternate Function mapping */
+#define GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO3 Alternate Function mapping */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
+#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
+#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
+#define GPIO_AF10_SDIO2 ((uint8_t)0xA) /* SDIO2 Alternate Function mapping */
+#define GPIO_AF10_SDIO3 ((uint8_t)0xA) /* SDIO3 Alternate Function mapping */
+#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
+#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF11_QUADSPI ((uint8_t)0x0B) /* QUADSPI Alternate Function mapping */
+#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
+#if defined (DSI)
+#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */
+#endif
+#define GPIO_AF11_SDIO1 ((uint8_t)0x0B) /* SDIO1 Alternate Function mapping */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF12_UART5 ((uint8_t)0xC) /* UART5 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SDIO1 Alternate Function mapping */
+#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
+#define GPIO_AF12_SAI4 ((uint8_t)0xC) /* SAI4 Alternate Function mapping */
+#define GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SAI4 Alternate Function mapping */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF13_UART7 ((uint8_t)0x0D) /* UART7 Alternate Function mapping */
+#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
+#define GPIO_AF13_LCD ((uint8_t)0x0D) /* LCD Alternate Function mapping */
+#if defined (DSI)
+#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
+#endif
+#define GPIO_AF13_RNG ((uint8_t)0x0D) /* RNG Alternate Function mapping */
+
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
+#define GPIO_AF14_LCD ((uint8_t)0x0E) /* LCD Alternate Function mapping */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+ * @{
+ */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+ * @{
+ */
+#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+ ((__GPIOx__) == (GPIOB))? 1U :\
+ ((__GPIOx__) == (GPIOC))? 2U :\
+ ((__GPIOx__) == (GPIOD))? 3U :\
+ ((__GPIOx__) == (GPIOE))? 4U :\
+ ((__GPIOx__) == (GPIOF))? 5U :\
+ ((__GPIOx__) == (GPIOG))? 6U :\
+ ((__GPIOx__) == (GPIOH))? 7U :\
+ ((__GPIOx__) == (GPIOI))? 8U :\
+ ((__GPIOx__) == (GPIOJ))? 9U :\
+ ((__GPIOx__) == (GPIOK))? 10U :\
+ ((__GPIOx__) == (GPIOZ))? 11U : 25U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIOEx_Exported_Functions GPIO Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup GPIOEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @{
+ */
+
+void HAL_GPIOEx_SecurePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIOEx_NonSecurePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+
+
+GPIO_PinState HAL_GPIOEx_IsPinSecured(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_hsem.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_hsem.h
new file mode 100644
index 0000000..3771456
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_hsem.h
@@ -0,0 +1,210 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_hsem.h
+ * @author MCD Application Team
+ * @brief Header file of HSEM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_HSEM_H
+#define STM32MP1xx_HAL_HSEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HSEM
+ * @{
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
+ * @{
+ */
+
+/**
+ * @brief SemID to mask helper Macro.
+ * @param __SEMID__: semaphore ID from 0 to 31
+ * @retval Semaphore Mask.
+ */
+#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
+
+/**
+ * @brief Enables the specified HSEM interrupts.
+ * @param __SEM_MASK__: semaphores Mask
+ * @retval None.
+ */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+ (HSEM->C1IER |= (__SEM_MASK__)) : \
+ (HSEM->C2IER |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+/**
+ * @brief Disables the specified HSEM interrupts.
+ * @param __SEM_MASK__: semaphores Mask
+ * @retval None.
+ */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+ (HSEM->C1IER &= ~(__SEM_MASK__)) : \
+ (HSEM->C2IER &= ~(__SEM_MASK__)))
+#else
+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+ * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
+ * @param __SEM_MASK__: semaphores Mask
+ * @retval semaphores Mask : Semaphores where an interrupt occurred.
+ */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+ ((__SEM_MASK__) & HSEM->C1MISR) : \
+ ((__SEM_MASK__) & HSEM->C2MISR1))
+#else
+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
+#endif /* DUAL_CORE */
+
+/**
+ * @brief Get the semaphores release status flags.
+ * @param __SEM_MASK__: semaphores Mask
+ * @retval semaphores Mask : Semaphores where Release flags rise.
+ */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+ (__SEM_MASK__) & HSEM->C1ISR : \
+ (__SEM_MASK__) & HSEM->C2ISR)
+#else
+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
+#endif /* DUAL_CORE */
+
+/**
+ * @brief Clears the HSEM Interrupt flags.
+ * @param __SEM_MASK__: semaphores Mask
+ * @retval None.
+ */
+#if defined(DUAL_CORE)
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
+ (HSEM->C1ICR |= (__SEM_MASK__)) : \
+ (HSEM->C2ICR |= (__SEM_MASK__)))
+#else
+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
+#endif /* DUAL_CORE */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
+ * @{
+ */
+
+/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
+ * @brief HSEM Take and Release functions
+ * @{
+ */
+
+/* HSEM semaphore take (lock) using 2-Step method ****************************/
+HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
+/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
+/* HSEM Check semaphore state Taken or not **********************************/
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
+/* HSEM Release **************************************************************/
+void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
+/* HSEM Release All************************************************************/
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
+
+/**
+ * @}
+ */
+
+/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+ * @brief HSEM Set and Get Key functions.
+ * @{
+ */
+/* HSEM Set Clear Key *********************************************************/
+void HAL_HSEM_SetClearKey(uint32_t Key);
+/* HSEM Get Clear Key *********************************************************/
+uint32_t HAL_HSEM_GetClearKey(void);
+/**
+ * @}
+ */
+
+/** @addtogroup HSEM_Exported_Functions_Group3
+ * @brief HSEM Notification functions
+ * @{
+ */
+/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
+void HAL_HSEM_ActivateNotification(uint32_t SemMask);
+/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
+/* HSEM Free Callback (When a semaphore is released) *******************************/
+void HAL_HSEM_FreeCallback(uint32_t SemMask);
+/* HSEM IRQ Handler **********************************************************/
+void HAL_HSEM_IRQHandler(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup HSEM_Private_Macros HSEM Private Macros
+ * @{
+ */
+
+#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
+
+#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
+
+#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
+
+#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
+ ((__COREID__) == HSEM_CPU2_COREID))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_HSEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h
new file mode 100644
index 0000000..ec59672
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ipcc.h
@@ -0,0 +1,291 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_ipcc.h
+ * @author MCD Application Team
+ * @brief Header file of Mailbox HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_IPCC_H
+#define STM32MP1xx_HAL_IPCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup IPCC IPCC
+ * @brief IPCC HAL module driver
+ * @{
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IPCC_Exported_Constants IPCC Exported Constants
+ * @{
+ */
+
+/** @defgroup IPCC_Channel IPCC Channel
+ * @{
+ */
+#define IPCC_CHANNEL_1 0x00000000U
+#define IPCC_CHANNEL_2 0x00000001U
+#define IPCC_CHANNEL_3 0x00000002U
+#define IPCC_CHANNEL_4 0x00000003U
+#define IPCC_CHANNEL_5 0x00000004U
+#define IPCC_CHANNEL_6 0x00000005U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup IPCC_Exported_Types IPCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL IPCC State structures definition
+ */
+typedef enum
+{
+ HAL_IPCC_STATE_RESET = 0x00U, /*!< IPCC not yet initialized or disabled */
+ HAL_IPCC_STATE_READY = 0x01U, /*!< IPCC initialized and ready for use */
+ HAL_IPCC_STATE_BUSY = 0x02U /*!< IPCC internal processing is ongoing */
+} HAL_IPCC_StateTypeDef;
+
+/**
+ * @brief IPCC channel direction structure definition
+ */
+typedef enum
+{
+ IPCC_CHANNEL_DIR_TX = 0x00U, /*!< Channel direction Tx is used by an MCU to transmit */
+ IPCC_CHANNEL_DIR_RX = 0x01U /*!< Channel direction Rx is used by an MCU to receive */
+} IPCC_CHANNELDirTypeDef;
+
+/**
+ * @brief IPCC channel status structure definition
+ */
+typedef enum
+{
+ IPCC_CHANNEL_STATUS_FREE = 0x00U, /*!< Means that a new msg can be posted on that channel */
+ IPCC_CHANNEL_STATUS_OCCUPIED = 0x01U /*!< An MCU has posted a msg the other MCU hasn't retrieved */
+} IPCC_CHANNELStatusTypeDef;
+
+/**
+ * @brief IPCC handle structure definition
+ */
+typedef struct __IPCC_HandleTypeDef
+{
+ IPCC_TypeDef *Instance; /*!< IPCC registers base address */
+ void (* ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Rx Callback registration table */
+ void (* ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Tx Callback registration table */
+ uint32_t callbackRequest; /*!< Store information about callback notification by channel */
+ __IO HAL_IPCC_StateTypeDef State; /*!< IPCC State: initialized or not */
+} IPCC_HandleTypeDef;
+
+/**
+ * @brief IPCC callback typedef
+ */
+typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup IPCC_Exported_Macros IPCC Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the specified interrupt.
+ * @param __HANDLE__ specifies the IPCC Handle
+ * @param __CHDIRECTION__ specifies the channels Direction
+ * This parameter can be one of the following values:
+ * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
+ * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
+ */
+#if defined(CORE_CM4)
+#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_RXOIE) : \
+ ((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_TXFIE))
+#else
+#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \
+ ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE))
+#endif
+
+/**
+ * @brief Disable the specified interrupt.
+ * @param __HANDLE__ specifies the IPCC Handle
+ * @param __CHDIRECTION__ specifies the channels Direction
+ * This parameter can be one of the following values:
+ * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
+ * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
+ */
+#if defined(CORE_CM4)
+#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_RXOIE) : \
+ ((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_TXFIE))
+#else
+#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \
+ ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE))
+#endif
+
+/**
+ * @brief Mask the specified interrupt.
+ * @param __HANDLE__ specifies the IPCC Handle
+ * @param __CHDIRECTION__ specifies the channels Direction
+ * This parameter can be one of the following values:
+ * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
+ * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
+ * @param __CHINDEX__ specifies the channels number:
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ */
+#if defined(CORE_CM4)
+#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
+ ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
+#else
+#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
+ ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
+#endif
+
+/**
+ * @brief Unmask the specified interrupt.
+ * @param __HANDLE__ specifies the IPCC Handle
+ * @param __CHDIRECTION__ specifies the channels Direction
+ * This parameter can be one of the following values:
+ * @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
+ * @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
+ * @param __CHINDEX__ specifies the channels number:
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ */
+#if defined(CORE_CM4)
+#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
+ ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
+#else
+#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
+ (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
+ ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
+ ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
+#endif
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IPCC_Exported_Functions IPCC Exported Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *******************************/
+/** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc);
+HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc);
+void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc);
+void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc);
+/**
+ * @}
+ */
+
+/** @defgroup IPCC_Exported_Functions_Group2 Communication functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
+HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+/**
+ * @}
+ */
+
+/** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions
+ * @{
+ */
+/* Peripheral State and Error functions ****************************************/
+HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc);
+/**
+ * @}
+ */
+
+/** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks
+ * @{
+ */
+/* IRQHandler and Callbacks used in non blocking modes ************************/
+void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
+void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
+void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_IPCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h
new file mode 100644
index 0000000..45fc113
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h
@@ -0,0 +1,858 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_mdma.h
+ * @author MCD Application Team
+ * @version V0.3.0
+ * @date 9-December-2016
+ * @brief Header file of DMA HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_MDMA_H
+#define __STM32MP1xx_HAL_MDMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MDMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Types MDMA Exported Types
+ * @brief MDMA Exported Types
+ * @{
+ */
+
+/**
+ * @brief MDMA Configuration Structure definition
+ */
+typedef struct
+{
+
+ uint32_t Request; /*!< Specifies the MDMA request.
+ This parameter can be a value of @ref MDMA_Request_selection*/
+
+ uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a :
+ a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
+ This parameter can be a value of @ref MDMA_Transfer_TriggerMode */
+
+ uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx.
+ This parameter can be a value of @ref MDMA_Priority_level */
+
+ uint32_t SecureMode; /*!< Specifies if the MDMA master transactions are done in secure mode.
+ This parameter can be a value of @ref MDMA_Secure_Mode */
+
+ uint32_t Endianess; /*!< Specifies if the MDMA transactions preserve the Little endianess.
+ This parameter can be a value of @ref MDMA_Endianess */
+
+ uint32_t SourceInc; /*!< Specifies if the Source increment mode .
+ This parameter can be a value of @ref MDMA_Source_increment_mode */
+
+ uint32_t DestinationInc; /*!< Specifies if the Destination increment mode .
+ This parameter can be a value of @ref MDMA_Destination_increment_mode */
+
+ uint32_t SourceDataSize; /*!< Specifies the source data size.
+ This parameter can be a value of @ref MDMA_Source_data_size */
+
+ uint32_t DestDataSize; /*!< Specifies the destination data size.
+ This parameter can be a value of @ref MDMA_Destination_data_size */
+
+
+ uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode.
+ This parameter can be a value of @ref MDMA_data_Alignment */
+
+ uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes),
+ this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
+
+ uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction.
+ This parameter can be a value of @ref MDMA_Source_burst
+ @note : the burst may be FIXED/INCR based on SourceInc value ,
+ the BURST must be programmed as to ensure that the burst size will be lower than than
+ BufferTransferLength */
+
+ uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptable
+ transaction.
+ This parameter can be a value of @ref MDMA_Destination_burst
+ @note : the burst may be FIXED/INCR based on DestinationInc value ,
+ the BURST must be programmed as to ensure that the burst size will be lower than than
+ BufferTransferLength */
+
+ int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset
+ signed value : if > 0 then increment the next block source Address by offset from where the last block ends
+ if < 0 then decrement the next block source Address by offset from where the last block ends
+ if == 0, the next block source address starts from where the last block ends
+ */
+
+
+ int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset
+ signed value : if > 0 then increment the next block destination Address by offset from where the last block ends
+ if < 0 then decrement the next block destination Address by offset from where the last block ends
+ if == 0, the next block destination address starts from where the last block ends
+ */
+
+}MDMA_InitTypeDef;
+
+/**
+ * @brief HAL MDMA linked list node structure definition
+ * @note The Linked list node allows to define a new MDMA configuration
+ * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
+ * When CLAR register is configured to a non NULL value , each time a transfer ends,
+ * a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
+ */
+typedef struct
+{
+ uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */
+ uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */
+ uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */
+ uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */
+ uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */
+ uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */
+ uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */
+ uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */
+ uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */
+
+}MDMA_LinkNodeTypeDef;
+
+/**
+ * @brief HAL MDMA linked list node configuration structure definition
+ * @note used with HAL_MDMA_LinkedList_CreateNode function
+ */
+typedef struct
+{
+ MDMA_InitTypeDef Init; /* !< configuration of the specified MDMA Linked List Node */
+ uint32_t SrcAddress; /* !< The source memory address for the Linked list Node */
+ uint32_t DstAddress; /* !< The destination memory address for the Linked list Node */
+ uint32_t BlockDataLength; /* !< The length of a block transfer in bytes */
+ uint32_t BlockCount; /* !< The number of a blocks to be transfer */
+
+ uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
+ PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
+
+ uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
+ PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
+
+
+}MDMA_LinkNodeConfTypeDef;
+
+
+/**
+ * @brief HAL MDMA State structure definition
+ */
+typedef enum
+{
+ HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */
+ HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */
+ HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */
+ HAL_MDMA_STATE_TIMEOUT = 0x03U, /*!< MDMA timeout state */
+ HAL_MDMA_STATE_ERROR = 0x04U, /*!< MDMA error state */
+ HAL_MDMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
+
+}HAL_MDMA_StateTypeDef;
+
+/**
+ * @brief HAL MDMA Level Complete structure definition
+ */
+typedef enum
+{
+ HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */
+ HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */
+ HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */
+
+}HAL_MDMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL MDMA Callbacks IDs structure definition
+ */
+typedef enum
+{
+ HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */
+ HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */
+ HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */
+ HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
+ HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
+ HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */
+
+}HAL_MDMA_CallbackIDTypeDef;
+
+
+/**
+ * @brief MDMA handle Structure definition
+ */
+typedef struct __MDMA_HandleTypeDef
+{
+ MDMA_Channel_TypeDef *Instance; /*!< Register base address */
+
+ MDMA_InitTypeDef Init; /*!< MDMA communication parameters */
+
+
+ HAL_LockTypeDef Lock; /*!< MDMA locking object */
+
+ __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */
+
+ void *Parent; /*!< Parent object state */
+
+ void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */
+
+ void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */
+
+ void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */
+
+ void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */
+
+ void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */
+
+ void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */
+
+
+ MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list
+ (after the initial node defined by the Init struct)
+ this parameter is used internally by the MDMA driver
+ to construct the liked list node
+ */
+
+ MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list
+ this parameter is used internally by the MDMA driver
+ to construct the liked list node
+ */
+ uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */
+
+ __IO uint32_t ErrorCode; /*!< MDMA Error code */
+
+} MDMA_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
+ * @brief MDMA Exported constants
+ * @{
+ */
+
+/** @defgroup MDMA_Error_Codes MDMA Error Codes
+ * @brief MDMA Error Codes
+ * @{
+ */
+#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */
+#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */
+#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */
+#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */
+#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */
+#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */
+#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
+#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */
+#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Request_selection MDMA Request selection
+ * @brief MDMA_Request_selection
+ * @{
+ */
+
+#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */
+#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */
+#define MDMA_REQUEST_FMC_DATA ((uint32_t)0x00000014U) /*!< MDMA HW request is NAND data transfer (Tx or Rx) channel */
+#define MDMA_REQUEST_FMC_ERROR ((uint32_t)0x00000015U) /*!< MDMA HW request is NAND ECC/BCH Error channel */
+#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */
+#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */
+#if defined(CRYP1)
+#define MDMA_REQUEST_CRYP1_IN ((uint32_t)0x0000001DU) /*!< MDMA HW request is CRYP1 4 word request from input */
+#define MDMA_REQUEST_CRYP1_OUT ((uint32_t)0x0000001EU) /*!< MDMA HW request is CRYP1 4 word request from output */
+#endif
+#define MDMA_REQUEST_HASH1_IN ((uint32_t)0x0000001FU) /*!< MDMA HW request is HASH1 16 word request from input */
+#define MDMA_REQUEST_USART1_RX ((uint32_t)0x00000020U) /*!< MDMA HW request is USART1 Rx Transfer Complete Flag */
+#define MDMA_REQUEST_USART1_TX ((uint32_t)0x00000021U) /*!< MDMA HW request is USART1 Tx Transfer Complete Flag */
+#define MDMA_REQUEST_SPI6_RX ((uint32_t)0x00000022U) /*!< MDMA HW request is SPI6 Rx Transfer Complete Flag */
+#define MDMA_REQUEST_SPI6_TX ((uint32_t)0x00000023U) /*!< MDMA HW request is SPI6 Tx Transfer Complete Flag */
+#define MDMA_REQUEST_I2C4_RX ((uint32_t)0x00000024U) /*!< MDMA HW request is I2C4 Rx Transfer Complete Flag */
+#define MDMA_REQUEST_I2C4_TX ((uint32_t)0x00000025U) /*!< MDMA HW request is I2C4 Tx Transfer Complete Flag */
+#define MDMA_REQUEST_I2C6_RX ((uint32_t)0x00000026U) /*!< MDMA HW request is I2C6 Rx Transfer Complete Flag */
+#define MDMA_REQUEST_I2C6_TX ((uint32_t)0x00000027U) /*!< MDMA HW request is I2C6 Tx Transfer Complete Flag */
+#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode
+ * @brief MDMA Transfer Trigger Mode
+ * @{
+ */
+#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
+#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
+#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
+#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Priority_level MDMA Priority level
+ * @brief MDMA Priority level
+ * @{
+ */
+#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
+#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */
+#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */
+#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Secure_Mode MDMA Secure Mode
+ * @brief MDMA Secure Mode
+ * @{
+ */
+#define MDMA_SECURE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< Secure Mode disabled */
+#define MDMA_SECURE_MODE_ENABLE ((uint32_t)MDMA_CCR_SM) /*!< Secure Mode enabled */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Endianess MDMA Endianess
+ * @brief MDMA Endianess
+ * @{
+ */
+#define MDMA_LITTLE_ENDIANESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianess preserve */
+#define MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianess exchange when destination data size is > Byte */
+#define MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianess exchange when destination data size is > HALF WORD*/
+#define MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianess exchange when destination data size is > DOUBLE WORD */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
+ * @brief MDMA Source increment mode
+ * @{
+ */
+#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
+#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
+#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
+#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
+#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
+#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
+ * @brief MDMA Destination increment mode
+ * @{
+ */
+#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
+#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
+#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
+#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
+#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
+#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
+#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Source_data_size MDMA Source data size
+ * @brief MDMA Source data size
+ * @{
+ */
+#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
+#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
+#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
+#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Destination_data_size MDMA Destination data size
+ * @brief MDMA Destination data size
+ * @{
+ */
+#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
+#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
+#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
+#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_data_Alignment MDMA data alignment
+ * @brief MDMA MDMA data alignment
+ * @{
+ */
+#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size
+ All data are right aligned, in Little Endien mode. */
+#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
+#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended ,
+ Note : this mode is allowed only if the Source data size smaller than Destination data size */
+#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Source_burst MDMA Source burst
+ * @brief MDMA Source burst
+ * @{
+ */
+#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
+#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
+#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
+#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
+#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
+#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
+#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
+#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_Destination_burst MDMA Destination burst
+ * @brief MDMA Destination burst
+ * @{
+ */
+#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
+#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
+#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
+#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
+#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
+#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
+#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
+#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
+ * @brief MDMA interrupt enable definitions
+ * @{
+ */
+#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
+#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */
+#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
+#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup MDMA_flag_definitions MDMA flag definitions
+ * @brief MDMA flag definitions
+ * @{
+ */
+#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
+#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
+#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
+#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
+#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
+#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup MDMA_Exported_Macros MDMA Exported Macros
+ * @{
+ */
+
+/**
+ * @brief Enable the specified MDMA Channel.
+ * @param __HANDLE__: MDMA handle
+ * @retval None
+ */
+#define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
+
+/**
+ * @brief Disable the specified DMA Channel.
+ * @param __HANDLE__: MDMA handle
+ * @retval None
+ */
+#define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
+
+/**
+ * @brief Get the MDMA Channel pending flags.
+ * @param __HANDLE__: MDMA handle
+ * @param __FLAG__: Get the specified flag.
+ * This parameter can be any combination of the following values:
+ * @arg MDMA_FLAG_TE : Transfer Error flag.
+ * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
+ * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
+ * @arg MDMA_FLAG_BT : Block Transfer complete flag.
+ * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+ * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
+ * @retval The state of FLAG (SET or RESET).
+ */
+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
+
+/**
+ * @brief Clear the MDMA Stream pending flags.
+ * @param __HANDLE__: MDMA handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg MDMA_FLAG_TE : Transfer Error flag.
+ * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
+ * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
+ * @arg MDMA_FLAG_BT : Block Transfer complete flag.
+ * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
+ * @retval None
+ */
+#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA Channel interrupts.
+ * @param __HANDLE__: MDMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg MDMA_IT_TE : Transfer Error interrupt mask
+ * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
+ * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
+ * @arg MDMA_IT_BT : Block Transfer interrupt mask
+ * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
+ * @retval None
+ */
+#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified MDMA Channel interrupts.
+ * @param __HANDLE__: MDMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg MDMA_IT_TE : Transfer Error interrupt mask
+ * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
+ * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
+ * @arg MDMA_IT_BT : Block Transfer interrupt mask
+ * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
+ * @retval None
+ */
+#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified MDMA Channel interrupt is enabled or not.
+ * @param __HANDLE__: DMA handle
+ * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * @arg MDMA_IT_TE : Transfer Error interrupt mask
+ * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
+ * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
+ * @arg MDMA_IT_BT : Block Transfer interrupt mask
+ * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
+ * @retval The state of MDMA_IT (SET or RESET).
+ */
+#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDMA_Exported_Functions MDMA Exported Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
+
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
+
+/**
+ * @}
+ */
+
+/* Linked list operation functions ********************************************/
+/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
+ * @brief Linked list operation functions
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+
+
+/**
+ * @}
+ */
+
+/* IO operation functions *****************************************************/
+/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
+ * @brief I/O operation functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
+
+/**
+ * @}
+ */
+
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
+uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
+
+void HAL_MDMA_MspInit(MDMA_HandleTypeDef *hmdma);
+void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Types MDMA Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MDMA_Private_Defines MDMA Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Variables MDMA Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Constants MDMA Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDMA_Private_Macros MDMA Private Macros
+ * @{
+ */
+
+/** @defgroup MDMA_IS_Definitions MDMA Private macros to check input parameters
+ * @{
+ */
+
+#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \
+ ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
+ ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
+ ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
+
+
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
+ ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+ ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
+ ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+
+#define IS_MDMA_SECURE_MODE(__SECURE_MODE__) (((__SECURE_MODE__) == MDMA_SECURE_MODE_DISABLE ) || \
+ ((__SECURE_MODE__) == MDMA_SECURE_MODE_ENABLE))
+
+#define IS_MDMA_ENDIANESS_MODE(__ENDIANESS__) (((__ENDIANESS__) == MDMA_LITTLE_ENDIANESS_PRESERVE ) || \
+ ((__ENDIANESS__) == MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE) || \
+ ((__ENDIANESS__) == MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE) || \
+ ((__ENDIANESS__) == MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE))
+
+
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_I2C6_TX))
+
+#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \
+ ((__INC__) == MDMA_SRC_INC_BYTE ) || \
+ ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \
+ ((__INC__) == MDMA_SRC_INC_WORD ) || \
+ ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
+ ((__INC__) == MDMA_SRC_DEC_BYTE) || \
+ ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \
+ ((__INC__) == MDMA_SRC_DEC_WORD) || \
+ ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \
+ ((__INC__) == MDMA_DEST_INC_BYTE ) || \
+ ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \
+ ((__INC__) == MDMA_DEST_INC_WORD ) || \
+ ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
+ ((__INC__) == MDMA_DEST_DEC_BYTE) || \
+ ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \
+ ((__INC__) == MDMA_DEST_DEC_WORD) || \
+ ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
+
+#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \
+ ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
+ ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \
+ ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \
+ ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
+ ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \
+ ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
+
+#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \
+ ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
+ ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
+ ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+
+
+#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
+ ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
+ ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
+ ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \
+ ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
+ ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
+ ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
+ ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
+
+
+#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
+ ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
+ ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
+ ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \
+ ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
+ ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
+ ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
+ ((__BURST__) == MDMA_DEST_BURST_128BEATS))
+
+ #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \
+ ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
+ ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+ ((__MODE__) == MDMA_FULL_TRANSFER))
+
+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
+
+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
+
+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
+
+#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MDMA_Private_Functions MDMA Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_MDMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr.h
new file mode 100644
index 0000000..50f21cd
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr.h
@@ -0,0 +1,496 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_pwr.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_PWR_H
+#define __STM32MP1xx_HAL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Types PWR Exported Types
+ * @{
+ */
+/**
+ * @brief PWR PVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
+ This parameter can be a value of @ref PWR_PVD_detection_level */
+
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWR_PVD_Mode */
+} PWR_PVDTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+ * @{
+ */
+#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /* 1.95V */
+#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /* 2.1V */
+#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /* 2.25V */
+#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /* 2.4V */
+#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /* 2.55V */
+#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /* 2.7V */
+#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /* 2.85V */
+#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /* External voltage level on PVD_IN
+ (compared to internal VREFINT) */
+
+#define IS_PWR_PVD_LEVEL(__LEVEL__) (((__LEVEL__) == PWR_PVDLEVEL_0) || ((__LEVEL__) == PWR_PVDLEVEL_1)|| \
+ ((__LEVEL__) == PWR_PVDLEVEL_2) || ((__LEVEL__) == PWR_PVDLEVEL_3)|| \
+ ((__LEVEL__) == PWR_PVDLEVEL_4) || ((__LEVEL__) == PWR_PVDLEVEL_5)|| \
+ ((__LEVEL__) == PWR_PVDLEVEL_6) || ((__LEVEL__) == PWR_PVDLEVEL_7))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+ * @{
+ */
+#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+
+#define IS_PWR_PVD_MODE(__MODE__) (((__MODE__) == PWR_PVD_MODE_NORMAL) || ((__MODE__) == PWR_PVD_MODE_IT_RISING) || \
+ ((__MODE__) == PWR_PVD_MODE_IT_FALLING) || ((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP_mode
+ * @{
+ */
+#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
+
+#define IS_PWR_REGULATOR(__REGULATOR__) (((__REGULATOR__) == PWR_MAINREGULATOR_ON) || \
+ ((__REGULATOR__) == PWR_LOWPOWERREGULATOR_ON))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+ * @{
+ */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
+#define IS_PWR_SLEEP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_SLEEPENTRY_WFI) || ((__ENTRY__) == PWR_SLEEPENTRY_WFE))
+/**
+ * @}
+ */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+ * @{
+ */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
+
+#define IS_PWR_STOP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_STOPENTRY_WFI) || ((__ENTRY__) == PWR_STOPENTRY_WFE))
+/**
+ * @}
+ */
+
+
+
+/** @defgroup PWR_Flag PWR Flag
+ * @{
+ */
+#define PWR_FLAG_SB ((uint8_t)0x01U) /* System STANDBY Flag */
+#define PWR_FLAG_STOP ((uint8_t)0x02U) /* STOP Flag */
+#define PWR_FLAG_CSB ((uint8_t)0x03U) /* MPU CSTANBY flag */
+#define PWR_FLAG_AVDO ((uint8_t)0x06U)
+#define PWR_FLAG_PVDO ((uint8_t)0x07U)
+#define PWR_FLAG_BRR ((uint8_t)0x08U)
+#define PWR_FLAG_RRR ((uint8_t)0x09U)
+#define PWR_FLAG_VBATL ((uint8_t)0x0AU)
+#define PWR_FLAG_VBATH ((uint8_t)0x0BU)
+#define PWR_FLAG_TEMPL ((uint8_t)0x0CU)
+#define PWR_FLAG_TEMPH ((uint8_t)0x0DU)
+#define PWR_FLAG_11R ((uint8_t)0x0EU)
+#define PWR_FLAG_18R ((uint8_t)0x0FU)
+#define PWR_FLAG_USB ((uint8_t)0x10U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+ * @{
+ */
+
+/** @brief Check PWR flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
+ * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
+ * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
+ * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode
+ * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+ * resumed from StandBy mode.
+ * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
+ * when the device wakes up from Standby mode or by a system reset
+ * or power reset.
+ * @arg PWR_FLAG_RRR: Retention Regulator ready flag. This bit is not reset
+ * when the device wakes up from Standby mode or by a system reset
+ * or power reset.
+ * @arg PWR_FLAG_VBATL:
+ * @arg PWR_FLAG_VBATH:
+ * @arg PWR_FLAG_TEMPL:
+ * @arg PWR_FLAG_TEMPH:
+ * @arg PWR_FLAG_11R: 1V1 regulator supply ready
+ * @arg PWR_FLAG_18R: 1V8 regulator supply ready
+ * @arg PWR_FLAG_USB: USB 3.3V supply ready
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @arg PWR_FLAG_STOP: STOP flag
+ * @arg PWR_FLAG_CSB_MPU: MPU CSTANBY flag
+ *
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#ifdef CORE_CM4
+#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
+((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
+((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
+((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
+((__FLAG__) == PWR_FLAG_RRR)?((PWR->CR2 & PWR_CR2_RRRDY) == PWR_CR2_RRRDY) : \
+((__FLAG__) == PWR_FLAG_VBATL)?((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL) : \
+((__FLAG__) == PWR_FLAG_VBATH)?((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) : \
+((__FLAG__) == PWR_FLAG_TEMPL)?((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) : \
+((__FLAG__) == PWR_FLAG_TEMPH)?((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) : \
+((__FLAG__) == PWR_FLAG_11R)?((PWR->CR3 & PWR_CR3_REG11RDY) == PWR_CR3_REG11RDY) : \
+((__FLAG__) == PWR_FLAG_18R)?((PWR->CR3 & PWR_CR3_REG18RDY) == PWR_CR3_REG18RDY) : \
+((__FLAG__) == PWR_FLAG_USB)?((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) : \
+((__FLAG__) == PWR_FLAG_SB)?((PWR->MCUCR & PWR_MCUCR_SBF) == PWR_MCUCR_SBF) : \
+((__FLAG__) == PWR_FLAG_STOP)?((PWR->MCUCR & PWR_MCUCR_STOPF) == PWR_MCUCR_STOPF) : \
+((PWR->MPUCR & PWR_MPUCR_SBF_MPU) == PWR_MPUCR_SBF_MPU))
+#elif defined (CORE_CA7)
+#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
+((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
+((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
+((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
+((__FLAG__) == PWR_FLAG_RRR)?((PWR->CR2 & PWR_CR2_RRRDY) == PWR_CR2_RRRDY) : \
+((__FLAG__) == PWR_FLAG_VBATL)?((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL) : \
+((__FLAG__) == PWR_FLAG_VBATH)?((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) : \
+((__FLAG__) == PWR_FLAG_TEMPL)?((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) : \
+((__FLAG__) == PWR_FLAG_TEMPH)?((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) : \
+((__FLAG__) == PWR_FLAG_11R)?((PWR->CR3 & PWR_CR3_REG11RDY) == PWR_CR3_REG11RDY) : \
+((__FLAG__) == PWR_FLAG_18R)?((PWR->CR3 & PWR_CR3_REG18RDY) == PWR_CR3_REG18RDY) : \
+((__FLAG__) == PWR_FLAG_USB)?((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) : \
+((__FLAG__) == PWR_FLAG_SB)?((PWR->MPUCR & PWR_MPUCR_SBF) == PWR_MPUCR_SBF) : \
+((__FLAG__) == PWR_FLAG_STOP)?((PWR->MPUCR & PWR_MPUCR_STOPF) == PWR_MPUCR_STOPF) : \
+((PWR->MPUCR & PWR_MPUCR_SBF_MPU) == PWR_MPUCR_SBF_MPU))
+#endif /*CORE_CA7*/
+
+#ifdef CORE_CM4
+/** @brief Clear the PWR's flags.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_FLAG_STOP
+ * @arg @ref PWR_FLAG_SB
+ * @retval None.
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->MCUCR, PWR_MCUCR_CSSF);
+#elif defined (CORE_CA7)
+/** @brief Clear the PWR's flags.
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg @ref PWR_FLAG_STOP
+ * @arg @ref PWR_FLAG_SB
+ * @arg @ref PWR_FLAG_CSB flags
+ * @retval None.
+ */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->MPUCR, PWR_MPUCR_CSSF);
+
+
+#endif /*CORE_CA7*/
+
+
+/**
+ * @brief Enable the PVD AVD Exti Line.
+ * @retval None.
+ */
+#ifdef CORE_CM4
+#define __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_C2->IMR1, PWR_EXTI_LINE_PVD_AVD)
+#elif defined (CORE_CA7)
+#define __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_C1->IMR1, PWR_EXTI_LINE_PVD_AVD)
+#endif /*CORE_CA7*/
+
+
+/**
+ * @brief Disable the PVD AVD EXTI Line.
+ * @retval None.
+ */
+#ifdef CORE_CM4
+#define __HAL_PWR_PVD_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_C2->IMR1, PWR_EXTI_LINE_PVD_AVD)
+#elif defined (CORE_CA7)
+#define __HAL_PWR_PVD_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_C1->IMR1, PWR_EXTI_LINE_PVD_AVD)
+#endif /*CORE_CA7*/
+
+
+/**
+ * @brief Enable the PVD AVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD_AVD)
+
+/**
+ * @brief Disable the PVD AVD Extended Interrupt Rising Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD_AVD)
+
+
+/**
+ * @brief Enable the PVD AVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD_AVD)
+
+
+/**
+ * @brief Disable the PVD AVD Extended Interrupt Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD_AVD)
+
+
+/**
+ * @brief PVD AVD EXTI line configuration: set rising & falling edge trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do { \
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_FALLING_EDGE(); \
+} while(0);
+
+/**
+ * @brief Disable the PVD AVD Extended Interrupt Rising & Falling Trigger.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do { \
+ __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_AVD_EXTI_DISABLE_FALLING_EDGE(); \
+} while(0);
+
+
+/**
+ * @brief Check whether the specified PVD AVD EXTI interrupt flag is set or not.
+ * @retval EXTI PVD AVD Line Status.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_GET_FLAG() \
+ (((EXTI->RPR1 & PWR_EXTI_LINE_PVD_AVD) == PWR_EXTI_LINE_PVD_AVD) || \
+ ((EXTI->FPR1 & PWR_EXTI_LINE_PVD_AVD) == PWR_EXTI_LINE_PVD_AVD))
+
+
+/**
+ * @brief Clear the PVD AVD Exti flag.
+ * @retval None.
+ */
+#define __HAL_PWR_PVD_AVD_EXTI_CLEAR_FLAG() \
+do { \
+ SET_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVD_AVD); \
+ SET_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVD_AVD); \
+} while(0);
+
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @retval None
+ */
+/* PVD AVD Event in Bank1 */
+#define __HAL_PWR_PVD_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD_AVD )
+
+
+/* Include PWR HAL Extension module */
+#include "stm32mp1xx_hal_pwr_ex.h"
+
+/**
+ * @brief Enable WKUPx pin wakeup interrupt on AIEC for core 2.
+ * @param __WKUP_LINE__: specifies the WKUP pin line.
+ * This parameter can be one of the following values:
+ * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 1 line
+ * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 2 line
+ * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 3 line
+ * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 4 line
+ * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 5 line
+ * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 6 line
+ * @retval None
+ */
+#ifdef CORE_CM4
+#define __HAL_WKUP_EXTI_ENABLE_IT(__WKUP_LINE__) (EXTI_C2->IMR2 |= (__WKUP_LINE__))
+#elif defined(CORE_CA7)
+#define __HAL_WKUP_EXTI_ENABLE_IT(__WKUP_LINE__) (EXTI_C1->IMR2 |= (__WKUP_LINE__))
+#endif /*CORE_CA7*/
+
+/**
+ * @brief Disable WKUPx pin wakeup interrupt on AIEC for core 2.
+ * * @param __WKUP_LINE__: specifies the WKUP pin line.
+ * This parameter can be one of the following values:
+ * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 1 line
+ * @arg AIEC_WKUP2_WAKEUP: Wakeup pin 2 line
+ * @arg AIEC_WKUP3_WAKEUP: Wakeup pin 3 line
+ * @arg AIEC_WKUP4_WAKEUP: Wakeup pin 4 line
+ * @arg AIEC_WKUP5_WAKEUP: Wakeup pin 5 line
+ * @arg AIEC_WKUP6_WAKEUP: Wakeup pin 6 line
+ * @retval None
+ */
+#ifdef CORE_CM4
+#define __HAL_WKUP_EXTI_DISABLE_IT(__WKUP_LINE__) CLEAR_BIT(EXTI_C2->IMR2, __WKUP_LINE__)
+#elif defined(CORE_CA7)
+#define __HAL_WKUP_EXTI_DISABLE_IT(__WKUP_LINE__) CLEAR_BIT(EXTI_C1->IMR2, __WKUP_LINE__)
+#endif /*CORE_CA7*/
+
+/**
+* @}
+*/
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+* @}
+*/
+
+/* Peripheral Control functions **********************************************/
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* WakeUp pin IT functions */
+void HAL_PWR_EnableWakeUpPinIT(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPinIT(uint32_t WakeUpPinx);
+
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+
+/* Power PVD IRQ Callback */
+void HAL_PWR_PVDCallback(void);
+
+/**
+* @}
+*/
+
+/* Cortex System Control functions *******************************************/
+/** @defgroup PWR_Exported_Functions_Group3 Cortex System Control functions
+ * @{
+ */
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+* @}
+*/
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
+
+/** @defgroup PWR_EXTI_LINE_PVD_AVD PWR EXTI Line PVD AVD
+ * @{
+ */
+#define PWR_EXTI_LINE_PVD_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
+ Connected to the PVD AVD EXTI
+ Line */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_PWR_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr_ex.h
new file mode 100644
index 0000000..876089a
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_pwr_ex.h
@@ -0,0 +1,440 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_pwr_ex.h
+ * @author MCD Application Team
+ * @brief Header file of PWR HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_PWR_EX_H
+#define __STM32MP1xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup PWREx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Types PWREx Exported Types
+ * @{
+ */
+/**
+ * @brief PWREx AVD configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level.
+ This parameter can be a value of @ref PWREx AVD detection level */
+ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref PWREx AVD Mode */
+} PWREx_AVDTypeDef;
+/**
+ * @}
+ */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Constants_Group1 PWREx_WakeUp_Pins
+ * @{
+ */
+
+#ifdef CORE_CA7
+/* Defines for legacy purpose */
+#define PWR_WAKEUP_PIN_MASK PWR_MPUWKUPENR_WKUPEN
+#define PWR_WAKEUP_PIN6 PWR_MPUWKUPENR_WKUPEN_6
+#define PWR_WAKEUP_PIN5 PWR_MPUWKUPENR_WKUPEN_5
+#define PWR_WAKEUP_PIN4 PWR_MPUWKUPENR_WKUPEN_4
+#define PWR_WAKEUP_PIN3 PWR_MPUWKUPENR_WKUPEN_3
+#define PWR_WAKEUP_PIN2 PWR_MPUWKUPENR_WKUPEN_2
+#define PWR_WAKEUP_PIN1 PWR_MPUWKUPENR_WKUPEN_1
+/* Defines for legacy purpose */
+
+/* High level + No pull */
+#define PWR_WAKEUP_PIN6_HIGH PWR_MPUWKUPENR_WKUPEN_6
+#define PWR_WAKEUP_PIN5_HIGH PWR_MPUWKUPENR_WKUPEN_5
+#define PWR_WAKEUP_PIN4_HIGH PWR_MPUWKUPENR_WKUPEN_4
+#define PWR_WAKEUP_PIN3_HIGH PWR_MPUWKUPENR_WKUPEN_3
+#define PWR_WAKEUP_PIN2_HIGH PWR_MPUWKUPENR_WKUPEN_2
+#define PWR_WAKEUP_PIN1_HIGH PWR_MPUWKUPENR_WKUPEN_1
+/* Low level + No pull */
+#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPCR_WKUPP_6 | PWR_MPUWKUPENR_WKUPEN_6)
+#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPCR_WKUPP_5 | PWR_MPUWKUPENR_WKUPEN_5)
+#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPCR_WKUPP_4 | PWR_MPUWKUPENR_WKUPEN_4)
+#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPCR_WKUPP_3 | PWR_MPUWKUPENR_WKUPEN_3)
+#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPCR_WKUPP_2 | PWR_MPUWKUPENR_WKUPEN_2)
+#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPCR_WKUPP_1 | PWR_MPUWKUPENR_WKUPEN_1)
+#endif /*CORE_CA7*/
+
+#ifdef CORE_CM4
+/* Defines for legacy purpose */
+#define PWR_WAKEUP_PIN_MASK PWR_MCUWKUPENR_WKUPEN
+#define PWR_WAKEUP_PIN6 PWR_MCUWKUPENR_WKUPEN6
+#define PWR_WAKEUP_PIN5 PWR_MCUWKUPENR_WKUPEN5
+#define PWR_WAKEUP_PIN4 PWR_MCUWKUPENR_WKUPEN4
+#define PWR_WAKEUP_PIN3 PWR_MCUWKUPENR_WKUPEN3
+#define PWR_WAKEUP_PIN2 PWR_MCUWKUPENR_WKUPEN2
+#define PWR_WAKEUP_PIN1 PWR_MCUWKUPENR_WKUPEN1
+/* Defines for legacy purpose */
+
+/* High level + No pull */
+#define PWR_WAKEUP_PIN6_HIGH PWR_MCUWKUPENR_WKUPEN6
+#define PWR_WAKEUP_PIN5_HIGH PWR_MCUWKUPENR_WKUPEN5
+#define PWR_WAKEUP_PIN4_HIGH PWR_MCUWKUPENR_WKUPEN4
+#define PWR_WAKEUP_PIN3_HIGH PWR_MCUWKUPENR_WKUPEN3
+#define PWR_WAKEUP_PIN2_HIGH PWR_MCUWKUPENR_WKUPEN2
+#define PWR_WAKEUP_PIN1_HIGH PWR_MCUWKUPENR_WKUPEN1
+/* Low level + No pull */
+#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPCR_WKUPP_6 | PWR_MCUWKUPENR_WKUPEN6)
+#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPCR_WKUPP_5 | PWR_MCUWKUPENR_WKUPEN5)
+#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPCR_WKUPP_4 | PWR_MCUWKUPENR_WKUPEN4)
+#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPCR_WKUPP_3 | PWR_MCUWKUPENR_WKUPEN3)
+#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPCR_WKUPP_2 | PWR_MCUWKUPENR_WKUPEN2)
+#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPCR_WKUPP_1 | PWR_MCUWKUPENR_WKUPEN1)
+#endif /*CORE_CM4*/
+
+/* High level + Pull-up */
+#define PWR_WAKEUP_PIN6_HIGH_PULLUP (uint32_t)(PWR_MPUWKUPENR_WKUPEN_6 | PWR_WKUPCR_WKUPPUPD6_0 )
+#define PWR_WAKEUP_PIN5_HIGH_PULLUP (uint32_t)(PWR_MPUWKUPENR_WKUPEN_5 | PWR_WKUPCR_WKUPPUPD5_0 )
+#define PWR_WAKEUP_PIN4_HIGH_PULLUP (uint32_t)(PWR_MPUWKUPENR_WKUPEN_4 | PWR_WKUPCR_WKUPPUPD4_0 )
+#define PWR_WAKEUP_PIN3_HIGH_PULLUP (uint32_t)(PWR_MPUWKUPENR_WKUPEN_3 | PWR_WKUPCR_WKUPPUPD3_0 )
+#define PWR_WAKEUP_PIN2_HIGH_PULLUP (uint32_t)(PWR_MPUWKUPENR_WKUPEN_2 | PWR_WKUPCR_WKUPPUPD2_0 )
+#define PWR_WAKEUP_PIN1_HIGH_PULLUP (uint32_t)(PWR_MPUWKUPENR_WKUPEN_1 | PWR_WKUPCR_WKUPPUPD1_0 )
+/* Low level + Pull-up */
+#define PWR_WAKEUP_PIN6_LOW_PULLUP (uint32_t)(PWR_WKUPCR_WKUPP_6 | PWR_MPUWKUPENR_WKUPEN_6 | PWR_WKUPCR_WKUPPUPD6_0)
+#define PWR_WAKEUP_PIN5_LOW_PULLUP (uint32_t)(PWR_WKUPCR_WKUPP_5 | PWR_MPUWKUPENR_WKUPEN_5 | PWR_WKUPCR_WKUPPUPD5_0)
+#define PWR_WAKEUP_PIN4_LOW_PULLUP (uint32_t)(PWR_WKUPCR_WKUPP_4 | PWR_MPUWKUPENR_WKUPEN_4 | PWR_WKUPCR_WKUPPUPD4_0)
+#define PWR_WAKEUP_PIN3_LOW_PULLUP (uint32_t)(PWR_WKUPCR_WKUPP_3 | PWR_MPUWKUPENR_WKUPEN_3 | PWR_WKUPCR_WKUPPUPD3_0)
+#define PWR_WAKEUP_PIN2_LOW_PULLUP (uint32_t)(PWR_WKUPCR_WKUPP_2 | PWR_MPUWKUPENR_WKUPEN_2 | PWR_WKUPCR_WKUPPUPD2_0)
+#define PWR_WAKEUP_PIN1_LOW_PULLUP (uint32_t)(PWR_WKUPCR_WKUPP_1 | PWR_MPUWKUPENR_WKUPEN_1 | PWR_WKUPCR_WKUPPUPD1_0)
+/* High level + Pull-down */
+#define PWR_WAKEUP_PIN6_HIGH_PULLDOWN (uint32_t)(PWR_MPUWKUPENR_WKUPEN_6 | PWR_WKUPCR_WKUPPUPD6_1 )
+#define PWR_WAKEUP_PIN5_HIGH_PULLDOWN (uint32_t)(PWR_MPUWKUPENR_WKUPEN_5 | PWR_WKUPCR_WKUPPUPD5_1 )
+#define PWR_WAKEUP_PIN4_HIGH_PULLDOWN (uint32_t)(PWR_MPUWKUPENR_WKUPEN_4 | PWR_WKUPCR_WKUPPUPD4_1 )
+#define PWR_WAKEUP_PIN3_HIGH_PULLDOWN (uint32_t)(PWR_MPUWKUPENR_WKUPEN_3 | PWR_WKUPCR_WKUPPUPD3_1 )
+#define PWR_WAKEUP_PIN2_HIGH_PULLDOWN (uint32_t)(PWR_MPUWKUPENR_WKUPEN_2 | PWR_WKUPCR_WKUPPUPD2_1 )
+#define PWR_WAKEUP_PIN1_HIGH_PULLDOWN (uint32_t)(PWR_MPUWKUPENR_WKUPEN_1 | PWR_WKUPCR_WKUPPUPD1_1 )
+/* Low level + Pull-down */
+#define PWR_WAKEUP_PIN6_LOW_PULLDOWN (uint32_t)(PWR_WKUPCR_WKUPP_6 | PWR_MPUWKUPENR_WKUPEN_6 | PWR_WKUPCR_WKUPPUPD6_1)
+#define PWR_WAKEUP_PIN5_LOW_PULLDOWN (uint32_t)(PWR_WKUPCR_WKUPP_5 | PWR_MPUWKUPENR_WKUPEN_5 | PWR_WKUPCR_WKUPPUPD5_1)
+#define PWR_WAKEUP_PIN4_LOW_PULLDOWN (uint32_t)(PWR_WKUPCR_WKUPP_4 | PWR_MPUWKUPENR_WKUPEN_4 | PWR_WKUPCR_WKUPPUPD4_1)
+#define PWR_WAKEUP_PIN3_LOW_PULLDOWN (uint32_t)(PWR_WKUPCR_WKUPP_3 | PWR_MPUWKUPENR_WKUPEN_3 | PWR_WKUPCR_WKUPPUPD3_1)
+#define PWR_WAKEUP_PIN2_LOW_PULLDOWN (uint32_t)(PWR_WKUPCR_WKUPP_2 | PWR_MPUWKUPENR_WKUPEN_2 | PWR_WKUPCR_WKUPPUPD2_1)
+#define PWR_WAKEUP_PIN1_LOW_PULLDOWN (uint32_t)(PWR_WKUPCR_WKUPP_1 | PWR_MPUWKUPENR_WKUPEN_1 | PWR_WKUPCR_WKUPPUPD1_1)
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Constants_Group2 PWREx Wakeup Pins Flags
+ * @{
+ */
+#define PWR_WAKEUP_PIN_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */
+#define PWR_WAKEUP_PIN_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */
+#define PWR_WAKEUP_PIN_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */
+#define PWR_WAKEUP_PIN_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */
+#define PWR_WAKEUP_PIN_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */
+#define PWR_WAKEUP_PIN_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */
+/**
+ * @}
+ */
+
+
+/** @defgroup PWREx_Exported_Constants_Group3 PWREx Core definition
+ * @{
+ */
+#define PWR_CORE_CPU1 ((uint32_t)0x00)
+#define PWR_CORE_CPU2 ((uint32_t)0x01)
+/**
+ * @}
+ */
+
+
+/** @defgroup PWREx_Exported_Constants_Group4 PWREx AVD detection level
+ * @{
+ */
+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /* 1.7 V */
+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /* 2.1 V */
+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /* 2.5 V */
+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /* 2.8 V */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Constants_Group5 PWREx AVD Mode
+ * @{
+ */
+#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
+#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Constants_Group6 PWR battery charging resistor selection
+ * @{
+ */
+#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhm resistor */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhm resistor */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Constants_Group7 PWREx VBAT Thresholds
+ * @{
+ */
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
+#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL /*!< Vsw low threshold is ~1.35V */
+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH /*!< Vsw high threshold is ~3.6V */
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Constants_Group8 PWREx Temperature Thresholds
+ * @{
+ */
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
+#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
+ * @{
+ */
+
+/** @brief Check Wake Up flag is set or not.
+ * @param __WUFLAG__: specifies the Wake Up flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag 1
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag 2
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag 3
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag 4
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag 5
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag 6
+ */
+#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->WKUPFR & (__WUFLAG__))
+
+/** @brief Clear the WakeUp pins flags.
+ * @param __WUFLAG__: specifies the Wake Up pin flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag 1
+ * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag 2
+ * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag 3
+ * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag 4
+ * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag 5
+ * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag 6
+ */
+#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) SET_BIT(PWR->WKUPCR, (__WUFLAG__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Low power control functions
+ * @{
+ */
+/* Power core holding functions */
+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
+void HAL_PWREx_ReleaseCore(uint32_t CPU);
+
+
+/* Power Wakeup PIN IRQ Handler */
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
+void HAL_PWREx_WKUP1_Callback(void);
+void HAL_PWREx_WKUP2_Callback(void);
+void HAL_PWREx_WKUP3_Callback(void);
+void HAL_PWREx_WKUP4_Callback(void);
+void HAL_PWREx_WKUP5_Callback(void);
+void HAL_PWREx_WKUP6_Callback(void);
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group2 Peripherals control functions
+ * @{
+ */
+/* Backup regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
+
+/* Retention regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_EnableRetReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableRetReg(void);
+
+/* 1V1 regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_Enable1V1Reg(void);
+HAL_StatusTypeDef HAL_PWREx_Disable1V1Reg(void);
+
+/* 1V8 regulator control functions */
+HAL_StatusTypeDef HAL_PWREx_Enable1V8Reg(void);
+HAL_StatusTypeDef HAL_PWREx_Disable1V8Reg(void);
+
+/* Battery control functions */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
+void HAL_PWREx_DisableBatteryCharging(void);
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_Exported_Functions_Group3 Power Monitoring functions
+ * @{
+ */
+/* Power VBAT/Temperature monitoring functions */
+void HAL_PWREx_EnableMonitoring(void);
+void HAL_PWREx_DisableMonitoring(void);
+uint32_t HAL_PWREx_GetTemperatureLevel(void);
+uint32_t HAL_PWREx_GetVBATLevel(void);
+
+/* USB Voltage level detector functions */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBVoltageDetector(void);
+HAL_StatusTypeDef HAL_PWREx_DisableUSBVoltageDetector(void);
+
+/* Power AVD configuration functions */
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
+void HAL_PWREx_EnableAVD(void);
+void HAL_PWREx_DisableAVD(void);
+
+/* Power PVD/AVD IRQ Handler */
+void HAL_PWREx_PVD_AVD_IRQHandler(void);
+void HAL_PWREx_AVDCallback(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+ * @{
+ */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+ * @{
+ */
+
+#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \
+ ((__PIN__) == PWR_WAKEUP_PIN2) || \
+ ((__PIN__) == PWR_WAKEUP_PIN3) || \
+ ((__PIN__) == PWR_WAKEUP_PIN4) || \
+ ((__PIN__) == PWR_WAKEUP_PIN5) || \
+ ((__PIN__) == PWR_WAKEUP_PIN6) || \
+ ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \
+ ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \
+ ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \
+ ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \
+ ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \
+ ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \
+ ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \
+ ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \
+ ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \
+ ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \
+ ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \
+ ((__PIN__) == PWR_WAKEUP_PIN6_LOW) || \
+ ((__PIN__) == PWR_WAKEUP_PIN6_HIGH_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN5_HIGH_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN4_HIGH_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN3_HIGH_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN2_HIGH_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN1_HIGH_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN6_LOW_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN5_LOW_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN4_LOW_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN3_LOW_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN2_LOW_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN1_LOW_PULLUP) || \
+ ((__PIN__) == PWR_WAKEUP_PIN6_HIGH_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN5_HIGH_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN4_HIGH_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN3_HIGH_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN2_HIGH_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN1_HIGH_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN6_LOW_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN5_LOW_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN4_LOW_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN3_LOW_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN2_LOW_PULLDOWN) || \
+ ((__PIN__) == PWR_WAKEUP_PIN1_LOW_PULLDOWN))
+
+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
+ ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))
+
+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
+ ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_NORMAL))
+
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+
+#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32MP1xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h
new file mode 100644
index 0000000..cdf8c66
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h
@@ -0,0 +1,4493 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_rcc.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_RCC_H
+#define __STM32MP1xx_HAL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/**
+ * @brief RCC PLL configuration structure definition
+ */
+typedef struct
+{
+ uint32_t PLLState; /*!< The new state of the PLL.
+ This parameter can be a value of @ref RCC_PLL_Config */
+
+ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
+ This parameter must be a value of @ref RCC_PLL12_Clock_Source */
+
+ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
+ This parameter must be a number between 1 and 64 */
+
+ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock
+ This parameter must be a number between:
+ Integer mode: 25 and 100 for PLL1600 (PLL1 and PLL2), 25 and 200 for PLL800
+ Fractional mode: 4 and 512 (PLL1600 and PLL800) */
+
+ uint32_t PLLP; /*!< PLLP: Division factor ck_pll1_p
+ This parameter must be a number between 1 and 128 */
+
+ uint32_t PLLQ; /*!< PLLQ: Division factor ck_pll1_q
+ This parameter must be a number between 1 and 128 */
+
+ uint32_t PLLR; /*!< PLLR: Division for ck_pll1_r
+ This parameter must be a number between 1 and 128 */
+
+ uint32_t PLLRGE; /*!< PLLRGE: PLL input frequency range for PLL3 and PLL4
+ This parameter must be a value of @ref RCC_PLL3_IF_Range and RCC_PLL4_IF_Range */
+
+ uint32_t PLLFRACV; /*!< PLLFRACV: Fractional Part Of The Multiplication Factor for PLL1 VCO
+ It should be a value between 0 and 8191 ((2^13)-1) */
+
+ uint32_t PLLMODE; /*!< PLLMODE: PLL mode used
+ This parameter must be a value of @ref RCC_PLL_Mode */
+
+ uint32_t MOD_PER; /*!< MOD_PER: Modulation Period Adjustment
+ This parameter must have a value contained on @ref RCC_MOD_PER */
+
+ uint32_t RPDFN_DIS; /*!< RPDFN_DIS: Dithering RPDF noise control
+ This parameter must be a value of @ref RCC_RPDFN_DIS*/
+
+ uint32_t TPDFN_DIS; /*!< TPDFN_DIS: Dithering TPDF noise control
+ This parameter must be a value of @ref RCC_TPDFN_DIS*/
+
+ uint32_t SSCG_MODE; /*!< SSCG_MODE: Spread spectrum clock generator mode
+ This parameter must be a value of @ref RCC_SSCG_MODE*/
+
+ uint32_t INC_STEP; /*!< INC_STEP: Modulation Depth Adjustment
+ This parameter must have a value contained on @ref RCC_INC_STEP */
+
+} RCC_PLLInitTypeDef;
+
+
+
+
+typedef struct
+{
+ uint32_t PLL1_P_Frequency;
+ uint32_t PLL1_Q_Frequency;
+ uint32_t PLL1_R_Frequency;
+} PLL1_ClocksTypeDef;
+
+/**
+ * @brief RCC PLL2 Clocks structure definition => [FCH] used in UART set_config use case
+ */
+typedef struct
+{
+ uint32_t PLL2_P_Frequency;
+ uint32_t PLL2_Q_Frequency;
+ uint32_t PLL2_R_Frequency;
+} PLL2_ClocksTypeDef;
+
+/**
+ * @brief RCC PLL3 Clocks structure definition => [FCH] used in UART set_config use case
+ */
+typedef struct
+{
+ uint32_t PLL3_P_Frequency;
+ uint32_t PLL3_Q_Frequency;
+ uint32_t PLL3_R_Frequency;
+} PLL3_ClocksTypeDef;
+
+
+typedef struct
+{
+ uint32_t PLL4_P_Frequency;
+ uint32_t PLL4_Q_Frequency;
+ uint32_t PLL4_R_Frequency;
+} PLL4_ClocksTypeDef;
+
+/**
+ * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
+ */
+typedef struct
+{
+
+ uint32_t OscillatorType; /*!< The oscillators to be configured.
+ This parameter can be a value of @ref RCC_Oscillator_Type */
+
+ uint32_t HSEState; /*!< The new state of the HSE.
+ This parameter can be a value of @ref RCC_HSE_Config */
+
+ uint32_t LSEState; /*!< The new state of the LSE.
+ This parameter can be a value of @ref RCC_LSE_Config */
+
+ uint32_t HSIState; /*!< The new state of the HSI.
+ This parameter can be a value of @ref RCC_HSI_Config */
+
+ uint32_t HSICalibrationValue; /*!< The calibration trimming value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
+ uint32_t HSIDivValue; /*!< The HSI Division value.
+ This parameter must be a value of @ref RCC_HSI_Clock_Prescaler */
+
+ uint32_t LSIState; /*!< The new state of the LSI.
+ This parameter can be a value of @ref RCC_LSI_Config */
+
+ uint32_t CSIState; /*!< The new state of the CSI.
+ This parameter can be a value of @ref RCC_CSI_Config */
+
+ uint32_t CSICalibrationValue; /*!< The calibration trimming value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+ RCC_PLLInitTypeDef PLL; /*!< PLL1 structure parameters */
+
+ RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */
+
+ RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */
+
+ RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters */
+
+} RCC_OscInitTypeDef;
+
+/**
+ * @brief MPU configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t MPU_Clock;
+ uint32_t MPU_Div;
+} RCC_MPUInitTypeDef;
+
+/**
+ * @brief AXI configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t AXI_Clock;
+ uint32_t AXI_Div;
+} RCC_AXISSInitTypeDef;
+
+
+/**
+ * @brief MCU configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t MCU_Clock;
+ uint32_t MCU_Div;
+} RCC_MCUInitTypeDef;
+
+/**
+ * @brief RCC MPU, MCU, AXI, AHB and APB busses clock configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t ClockType; /*!< The clock to be configured.
+ This parameter can be a value of @ref RCC_System_Clock_Type */
+
+ RCC_MPUInitTypeDef MPUInit;
+ RCC_AXISSInitTypeDef AXISSInit;
+ RCC_MCUInitTypeDef MCUInit;
+ uint32_t APB4_Div;
+ uint32_t APB5_Div;
+ uint32_t APB1_Div;
+ uint32_t APB2_Div;
+ uint32_t APB3_Div;
+} RCC_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+ * @{
+ */
+#define DBP_TIMEOUT_VALUE ((uint32_t)100)
+#define LSE_TIMEOUT_VALUE ((uint32_t)5000)
+
+/** @defgroup RCC_Oscillator_Type RCC_Oscillator_Type
+ * @{
+ */
+#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
+#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
+#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
+#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
+#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+#define RCC_OSCILLATORTYPE_CSI ((uint32_t)0x00000010)
+
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_System_Clock_Type RCC_System_Clock_Type
+ * @{
+ */
+#define RCC_CLOCKTYPE_NONE ((uint32_t)0x00000000)
+#define RCC_CLOCKTYPE_MPU ((uint32_t)0x00000001)
+#define RCC_CLOCKTYPE_ACLK ((uint32_t)0x00000002)
+#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000004)
+#define RCC_CLOCKTYPE_PCLK4 ((uint32_t)0x00000008)
+#define RCC_CLOCKTYPE_PCLK5 ((uint32_t)0x00000010)
+#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000020)
+#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000040)
+#define RCC_CLOCKTYPE_PCLK3 ((uint32_t)0x00000080)
+
+
+
+#define IS_RCC_CLOCKTYPETYPE(CLOCK) (((CLOCK) == RCC_CLOCKTYPE_NONE) || \
+ (((CLOCK) & RCC_CLOCKTYPE_MPU) == RCC_CLOCKTYPE_MPU) || \
+ (((CLOCK) & RCC_CLOCKTYPE_ACLK)== RCC_CLOCKTYPE_ACLK) || \
+ (((CLOCK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((CLOCK) & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4) || \
+ (((CLOCK) & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5) || \
+ (((CLOCK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
+ (((CLOCK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) || \
+ (((CLOCK) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSE_Config RCC_HSE_Config
+ * @{
+ */
+#define RCC_HSE_OFF ((uint32_t)0x00000000)
+#define RCC_HSE_ON RCC_OCENSETR_HSEON
+#define RCC_HSE_BYPASS (RCC_OCENSETR_HSEBYP | RCC_OCENSETR_HSEON)
+#define RCC_HSE_BYPASS_DIG (RCC_OCENSETR_HSEBYP | RCC_OCENSETR_HSEON | RCC_OCENSETR_DIGBYP)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIG))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSE_Config RCC_LSE_Config
+ * @{
+ */
+#define RCC_LSE_OFF ((uint32_t)0x00000000)
+#define RCC_LSE_ON RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)
+#define RCC_LSE_BYPASS_DIG (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON | RCC_BDCR_DIGBYP)
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIG))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Config RCC_HSI_Config
+ * @{
+ */
+#define RCC_HSI_OFF ((uint32_t)0x00000000)
+#define RCC_HSI_ON RCC_OCENSETR_HSION
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_HSI_Clock_Prescaler RCC_HSI_Clock_Prescaler
+ * @{
+ */
+#define RCC_HSI_DIV1 RCC_HSICFGR_HSIDIV_0 /* Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)*/
+#define RCC_HSI_DIV2 RCC_HSICFGR_HSIDIV_1 /* Division by 2, ck_hsi(_ker) = 32 MHz*/
+#define RCC_HSI_DIV4 RCC_HSICFGR_HSIDIV_2 /* Division by 4, ck_hsi(_ker) = 16 MHz*/
+#define RCC_HSI_DIV8 RCC_HSICFGR_HSIDIV_3 /* Division by 8, ck_hsi(_ker) = 8 MHz*/
+
+#define IS_RCC_HSIDIV(DIV) (((DIV) == RCC_HSI_DIV1) || ((DIV) == RCC_HSI_DIV2) || \
+ ((DIV) == RCC_HSI_DIV4) || ((DIV) == RCC_HSI_DIV8) )
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_LSI_Config RCC_LSI_Config
+ * @{
+ */
+#define RCC_LSI_OFF ((uint32_t)0x00000000)
+#define RCC_LSI_ON RCC_RDLSICR_LSION
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_CSI_Config RCC_CSI_Config
+ * @{
+ */
+#define RCC_CSI_OFF ((uint32_t)0x00000000)
+#define RCC_CSI_ON RCC_OCENSETR_CSION
+
+#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_MCO_Index RCC_MCO_Index
+ * @{
+ */
+#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO2 ((uint32_t)0x00000001)
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO1_Clock_Source RCC_MCO1_Clock_Source
+ * @{
+ */
+#define RCC_MCO1SOURCE_HSI RCC_MCO1CFGR_MCO1SEL_0
+#define RCC_MCO1SOURCE_HSE RCC_MCO1CFGR_MCO1SEL_1
+#define RCC_MCO1SOURCE_CSI RCC_MCO1CFGR_MCO1SEL_2
+#define RCC_MCO1SOURCE_LSI RCC_MCO1CFGR_MCO1SEL_3
+#define RCC_MCO1SOURCE_LSE RCC_MCO1CFGR_MCO1SEL_4
+
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
+ ((SOURCE) == RCC_MCO1SOURCE_CSI) || ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
+ ((SOURCE) == RCC_MCO1SOURCE_LSE) )
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCO2_Clock_Source RCC_MCO2_Clock_Source
+ * @{
+ */
+#define RCC_MCO2SOURCE_MPU RCC_MCO2CFGR_MCO2SEL_0
+#define RCC_MCO2SOURCE_AXI RCC_MCO2CFGR_MCO2SEL_1
+#define RCC_MCO2SOURCE_MCU RCC_MCO2CFGR_MCO2SEL_2
+#define RCC_MCO2SOURCE_PLL4 RCC_MCO2CFGR_MCO2SEL_3
+#define RCC_MCO2SOURCE_HSE RCC_MCO2CFGR_MCO2SEL_4
+#define RCC_MCO2SOURCE_HSI RCC_MCO2CFGR_MCO2SEL_5
+
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_MPU) || ((SOURCE) == RCC_MCO2SOURCE_AXI) || \
+ ((SOURCE) == RCC_MCO2SOURCE_MCU) || ((SOURCE) == RCC_MCO2SOURCE_PLL4) || \
+ ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_HSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler RCC_MCOx_Clock_Prescaler
+ * @{
+ * @note: MCO1 division factors are used for MCODIV values as they are the same for MCO2
+ */
+#define RCC_MCODIV_1 RCC_MCO1CFGR_MCO1DIV_0
+#define RCC_MCODIV_2 RCC_MCO1CFGR_MCO1DIV_1
+#define RCC_MCODIV_3 RCC_MCO1CFGR_MCO1DIV_2
+#define RCC_MCODIV_4 RCC_MCO1CFGR_MCO1DIV_3
+#define RCC_MCODIV_5 RCC_MCO1CFGR_MCO1DIV_4
+#define RCC_MCODIV_6 RCC_MCO1CFGR_MCO1DIV_5
+#define RCC_MCODIV_7 RCC_MCO1CFGR_MCO1DIV_6
+#define RCC_MCODIV_8 RCC_MCO1CFGR_MCO1DIV_7
+#define RCC_MCODIV_9 RCC_MCO1CFGR_MCO1DIV_8
+#define RCC_MCODIV_10 RCC_MCO1CFGR_MCO1DIV_9
+#define RCC_MCODIV_11 RCC_MCO1CFGR_MCO1DIV_10
+#define RCC_MCODIV_12 RCC_MCO1CFGR_MCO1DIV_11
+#define RCC_MCODIV_13 RCC_MCO1CFGR_MCO1DIV_12
+#define RCC_MCODIV_14 RCC_MCO1CFGR_MCO1DIV_13
+#define RCC_MCODIV_15 RCC_MCO1CFGR_MCO1DIV_14
+#define RCC_MCODIV_16 RCC_MCO1CFGR_MCO1DIV_15
+
+
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
+ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+ ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \
+ ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \
+ ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \
+ ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \
+ ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \
+ ((DIV) == RCC_MCODIV_15) || ((DIV) == RCC_MCODIV_16) )
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_MPU_Clock_Source RCC_MPU_Clock_Source
+ * @{
+ */
+#define RCC_MPUSOURCE_HSI RCC_MPCKSELR_MPUSRC_0
+#define RCC_MPUSOURCE_HSE RCC_MPCKSELR_MPUSRC_1
+#define RCC_MPUSOURCE_PLL1 RCC_MPCKSELR_MPUSRC_2
+#define RCC_MPUSOURCE_MPUDIV RCC_MPCKSELR_MPUSRC_3
+
+#define IS_RCC_MPUSOURCE(SOURCE) (((SOURCE) == RCC_MPUSOURCE_HSI) || \
+ ((SOURCE) == RCC_MPUSOURCE_HSE) || \
+ ((SOURCE) == RCC_MPUSOURCE_PLL1) || \
+ ((SOURCE) == RCC_MPUSOURCE_MPUDIV))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AXISS_Clock_Source RCC_AXISS_Clock_Source
+ * @{
+ */
+#define RCC_AXISSOURCE_HSI RCC_ASSCKSELR_AXISSRC_0
+#define RCC_AXISSOURCE_HSE RCC_ASSCKSELR_AXISSRC_1
+#define RCC_AXISSOURCE_PLL2 RCC_ASSCKSELR_AXISSRC_2
+#define RCC_AXISSOURCE_OFF RCC_ASSCKSELR_AXISSRC_3
+
+#define IS_RCC_AXISSOURCE(SOURCE) (((SOURCE) == RCC_AXISSOURCE_HSI) || \
+ ((SOURCE) == RCC_AXISSOURCE_HSE) || \
+ ((SOURCE) == RCC_AXISSOURCE_PLL2) || \
+ ((SOURCE) == RCC_AXISSOURCE_OFF))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCU_Clock_Source RCC_MCU_Clock_Source
+ * @{
+ */
+#define RCC_MCUSSOURCE_HSI RCC_MSSCKSELR_MCUSSRC_0
+#define RCC_MCUSSOURCE_HSE RCC_MSSCKSELR_MCUSSRC_1
+#define RCC_MCUSSOURCE_CSI RCC_MSSCKSELR_MCUSSRC_2
+#define RCC_MCUSSOURCE_PLL3 RCC_MSSCKSELR_MCUSSRC_3
+
+#define IS_RCC_MCUSSOURCE(SOURCE) (((SOURCE) == RCC_MCUSSOURCE_HSI) || \
+ ((SOURCE) == RCC_MCUSSOURCE_HSE) || \
+ ((SOURCE) == RCC_MCUSSOURCE_CSI) || \
+ ((SOURCE) == RCC_MCUSSOURCE_PLL3))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_RTC_Division_Factor RCC_RTC_Division_Factor
+ * @{
+ */
+#define RCC_RTCDIV(x) RCC_RTCDIVR_RTCDIV_(y)
+
+#define IS_RCC_RTC_HSEDIV(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MPU_Clock_Divider RCC_MPU_Clock_Divider
+ * @{
+ */
+#define RCC_MPU_DIV_OFF RCC_MPCKDIVR_MPUDIV_0
+#define RCC_MPU_DIV2 RCC_MPCKDIVR_MPUDIV_1
+#define RCC_MPU_DIV4 RCC_MPCKDIVR_MPUDIV_2
+#define RCC_MPU_DIV8 RCC_MPCKDIVR_MPUDIV_3
+#define RCC_MPU_DIV16 RCC_MPCKDIVR_MPUDIV_4
+
+#define IS_RCC_MPUDIV(DIVIDER) ( ((DIVIDER) == RCC_MPU_DIV2) || \
+ ((DIVIDER) == RCC_MPU_DIV4) || \
+ ((DIVIDER) == RCC_MPU_DIV8) || \
+ ((DIVIDER) == RCC_MPU_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AXI_Clock_Divider RCC_AXI_Clock_Divider
+ * @{
+ */
+#define RCC_AXI_DIV1 RCC_AXIDIVR_AXIDIV_0
+#define RCC_AXI_DIV2 RCC_AXIDIVR_AXIDIV_1
+#define RCC_AXI_DIV3 RCC_AXIDIVR_AXIDIV_2
+#define RCC_AXI_DIV4 RCC_AXIDIVR_AXIDIV_3
+
+#define IS_RCC_AXIDIV(DIVIDER) (((DIVIDER) == RCC_AXI_DIV1) || \
+ ((DIVIDER) == RCC_AXI_DIV2) || \
+ ((DIVIDER) == RCC_AXI_DIV3) || \
+ ((DIVIDER) == RCC_AXI_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB4_Clock_Divider RCC_APB4_Clock_Divider
+ * @{
+ */
+#define RCC_APB4_DIV1 RCC_APB4DIVR_APB4DIV_0
+#define RCC_APB4_DIV2 RCC_APB4DIVR_APB4DIV_1
+#define RCC_APB4_DIV4 RCC_APB4DIVR_APB4DIV_2
+#define RCC_APB4_DIV8 RCC_APB4DIVR_APB4DIV_3
+#define RCC_APB4_DIV16 RCC_APB4DIVR_APB4DIV_4
+
+#define IS_RCC_APB4DIV(DIVIDER) (((DIVIDER) == RCC_APB4_DIV1) || \
+ ((DIVIDER) == RCC_APB4_DIV2) || \
+ ((DIVIDER) == RCC_APB4_DIV4) || \
+ ((DIVIDER) == RCC_APB4_DIV8) || \
+ ((DIVIDER) == RCC_APB4_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB5_Clock_Divider RCC_APB5_Clock_Divider
+ * @{
+ */
+#define RCC_APB5_DIV1 RCC_APB5DIVR_APB5DIV_0
+#define RCC_APB5_DIV2 RCC_APB5DIVR_APB5DIV_1
+#define RCC_APB5_DIV4 RCC_APB5DIVR_APB5DIV_2
+#define RCC_APB5_DIV8 RCC_APB5DIVR_APB5DIV_3
+#define RCC_APB5_DIV16 RCC_APB5DIVR_APB5DIV_4
+
+#define IS_RCC_APB5DIV(DIVIDER) (((DIVIDER) == RCC_APB5_DIV1) || \
+ ((DIVIDER) == RCC_APB5_DIV2) || \
+ ((DIVIDER) == RCC_APB5_DIV4) || \
+ ((DIVIDER) == RCC_APB5_DIV8) || \
+ ((DIVIDER) == RCC_APB5_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MCU_Clock_Divider RCC_MCU_Clock_Divider
+ * @{
+ */
+#define RCC_MCU_DIV1 RCC_MCUDIVR_MCUDIV_0
+#define RCC_MCU_DIV2 RCC_MCUDIVR_MCUDIV_1
+#define RCC_MCU_DIV4 RCC_MCUDIVR_MCUDIV_2
+#define RCC_MCU_DIV8 RCC_MCUDIVR_MCUDIV_3
+#define RCC_MCU_DIV16 RCC_MCUDIVR_MCUDIV_4
+#define RCC_MCU_DIV32 RCC_MCUDIVR_MCUDIV_5
+#define RCC_MCU_DIV64 RCC_MCUDIVR_MCUDIV_6
+#define RCC_MCU_DIV128 RCC_MCUDIVR_MCUDIV_7
+#define RCC_MCU_DIV256 RCC_MCUDIVR_MCUDIV_8
+#define RCC_MCU_DIV512 RCC_MCUDIVR_MCUDIV_9
+
+#define IS_RCC_MCUDIV(DIVIDER) (((DIVIDER) == RCC_MCU_DIV1) || \
+ ((DIVIDER) == RCC_MCU_DIV2) || \
+ ((DIVIDER) == RCC_MCU_DIV4) || \
+ ((DIVIDER) == RCC_MCU_DIV8) || \
+ ((DIVIDER) == RCC_MCU_DIV16) || \
+ ((DIVIDER) == RCC_MCU_DIV32) || \
+ ((DIVIDER) == RCC_MCU_DIV64) || \
+ ((DIVIDER) == RCC_MCU_DIV128) || \
+ ((DIVIDER) == RCC_MCU_DIV256) || \
+ ((DIVIDER) == RCC_MCU_DIV512))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB1_Clock_Divider RCC_APB1_Clock_Divider
+ * @{
+ */
+#define RCC_APB1_DIV1 RCC_APB1DIVR_APB1DIV_0
+#define RCC_APB1_DIV2 RCC_APB1DIVR_APB1DIV_1
+#define RCC_APB1_DIV4 RCC_APB1DIVR_APB1DIV_2
+#define RCC_APB1_DIV8 RCC_APB1DIVR_APB1DIV_3
+#define RCC_APB1_DIV16 RCC_APB1DIVR_APB1DIV_4
+
+#define IS_RCC_APB1DIV(DIVIDER) (((DIVIDER) == RCC_APB1_DIV1) || \
+ ((DIVIDER) == RCC_APB1_DIV2) || \
+ ((DIVIDER) == RCC_APB1_DIV4) || \
+ ((DIVIDER) == RCC_APB1_DIV8) || \
+ ((DIVIDER) == RCC_APB1_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB2_Clock_Divider RCC_APB2_Clock_Divider
+ * @{
+ */
+#define RCC_APB2_DIV1 RCC_APB2DIVR_APB2DIV_0
+#define RCC_APB2_DIV2 RCC_APB2DIVR_APB2DIV_1
+#define RCC_APB2_DIV4 RCC_APB2DIVR_APB2DIV_2
+#define RCC_APB2_DIV8 RCC_APB2DIVR_APB2DIV_3
+#define RCC_APB2_DIV16 RCC_APB2DIVR_APB2DIV_4
+
+#define IS_RCC_APB2DIV(DIVIDER) (((DIVIDER) == RCC_APB2_DIV1) || \
+ ((DIVIDER) == RCC_APB2_DIV2) || \
+ ((DIVIDER) == RCC_APB2_DIV4) || \
+ ((DIVIDER) == RCC_APB2_DIV8) || \
+ ((DIVIDER) == RCC_APB2_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_APB3_Clock_Divider RCC_APB3_Clock_Divider
+ * @{
+ */
+#define RCC_APB3_DIV1 RCC_APB3DIVR_APB3DIV_0
+#define RCC_APB3_DIV2 RCC_APB3DIVR_APB3DIV_1
+#define RCC_APB3_DIV4 RCC_APB3DIVR_APB3DIV_2
+#define RCC_APB3_DIV8 RCC_APB3DIVR_APB3DIV_3
+#define RCC_APB3_DIV16 RCC_APB3DIVR_APB3DIV_4
+
+#define IS_RCC_APB3DIV(DIVIDER) (((DIVIDER) == RCC_APB3_DIV1) || \
+ ((DIVIDER) == RCC_APB3_DIV2) || \
+ ((DIVIDER) == RCC_APB3_DIV4) || \
+ ((DIVIDER) == RCC_APB3_DIV8) || \
+ ((DIVIDER) == RCC_APB3_DIV16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Config RCC_PLL_Config
+ * @{
+ */
+#define RCC_PLL_NONE ((uint32_t)0x00000000)
+#define RCC_PLL_OFF ((uint32_t)0x00000001)
+#define RCC_PLL_ON ((uint32_t)0x00000002)
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \
+ ((PLL) == RCC_PLL_ON))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Mode RCC_PLL_Mode
+ * @{
+ */
+#define RCC_PLL_INTEGER ((uint32_t)0x00000000)
+#define RCC_PLL_FRACTIONAL ((uint32_t)0x00000001)
+#define RCC_PLL_SPREAD_SPECTRUM ((uint32_t)0x00000002)
+
+#define IS_RCC_PLLMODE(MODE) (((MODE) == RCC_PLL_FRACTIONAL) || \
+ ((MODE) == RCC_PLL_INTEGER) || \
+ ((MODE) == RCC_PLL_SPREAD_SPECTRUM))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_SSCG_MODE RCC_SSCG_MODE
+ * @{
+ */
+#define RCC_SSCG_CENTER_SPREAD ((uint32_t)0x00000000)
+#define RCC_SSCG_DOWN_SPREAD ((uint32_t)RCC_PLL1CSGR_SSCG_MODE)
+
+#define IS_RCC_SSCG_MODE(MODE) (((MODE) == RCC_SSCG_CENTER_SPREAD) || \
+ ((MODE) == RCC_SSCG_DOWN_SPREAD))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_MOD_PER RCC_MOD_PER
+ * @{
+ */
+#define RCC_MOD_PER_MIN ((uint32_t)0x00000001)
+#define RCC_MOD_PER_MAX ((uint32_t)RCC_PLL1CSGR_MOD_PER) /* 8191 */
+
+#define IS_RCC_MOD_PER(ADJ) ((RCC_MOD_PER_MIN <= (ADJ)) && \
+ ((ADJ) <= RCC_MOD_PER_MAX))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_INC_STEP RCC_INC_STEP
+ * @{
+ */
+#define RCC_INC_STEP_MIN ((uint32_t)0x00000001)
+#define RCC_INC_STEP_MAX ((uint32_t)0x7FFF) /* 32767 */
+
+#define IS_RCC_INC_STEP(ADJ) ((RCC_INC_STEP_MIN <= (ADJ)) && \
+ ((ADJ) <= RCC_INC_STEP_MAX))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_RPDFN_DIS RCC_RPDFN_DIS
+ * @{
+ */
+#define RCC_RPDFN_DIS_ENABLED ((uint32_t)0x00000000)
+#define RCC_RPDFN_DIS_DISABLED ((uint32_t)RCC_PLL1CSGR_RPDFN_DIS)
+
+#define IS_RCC_RPDFN_DIS(STATE) (((STATE) == RCC_RPDFN_DIS_DISABLED) || \
+ ((STATE) == RCC_RPDFN_DIS_ENABLED))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_TPDFN_DIS RCC_TPDFN_DIS
+ * @{
+ */
+#define RCC_TPDFN_DIS_ENABLED ((uint32_t)0x00000000)
+#define RCC_TPDFN_DIS_DISABLED ((uint32_t)RCC_PLL1CSGR_TPDFN_DIS)
+
+#define IS_RCC_TPDFN_DIS(STATE) (((STATE) == RCC_TPDFN_DIS_DISABLED) || \
+ ((STATE) == RCC_TPDFN_DIS_ENABLED))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_PLL12_Clock_Source RCC_PLL12_Clock_Source
+ * @{
+ */
+#define RCC_PLL12SOURCE_HSI RCC_RCK12SELR_PLL12SRC_0
+#define RCC_PLL12SOURCE_HSE RCC_RCK12SELR_PLL12SRC_1
+#define RCC_PLL12SOURCE_OFF RCC_RCK12SELR_PLL12SRC_2
+
+#define IS_RCC_PLL12SOURCE(SOURCE) (((SOURCE) == RCC_PLL12SOURCE_HSI) || \
+ ((SOURCE) == RCC_PLL12SOURCE_HSE) || \
+ ((SOURCE) == RCC_PLL12SOURCE_OFF))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_PLL3_Clock_Source RCC_PLL3_Clock_Source
+ * @{
+ */
+#define RCC_PLL3SOURCE_HSI RCC_RCK3SELR_PLL3SRC_0
+#define RCC_PLL3SOURCE_HSE RCC_RCK3SELR_PLL3SRC_1
+#define RCC_PLL3SOURCE_CSI RCC_RCK3SELR_PLL3SRC_2
+#define RCC_PLL3SOURCE_OFF RCC_RCK3SELR_PLL3SRC_3
+
+
+#define IS_RCC_PLL3SOURCE(SOURCE) (((SOURCE) == RCC_PLL3SOURCE_HSI) || \
+ ((SOURCE) == RCC_PLL3SOURCE_HSE) || \
+ ((SOURCE) == RCC_PLL3SOURCE_CSI) || \
+ ((SOURCE) == RCC_PLL3SOURCE_OFF))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_PLL4_Clock_Source RCC_PLL4_Clock_Source
+ * @{
+ */
+#define RCC_PLL4SOURCE_HSI RCC_RCK4SELR_PLL4SRC_0
+#define RCC_PLL4SOURCE_HSE RCC_RCK4SELR_PLL4SRC_1
+#define RCC_PLL4SOURCE_CSI RCC_RCK4SELR_PLL4SRC_2
+#define RCC_PLL4SOURCE_I2S_CKIN RCC_RCK4SELR_PLL4SRC_3
+
+
+#define IS_RCC_PLL4SOURCE(SOURCE) (((SOURCE) == RCC_PLL4SOURCE_HSI) || \
+ ((SOURCE) == RCC_PLL4SOURCE_HSE) || \
+ ((SOURCE) == RCC_PLL4SOURCE_CSI) || \
+ ((SOURCE) == RCC_PLL4SOURCE_I2S_CKIN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL1_MUL_DIV_Factors RCC_PLL1_MUL_DIV_Factors
+ * @{
+ */
+#define IS_RCC_PLLM1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64))
+/* @note DIVN limits are different depending if using integer or fractional mode */
+#define IS_RCC_PLLN1_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100))
+#define IS_RCC_PLLN1_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
+#define IS_RCC_PLLP1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLQ1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLR1_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL2_MUL_DIV_Factors RCC_PLL2_MUL_DIV_Factors
+ * @{
+ */
+#define IS_RCC_PLLM2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64))
+/* @note DIVN limits are different depending if using integer or fractional mode */
+#define IS_RCC_PLLN2_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 100))
+#define IS_RCC_PLLN2_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
+#define IS_RCC_PLLP2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLQ2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLR2_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL3_MUL_DIV_Factors RCC_PLL3_MUL_DIV_Factors
+ * @{
+ */
+#define IS_RCC_PLLM3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64))
+/* @note DIVN limits are different depending if using integer or fractional mode */
+#define IS_RCC_PLLN3_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 200))
+#define IS_RCC_PLLN3_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
+#define IS_RCC_PLLP3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLQ3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLR3_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL4_MUL_DIV_Factors RCC_PLL4_MUL_DIV_Factors
+ * @{
+ */
+#define IS_RCC_PLLM4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 64))
+/* @note DIVN limits are different depending if using integer or fractional mode */
+#define IS_RCC_PLLN4_INT_VALUE(VALUE) ((25 <= (VALUE)) && ((VALUE) <= 200))
+#define IS_RCC_PLLN4_FRAC_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 512))
+#define IS_RCC_PLLP4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLQ4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+#define IS_RCC_PLLR4_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 128))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL1_Clock_Output RCC_PLL1_Clock_Output
+ * @{
+ */
+#define RCC_PLL1_DIVP RCC_PLL1CR_DIVPEN
+#define RCC_PLL1_DIVQ RCC_PLL1CR_DIVQEN
+#define RCC_PLL1_DIVR RCC_PLL1CR_DIVREN
+
+#define IS_RCC_PLL1CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \
+ ((VALUE) == RCC_PLL1_DIVQ) || \
+ ((VALUE) == RCC_PLL1_DIVR))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_PLL2_Clock_Output RCC_PLL2_Clock_Output
+ * @{
+ */
+#define RCC_PLL2_DIVP RCC_PLL2CR_DIVPEN
+#define RCC_PLL2_DIVQ RCC_PLL2CR_DIVQEN
+#define RCC_PLL2_DIVR RCC_PLL2CR_DIVREN
+
+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2CR_DIVPEN) || \
+ ((VALUE) == RCC_PLL2CR_DIVQEN) || \
+ ((VALUE) == RCC_PLL2CR_DIVREN))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL3_Clock_Output RCC_PLL3_Clock_Output
+ * @{
+ */
+
+#define RCC_PLL3_DIVP RCC_PLL3CR_DIVPEN
+#define RCC_PLL3_DIVQ RCC_PLL3CR_DIVQEN
+#define RCC_PLL3_DIVR RCC_PLL3CR_DIVREN
+
+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \
+ ((VALUE) == RCC_PLL3_DIVQ) || \
+ ((VALUE) == RCC_PLL3_DIVR))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL4_Clock_Output RCC_PLL4_Clock_Output
+ * @{
+ */
+#define RCC_PLL4_DIVP RCC_PLL4CR_DIVPEN
+#define RCC_PLL4_DIVQ RCC_PLL4CR_DIVQEN
+#define RCC_PLL4_DIVR RCC_PLL4CR_DIVREN
+
+#define IS_RCC_PLL4CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL4_DIVP) || \
+ ((VALUE) == RCC_PLL4_DIVQ) || \
+ ((VALUE) == RCC_PLL4_DIVR))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL3_IF_Range RCC_PLL3_IF_Range
+ * @{
+ */
+#define RCC_PLL3IFRANGE_0 RCC_PLL3CFGR1_IFRGE_0
+#define RCC_PLL3IFRANGE_1 RCC_PLL3CFGR1_IFRGE_1
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL4_IF_Range RCC_PLL4_IF_Range
+ * @{
+ */
+#define RCC_PLL4IFRANGE_0 RCC_PLL4CFGR1_IFRGE_0
+#define RCC_PLL4IFRANGE_1 RCC_PLL4CFGR1_IFRGE_1
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_RTC_Clock_Source RCC_RTC_Clock_Source
+ * @{
+ */
+#define RCC_RTCCLKSOURCE_OFF RCC_BDCR_RTCSRC_0 /* No clock (default after backup domain reset)*/
+#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSRC_1
+#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSRC_2
+#define RCC_RTCCLKSOURCE_HSE_DIV RCC_BDCR_RTCSRC_3 /* HSE clock divided by RTCDIV value is used as RTC clock*/
+
+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_OFF) || ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag RCC_Flag
+ * @{
+ */
+/* Flags in the OCRDYR register */
+#define RCC_FLAG_HSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == RCC_OCRDYR_HSIRDY )
+#define RCC_FLAG_HSIDIVRDY ( (RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == RCC_OCRDYR_HSIDIVRDY )
+#define RCC_FLAG_CSIRDY ( (RCC->OCRDYR & RCC_OCRDYR_CSIRDY) == RCC_OCRDYR_CSIRDY )
+#define RCC_FLAG_HSERDY ( (RCC->OCRDYR & RCC_OCRDYR_HSERDY) == RCC_OCRDYR_HSERDY )
+#define RCC_FLAG_AXICKRDY ( (RCC->OCRDYR & RCC_OCRDYR_AXICKRDY) == RCC_OCRDYR_AXICKRDY )
+#define RCC_FLAG_CKREST ( (RCC->OCRDYR & RCC_OCRDYR_CKREST) == RCC_OCRDYR_CKREST )
+
+/* Flags in the MPCKSELR register */
+#define RCC_FLAG_MPUSRCRDY ( (RCC->MPCKSELR & RCC_MPCKSELR_MPUSRCRDY) == RCC_MPCKSELR_MPUSRCRDY )
+
+/* Flags in the ASSCKSELR register */
+#define RCC_FLAG_AXISSRCRDY ( (RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRCRDY) == RCC_ASSCKSELR_AXISSRCRDY )
+
+/* Flags in the MSSCKSELR register */
+#define RCC_FLAG_MCUSSRCRDY ( (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRCRDY) == RCC_MSSCKSELR_MCUSSRCRDY )
+
+/* Flags in the RCK12SELR register */
+#define RCC_FLAG_PLL12SRCRDY ( (RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRCRDY) == RCC_RCK12SELR_PLL12SRCRDY )
+
+/* Flags in the RCK3SELR */
+#define RCC_FLAG_PLL3SRCRDY ( (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRCRDY) == RCC_RCK3SELR_PLL3SRCRDY )
+
+/* Flags in the RCK4SELR register */
+#define RCC_FLAG_PLL4SRCRDY ( (RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRCRDY) == RCC_RCK4SELR_PLL4SRCRDY )
+
+/* Flags in the TIMG1PRER register */
+#define RCC_FLAG_TIMG1PRERDY ( (RCC->TIMG1PRER & RCC_TIMG1PRER_TIMG1PRERDY) == RCC_TIMG1PRER_TIMG1PRERDY )
+
+/* Flags in the TIMG2PRER register */
+#define RCC_FLAG_TIMG2PRERDY ( (RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRERDY) == RCC_TIMG2PRER_TIMG2PRERDY )
+
+/* Flags in the MPCKDIVR register */
+#define RCC_FLAG_MPUDIVRDY ( (RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIVRDY) == RCC_MPCKDIVR_MPUDIVRDY )
+
+/* Flags in the AXIDIVR register */
+#define RCC_FLAG_AXIDIVRDY ( (RCC->AXIDIVR & RCC_AXIDIVR_AXIDIVRDY) == RCC_AXIDIVR_AXIDIVRDY )
+
+/* Flags in the APB4DIVR register */
+#define RCC_FLAG_APB4DIVRDY ( (RCC->APB4DIVR & RCC_APB4DIVR_APB4DIVRDY) == RCC_APB4DIVR_APB4DIVRDY )
+
+/* Flags in the APB5DIVR register */
+#define RCC_FLAG_APB5DIVRDY ( (RCC->APB5DIVR & RCC_APB5DIVR_APB5DIVRDY) == RCC_APB5DIVR_APB5DIVRDY )
+
+/* Flags in the MCUDIVR register */
+#define RCC_FLAG_MCUDIVRDY ( (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIVRDY) == RCC_MCUDIVR_MCUDIVRDY )
+
+/* Flags in the APB1DIVR register */
+#define RCC_FLAG_APB1DIVRDY ((RCC->APB1DIVR & RCC_APB1DIVR_APB1DIVRDY) == RCC_APB1DIVR_APB1DIVRDY )
+
+/* Flags in the APB2DIVR register */
+#define RCC_FLAG_APB2DIVRDY ((RCC->APB2DIVR & RCC_APB2DIVR_APB2DIVRDY) == RCC_APB2DIVR_APB2DIVRDY )
+
+/* Flags in the APB3DIVR register */
+#define RCC_FLAG_APB3DIVRDY ((RCC->APB3DIVR & RCC_APB3DIVR_APB3DIVRDY) == RCC_APB3DIVR_APB3DIVRDY )
+
+/* Flags in the PLL1CR register */
+#define RCC_FLAG_PLL1RDY ((RCC->PLL1CR & RCC_PLL1CR_PLL1RDY) == RCC_PLL1CR_PLL1RDY )
+
+/* Flags in the PLL2CR register */
+#define RCC_FLAG_PLL2RDY ((RCC->PLL2CR & RCC_PLL2CR_PLL2RDY) == RCC_PLL2CR_PLL2RDY )
+
+/* Flags in the PLL3CR register */
+#define RCC_FLAG_PLL3RDY ((RCC->PLL3CR & RCC_PLL3CR_PLL3RDY) == RCC_PLL3CR_PLL3RDY )
+
+/* Flags in the PLL4CR register */
+#define RCC_FLAG_PLL4RDY ((RCC->PLL4CR & RCC_PLL4CR_PLL4RDY) == RCC_PLL4CR_PLL4RDY )
+
+/* Flags in the DDRCKSELR register */
+#define RCC_FLAG_DDRPHYCSRCRDY ((RCC->DDRCKSELR & RCC_DDRCKSELR_DDRPHYCSRCRDY) == RCC_DDRCKSELR_DDRPHYCSRCRDY )
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY ((RCC->BDCR & RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY )
+
+/* Flags in the RDLSICR register */
+#define RCC_FLAG_LSIRDY ((RCC->RDLSICR & RCC_RDLSICR_LSIRDY) == RCC_RDLSICR_LSIRDY )
+
+#if defined(CORE_CA7)
+/* Flags in the RCC_MP_RSTSCLRR */
+#define RCC_MASK_ALL_RESET_FLAGS (0x00001BDFU)
+#define RCC_FLAG_PORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PORRSTF) == RCC_MP_RSTSCLRR_PORRSTF)
+#define RCC_FLAG_BORRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_BORRSTF) == RCC_MP_RSTSCLRR_BORRSTF)
+#define RCC_FLAG_PADRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_PADRSTF) == RCC_MP_RSTSCLRR_PADRSTF)
+#define RCC_FLAG_HCSSRST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_HCSSRSTF) == RCC_MP_RSTSCLRR_HCSSRSTF)
+#define RCC_FLAG_VCORERST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_VCORERSTF) == RCC_MP_RSTSCLRR_VCORERSTF)
+#define RCC_FLAG_MPSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPSYSRSTF) == RCC_MP_RSTSCLRR_MPSYSRSTF)
+#define RCC_FLAG_MCSYSRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MCSYSRSTF) == RCC_MP_RSTSCLRR_MCSYSRSTF)
+#define RCC_FLAG_IWDG1RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG1RSTF) == RCC_MP_RSTSCLRR_IWDG1RSTF)
+#define RCC_FLAG_IWDG2RST ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_IWDG2RSTF) == RCC_MP_RSTSCLRR_IWDG2RSTF)
+#define RCC_FLAG_STDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_STDBYRSTF) == RCC_MP_RSTSCLRR_STDBYRSTF)
+#define RCC_FLAG_CSTDBYRSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_CSTDBYRSTF) == RCC_MP_RSTSCLRR_CSTDBYRSTF)
+#define RCC_FLAG_MPUP0RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP0RSTF) == RCC_MP_RSTSCLRR_MPUP0RSTF)
+#define RCC_FLAG_MPUP1RSTF ((RCC->MP_RSTSCLRR & RCC_MP_RSTSCLRR_MPUP1RSTF) == RCC_MP_RSTSCLRR_MPUP1RSTF)
+#elif defined(CORE_CM4)
+/* Flags in the RCC_MC_RSTSCLRR */
+#define RCC_MASK_ALL_RESET_FLAGS (0x000007FFU)
+#define RCC_FLAG_PORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PORRSTF) == RCC_MC_RSTSCLRR_PORRSTF)
+#define RCC_FLAG_BORRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_BORRSTF) == RCC_MC_RSTSCLRR_BORRSTF)
+#define RCC_FLAG_PADRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_PADRSTF) == RCC_MC_RSTSCLRR_PADRSTF)
+#define RCC_FLAG_HCSSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_HCSSRSTF) == RCC_MC_RSTSCLRR_HCSSRSTF)
+#define RCC_FLAG_VCORERST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_VCORERSTF) == RCC_MC_RSTSCLRR_VCORERSTF)
+#define RCC_FLAG_MCURST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCURSTF) == RCC_MC_RSTSCLRR_MCURSTF)
+#define RCC_FLAG_MPSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MPSYSRSTF) == RCC_MC_RSTSCLRR_MPSYSRSTF)
+#define RCC_FLAG_MCSYSRST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_MCSYSRSTF) == RCC_MC_RSTSCLRR_MCSYSRSTF)
+#define RCC_FLAG_IWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG1RSTF) == RCC_MC_RSTSCLRR_IWDG1RSTF)
+#define RCC_FLAG_IWDG2RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_IWDG2RSTF) == RCC_MC_RSTSCLRR_IWDG2RSTF)
+#define RCC_FLAG_WWDG1RST ((RCC->MC_RSTSCLRR & RCC_MC_RSTSCLRR_WWDG1RSTF) == RCC_MC_RSTSCLRR_WWDG1RSTF)
+#endif
+
+/** @brief Clear all the reset flags
+ * @note Writing a '1' clears the corresponding bit to '0'
+ */
+#if defined(CORE_CA7)
+#define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MP_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS)
+#elif defined(CORE_CM4)
+#define __HAL_RCC_CLEAR_RESET_FLAGS() WRITE_REG(RCC->MC_RSTSCLRR, RCC_MASK_ALL_RESET_FLAGS)
+#endif /* CORE_CA7 */
+
+#if defined(CORE_CA7)
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_PORRST
+ * @arg RCC_FLAG_BORRST
+ * @arg RCC_FLAG_PADRST
+ * @arg RCC_FLAG_HCSSRST
+ * @arg RCC_FLAG_VCORERST
+ * @arg RCC_FLAG_MPSYSRSTF
+ * @arg RCC_FLAG_MCSYSRSTF
+ * @arg RCC_FLAG_IWDG1RST
+ * @arg RCC_FLAG_IWDG2RST
+ * @arg RCC_FLAG_STDBYRSTF
+ * @arg RCC_FLAG_CSTDBYRSTF
+ * @arg RCC_FLAG_MPUP0RSTF
+ * @arg RCC_FLAG_MPUP1RSTF
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+#elif defined(CORE_CM4)
+/** @brief Check RCC flag is set or not.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_FLAG_PORRST
+ * @arg RCC_FLAG_BORRST
+ * @arg RCC_FLAG_PADRST
+ * @arg RCC_FLAG_HCSSRST
+ * @arg RCC_FLAG_VCORERST
+ * @arg RCC_FLAG_MCURST
+ * @arg RCC_FLAG_MPSYSRST
+ * @arg RCC_FLAG_MCSYSRST
+ * @arg RCC_FLAG_IWDG1RST
+ * @arg RCC_FLAG_IWDG2RST
+ * @arg RCC_FLAG_WWDG1RST
+ * @retval The state of __FLAG__ (TRUE or FALSE).
+ */
+#endif /* CORE_CA7 */
+#define __HAL_RCC_GET_FLAG(__FLAG__) ( __FLAG__ ? 1:0 )
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Calibration RCC_Calibration limits
+ * @{
+ */
+/** RCC_Calibration limits*/
+#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LSEDrive_Config RCC_LSEDrive_Config
+ * @{
+ */
+#define RCC_LSEDRIVE_LOW RCC_BDCR_LSEDRV_0 /*!< LSE low drive capability */
+#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< LSE medium low drive capability */
+#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_2 /*!< LSE medium high drive capability */
+#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV_3 /*!< LSE high drive capability */
+
+#define IS_RCC_LSEDRIVE(VALUE) (((VALUE) == RCC_LSEDRIVE_LOW) || ((VALUE) == RCC_LSEDRIVE_MEDIUMLOW) || \
+ ((VALUE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((VALUE) == RCC_LSEDRIVE_HIGH))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_Interrupt RCC_Interrupt
+ * @{
+ */
+#ifdef CORE_CM4
+#define RCC_IT_LSIRDY RCC_MC_CIFR_LSIRDYF
+#define RCC_IT_LSERDY RCC_MC_CIFR_LSERDYF
+#define RCC_IT_HSIRDY RCC_MC_CIFR_HSIRDYF
+#define RCC_IT_HSERDY RCC_MC_CIFR_HSERDYF
+#define RCC_IT_CSIRDY RCC_MC_CIFR_CSIRDYF
+#define RCC_IT_PLLRDY RCC_MC_CIFR_PLL1DYF
+#define RCC_IT_PLL2RDY RCC_MC_CIFR_PLL2DYF
+#define RCC_IT_PLL3RDY RCC_MC_CIFR_PLL3DYF
+#define RCC_IT_PLL4RDY RCC_MC_CIFR_PLL4DYF
+#define RCC_IT_LSECSS RCC_MC_CIFR_LSECSSF
+#define RCC_IT_WKUP RCC_MC_CIFR_WKUPF
+#endif /* CORE_CM4*/
+
+#ifdef CORE_CA7
+#define RCC_IT_LSIRDY RCC_MP_CIFR_LSIRDYF
+#define RCC_IT_LSERDY RCC_MP_CIFR_LSERDYF
+#define RCC_IT_HSIRDY RCC_MP_CIFR_HSIRDYF
+#define RCC_IT_HSERDY RCC_MP_CIFR_HSERDYF
+#define RCC_IT_CSIRDY RCC_MP_CIFR_CSIRDYF
+#define RCC_IT_PLLRDY RCC_MP_CIFR_PLL1DYF
+#define RCC_IT_PLL2RDY RCC_MP_CIFR_PLL2DYF
+#define RCC_IT_PLL3RDY RCC_MP_CIFR_PLL3DYF
+#define RCC_IT_PLL4RDY RCC_MP_CIFR_PLL4DYF
+#define RCC_IT_LSECSS RCC_MP_CIFR_LSECSSF
+#define RCC_IT_WKUP RCC_MP_CIFR_WKUPF
+#endif /* CORE_CA7 */
+
+#define RCC_IT_ALL (RCC_IT_LSIRDY | RCC_IT_LSERDY | RCC_IT_HSIRDY | \
+ RCC_IT_HSERDY | RCC_IT_CSIRDY | RCC_IT_PLLRDY | \
+ RCC_IT_PLL2RDY | RCC_IT_PLL3RDY | RCC_IT_PLL4RDY | \
+ RCC_IT_LSECSS | RCC_IT_WKUP)
+
+#define IS_RCC_IT(VALUE) (((VALUE) == RCC_IT_LSIRDY) || ((VALUE) == RCC_IT_LSERDY) || \
+ ((VALUE) == RCC_IT_HSIRDY) || ((VALUE) == RCC_IT_HSERDY) || \
+ ((VALUE) == RCC_IT_CSIRDY) || ((VALUE) == RCC_IT_PLLRDY) || \
+ ((VALUE) == RCC_IT_PLL2RDY) || ((VALUE) == RCC_IT_PLL3RDY) || \
+ ((VALUE) == RCC_IT_PLL4RDY) || ((VALUE) == RCC_IT_LSECSS) || \
+ ((VALUE) == RCC_IT_WKUP))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Macros RCC_Exported_Macros
+ * @{
+ */
+/** @brief Force or release the APB1 peripheral reset */
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTSETR = 0xADEFDBFFU)
+#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM2RST)
+#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM3RST)
+#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM4RST)
+#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM5RST)
+#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM6RST)
+#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM7RST)
+#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM12RST)
+#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM13RST)
+#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_TIM14RST)
+#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_LPTIM1RST)
+#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI2RST)
+#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPI3RST)
+#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART2RST)
+#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_USART3RST)
+#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART4RST)
+#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART5RST)
+#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART7RST)
+#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_UART8RST)
+#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C1RST)
+#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C2RST)
+#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C3RST)
+#define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_I2C5RST)
+#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_SPDIFRST)
+#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_CECRST)
+#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_DAC12RST)
+#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1RSTSETR = RCC_APB1RSTSETR_MDIOSRST)
+
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTCLRR = 0xADEFDBFFU)
+#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM2RST)
+#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM3RST)
+#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM4RST)
+#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM5RST)
+#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM6RST)
+#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM7RST)
+#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM12RST)
+#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM13RST)
+#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_TIM14RST)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_LPTIM1RST)
+#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI2RST)
+#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPI3RST)
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART2RST)
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_USART3RST)
+#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART4RST)
+#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART5RST)
+#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART7RST)
+#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_UART8RST)
+#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C1RST)
+#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C2RST)
+#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C3RST)
+#define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_I2C5RST)
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_SPDIFRST)
+#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_CECRST)
+#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_DAC12RST)
+#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1RSTCLRR = RCC_APB1RSTCLRR_MDIOSRST)
+
+/** @brief Force or release the APB2 peripheral reset. */
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTSETR = 0x117271FU)
+#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM1RST)
+#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM8RST)
+#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM15RST)
+#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM16RST)
+#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_TIM17RST)
+#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI1RST)
+#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI4RST)
+#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SPI5RST)
+#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_USART6RST)
+#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI1RST)
+#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI2RST)
+#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_SAI3RST)
+#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_DFSDMRST)
+#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB2RSTSETR = RCC_APB2RSTSETR_FDCANRST)
+
+#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTCLRR = 0x117271FU)
+#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM1RST)
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM8RST)
+#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM15RST)
+#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM16RST)
+#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_TIM17RST)
+#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI1RST)
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI4RST)
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SPI5RST)
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_USART6RST)
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI1RST)
+#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI2RST)
+#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_SAI3RST)
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_DFSDMRST)
+#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB2RSTCLRR = RCC_APB2RSTCLRR_FDCANRST)
+
+/** @brief Force or release the APB3 peripheral reset. */
+#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTSETR = 0x0003290FU)
+#define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM3RST)
+#define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM4RST)
+#define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_LPTIM5RST)
+#define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SAI4RST)
+#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_SYSCFGRST)
+#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_VREFRST)
+#define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_DTSRST)
+#define __HAL_RCC_PMBCTRL_FORCE_RESET() (RCC->APB3RSTSETR = RCC_APB3RSTSETR_PMBCTRLRST)
+
+#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTCLRR = 0x0003290FU)
+#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM2RST)
+#define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM3RST)
+#define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM4RST)
+#define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_LPTIM5RST)
+#define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SAI4RST)
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_SYSCFGRST)
+#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_VREFRST)
+#define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_DTSRST)
+#define __HAL_RCC_PMBCTRL_RELEASE_RESET() (RCC->APB3RSTCLRR = RCC_APB3RSTCLRR_PMBCTRLRST)
+
+/** @brief Force or release the AHB2 peripheral reset. */
+#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTSETR = 0x00010127U)
+#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA1RST)
+#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMA2RST)
+#define __HAL_RCC_DMAMUX_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_DMAMUXRST)
+#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_ADC12RST)
+#define __HAL_RCC_USBO_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_USBORST)
+#define __HAL_RCC_SDMMC3_FORCE_RESET() (RCC->AHB2RSTSETR = RCC_AHB2RSTSETR_SDMMC3RST)
+
+#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTCLRR = 0x00010127U)
+#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA1RST)
+#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMA2RST)
+#define __HAL_RCC_DMAMUX_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_DMAMUXRST)
+#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_ADC12RST)
+#define __HAL_RCC_USBO_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_USBORST)
+#define __HAL_RCC_SDMMC3_RELEASE_RESET() (RCC->AHB2RSTCLRR = RCC_AHB2RSTCLRR_SDMMC3RST)
+
+/** @brief Force or release the AHB3 peripheral reset. */
+#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_DCMIRST)
+#if defined(CRYP2)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018F1U)
+#define __HAL_RCC_CRYP2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRYP2RST)
+#else
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTSETR = 0x000018E1U)
+#endif /* CRYP2 */
+#define __HAL_RCC_HASH2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HASH2RST)
+#define __HAL_RCC_RNG2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_RNG2RST)
+#define __HAL_RCC_CRC2_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_CRC2RST)
+#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_HSEMRST)
+#define __HAL_RCC_IPCC_FORCE_RESET() (RCC->AHB3RSTSETR = RCC_AHB3RSTSETR_IPCCRST)
+
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_DCMIRST)
+#if defined(CRYP2)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018F1U)
+#define __HAL_RCC_CRYP2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRYP2RST)
+#else
+#define __HAL_RCC_AHB3_REALEASE_RESET() (RCC->AHB3RSTCLRR = 0x000018E1U)
+#endif /* CRYP2 */
+#define __HAL_RCC_HASH2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HASH2RST)
+#define __HAL_RCC_RNG2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_RNG2RST)
+#define __HAL_RCC_CRC2_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_CRC2RST)
+#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_HSEMRST)
+#define __HAL_RCC_IPCC_RELEASE_RESET() (RCC->AHB3RSTCLRR = RCC_AHB3RSTCLRR_IPCCRST)
+
+/** @brief Force or release the AHB4 peripheral reset. */
+#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTSETR = 0x000007FFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOARST)
+#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOBRST)
+#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOCRST)
+#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIODRST)
+#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOERST)
+#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOFRST)
+#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOGRST)
+#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOHRST)
+#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOJRST)
+#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTSETR = RCC_AHB4RSTSETR_GPIOKRST)
+
+#define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTCLRR = 0x000007FFU)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOARST)
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOBRST)
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOCRST)
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIODRST)
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOERST)
+#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOFRST)
+#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOGRST)
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOHRST)
+#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOIRST)
+#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOJRST)
+#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTCLRR = RCC_AHB4RSTCLRR_GPIOKRST)
+
+/** @brief Force or release the APB4 peripheral reset. */
+#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTSETR = 0x00010111U)
+#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_LTDCRST)
+#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DSIRST)
+#define __HAL_RCC_DDRPERFM_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_DDRPERFMRST)
+#define __HAL_RCC_USBPHY_FORCE_RESET() (RCC->APB4RSTSETR = RCC_APB4RSTSETR_USBPHYRST)
+
+#define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTCLRR = 0x00010111U)
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_LTDCRST)
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DSIRST)
+#define __HAL_RCC_DDRPERFM_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_DDRPERFMRST)
+#define __HAL_RCC_USBPHY_RELEASE_RESET() (RCC->APB4RSTCLRR = RCC_APB4RSTCLRR_USBPHYRST)
+
+/** @brief Force or release the APB5 peripheral reset. */
+/** @note Note that when the secure mode is enabled, only secure accesses can
+ * reset the peripherals connected to APB5.
+ */
+#define __HAL_RCC_APB5_FORCE_RESET() (RCC->APB5RSTSETR = 0x0010001DU)
+#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_SPI6RST)
+#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C4RST)
+#define __HAL_RCC_I2C6_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_I2C6RST)
+#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_USART1RST)
+#define __HAL_RCC_STGEN_FORCE_RESET() (RCC->APB5RSTSETR = RCC_APB5RSTSETR_STGENRST)
+
+#define __HAL_RCC_APB5_RELEASE_RESET() (RCC->APB5RSTCLRR = 0x0010001DU)
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_SPI6RST)
+#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C4RST)
+#define __HAL_RCC_I2C6_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_I2C6RST)
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_USART1RST)
+#define __HAL_RCC_STGEN_RELEASE_RESET() (RCC->APB5RSTCLRR = RCC_APB5RSTCLRR_STGENRST)
+
+/** @brief Force or release the AHB5 peripheral reset. */
+#define __HAL_RCC_GPIOZ_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_GPIOZRST)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_CRYP1RST)
+#define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010071U)
+#else
+#define __HAL_RCC_AHB5_FORCE_RESET() (RCC->AHB5RSTSETR = 0x00010061U)
+#endif /* CRYP1 */
+#define __HAL_RCC_HASH1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_HASH1RST)
+#define __HAL_RCC_RNG1_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_RNG1RST)
+#define __HAL_RCC_AXIMC_FORCE_RESET() (RCC->AHB5RSTSETR = RCC_AHB5RSTSETR_AXIMCRST)
+
+#define __HAL_RCC_GPIOZ_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_GPIOZRST)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_CRYP1RST)
+#define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010071U)
+#else
+#define __HAL_RCC_AHB5_RELEASE_RESET() (RCC->AHB5RSTCLRR = 0x00010061U)
+#endif /* CRYP1 */
+#define __HAL_RCC_HASH1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_HASH1RST)
+#define __HAL_RCC_RNG1_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_RNG1RST)
+#define __HAL_RCC_AXIMC_RELEASE_RESET() (RCC->AHB5RSTCLRR = RCC_AHB5RSTCLRR_AXIMCRST)
+
+/** @brief Force or release the AHB6 peripheral reset. */
+#define __HAL_RCC_AHB6_FORCE_RESET() (RCC->AHB6RSTSETR = 0x01135420U)
+#define __HAL_RCC_GPU_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_GPURST)
+#define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_ETHMACRST)
+#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_FMCRST)
+#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_QSPIRST)
+#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC1RST)
+#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_SDMMC2RST)
+#define __HAL_RCC_CRC1_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_CRC1RST)
+#define __HAL_RCC_USBH_FORCE_RESET() (RCC->AHB6RSTSETR = RCC_AHB6RSTSETR_USBHRST)
+
+/** @note __HAL_RCC_GPU_RELEASE_RESET does not exist as GPU reset process may
+ * take several clock cycles, for that purpose, the application can
+ * read-back the reset bit RCC_AHB6RSTSETR_GPURST in order to check if
+ * the reset process is on-going or completed after setting
+ * RCC_AHB6RSTSETR_GPURST
+ */
+#define __HAL_RCC_AHB6_RELEASE_RESET() (RCC->AHB6RSTCLRR = 0x01135400U)
+#define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_ETHMACRST)
+#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_FMCRST)
+#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_QSPIRST)
+#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC1RST)
+#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_SDMMC2RST)
+#define __HAL_RCC_CRC1_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_CRC1RST)
+#define __HAL_RCC_USBH_RELEASE_RESET() (RCC->AHB6RSTCLRR = RCC_AHB6RSTCLRR_USBHRST)
+
+/** @brief Force or release the TZAHB6 peripheral reset. */
+#define __HAL_RCC_TZAHB6_FORCE_RESET() (RCC->TZAHB6RSTSETR = 0x00000001U)
+#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->TZAHB6RSTSETR = RCC_TZAHB6RSTSETR_MDMARST)
+
+#define __HAL_RCC_TZAHB6_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = 0x00000001U)
+#define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->TZAHB6RSTCLRR = RCC_TZAHB6RSTCLRR_MDMARST)
+
+#ifdef CORE_CA7
+/** @brief Enable or disable the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN)
+#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN)
+#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN)
+#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN)
+#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN)
+#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN)
+#define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN)
+#define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN)
+#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN)
+#define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN)
+#define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN)
+#define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN)
+#define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MP_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN)
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN)
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN)
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN)
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN)
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN)
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN)
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN)
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN)
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN)
+#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN)
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN)
+#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN)
+#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MP_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN)
+
+/** @brief Enable or disable the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN)
+#define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN)
+#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN)
+#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN)
+#define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN)
+#define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN)
+#define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN)
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN)
+#define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN)
+#define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MP_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN)
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN)
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN)
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN)
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN)
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN)
+#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN)
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN)
+#define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MP_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN)
+
+/** @brief Enable or disable the APB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN)
+#define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN)
+#define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN)
+#define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN)
+#define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN)
+#define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN)
+#define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN)
+#define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MP_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN)
+
+#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN)
+#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN)
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN)
+#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN)
+#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN)
+#define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN)
+#define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MP_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN)
+
+/** @brief Enable or disable the APB4 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN)
+#define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN)
+#define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN)
+#define __HAL_RCC_IWDG2APB_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MP_APB4ENSETR_IWDG2APBEN)
+#define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN)
+#define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MP_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN)
+
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN)
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN)
+#define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN)
+#define __HAL_RCC_IWDG2APB_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MP_APB4ENCLRR_IWDG2APBEN)
+#define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN)
+#define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MP_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN)
+
+/** @brief Enable or disable the APB5 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN)
+#define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN)
+#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN)
+#define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN)
+#define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN)
+#define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN)
+#define __HAL_RCC_IWDG1APB_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MP_APB5ENSETR_IWDG1APBEN)
+#define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN)
+#define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MP_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN)
+
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN)
+#define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN)
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN)
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN)
+#define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN)
+#define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN)
+#define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN)
+#define __HAL_RCC_IWDG1APB_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MP_APB5ENCLRR_IWDG1APBEN)
+#define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN)
+#define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MP_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN)
+
+/** @brief Enable or disable the AHB5 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN)
+#endif
+#define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN)
+#define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN)
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MP_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN)
+
+#define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN)
+#endif
+#define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN)
+#define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN)
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MP_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN)
+
+/** @brief Enable or disable the AHB6 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN)
+#define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN)
+#define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN)
+#define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN)
+#define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN)
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN)
+#define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN)
+#define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN)
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN)
+#define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN)
+#define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN)
+#define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MP_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN)
+
+#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN)
+#define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN)
+#define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN)
+#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN)
+#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN)
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN)
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN)
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN)
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN)
+#define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN)
+#define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MP_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN)
+
+/** @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN)
+#define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN)
+#define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN)
+#define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN)
+#define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN)
+#define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MP_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN)
+
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN)
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN)
+#define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN)
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN)
+#define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN)
+#define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MP_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN)
+
+/** @brief Enable or disable the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN)
+#endif
+#define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN)
+#define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN)
+#define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN)
+#define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN)
+#define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MP_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN)
+
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN)
+#endif
+#define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN)
+#define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN)
+#define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN)
+#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN)
+#define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MP_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN)
+
+/** @brief Enable or disable the AHB4 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MP_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MP_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN)
+
+
+/** @brief Enable or disable the MLAHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MP_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN)
+
+#define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MP_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN)
+
+/** @brief MCU reset
+ * @note It generates a reset of the MCU core
+ * MCURST bit is set by software, cleared by hardware when the reset
+ * command is executed.
+ */
+#define __HAL_RCC_MCU_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MCURST)
+
+/** @brief System reset
+ * @note It generates a system reset
+ * MPSYSRST bit is set by software, cleared by hardware.
+ */
+#define __HAL_RCC_SYS_RESET() (RCC->MP_GRSTCSETR = RCC_MP_GRSTCSETR_MPSYSRST)
+
+
+
+
+/** @brief Enable or disable the APB1 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM1LPEN)
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3LPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3LPEN)
+#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIFLPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12LPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MP_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOSLPEN)
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM1LPEN)
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3LPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3LPEN)
+#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIFLPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12LPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MP_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOSLPEN)
+
+
+/** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17LPEN)
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART6LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2LPEN)
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3LPEN)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDMLPEN)
+#define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSDMLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MP_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCANLPEN)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17LPEN)
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART6LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2LPEN)
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3LPEN)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDMLPEN)
+#define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSDMLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MP_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCANLPEN)
+
+
+/** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM3LPEN)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM4LPEN)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM5LPEN)
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4LPEN)
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN)
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLPEN)
+#define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MP_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN)
+
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM4LPEN)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM5LPEN)
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4LPEN)
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLPEN)
+#define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MP_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN)
+
+/** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCLPEN)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILPEN)
+#define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPERFMLPEN)
+#define __HAL_RCC_IWDG2APB_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MP_APB4LPENSETR_IWDG2APBLPEN)
+#define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPHYLPEN)
+#define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROLPEN)
+#define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MP_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROSTPEN)
+
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCLPEN)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILPEN)
+#define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPERFMLPEN)
+#define __HAL_RCC_IWDG2APB_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MP_APB4LPENCLRR_IWDG2APBLPEN)
+#define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPHYLPEN)
+#define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROLPEN)
+#define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MP_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROSTPEN)
+
+/** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4LPEN)
+#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART1LPEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAPBLPEN)
+#define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1LPEN)
+#define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2LPEN)
+#define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCLPEN)
+#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECLPEN)
+#define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MP_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGENLPEN)
+
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4LPEN)
+#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART1LPEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAPBLPEN)
+#define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1LPEN)
+#define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2LPEN)
+#define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCLPEN)
+#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECLPEN)
+#define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MP_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGENLPEN)
+
+
+/** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZLPEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1LPEN)
+#endif
+#define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1LPEN)
+#define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1LPEN)
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSRAMLPEN)
+
+#define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZLPEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1LPEN)
+#endif
+#define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1LPEN)
+#define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1LPEN)
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN)
+
+
+/** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMALPEN)
+#define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULPEN)
+#define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCKLPEN)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTXLPEN)
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRXLPEN)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMACLPEN)
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLPEN)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPILPEN)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC1LPEN)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC2LPEN)
+#define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1LPEN)
+#define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MP_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHLPEN)
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMALPEN)
+#define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULPEN)
+#define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCKLPEN)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTXLPEN)
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRXLPEN)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMACLPEN)
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLPEN)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPILPEN)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC1LPEN)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC2LPEN)
+#define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1LPEN)
+#define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MP_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHLPEN)
+
+
+/** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1LPEN)
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2LPEN)
+#define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMUXLPEN)
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12LPEN)
+#define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOLPEN)
+#define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MP_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC3LPEN)
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1LPEN)
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2LPEN)
+#define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMUXLPEN)
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12LPEN)
+#define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOLPEN)
+#define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MP_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC3LPEN)
+
+/** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMILPEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2LPEN)
+#endif
+#define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2LPEN)
+#define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2LPEN)
+#define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2LPEN)
+#define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEMLPEN)
+#define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MP_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCLPEN)
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMILPEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2LPEN)
+#endif
+#define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2LPEN)
+#define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2LPEN)
+#define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2LPEN)
+#define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEMLPEN)
+#define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MP_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCLPEN)
+
+
+/** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MP_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOKLPEN)
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MP_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOKLPEN)
+
+/** @brief Enable or disable the AXI peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MP_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRAMLPEN)
+
+#define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MP_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRAMLPEN)
+
+
+/** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MP_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RETRAMLPEN)
+
+#define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MP_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RETRAMLPEN)
+
+
+
+
+
+#else /* CORE_CA7 */
+
+
+
+
+/** @brief Enable or disable the APB1 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_LPTIM1EN)
+#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPI3EN)
+#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART2EN)
+#define __HAL_RCC_USART3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_USART3EN)
+#define __HAL_RCC_UART4_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART4EN)
+#define __HAL_RCC_UART5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART5EN)
+#define __HAL_RCC_UART7_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART7EN)
+#define __HAL_RCC_UART8_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_UART8EN)
+#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C3EN)
+#define __HAL_RCC_I2C5_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_I2C5EN)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_SPDIFEN)
+#define __HAL_RCC_CEC_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_CECEN)
+#define __HAL_RCC_WWDG1_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_WWDG1EN)
+#define __HAL_RCC_DAC12_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_DAC12EN)
+#define __HAL_RCC_MDIOS_CLK_ENABLE() (RCC->MC_APB1ENSETR = RCC_MC_APB1ENSETR_MDIOSEN)
+
+#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM2EN)
+#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM3EN)
+#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM4EN)
+#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM5EN)
+#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM6EN)
+#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM7EN)
+#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM12EN)
+#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM13EN)
+#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_TIM14EN)
+#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_LPTIM1EN)
+#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI2EN)
+#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPI3EN)
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART2EN)
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_USART3EN)
+#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART4EN)
+#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART5EN)
+#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART7EN)
+#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_UART8EN)
+#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C1EN)
+#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C2EN)
+#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C3EN)
+#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_I2C5EN)
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_SPDIFEN)
+#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_CECEN)
+#define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_WWDG1EN)
+#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_DAC12EN)
+#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->MC_APB1ENCLRR = RCC_MC_APB1ENCLRR_MDIOSEN)
+
+/** @brief Enable or disable the APB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_TIM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM8EN)
+#define __HAL_RCC_TIM15_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_TIM17EN)
+#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI4EN)
+#define __HAL_RCC_SPI5_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SPI5EN)
+#define __HAL_RCC_USART6_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_USART6EN)
+#define __HAL_RCC_SAI1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI2EN)
+#define __HAL_RCC_SAI3_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_SAI3EN)
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_DFSDMEN)
+#define __HAL_RCC_ADFSDM1_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_ADFSDMEN)
+#define __HAL_RCC_FDCAN_CLK_ENABLE() (RCC->MC_APB2ENSETR = RCC_MC_APB2ENSETR_FDCANEN)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM1EN)
+#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM8EN)
+#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM15EN)
+#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM16EN)
+#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_TIM17EN)
+#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI1EN)
+#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI4EN)
+#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SPI5EN)
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_USART6EN)
+#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI1EN)
+#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI2EN)
+#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_SAI3EN)
+#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_DFSDMEN)
+#define __HAL_RCC_ADFSDM1_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_ADFSDMEN)
+#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->MC_APB2ENCLRR = RCC_MC_APB2ENCLRR_FDCANEN)
+
+/** @brief Enable or disable the APB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_LPTIM2_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM3EN)
+#define __HAL_RCC_LPTIM4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM4EN)
+#define __HAL_RCC_LPTIM5_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_LPTIM5EN)
+#define __HAL_RCC_SAI4_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SAI4EN)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_SYSCFGEN)
+#define __HAL_RCC_VREF_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_VREFEN)
+#define __HAL_RCC_DTS_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_DTSEN)
+#define __HAL_RCC_PMBCTRL_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_PMBCTRLEN)
+#define __HAL_RCC_HDP_CLK_ENABLE() (RCC->MC_APB3ENSETR = RCC_MC_APB3ENSETR_HDPEN)
+
+#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM2EN)
+#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM3EN)
+#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM4EN)
+#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_LPTIM5EN)
+#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SAI4EN)
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_SYSCFGEN)
+#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_VREFEN)
+#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_DTSEN)
+#define __HAL_RCC_PMBCTRL_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_PMBCTRLEN)
+#define __HAL_RCC_HDP_CLK_DISABLE() (RCC->MC_APB3ENCLRR = RCC_MC_APB3ENCLRR_HDPEN)
+
+/** @brief Enable or disable the APB4 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_LTDCEN)
+#define __HAL_RCC_DSI_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DSIEN)
+#define __HAL_RCC_DDRPERFM_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_DDRPERFMEN)
+#define __HAL_RCC_USBPHY_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_USBPHYEN)
+#define __HAL_RCC_STGENRO_CLK_ENABLE() (RCC->MC_APB4ENSETR = RCC_MC_APB4ENSETR_STGENROEN)
+
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_LTDCEN)
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DSIEN)
+#define __HAL_RCC_DDRPERFM_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_DDRPERFMEN)
+#define __HAL_RCC_USBPHY_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_USBPHYEN)
+#define __HAL_RCC_STGENRO_CLK_DISABLE() (RCC->MC_APB4ENCLRR = RCC_MC_APB4ENCLRR_STGENROEN)
+
+/** @brief Enable or disable the APB5 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_SPI6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C4EN)
+#define __HAL_RCC_I2C6_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_I2C6EN)
+#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_USART1EN)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_RTCAPBEN)
+#define __HAL_RCC_TZC1_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC1EN)
+#define __HAL_RCC_TZC2_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZC2EN)
+#define __HAL_RCC_TZPC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_TZPCEN)
+#define __HAL_RCC_BSEC_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_BSECEN)
+#define __HAL_RCC_STGEN_CLK_ENABLE() (RCC->MC_APB5ENSETR = RCC_MC_APB5ENSETR_STGENEN)
+
+#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_SPI6EN)
+#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C4EN)
+#define __HAL_RCC_I2C6_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_I2C6EN)
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_USART1EN)
+#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_RTCAPBEN)
+#define __HAL_RCC_TZC1_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC1EN)
+#define __HAL_RCC_TZC2_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZC2EN)
+#define __HAL_RCC_TZPC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENCLRR_TZPCEN)
+#define __HAL_RCC_BSEC_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_BSECEN)
+#define __HAL_RCC_STGEN_CLK_DISABLE() (RCC->MC_APB5ENCLRR = RCC_MC_APB5ENSETR_STGENEN)
+
+/** @brief Enable or disable the AHB5 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_GPIOZ_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_GPIOZEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_CRYP1EN)
+#endif
+#define __HAL_RCC_HASH1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_HASH1EN)
+#define __HAL_RCC_RNG1_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_RNG1EN)
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() (RCC->MC_AHB5ENSETR = RCC_MC_AHB5ENSETR_BKPSRAMEN)
+
+#define __HAL_RCC_GPIOZ_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_GPIOZEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_CRYP1EN)
+#endif
+#define __HAL_RCC_HASH1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_HASH1EN)
+#define __HAL_RCC_RNG1_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_RNG1EN)
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->MC_AHB5ENCLRR = RCC_MC_AHB5ENCLRR_BKPSRAMEN)
+
+/** @brief Enable or disable the AHB6 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_MDMA_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_MDMAEN)
+#define __HAL_RCC_GPU_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_GPUEN)
+#define __HAL_RCC_ETH1CK_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHCKEN)
+#define __HAL_RCC_ETH1TX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHTXEN)
+#define __HAL_RCC_ETH1RX_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHRXEN)
+#define __HAL_RCC_ETH1MAC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_ETHMACEN)
+#define __HAL_RCC_FMC_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_FMCEN)
+#define __HAL_RCC_QSPI_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_QSPIEN)
+#define __HAL_RCC_SDMMC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC1EN)
+#define __HAL_RCC_SDMMC2_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_SDMMC2EN)
+#define __HAL_RCC_CRC1_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_CRC1EN)
+#define __HAL_RCC_USBH_CLK_ENABLE() (RCC->MC_AHB6ENSETR = RCC_MC_AHB6ENSETR_USBHEN)
+
+#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_MDMAEN)
+#define __HAL_RCC_GPU_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_GPUEN)
+#define __HAL_RCC_ETH1CK_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHCKEN)
+#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHTXEN)
+#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHRXEN)
+#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_ETHMACEN)
+#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_FMCEN)
+#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_QSPIEN)
+#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC1EN)
+#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_SDMMC2EN)
+#define __HAL_RCC_CRC1_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_CRC1EN)
+#define __HAL_RCC_USBH_CLK_DISABLE() (RCC->MC_AHB6ENCLRR = RCC_MC_AHB6ENCLRR_USBHEN)
+
+/** @brief Enable or disable the AHB2 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_DMA1_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA1EN)
+#define __HAL_RCC_DMA2_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMA2EN)
+#define __HAL_RCC_DMAMUX_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_DMAMUXEN)
+#define __HAL_RCC_ADC12_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_ADC12EN)
+#define __HAL_RCC_USBO_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_USBOEN)
+#define __HAL_RCC_SDMMC3_CLK_ENABLE() (RCC->MC_AHB2ENSETR = RCC_MC_AHB2ENSETR_SDMMC3EN)
+
+#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA1EN)
+#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMA2EN)
+#define __HAL_RCC_DMAMUX_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_DMAMUXEN)
+#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_ADC12EN)
+#define __HAL_RCC_USBO_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_USBOEN)
+#define __HAL_RCC_SDMMC3_CLK_DISABLE() (RCC->MC_AHB2ENCLRR = RCC_MC_AHB2ENCLRR_SDMMC3EN)
+
+/** @brief Enable or disable the AHB3 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_DCMI_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_DCMIEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRYP2EN)
+#endif
+#define __HAL_RCC_HASH2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HASH2EN)
+#define __HAL_RCC_RNG2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_RNG2EN)
+#define __HAL_RCC_CRC2_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_CRC2EN)
+#define __HAL_RCC_HSEM_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_HSEMEN)
+#define __HAL_RCC_IPCC_CLK_ENABLE() (RCC->MC_AHB3ENSETR = RCC_MC_AHB3ENSETR_IPCCEN)
+
+#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_DCMIEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRYP2EN)
+#endif
+#define __HAL_RCC_HASH2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HASH2EN)
+#define __HAL_RCC_RNG2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_RNG2EN)
+#define __HAL_RCC_CRC2_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_CRC2EN)
+#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_HSEMEN)
+#define __HAL_RCC_IPCC_CLK_DISABLE() (RCC->MC_AHB3ENCLRR = RCC_MC_AHB3ENCLRR_IPCCEN)
+
+/** @brief Enable or disable the AHB4 peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_GPIOA_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_ENABLE() (RCC->MC_AHB4ENSETR = RCC_MC_AHB4ENSETR_GPIOKEN)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOAEN)
+#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOBEN)
+#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOCEN)
+#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIODEN)
+#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOEEN)
+#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOFEN)
+#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOGEN)
+#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOHEN)
+#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOIEN)
+#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOJEN)
+#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->MC_AHB4ENCLRR = RCC_MC_AHB4ENCLRR_GPIOKEN)
+
+/** @brief Enable or disable the AXI peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_SYSRAM_CLK_ENABLE() (RCC->MC_AXIMENSETR = RCC_MC_AXIMENSETR_SYSRAMEN)
+
+#define __HAL_RCC_SYSRAM_CLK_DISABLE() (RCC->MC_AXIMENCLRR = RCC_MC_AXIMENCLRR_SYSRAMEN)
+
+/** @brief Enable or disable the MLAHB peripheral clock.
+ * @note After reset, the peripheral clock (used for registers read/write access)
+ * is disabled and the application software has to enable this clock before
+ * using it. It shall be used to allocate a peripheral to the MCU.
+ */
+#define __HAL_RCC_RETRAM_CLK_ENABLE() (RCC->MC_MLAHBENSETR = RCC_MC_MLAHBENSETR_RETRAMEN)
+
+#define __HAL_RCC_RETRAM_CLK_DISABLE() (RCC->MC_MLAHBENCLRR = RCC_MC_MLAHBENCLRR_RETRAMEN)
+
+
+
+
+
+
+
+/** @brief Enable or disable the APB1 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_LPTIM1LPEN)
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPI3LPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART5LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_UART8LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C3LPEN)
+#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_I2C5LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_SPDIFLPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_CECLPEN)
+#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_WWDG1LPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_DAC12LPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->MC_APB1LPENSETR = RCC_MC_APB1LPENSETR_MDIOSLPEN)
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM2LPEN)
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM3LPEN)
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM4LPEN)
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM5LPEN)
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM6LPEN)
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM7LPEN)
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM12LPEN)
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM13LPEN)
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_TIM14LPEN)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_LPTIM1LPEN)
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI2LPEN)
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPI3LPEN)
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART2LPEN)
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_USART3LPEN)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART4LPEN)
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART5LPEN)
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART7LPEN)
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_UART8LPEN)
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C1LPEN)
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C2LPEN)
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C3LPEN)
+#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_I2C5LPEN)
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_SPDIFLPEN)
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_CECLPEN)
+#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_WWDG1LPEN)
+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_DAC12LPEN)
+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->MC_APB1LPENCLRR = RCC_MC_APB1LPENCLRR_MDIOSLPEN)
+
+
+/** @brief Enable or disable the APB2 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM8LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_TIM17LPEN)
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI4LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SPI5LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_USART6LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI2LPEN)
+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_SAI3LPEN)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_DFSDMLPEN)
+#define __HAL_RCC_ADFSDM1_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_ADFSDMLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->MC_APB2LPENSETR = RCC_MC_APB2LPENSETR_FDCANLPEN)
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM1LPEN)
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM8LPEN)
+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM15LPEN)
+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM16LPEN)
+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_TIM17LPEN)
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI1LPEN)
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI4LPEN)
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SPI5LPEN)
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_USART6LPEN)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI1LPEN)
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI2LPEN)
+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_SAI3LPEN)
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_DFSDMLPEN)
+#define __HAL_RCC_ADFSDM1_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_ADFSDMLPEN)
+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->MC_APB2LPENCLRR = RCC_MC_APB2LPENCLRR_FDCANLPEN)
+
+
+/** @brief Enable or disable the APB3 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM3LPEN)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM4LPEN)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_LPTIM5LPEN)
+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SAI4LPEN)
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_SYSCFGLPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_VREFLPEN)
+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_DTSLPEN)
+#define __HAL_RCC_PMBCTRL_CLK_SLEEP_ENABLE() (RCC->MC_APB3LPENSETR = RCC_MC_APB3LPENSETR_PMBCTRLLPEN)
+
+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM2LPEN)
+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM3LPEN)
+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM4LPEN)
+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_LPTIM5LPEN)
+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SAI4LPEN)
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_SYSCFGLPEN)
+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_VREFLPEN)
+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_DTSLPEN)
+#define __HAL_RCC_PMBCTRL_CLK_SLEEP_DISABLE() (RCC->MC_APB3LPENCLRR = RCC_MC_APB3LPENCLRR_PMBCTRLLPEN)
+
+/** @brief Enable or disable the APB4 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_LTDCLPEN)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DSILPEN)
+#define __HAL_RCC_DDRPERFM_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_DDRPERFMLPEN)
+#define __HAL_RCC_USBPHY_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_USBPHYLPEN)
+#define __HAL_RCC_STGENRO_CLK_SLEEP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROLPEN)
+#define __HAL_RCC_STGENRO_CLK_STOP_ENABLE() (RCC->MC_APB4LPENSETR = RCC_MC_APB4LPENSETR_STGENROSTPEN)
+
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_LTDCLPEN)
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DSILPEN)
+#define __HAL_RCC_DDRPERFM_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_DDRPERFMLPEN)
+#define __HAL_RCC_USBPHY_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_USBPHYLPEN)
+#define __HAL_RCC_STGENRO_CLK_SLEEP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROLPEN)
+#define __HAL_RCC_STGENRO_CLK_STOP_DISABLE() (RCC->MC_APB4LPENCLRR = RCC_MC_APB4LPENCLRR_STGENROSTPEN)
+
+/** @brief Enable or disable the APB5 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C4LPEN)
+#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_I2C6LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_USART1LPEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_RTCAPBLPEN)
+#define __HAL_RCC_TZC1_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC1LPEN)
+#define __HAL_RCC_TZC2_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZC2LPEN)
+#define __HAL_RCC_TZPC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_TZPCLPEN)
+#define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_BSECLPEN)
+#define __HAL_RCC_STGEN_CLK_SLEEP_ENABLE() (RCC->MC_APB5LPENSETR = RCC_MC_APB5LPENSETR_STGENLPEN)
+
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_SPI6LPEN)
+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C4LPEN)
+#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_I2C6LPEN)
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_USART1LPEN)
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_RTCAPBLPEN)
+#define __HAL_RCC_TZC1_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC1LPEN)
+#define __HAL_RCC_TZC2_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZC2LPEN)
+#define __HAL_RCC_TZPC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENCLRR_TZPCLPEN)
+#define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_BSECLPEN)
+#define __HAL_RCC_STGEN_CLK_SLEEP_DISABLE() (RCC->MC_APB5LPENCLRR = RCC_MC_APB5LPENSETR_STGENLPEN)
+
+
+/** @brief Enable or disable the AHB5 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_GPIOZ_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_GPIOZLPEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_CRYP1LPEN)
+#endif
+#define __HAL_RCC_HASH1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_HASH1LPEN)
+#define __HAL_RCC_RNG1_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_RNG1LPEN)
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AHB5LPENSETR = RCC_MC_AHB5LPENSETR_BKPSRAMLPEN)
+
+#define __HAL_RCC_GPIOZ_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_GPIOZLPEN)
+#if defined(CRYP1)
+#define __HAL_RCC_CRYP1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_CRYP1LPEN)
+#endif
+#define __HAL_RCC_HASH1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_HASH1LPEN)
+#define __HAL_RCC_RNG1_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_RNG1LPEN)
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AHB5LPENCLRR = RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN)
+
+
+/** @brief Enable or disable the AHB6 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_MDMALPEN)
+#define __HAL_RCC_GPU_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_GPULPEN)
+#define __HAL_RCC_ETH1CK_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHCKLPEN)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHTXLPEN)
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHRXLPEN)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHMACLPEN)
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_FMCLPEN)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_QSPILPEN)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC1LPEN)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_SDMMC2LPEN)
+#define __HAL_RCC_CRC1_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_CRC1LPEN)
+#define __HAL_RCC_USBH_CLK_SLEEP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_USBHLPEN)
+
+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_MDMALPEN)
+#define __HAL_RCC_GPU_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_GPULPEN)
+#define __HAL_RCC_ETH1CK_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHCKLPEN)
+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHTXLPEN)
+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHRXLPEN)
+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_ETHMACLPEN)
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_FMCLPEN)
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_QSPILPEN)
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC1LPEN)
+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_SDMMC2LPEN)
+#define __HAL_RCC_CRC1_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_CRC1LPEN)
+#define __HAL_RCC_USBH_CLK_SLEEP_DISABLE() (RCC->MC_AHB6LPENCLRR = RCC_MC_AHB6LPENCLRR_USBHLPEN)
+
+
+/** @brief Enable or disable the AHB2 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA1LPEN)
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMA2LPEN)
+#define __HAL_RCC_DMAMUX_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_DMAMUXLPEN)
+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_ADC12LPEN)
+#define __HAL_RCC_USBO_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_USBOLPEN)
+#define __HAL_RCC_SDMMC3_CLK_SLEEP_ENABLE() (RCC->MC_AHB2LPENSETR = RCC_MC_AHB2LPENSETR_SDMMC3LPEN)
+
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA1LPEN)
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMA2LPEN)
+#define __HAL_RCC_DMAMUX_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_DMAMUXLPEN)
+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_ADC12LPEN)
+#define __HAL_RCC_USBO_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_USBOLPEN)
+#define __HAL_RCC_SDMMC3_CLK_SLEEP_DISABLE() (RCC->MC_AHB2LPENCLRR = RCC_MC_AHB2LPENCLRR_SDMMC3LPEN)
+
+/** @brief Enable or disable the AHB3 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_DCMILPEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRYP2LPEN)
+#endif
+#define __HAL_RCC_HASH2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HASH2LPEN)
+#define __HAL_RCC_RNG2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_RNG2LPEN)
+#define __HAL_RCC_CRC2_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_CRC2LPEN)
+#define __HAL_RCC_HSEM_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_HSEMLPEN)
+#define __HAL_RCC_IPCC_CLK_SLEEP_ENABLE() (RCC->MC_AHB3LPENSETR = RCC_MC_AHB3LPENSETR_IPCCLPEN)
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_DCMILPEN)
+#if defined(CRYP2)
+#define __HAL_RCC_CRYP2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRYP2LPEN)
+#endif
+#define __HAL_RCC_HASH2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HASH2LPEN)
+#define __HAL_RCC_RNG2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_RNG2LPEN)
+#define __HAL_RCC_CRC2_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_CRC2LPEN)
+#define __HAL_RCC_HSEM_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_HSEMLPEN)
+#define __HAL_RCC_IPCC_CLK_SLEEP_DISABLE() (RCC->MC_AHB3LPENCLRR = RCC_MC_AHB3LPENCLRR_IPCCLPEN)
+
+
+/** @brief Enable or disable the AHB4 peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->MC_AHB4LPENSETR = RCC_MC_AHB4LPENSETR_GPIOKLPEN)
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOALPEN)
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOBLPEN)
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOCLPEN)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIODLPEN)
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOELPEN)
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOFLPEN)
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOGLPEN)
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOHLPEN)
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOILPEN)
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOJLPEN)
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->MC_AHB4LPENCLRR = RCC_MC_AHB4LPENCLRR_GPIOKLPEN)
+
+/** @brief Enable or disable the AXI peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_SYSRAM_CLK_SLEEP_ENABLE() (RCC->MC_AXIMLPENSETR = RCC_MC_AXIMLPENSETR_SYSRAMLPEN)
+
+#define __HAL_RCC_SYSRAM_CLK_SLEEP_DISABLE() (RCC->MC_AXIMLPENCLRR = RCC_MC_AXIMLPENCLRR_SYSRAMLPEN)
+
+
+/** @brief Enable or disable the MLAHB peripheral clock during CSLEEP mode.
+ * @note Peripheral clock gating in SLEEP mode can be used to further reduce
+ * power consumption.
+ * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
+ * @note By default, all peripheral clocks are enabled during CSLEEP mode.
+ */
+#define __HAL_RCC_RETRAM_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_RETRAMLPEN)
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM1LPEN)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM2LPEN)
+#define __HAL_RCC_SRAM34_CLK_SLEEP_ENABLE() (RCC->MC_MLAHBLPENSETR = RCC_MC_MLAHBLPENSETR_SRAM34LPEN)
+
+#define __HAL_RCC_RETRAM_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_RETRAMLPEN)
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM1LPEN)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM2LPEN)
+#define __HAL_RCC_SRAM34_CLK_SLEEP_DISABLE() (RCC->MC_MLAHBLPENCLRR = RCC_MC_MLAHBLPENCLRR_SRAM3LPEN)
+
+/** @brief Enable or disable the AHB6 peripheral clock during (C)STOP mode.
+ * @note Peripheral clock gating in (C)STOP mode can be used to further reduce
+ * power consumption.
+ * @note It is possible to control the gating of clocks coming from PADs ETH_RX_CLK and ETH_TX_CLK
+ * in CSTOP and STOP modes via the ETHSTPEN bit
+ */
+#define __HAL_RCC_ETH1CK_CLK_STOP_ENABLE() (RCC->MC_AHB6LPENSETR = RCC_MC_AHB6LPENSETR_ETHSTPEN)
+
+#define __HAL_RCC_ETH1CK_CLK_STOP_DISABLE() (RCC->MC_AHB6LPENSETR) = (RCC_MC_AHB6LPENCLRR_ETHSTPEN)
+
+#endif /* !CORE_CA7 */
+
+/** @brief Macro to test if HSE oscillator is used somewhere in the core system
+ * @note HAL driver does not ensure these clocks are used by peripherals, it's
+ * up to user code
+ */
+#define IS_HSE_IN_USE() \
+ (( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) ) || \
+ ((__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY)) || \
+ ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_HSE ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY)) || \
+ \
+ ((__HAL_RCC_GET_PLL12_SOURCE() == RCC_PLL12SOURCE_HSE) && \
+ ( __HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) || __HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) )) || \
+ \
+ ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_HSE) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \
+ \
+ ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_HSE) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) ))? 1 : 0)
+
+/** @brief Macro to test if HSI oscillator is used somewhere in the core system
+ * @note HAL driver does not ensure these clocks are used by peripherals, it's
+ * up to user code
+ */
+#define IS_HSI_IN_USE() \
+ (( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) ) || \
+ ((__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) ) || \
+ ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_HSI ) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) ) || \
+ \
+ ((__HAL_RCC_GET_PLL12_SOURCE() == RCC_PLL12SOURCE_HSI) && \
+ ( __HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) || __HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) )) || \
+ \
+ ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_HSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \
+ \
+ ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_HSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) ))? 1 : 0)
+
+
+/** @brief Macro to test if CSI oscillator is used somewhere in the core system
+ * @note HAL driver does not ensure these clocks are used by peripherals, it's
+ * up to user code
+ */
+#define IS_CSI_IN_USE() \
+ (( ((__HAL_RCC_GET_PLL3_SOURCE() == RCC_PLL3SOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) ) || \
+ ((__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY)) || \
+ \
+ ((__HAL_RCC_GET_PLL4_SOURCE() == RCC_PLL4SOURCE_CSI) && __HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY)))? 1 : 0)
+
+/** @brief Macros to test if PLLx are used on the Core and buses clock generation system (MPU, MCU or AXIS blocks)
+ * @note HAL driver does not ensure these clocks are used by peripherals, it's up to user code */
+#define __IS_PLL1_IN_USE() \
+ ( ( ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_PLL1) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY)) || \
+ ((__HAL_RCC_GET_MPU_SOURCE() == RCC_MPUSOURCE_MPUDIV) && __HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY)) ) ? 1:0)
+
+#define __IS_PLL2_IN_USE() \
+ ( ( (__HAL_RCC_GET_AXIS_SOURCE() == RCC_AXISSOURCE_PLL2) && __HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) )? 1:0)
+
+#define __IS_PLL3_IN_USE() \
+ ( ( (__HAL_RCC_GET_MCU_SOURCE() == RCC_MCUSSOURCE_PLL3) && __HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) )? 1:0)
+
+/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
+ * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after startup
+ * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+ * of the HSE used directly or indirectly as system clock (if the Clock
+ * Security System CSS is enabled).
+ * @note HSI can not be stopped if it is used as system clock source. In this case,
+ * you have to select another source of the system clock then stop the HSI.
+ * @note After enabling the HSI, the application software should wait on HSIRDY
+ * flag to be set indicating that HSI clock is stable and can be used as
+ * system clock source.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSION)
+#define __HAL_RCC_HSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSION)
+
+/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal HSI RC.
+ * @param __HSICalibrationValue__: specifies the calibration trimming value
+ * HSITRIM. HSITRIM represents a signed value. HSITRIM field is added
+ * to the engineering Option Bytes loaded during reset phase
+ * (bsec_hsi_cal[11:0]) in order to form the calibration trimming value.
+ * HSICAL[11:0] = bsec_hsi_cal[11:0] + HSITRIM[6:0]
+ * This parameter must be a number between 0 and 0x7F:
+ * 0x40: bsec_hsi_cal[11:0] - 64
+ * 0x41: bsec_hsi_cal[11:0] - 63
+ * ...
+ * 0x0: bsec_hsi_cal[11:0] (default after reset)
+ * ...
+ * 0x3E: bsec_hsi_cal[11:0] + 62
+ * 0x3F: bsec_hsi_cal[11:0] + 63
+ */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
+ MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, \
+ (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos)
+
+
+/**
+ * @brief Macro to configure HSI clock divider
+ * @note Set and reset by software to control the HSI clock division factor.
+ * @note It is not allowed to change HSIDIV, if the HSI is currently used as
+ * reference clock for a PLL.
+ * @note If TZEN = 1, this parameter can only be modified in secure mode.
+ * @note Write access to this register is not allowed during the clock restore sequence
+ * @note The application can check if the new division factor is taken into
+ * account by reading back the HSIDIVRDY flag
+ *
+ * @param __RCC_HSIDIV__: specifies the HSI division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_HSI_DIV1: Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)
+ * @arg RCC_HSI_DIV2: Division by 2, ck_hsi(_ker) = 32 MHz
+ * @arg RCC_HSI_DIV4: Division by 4, ck_hsi(_ker) = 16 MHz
+ * @arg RCC_HSI_DIV8: Division by 8, ck_hsi(_ker) = 8 MHz
+ */
+#define __HAL_RCC_HSI_DIV(__RCC_HSIDIV__) \
+ do{ MODIFY_REG( RCC->HSICFGR, RCC_HSICFGR_HSIDIV , __RCC_HSIDIV__ );\
+ } while(0)
+
+/** @brief Macro to get the HSI clock division factor.
+ * @retval The HSI clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_HSI_DIV1: Division by 1, ck_hsi(_ker) = 64 MHz (default after reset)
+ * - RCC_HSI_DIV2: Division by 2, ck_hsi(_ker) = 32 MHz
+ * - RCC_HSI_DIV4: Division by 4, ck_hsi(_ker) = 16 MHz
+ * - RCC_HSI_DIV8: Division by 8, ck_hsi(_ker) = 8 MHz
+ */
+#define __HAL_RCC_GET_HSI_DIV() ((uint32_t)(RCC->HSICFGR & RCC_HSICFGR_HSIDIV ))
+
+
+/**
+ * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
+ * in STOP mode to be quickly available as kernel clock.
+ * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
+ * speed because of the HSI startup time.
+ * @note The enable of this function has not effect on the HSION bit.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSIKERON)
+#define __HAL_RCC_HSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON)
+
+
+/**
+ * @brief Macros to enable or disable the Internal oscillator (CSI).
+ * @note The CSI is stopped by hardware when entering STOP and STANDBY modes.
+ * It is used (enabled by hardware) as system clock source after
+ * startup from Reset, wakeup from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ * @note CSI can not be stopped if it is used as system clock source.
+ * In this case, you have to select another source of the system
+ * clock then stop the CSI.
+ * @note After enabling the CSI, the application software should wait on
+ * CSIRDY flag to be set indicating that CSI clock is stable and can
+ * be used as system clock source.
+ * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSION)
+#define __HAL_RCC_CSI_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENSETR_CSION)
+
+/** @brief Macro Adjusts the Internal oscillator (CSI) calibration value.
+ * @note The calibration is used to compensate for the variations in voltage
+ * and temperature that influence the frequency of the internal CSI RC.
+ * Please refer to the datasheet of the product for for more details on how to
+ * calibrate the CSI.
+ * @param __CSICalibrationValue__: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ */
+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \
+ MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, \
+ (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos)
+
+/**
+ * @brief Macros to enable or disable the force of the Internal High Speed oscillator (CSI)
+ * in STOP mode to be quickly available as kernel clock.
+ * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication
+ * speed because of the CSI startup time.
+ * @note The enable of this function has not effect on the CSION bit.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_CSIKERON)
+#define __HAL_RCC_CSISTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_CSIKERON)
+
+
+/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
+ * @note After enabling the LSI, the application software should wait on
+ * LSIRDY flag to be set indicating that LSI clock is stable and can
+ * be used to clock the IWDG and/or the RTC.
+ * @note LSI can not be disabled if the IWDG is running.
+ * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+ * clock cycles.
+ */
+#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION)
+#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION)
+
+
+
+
+/** @brief Macro to configure the Minimum Reset Duration
+ * @note Set and reset by software. They define the minimum guaranteed
+ * duration of the NRST low pulse. The LSI oscillator is automatically
+ * enabled when needed by the RPCTL.
+ * @note 00000: NRST low pulse duration is guaranteed by the pulse stretcher
+ * of the PAD. The RPCTL is bypassed (default after reset)
+ * 00010: The guaranteed NRST low pulse duration is about 2 ms (2 x 32 ck_lsi cycles),
+ * ...
+ * 11111: The guaranteed NRST low pulse duration is about 31 ms (31 x 32 ck_lsi cycles).
+ */
+#define __HAL_RCC_MRD_CONFIG(__DURATION__) \
+ do { MODIFY_REG(RCC->RDLSICR, RCC_RDLSICR_MRD, \
+ (uint32_t)(__DURATION__) << RCC_RDLSICR_MRD_Pos) \
+ HAL_Delay(1); \
+ } while(0)
+
+
+
+/**
+ * @brief Macro (depricated) to configure the External High Speed oscillator (HSE).
+ * @note Macro name is kept to mantain compatibility and it is mapped on
+ * HAL_RCC_HSEConfig function which replaces macro and should be used
+ * instead.
+ * @note HSE state can not be changed if it is used directly or through the
+ * PLL as system clock. In this case, you have to select another source
+ * of the system clock then change the HSE state (ex. disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param __STATE__: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator using an external
+ * crystal/ceramic resonator
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
+ * using a low-swing analog signal provided to OSC_IN
+ * @arg RCC_HSE_BYPASS_DIG: HSE oscillator bypassed with external
+ * clock using a full-swing digital signal provided to OSC_IN
+ */
+#define __HAL_RCC_HSE_CONFIG(__STATE__) HAL_RCC_HSEConfig(__STATE__)
+
+
+/**
+ * @brief Macros to enable or disable the force of the External High Speed oscillator (HSE)
+ * in STOP mode to be quickly available as kernel clock.
+ * @note Keeping the HSE ON in STOP mode allows to avoid slowing down the communication
+ * speed because of the HSE startup time.
+ * @note The enable of this function has not effect on the HSION bit.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+#define __HAL_RCC_HSESTOP_ENABLE() SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEKERON)
+#define __HAL_RCC_HSESTOP_DISABLE() WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEKERON)
+
+
+/**
+ * @brief Macro (depricated) to configure the External Low Speed oscillator (LSE).
+ * @note Macro name is kept to mantain compatibility and it is mapped on
+ * HAL_RCC_LSEConfig function which replaces macro and should be used
+ * instead.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @param __STATE__: specifies the new state of the LSE.
+ * This parameter can be a value of @ref RCC_LSE_Config
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator using an external
+ * crystal/ceramic resonator
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
+ * using a low-swing analog signal provided to OSC32_IN
+ * @arg RCC_LSE_BYPASS_DIG: LSE oscillator bypassed with external clock using
+ * a full-swing digital signal provided to OSC32_IN
+ */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) HAL_RCC_LSEConfig(__STATE__)
+
+
+/**
+ * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+ * (to be done once after reset).
+ * @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability (default after backup domain reset)
+ * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
+ * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
+ * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
+ * @retval None
+ */
+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
+
+
+/** @brief Macro to get the LSE driving capability.
+ * @retval The LSE Driving capability . The returned value can be one
+ * of the following:
+ * - RCC_LSEDRIVE_LOW: LSE oscillator low drive capability (default after backup domain reset)
+ * - RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
+ * - RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
+ * - RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
+ */
+#define __HAL_RCC_GET_LSEDRIVE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)))
+
+/** @brief Macros to enable or disable the the RTC clock.
+ * @note These macros must be used only after the RTC clock source was selected.
+ */
+#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN)
+#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCCKEN)
+
+/** @brief Macros to configure the RTC clock (RTCCLK).
+ * @note As the RTC clock configuration bits are in the Backup domain and write
+ * access is protected to this domain after reset, you have to enable write
+ * access using the Power Backup Access macro ( DBP bit in the PWR control
+ * register 1 PWR_CR1 has to be set to 1) before to configure
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
+ * Backup domain is reset using __HAL_RCC_BACKUPRESET_RELEASE() macro, or by
+ * a Power On Reset (POR).
+ * @param __RTCCLKSource__: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSOURCE_OFF: No clock (default after backup domain reset)
+ * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+ * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+ * @arg RCC_RTCCLKSOURCE_HSE_DIV: HSE clock divided by RTCDIV value is used as RTC clock
+ *
+ * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
+ * work in STOP and STANDBY modes, and can be used as wakeup source.
+ * However, when the HSE clock is used as RTC clock source, the RTC
+ * cannot be used in STOP and STANDBY modes.
+ * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
+ * RTC clock source).
+ */
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
+ MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSRC, (__RTCCLKSource__))
+
+
+/** @brief Macro to get the clock source used as RTC clock.
+ * @retval The clock source used as RTC clock. The returned value can be one
+ * of the following:
+ * - RCC_RTCCLKSOURCE_OFF: No clock (default after backup domain reset)
+ * - RCC_RTCCLKSOURCE_LSE: LSE used as RTC clock.
+ * - RCC_RTCCLKSOURCE_LSI: LSI used as RTC clock.
+ * - RCC_RTCCLKSOURCE_HSE_DIV: HSE clock divided by RTCDIV value is used as RTC clock
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSRC)))
+
+
+/** @brief Macros to force or release the Backup domain reset.
+ * @note This function resets the RTC peripheral (including the backup registers)
+ *
+ * @note The BKPSRAM and RETRAM are not affected
+ */
+#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST)
+
+
+/** @brief Macros to enable or disable the PLL1.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The PLL1 can not be disabled if it is used as MPU clock source
+ * @note The PLL1 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+
+#define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON )
+#define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON)
+
+/**
+ * @brief Enables or disables each clock output
+ * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL,
+ * with the exception of ck_pll_p cannot be stopped if used as MPU Clock
+ * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputed
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL1_DIVP
+ * @arg RCC_PLL1_DIVQ
+ * @arg RCC_PLL1_DIVR
+ * @retval None
+ */
+
+#define __HAL_RCC_PLL1CLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLL1CR, __RCC_PLL1ClockOut__ )
+
+#define __HAL_RCC_PLL1CLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLL1CR, __RCC_PLL1ClockOut__ )
+
+
+/**
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO
+ * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL1
+ * @retval None
+ */
+
+#define __HAL_RCC_PLL1FRACV_ENABLE() SET_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE)
+
+#define __HAL_RCC_PLL1FRACV_DISABLE() CLEAR_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACLE)
+
+
+
+/**
+ * @brief Macro to configure PLL1 and PLL2 clock source
+ * @note This function must be used only when the PLLs are disabled.
+ *
+ * @param __RCC_PLL12SOURCE__: specifies the PLL1 and PLL2 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL12SOURCE_HSI: HSI oscillator clock selected as PLL1 and PLL2 clock entry
+ * @arg RCC_PLL12SOURCE_HSE: HSE oscillator clock selected as PLL1 and PLL2 clock entry
+ * @arg RCC_PLL12SOURCE_OFF: No clock send to DIVMx divider and PLLs
+ * @note This clock source (__RCC_PLL12Source__) is common for the PLL1 and PLL2 .
+ * @retval None
+ */
+#define __HAL_RCC_PLL12_SOURCE(__RCC_PLL12SOURCE__ ) \
+ do{ MODIFY_REG( RCC->RCK12SELR, RCC_RCK12SELR_PLL12SRC, __RCC_PLL12SOURCE__ ); \
+ } while(0)
+
+/** @brief Macro to get the clock source used as PLL1 and PLL2 clocks.
+ * @retval The clock source used as PLL1 and PLL1 clocks. The returned value can be one
+ * of the following:
+ * - RCC_PLL12SOURCE_HSI: HSI used as PLL12 clock.
+ * - RCC_PLL12SOURCE_HSE: HSE used as PLL12 clock.
+ * - RCC_PLL12SOURCE_OFF: PLL1 and PLL2 clock is gated.
+ */
+#define __HAL_RCC_GET_PLL12_SOURCE() ((uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC))
+
+/**
+ * @brief Macro to configure PLL1 multiplication and division factors.
+ * @note This function must be used only when the PLL1 is disabled.
+ *
+ * @param __PLLM1__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 1 and 64
+ * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input
+ * frequency ranges from 8 to 16 MHz
+ * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 25 and 100
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 800 to 1600 MHz
+ * @param __PLLP1__: specifies the division factor for the PLL1 P output
+ * This parameter must be a number in the range 1 to 128
+ * @param __PLLQ1__: specifies the division factor for for the PLL1 Q output
+ * This parameter must be in the range 1 to 128
+ * @param __PLLR1__: specifies the division factor for for the PLL1 R output
+ * This parameter must be in the range 1 to 128
+ * @retval None
+ */
+#define __HAL_RCC_PLL1_CONFIG(__PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \
+ do{ MODIFY_REG( RCC->PLL1CFGR1, (RCC_PLL1CFGR1_DIVN | RCC_PLL1CFGR1_DIVM1) , \
+ ( (__PLLN1__ - 1U) | ( (__PLLM1__ - 1U) << 16U) ) ); \
+ MODIFY_REG( RCC->PLL1CFGR2, (RCC_PLL1CFGR2_DIVP | RCC_PLL1CFGR2_DIVQ | RCC_PLL1CFGR2_DIVR), \
+ ( (__PLLP1__ - 1U) | ( (__PLLQ1__ - 1U) <<8U ) | ( (__PLLR1__ - 1U) <<16U) )); \
+ } while(0)
+
+
+
+/**
+ * @brief Macro to configure the PLL1 clock Fractional Part Of The Multiplication Factor
+ *
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO
+ *
+ * @param __RCC_PLL1FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL1 VCO
+ * It should be a value between 0 and 8191 ((2^13)-1)
+ * @note Warning: the software has to set correctly these bits to insure that the VCO
+ * output frequency is between its valid frequency range, which is: 800 to 1600 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL1FRACV_CONFIG(__RCC_PLL1FRACV__) \
+ MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACV,\
+ (uint32_t)(__RCC_PLL1FRACV__) << RCC_PLL1FRACR_FRACV_Pos)
+
+
+/** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL1
+ */
+#define __HAL_RCC_PLL1_SSMODE_ENABLE() SET_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL)
+
+#define __HAL_RCC_PLL1_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL)
+
+
+/** @brief Macro to config the PLL1 Clock Spreading Generator
+ * @param __RCC_PLL1_MOD_PER__: Modulation Period Adjustment for PLL1
+ * This parameter must have a value between 1 and 8191
+ *
+ * @param __RCC_PLL1_TPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled
+
+ * @param __RCC_PLL1_RPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled
+ *
+ *
+ * @param __RCC_PLL1_SSCG_MODE__: Spread spectrum clock generator mode
+ * This parameter can be one of the following values:
+ * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset)
+ * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected
+ *
+ * @param __RCC_PLL1_INC_STEP__: Modulation Depth Adjustment for PLL1
+ * This parameter must have a value between 1 and 32767
+ * @note MOD_PER x INC_STEP shall not exceed (2^15)-1
+ * @retval None
+ */
+#define __HAL_RCC_PLL1CSGCONFIG(__RCC_PLL1_MOD_PER__, __RCC_PLL1_TPDFN_DIS__, __RCC_PLL1_RPDFN_DIS__, \
+ __RCC_PLL1_SSCG_MODE__, __RCC_PLL1_INC_STEP__ ) \
+ do{ MODIFY_REG( RCC->PLL1CSGR, (RCC_PLL1CSGR_MOD_PER | RCC_PLL1CSGR_TPDFN_DIS | RCC_PLL1CSGR_RPDFN_DIS | \
+ RCC_PLL1CSGR_SSCG_MODE | RCC_PLL1CSGR_INC_STEP) , \
+ (__RCC_PLL1_MOD_PER__ | __RCC_PLL1_TPDFN_DIS__ | __RCC_PLL1_RPDFN_DIS__ | \
+ __RCC_PLL1_SSCG_MODE__ | (__RCC_PLL1_INC_STEP__ << RCC_PLL1CSGR_INC_STEP_Pos)) ) ; \
+ } while(0)
+
+
+
+/** @brief Macros to enable or disable the PLL2.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The PLL2 can not be disabled if it is used as MPU clock source
+ * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON )
+#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON)
+
+/**
+ * @brief Enables or disables each clock output
+ * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL
+ * @param __RCC_PLL2ClockOut__: specifies the PLL clock to be outputed
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL2_DIVP
+ * @arg RCC_PLL2_DIVQ
+ * @arg RCC_PLL2_DIVR
+ * @retval None
+ */
+
+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLL2CR, __RCC_PLL2ClockOut__ )
+
+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLL2CR, __RCC_PLL2ClockOut__ )
+
+/**
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
+ * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL2
+ * @retval None
+ */
+
+#define __HAL_RCC_PLL2FRACV_ENABLE() SET_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE)
+
+#define __HAL_RCC_PLL2FRACV_DISABLE() CLEAR_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACLE)
+
+/**
+ * @brief Macro to configure PLL2 multiplication and division factors.
+ * @note This function must be used only when the PLL2 is disabled.
+ *
+ * @param __PLLM2__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 1 and 64
+ * @note You have to set the PLLM2 parameter correctly to ensure that the VCO input
+ * frequency ranges from 8 to 16 MHz
+ * @param __PLLN2__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 25 and 100
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 800 to 1600 MHz
+ * @param __PLLP2__: specifies the division factor for the PLL2 P output
+ * This parameter must be a number in the range 1 to 128
+ * @param __PLLQ2__: specifies the division factor for for the PLL2 Q output
+ * This parameter must be in the range 1 to 128
+ * @param __PLLR2__: specifies the division factor for for the PLL2 R output
+ * This parameter must be in the range 1 to 128
+ * @retval None
+ */
+#define __HAL_RCC_PLL2_CONFIG(__PLLM2__, __PLLN2__, __PLLP2__, __PLLQ2__,__PLLR2__ ) \
+ do{ MODIFY_REG( RCC->PLL2CFGR1, (RCC_PLL2CFGR1_DIVN | RCC_PLL2CFGR1_DIVM2) , \
+ ( (__PLLN2__ - 1U) | ( (__PLLM2__ - 1U) << 16U) ) ); \
+ MODIFY_REG( RCC->PLL2CFGR2, (RCC_PLL2CFGR2_DIVP | RCC_PLL2CFGR2_DIVQ | RCC_PLL2CFGR2_DIVR), \
+ ( (__PLLP2__ - 1U) | ( (__PLLQ2__ - 1U) <<8U ) | ( (__PLLR2__ - 1U) <<16U) )); \
+ } while(0)
+
+/**
+ * @brief Macro to configure the PLL2 clock Fractional Part Of The Multiplication Factor
+ *
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
+ *
+ * @param __RCC_PLL2FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL2 VCO
+ * It should be a value between 0 and 8191 ((2^13)-1)
+ * @note Warning: the software has to set correctly these bits to insure that the VCO
+ * output frequency is between its valid frequency range, which is: 800 to 1600 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL2FRACV_CONFIG(__RCC_PLL2FRACV__) \
+ MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACV, \
+ (uint32_t)(__RCC_PLL2FRACV__) << RCC_PLL2FRACR_FRACV_Pos)
+
+
+/** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL2
+ */
+#define __HAL_RCC_PLL2_SSMODE_ENABLE() SET_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL)
+
+#define __HAL_RCC_PLL2_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL)
+
+
+/** @brief Macro to config the PLL2 Clock Spreading Generator
+ * @param __RCC_PLL2_MOD_PER__: Modulation Period Adjustment for PLL2
+ * This parameter must have a value between 1 and 8191
+ *
+ * @param __RCC_PLL2_TPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled
+
+ * @param __RCC_PLL2_RPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled
+ *
+ *
+ * @param __RCC_PLL2_SSCG_MODE__: Spread spectrum clock generator mode
+ * This parameter can be one of the following values:
+ * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset)
+ * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected
+ *
+ * @param __RCC_PLL2_INC_STEP__: Modulation Depth Adjustment for PLL2
+ * This parameter must have a value between 1 and 32767
+ *
+ * @note MOD_PER x INC_STEP shall not exceed (2^15)-1
+ * @retval None
+ */
+#define __HAL_RCC_PLL2CSGCONFIG(__RCC_PLL2_MOD_PER__, __RCC_PLL2_TPDFN_DIS__, __RCC_PLL2_RPDFN_DIS__, \
+ __RCC_PLL2_SSCG_MODE__, __RCC_PLL2_INC_STEP__ ) \
+ do{ MODIFY_REG( RCC->PLL2CSGR, (RCC_PLL2CSGR_MOD_PER | RCC_PLL2CSGR_TPDFN_DIS | RCC_PLL2CSGR_RPDFN_DIS | \
+ RCC_PLL2CSGR_SSCG_MODE | RCC_PLL2CSGR_INC_STEP) , \
+ (__RCC_PLL2_MOD_PER__ | __RCC_PLL2_TPDFN_DIS__ | __RCC_PLL2_RPDFN_DIS__ | \
+ __RCC_PLL2_SSCG_MODE__ | (__RCC_PLL2_INC_STEP__ << RCC_PLL2CSGR_INC_STEP_Pos)) ) ; \
+ } while(0)
+
+/** @brief Macros to enable or disable the PLL3.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The PLL3 can not be disabled if it is used as MPU clock source
+ * @note The PLL3 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON )
+#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON)
+
+/**
+ * @brief Enables or disables each clock output
+ * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL,
+ * with the exception of ck_pll_p cannot be stopped if used as MPU Clock
+ * @param __RCC_PLL3ClockOut__: specifies the PLL clock to be outputed
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL3_DIVP
+ * @arg RCC_PLL3_DIVQ
+ * @arg RCC_PLL3_DIVR
+ * @retval None
+ */
+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLL3CR, __RCC_PLL3ClockOut__ )
+
+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLL3CR, __RCC_PLL3ClockOut__ )
+
+
+/**
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
+ * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL3
+ * @retval None
+ */
+
+#define __HAL_RCC_PLL3FRACV_ENABLE() SET_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE)
+
+#define __HAL_RCC_PLL3FRACV_DISABLE() CLEAR_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACLE)
+
+
+/** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL3
+ */
+#define __HAL_RCC_PLL3_SSMODE_ENABLE() SET_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL)
+
+#define __HAL_RCC_PLL3_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL)
+
+
+/** @brief Macro to config the PLL3 Clock Spreading Generator
+ * @param __RCC_PLL3_MOD_PER__: Modulation Period Adjustment for PLL3
+ * This parameter must have a value between 1 and 8191
+ *
+ * @param __RCC_PLL3_TPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled
+
+ * @param __RCC_PLL3_RPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled
+ *
+ *
+ * @param __RCC_PLL3_SSCG_MODE__: Spread spectrum clock generator mode
+ * This parameter can be one of the following values:
+ * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset)
+ * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected
+ *
+ * @param __RCC_PLL3_INC_STEP__: Modulation Depth Adjustment for PLL3
+ * This parameter must have a value between 1 and 32767
+ *
+ * @note MOD_PER x INC_STEP shall not exceed (2^15)-1
+ * @retval None
+ */
+#define __HAL_RCC_PLL3CSGCONFIG(__RCC_PLL3_MOD_PER__, __RCC_PLL3_TPDFN_DIS__, __RCC_PLL3_RPDFN_DIS__, \
+ __RCC_PLL3_SSCG_MODE__, __RCC_PLL3_INC_STEP__ ) \
+ do{ MODIFY_REG( RCC->PLL3CSGR, (RCC_PLL3CSGR_MOD_PER | RCC_PLL3CSGR_TPDFN_DIS | RCC_PLL3CSGR_RPDFN_DIS | \
+ RCC_PLL3CSGR_SSCG_MODE | RCC_PLL3CSGR_INC_STEP) , \
+ (__RCC_PLL3_MOD_PER__ | __RCC_PLL3_TPDFN_DIS__ | __RCC_PLL3_RPDFN_DIS__ | \
+ __RCC_PLL3_SSCG_MODE__ | (__RCC_PLL3_INC_STEP__ << RCC_PLL3CSGR_INC_STEP_Pos)) ) ; \
+ } while(0)
+
+
+/**
+ * @brief Macro to configure PLL3 clock source
+ * @note This function must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLL3SOURCE__: specifies the PLL3 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL3SOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry
+ * @arg RCC_PLL3SOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry
+ * @arg RCC_PLL3SOURCE_CSI: HSE oscillator clock selected as PLL3 clock entry
+ * @arg RCC_PLL3SOURCE_OFF: No clock send to DIVMx divider and PLL
+ * @retval None
+ */
+#define __HAL_RCC_PLL3_SOURCE(__RCC_PLL3SOURCE__ ) \
+ do{ MODIFY_REG( RCC->RCK3SELR, RCC_RCK3SELR_PLL3SRC, __RCC_PLL3SOURCE__ ); \
+ } while(0)
+
+/** @brief Macro to get the clock source used as PLL3 clock.
+ * @retval The clock source used as PLL3 clock. The returned value can be one
+ * of the following:
+ * - RCC_PLL3SOURCE_HSI: HSI used as PLL3 clock.
+ * - RCC_PLL3SOURCE_HSE: HSE used as PLL3 clock.
+ * - RCC_PLL3SOURCE_CSI: CSI used as PLL3 clock.
+ * - RCC_PLL3SOURCE_OFF: PLL3 clock is gated.
+ */
+#define __HAL_RCC_GET_PLL3_SOURCE() ((uint32_t)(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC))
+
+/**
+ * @brief Macro to configure PLL3 multiplication and division factors.
+ * @note This function must be used only when the PLL3 is disabled.
+ *
+ * @param __PLLM3__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 1 and 64
+ * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input
+ * frequency ranges from 4 to 16 MHz
+ * @param __PLLN3__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 25 and 200
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 400 to 800 MHz
+ * @param __PLLP3__: specifies the division factor for the PLL3 P output
+ * This parameter must be a number in the range 1 to 128
+ * @param __PLLQ3__: specifies the division factor for for the PLL3 Q output
+ * This parameter must be in the range 1 to 128
+ * @param __PLLR3__: specifies the division factor for for the PLL3 R output
+ * This parameter must be in the range 1 to 128
+ * @retval None
+ */
+#define __HAL_RCC_PLL3_CONFIG(__PLLM3__, __PLLN3__, __PLLP3__, __PLLQ3__,__PLLR3__ ) \
+ do{ MODIFY_REG( RCC->PLL3CFGR1, (RCC_PLL3CFGR1_DIVN | RCC_PLL3CFGR1_DIVM3) , \
+ ( (__PLLN3__ - 1U) | ( (__PLLM3__ - 1U) << 16U) ) ); \
+ MODIFY_REG( RCC->PLL3CFGR2, (RCC_PLL3CFGR2_DIVP | RCC_PLL3CFGR2_DIVQ | RCC_PLL3CFGR2_DIVR), \
+ ( (__PLLP3__ - 1U) | ( (__PLLQ3__ - 1U) <<8U ) | ( (__PLLR3__ - 1U) <<16U) )); \
+ } while(0)
+
+/**
+ * @brief Macro to configure the PLL3 clock Fractional Part Of The Multiplication Factor
+ *
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
+ *
+ * @param __RCC_PLL3FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL3 VCO
+ * It should be a value between 0 and 8191 ((2^13)-1)
+ * @note Warning: the software has to set correctly these bits to insure that the VCO
+ * output frequency is between its valid frequency range, which is: 400 to 800 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL3FRACV_CONFIG(__RCC_PLL3FRACV__) \
+ MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACV, \
+ (uint32_t)(__RCC_PLL3FRACV__) << RCC_PLL3FRACR_FRACV_Pos)
+
+
+/** @brief Macro to select the PLL3 input frequency range.
+ * @param __RCC_PLL3IFRange__: specifies the PLL3 input frequency range
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL3IFRANGE_0: Range frequency is between 4 and 8 MHz (default after reset)
+ * @arg RCC_PLL3IFRANGE_1: Range frequency is between 8 and 16 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL3_IFRANGE(__RCC_PLL3IFRange__) \
+ MODIFY_REG(RCC->PLL3CFGR1, RCC_PLL3CFGR1_IFRGE, (__RCC_PLL3IFRange__))
+
+
+/** @brief Macros to enable or disable the PLL4.
+ * @note After enabling the main PLL, the application software should wait on
+ * PLLRDY flag to be set indicating that PLL clock is stable and can
+ * be used as system clock source.
+ * @note The PLL4 can not be disabled if it is used as MPU clock source
+ * @note The PLL4 is disabled by hardware when entering STOP and STANDBY modes.
+ */
+#define __HAL_RCC_PLL4_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON )
+#define __HAL_RCC_PLL4_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON)
+
+/**
+ * @brief Enables or disables each clock output
+ * @note Enabling/disabling Those Clocks outputs can be disabled anytime without the need to stop the PLL,
+ * with the exception of ck_pll_p cannot be stopped if used as MPU Clock
+ * @param __RCC_PLL4ClockOut__: specifies the PLL clock to be outputed
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL4_DIVP
+ * @arg RCC_PLL4_DIVQ
+ * @arg RCC_PLL4_DIVR
+ * @retval None
+ */
+#define __HAL_RCC_PLL4CLKOUT_ENABLE(__RCC_PLL4ClockOut__) SET_BIT(RCC->PLL4CR, __RCC_PLL4ClockOut__ )
+
+#define __HAL_RCC_PLL4CLKOUT_DISABLE(__RCC_PLL4ClockOut__) CLEAR_BIT(RCC->PLL4CR, __RCC_PLL4ClockOut__ )
+
+
+/**
+ * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL4 VCO
+ * @note Enabling/disabling Fractional Part can be done anytime without the need to stop the PLL4
+ * @retval None
+ */
+
+#define __HAL_RCC_PLL4FRACV_ENABLE() SET_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE)
+
+#define __HAL_RCC_PLL4FRACV_DISABLE() CLEAR_BIT(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACLE)
+
+
+/** @brief Macros to enable or disable the Spread Spectrum Clock Generator of PLL4
+ */
+#define __HAL_RCC_PLL4_SSMODE_ENABLE() SET_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL)
+
+#define __HAL_RCC_PLL4_SSMODE_DISABLE() CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL)
+
+
+/** @brief Macro to config the PLL4 Clock Spreading Generator
+ * @param __RCC_PLL4_MOD_PER__: Modulation Period Adjustment for PLL4
+ * This parameter must have a value between 1 and 8191
+ *
+ * @param __RCC_PLL4_TPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_TPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_TPDFN_DIS_DISABLED: Dithering noise injection disabled
+
+ * @param __RCC_PLL4_RPDFN_DIS__: Dithering TPDF noise control
+ * This parameter can be one of the following values:
+ * @arg RCC_RPDFN_DIS_ENABLED: Dithering noise injection enabled (default after reset)
+ * @arg RCC_RPDFN_DIS_DISABLED: Dithering noise injection disabled
+ *
+ *
+ * @param __RCC_PLL4_SSCG_MODE__: Spread spectrum clock generator mode
+ * This parameter can be one of the following values:
+ * @arg RCC_SSCG_CENTER_SPREAD: Center-spread modulation selected (default after reset)
+ * @arg RCC_SSCG_DOWN_SPREAD: Down-spread modulation selected
+ *
+ * @param __RCC_PLL4_INC_STEP__: Modulation Depth Adjustment for PLL4
+ * This parameter must have a value between 1 and 32767
+ *
+ * @note MOD_PER x INC_STEP shall not exceed (2^15)-1
+ * @retval None
+ */
+#define __HAL_RCC_PLL4CSGCONFIG(__RCC_PLL4_MOD_PER__, __RCC_PLL4_TPDFN_DIS__, __RCC_PLL4_RPDFN_DIS__, \
+ __RCC_PLL4_SSCG_MODE__, __RCC_PLL4_INC_STEP__ ) \
+ do{ MODIFY_REG( RCC->PLL4CSGR, (RCC_PLL4CSGR_MOD_PER | RCC_PLL4CSGR_TPDFN_DIS | RCC_PLL4CSGR_RPDFN_DIS | \
+ RCC_PLL4CSGR_SSCG_MODE | RCC_PLL4CSGR_INC_STEP) , \
+ (__RCC_PLL4_MOD_PER__ | __RCC_PLL4_TPDFN_DIS__ | __RCC_PLL4_RPDFN_DIS__ | \
+ __RCC_PLL4_SSCG_MODE__ | (__RCC_PLL4_INC_STEP__ << RCC_PLL4CSGR_INC_STEP_Pos)) ) ; \
+ } while(0)
+
+
+/**
+ * @brief Macro to configure PLL4 clock source
+ * @note This function must be used only when the PLL is disabled.
+ *
+ * @param __RCC_PLL4SOURCE__: specifies the PLL4 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL4SOURCE_HSI: HSI oscillator clock selected as PLL4 clock entry
+ * @arg RCC_PLL4SOURCE_HSE: HSE oscillator clock selected as PLL4 clock entry
+ * @arg RCC_PLL4SOURCE_CSI: HSE oscillator clock selected as PLL4 clock entry
+ * @arg RCC_PLL4SOURCE_I2S_CKIN: Signal I2S_CKIN used as reference clock
+ * @retval None
+ */
+#define __HAL_RCC_PLL4_SOURCE(__RCC_PLL4SOURCE__ ) \
+ do{ MODIFY_REG( RCC->RCK4SELR, RCC_RCK4SELR_PLL4SRC, __RCC_PLL4SOURCE__ ); \
+ } while(0)
+
+/** @brief Macro to get the clock source used as PLL4 clock.
+ * @retval The clock source used as PLL4 clock. The returned value can be one
+ * of the following:
+ * - RCC_PLL4SOURCE_HSI: HSI used as PLL4 clock.
+ * - RCC_PLL4SOURCE_HSE: HSE used as PLL4 clock.
+ * - RCC_PLL4SOURCE_CSI: CSI used as PLL4 clock.
+ * - RCC_PLL4SOURCE_I2S_CKIN: I2S_CKIN used as PLL4 clock.
+ */
+#define __HAL_RCC_GET_PLL4_SOURCE() ((uint32_t)(RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRC))
+
+
+/**
+ * @brief Macro to configure PLL4 multiplication and division factors.
+ * @note This function must be used only when the PLL4 is disabled.
+ *
+ * @param __PLLM4__: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 1 and 64
+ * @note You have to set the PLLM1 parameter correctly to ensure that the VCO input
+ * frequency ranges from 4 to 16 MHz
+ * @param __PLLN4__: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 25 and 200
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 400 to 800 MHz
+ * @param __PLLP4__: specifies the division factor for the PLL4 P output
+ * This parameter must be a number in the range 1 to 128
+ * @param __PLLQ4__: specifies the division factor for for the PLL4 Q output
+ * This parameter must be in the range 1 to 128
+ * @param __PLLR4__: specifies the division factor for for the PLL4 R output
+ * This parameter must be in the range 1 to 128
+ * @retval None
+ */
+#define __HAL_RCC_PLL4_CONFIG(__PLLM4__, __PLLN4__, __PLLP4__, __PLLQ4__,__PLLR4__ ) \
+ do{ MODIFY_REG( RCC->PLL4CFGR1, (RCC_PLL4CFGR1_DIVN | RCC_PLL4CFGR1_DIVM4) , \
+ ( (__PLLN4__ - 1U) | ( (__PLLM4__ - 1U) << 16U) ) ); \
+ MODIFY_REG( RCC->PLL4CFGR2, (RCC_PLL4CFGR2_DIVP | RCC_PLL4CFGR2_DIVQ | RCC_PLL4CFGR2_DIVR), \
+ ( (__PLLP4__ - 1U) | ( (__PLLQ4__ - 1U) <<8U ) | ( (__PLLR4__ - 1U) <<16U) )); \
+ } while(0)
+
+
+/**
+ * @brief Macro to configure the PLL4 clock Fractional Part Of The Multiplication Factor
+ *
+ * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL4 VCO
+ *
+ * @param __RCC_PLL4FRACV__: specifies Fractional Part Of The Multiplication Factorfor PLL4 VCO
+ * It should be a value between 0 and 8191 ((2^13)-1)
+ * @note Warning: the software has to set correctly these bits to insure that the VCO
+ * output frequency is between its valid frequency range, which is: 400 to 800 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL4FRACV_CONFIG(__RCC_PLL4FRACV__) \
+ MODIFY_REG(RCC->PLL4FRACR, RCC_PLL4FRACR_FRACV, \
+ (uint32_t)(__RCC_PLL4FRACV__) << RCC_PLL4FRACR_FRACV_Pos)
+
+
+/** @brief Macro to select the PLL4 input frequency range.
+ * @param __RCC_PLL4IFRange__: specifies the PLL4 input frequency range
+ * This parameter can be one of the following values:
+ * @arg RCC_PLL4IFRANGE_0: Range frequency is between 4 and 8 MHz (default after reset)
+ * @arg RCC_PLL4IFRANGE_1: Range frequency is between 8 and 16 MHz
+ * @retval None
+ */
+#define __HAL_RCC_PLL4_IFRANGE(__RCC_PLL4IFRange__) \
+ MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE, (__RCC_PLL4IFRange__))
+
+
+/** @brief Macros to enable or disable the MCO1 output.
+ *
+ */
+#define __HAL_RCC_MCO1_ENABLE() SET_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON)
+#define __HAL_RCC_MCO1_DISABLE() CLEAR_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON)
+
+/**
+ * @brief Macro to configure MCO1 prescaler
+ * @note Set and cleared by software to configure the prescaler of the MCO1.
+ * @note Modification of this prescaler may generate glitches on MCO1.
+ * @note It is highly recommended to change this prescaler only after reset,
+ * before enabling the external oscillators and the PLLs.
+ *
+ * @param __RCC_MCO1SOURCE__: specifies the MCO1 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 clock entry (default after reset)
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 clock entry
+ * @arg RCC_MCO1SOURCE_CSI: CSI clock selected as MCO1 clock entry
+ * @arg RCC_MCO1SOURCE_LSI: LSI clock selected as MCO1 clock entry
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 clock entry
+ *
+ * @param __RCC_MCO1PRESCALER__: specifies the MCO1 prescaler value.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: bypass (default after reset)
+ * @arg RCC_MCODIV_2: division by 2
+ * @arg RCC_MCODIV_3: division by 3
+ * @arg RCC_MCODIV_4: division by 4
+ * @arg RCC_MCODIV_5: division by 5
+ * @arg RCC_MCODIV_6: division by 6
+ * @arg RCC_MCODIV_7: division by 7
+ * @arg RCC_MCODIV_8: division by 8
+ * @arg RCC_MCODIV_9: division by 9
+ * @arg RCC_MCODIV_10: division by 10
+ * @arg RCC_MCODIV_11: division by 11
+ * @arg RCC_MCODIV_12: division by 12
+ * @arg RCC_MCODIV_13: division by 13
+ * @arg RCC_MCODIV_14: division by 14
+ * @arg RCC_MCODIV_15: division by 15
+ * @arg RCC_MCODIV_16: division by 16
+ * @retval None
+ */
+#define __HAL_RCC_MCO1_CONFIGURE(__RCC_MCO1SOURCE__ , __RCC_MCO1PRESCALER__ ) \
+ do{ MODIFY_REG( RCC->MCO1CFGR, (RCC_MCO1CFGR_MCO1SEL | RCC_MCO1CFGR_MCO1DIV) , \
+ (__RCC_MCO1SOURCE__ | __RCC_MCO1PRESCALER__) );\
+ } while(0)
+
+
+/** @brief Macro to get the clock source used as MCO1 clock.
+ * @retval The clock source used as MCO1 clock. The returned value can be one
+ * of the following:
+ * - RCC_MCO1SOURCE_HSI: HSI used as MCO1 clock (default after reset).
+ * - RCC_MCO1SOURCE_HSE: HSE used as MCO1 clock.
+ * - RCC_MCO1SOURCE_CSI: CSI used as MCO1 clock.
+ * - RCC_MCO1SOURCE_LSI: LSI used as MCO1 clock.
+ * - RCC_MCO1SOURCE_LSE: LSE used as MCO1 clock.
+ */
+#define __HAL_RCC_GET_MCO1_SOURCE() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1SEL))
+
+/** @brief Macro to get the MCO1 prescaler value
+ * @retval The MCO1 prescaler value. The returned value can be one
+ * of the following:
+ * - RCC_MCODIV_1: bypass (default after reset)
+ * - RCC_MCODIV_2: division by 2
+ * - RCC_MCODIV_3: division by 3
+ * - RCC_MCODIV_4: division by 4
+ * - RCC_MCODIV_5: division by 5
+ * - RCC_MCODIV_6: division by 6
+ * - RCC_MCODIV_7: division by 7
+ * - RCC_MCODIV_8: division by 8
+ * - RCC_MCODIV_9: division by 9
+ * - RCC_MCODIV_10: division by 10
+ * - RCC_MCODIV_11: division by 11
+ * - RCC_MCODIV_12: division by 12
+ * - RCC_MCODIV_13: division by 13
+ * - RCC_MCODIV_14: division by 14
+ * - RCC_MCODIV_15: division by 15
+ * - RCC_MCODIV_16: division by 16
+ */
+#define __HAL_RCC_GET_MCO1_DIV() ((uint32_t)(RCC->MCO1CFGR & RCC_MCO1CFGR_MCO1DIV))
+
+
+/** @brief Macros to enable or disable the MCO2 output.
+ *
+ */
+#define __HAL_RCC_MCO2_ENABLE() SET_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON)
+#define __HAL_RCC_MCO2_DISABLE() CLEAR_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON)
+
+/**
+ * @brief Macro to configure MCO2 prescaler
+ * @note Set and cleared by software to configure the prescaler of the MCO2.
+ * @note Modification of this prescaler may generate glitches on MCO2.
+ * @note It is highly recommended to change this prescaler only after reset,
+ * before enabling the external oscillators and the PLLs.
+ *
+ * @param __RCC_MCO2SOURCE__: specifies the MCO2 entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO2SOURCE_MPU: MPU clock selected as MCO2 clock entry (default after reset)
+ * @arg RCC_MCO2SOURCE_AXI: AXI clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_MCU: MCU clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_PLL4: PLL4 clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_HSI: HSI clock selected as MCO2 clock entry
+ *
+ * @param __RCC_MCO2PRESCALER__: specifies the MCO2 prescaler value.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1: bypass (default after reset)
+ * @arg RCC_MCODIV_2: division by 2
+ * @arg RCC_MCODIV_3: division by 3
+ * @arg RCC_MCODIV_4: division by 4
+ * @arg RCC_MCODIV_5: division by 5
+ * @arg RCC_MCODIV_6: division by 6
+ * @arg RCC_MCODIV_7: division by 7
+ * @arg RCC_MCODIV_8: division by 8
+ * @arg RCC_MCODIV_9: division by 9
+ * @arg RCC_MCODIV_10: division by 10
+ * @arg RCC_MCODIV_11: division by 11
+ * @arg RCC_MCODIV_12: division by 12
+ * @arg RCC_MCODIV_13: division by 13
+ * @arg RCC_MCODIV_14: division by 14
+ * @arg RCC_MCODIV_15: division by 15
+ * @arg RCC_MCODIV_16: division by 16
+ * @retval None
+ */
+#define __HAL_RCC_MCO2_CONFIGURE(__RCC_MCO2SOURCE__ , __RCC_MCO2PRESCALER__ ) \
+ do{ MODIFY_REG( RCC->MCO2CFGR, (RCC_MCO2CFGR_MCO2SEL | RCC_MCO2CFGR_MCO2DIV) , \
+ (__RCC_MCO2SOURCE__ | __RCC_MCO2PRESCALER__) );\
+ } while(0)
+
+
+/** @brief Macro to get the clock source used as MCO2 clock.
+ * @retval The clock source used as MCO2 clock. The returned value can be one
+ * of the following:
+ * - RCC_MCO2SOURCE_MPU: MPU used as MCO2 clock (default after reset).
+ * - RCC_MCO2SOURCE_AXI: AXI used as MCO2 clock.
+ * - RCC_MCO2SOURCE_MCU: MCU used as MCO2 clock.
+ * - RCC_MCO2SOURCE_PLL4: PLL4 used as MCO2 clock.
+ * - RCC_MCO2SOURCE_HSE: HSE used as MCO2 clock.
+ * - RCC_MCO2SOURCE_HSI: HSI used as MCO2 clock.
+ */
+#define __HAL_RCC_GET_MCO2_SOURCE() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2SEL))
+
+/** @brief Macro to get the MCO2 prescaler value
+ * @retval The MCO2 prescaler value. The returned value can be one
+ * of the following:
+ * - RCC_MCODIV_1: bypass (default after reset)
+ * - RCC_MCODIV_2: division by 2
+ * - RCC_MCODIV_3: division by 3
+ * - RCC_MCODIV_4: division by 4
+ * - RCC_MCODIV_5: division by 5
+ * - RCC_MCODIV_6: division by 6
+ * - RCC_MCODIV_7: division by 7
+ * - RCC_MCODIV_8: division by 8
+ * - RCC_MCODIV_9: division by 9
+ * - RCC_MCODIV_10: division by 10
+ * - RCC_MCODIV_11: division by 11
+ * - RCC_MCODIV_12: division by 12
+ * - RCC_MCODIV_13: division by 13
+ * - RCC_MCODIV_14: division by 14
+ * - RCC_MCODIV_15: division by 15
+ * - RCC_MCODIV_16: division by 16
+ */
+#define __HAL_RCC_GET_MCO2_DIV() ((uint32_t)(RCC->MCO2CFGR & RCC_MCO2CFGR_MCO2DIV))
+
+
+/**
+ * @brief Macro to configure MPU sub-system clock source
+ * @note Set and reset by software to select the MPU sub-system clock source (ck_mpuss)
+ * @note If TZEN = 1, it is only possible to modify this parameter in secure mode
+ * @note Write access is not allowed during the clock restore sequence
+ *
+ * @param __RCC_MPUSOURCE__: specifies the MPU entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MPUSOURCE_HSI: HSI used as MPU clock (default after reset).
+ * @arg RCC_MPUSOURCE_HSE: HSE used as MPU clock.
+ * @arg RCC_MPUSOURCE_PLL1: PLL1 used as MPU clock.
+ * @arg RCC_MPUSOURCE_MPUDIV: MPUDIV used as MPU clock.
+ */
+#define __HAL_RCC_MPU_SOURCE(__RCC_MPUSOURCE__) \
+ do{ MODIFY_REG( RCC->MPCKSELR, RCC_MPCKSELR_MPUSRC , __RCC_MPUSOURCE__ );\
+ } while(0)
+
+/** @brief Macro to get the clock source used as MPU clock.
+ * @retval The clock source used as MPU clock. The returned value can be one
+ * of the following:
+ * - RCC_MPUSOURCE_HSI: HSI used as MPU clock (default after reset).
+ * - RCC_MPUSOURCE_HSE: HSE used as MPU clock.
+ * - RCC_MPUSOURCE_PLL1: PLL1 used as MPU clock.
+ * - RCC_MPUSOURCE_MPUDIV: MPU used as MPU clock.
+ */
+#define __HAL_RCC_GET_MPU_SOURCE() ((uint32_t)(RCC->MPCKSELR & RCC_MPCKSELR_MPUSRC))
+
+
+/**
+ * @brief Macro to configure AXISS clock source
+ * @note Set and reset by software to select the AXI sub-system clock source (ck_axiss)
+ * @note If TZEN = 1, it is only possible to modify this parameter in secure mode
+ * @note Write access is not allowed during the clock restore sequence
+ *
+ * @param __RCC_AXISSOURCE__: specifies the AXISS entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_AXISSOURCE_HSI: HSI used as AXISS clock (default after reset).
+ * @arg RCC_AXISSOURCE_HSE: HSE used as AXISS clock.
+ * @arg RCC_AXISSOURCE_PLL2: PLL2 used as AXISS clock.
+ * @arg RCC_AXISSOURCE_OFF: AXISS clock is gated.
+ */
+#define __HAL_RCC_AXISS_SOURCE(__RCC_AXISSOURCE__) \
+ do{ MODIFY_REG( RCC->ASSCKSELR, RCC_ASSCKSELR_AXISSRC , __RCC_AXISSOURCE__ );\
+ } while(0)
+
+/** @brief Macro to get the clock source used as AXIS clock.
+ * @retval The clock source used as AXIS clock. The returned value can be one
+ * of the following:
+ * - RCC_AXISSOURCE_HSI: HSI used as AXIS clock (default after reset).
+ * - RCC_AXISSOURCE_HSE: HSE used as AXIS clock.
+ * - RCC_AXISSOURCE_PLL2: PLL2 used as AXIS clock.
+ * - RCC_AXISSOURCE_OFF: AXIS clock is gated.
+ */
+#define __HAL_RCC_GET_AXIS_SOURCE() ((uint32_t)(RCC->ASSCKSELR & RCC_ASSCKSELR_AXISSRC))
+
+
+/**
+ * @brief Macro to configure MCU sub-system clock source
+ * @note Set and reset by software to select the mcu sub-system clock source (ck_mcuss)
+ * @note If TZEN = 1, it is only possible to modify this parameter in secure mode
+ * @note Write access is not allowed during the clock restore sequence
+ *
+ * @param __RCC_MCUSSOURCE__: specifies the MCU entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCUSSOURCE_HSI: HSI used as MCU clock (default after reset).
+ * @arg RCC_MCUSSOURCE_HSE: HSE used as MCU clock.
+ * @arg RCC_MCUSSOURCE_PLL3: PLL3 used as MCU clock.
+ */
+#define __HAL_RCC_MCU_SOURCE(__RCC_MCUSSOURCE__) \
+ do{ MODIFY_REG( RCC->MSSCKSELR, RCC_MSSCKSELR_MCUSSRC , __RCC_MCUSSOURCE__ );\
+ } while(0)
+
+/** @brief Macro to get the clock source used as MCU clock.
+ * @retval The clock source used as MCU clock. The returned value can be one
+ * of the following:
+ * - RCC_MCUSSOURCE_HSI: HSI used as MCU clock (default after reset).
+ * - RCC_MCUSSOURCE_HSE: HSE used as MCU clock.
+ * - RCC_MCUSSOURCE_CSI: CSI used as MCU clock.
+ * - RCC_MCUSSOURCE_PLL3: PLL3 used as MCU clock.
+ */
+#define __HAL_RCC_GET_MCU_SOURCE() ((uint32_t)(RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC))
+
+
+
+/**
+ * @brief Macro to set the HSE division factor for RTC clock
+ * @note Set and cleared by software to divide the HSE to generate a clock for RTC.
+ * @note If TZEN = 1, this parameter can only be modified in secure mode
+ * @note Caution: The software has to set these bits correctly to ensure that the clock supplied to the RTC is lower than 4 MHz.
+ * @note These bits must be configured if needed before selecting the RTC clock source
+ *
+ * @param __HSEDIV__: Specifies the HSE division factor for RTC clock
+ * This parameter must be a number between 1 and 64. Eg.:
+ * 1: HSE (default after reset)
+ * 2: HSE/2
+ * 64: HSE/64
+ * @retval None
+ */
+#define __HAL_RCC_RTC_HSEDIV(__HSEDIV__) \
+ do{ MODIFY_REG( RCC->RTCDIVR, RCC_RTCDIVR_RTCDIV , (__HSEDIV__ -1U )); \
+ } while(0)
+
+/** @brief Macro to get the HSE division factor for RTC clock.
+ * @retval The HSE division factor for RTC clock. The returned value can be a number between 1 and 64 Eg.:
+ * 1: HSE (default after reset)
+ * 2: HSE/2
+ * 64: HSE/64
+ */
+#define __HAL_RCC_GET_RTC_HSEDIV() ((uint32_t)((RCC->RTCDIVR & RCC_RTCDIVR_RTCDIV) + 1U ))
+
+/**
+ * @brief Macro to configure MPU Core clock divider
+ * @note Set and reset by software to control the MPU clock division factor.
+ * @note If TZEN = 1, this parameter can only be modified in secure mode.
+ * @note It is possible to change this division ratio on-the-fly. It impacts only the frequency of MPU clock.
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_mpuss cycles after MPUDIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the MPUDIVRDY flag
+ *
+ * @param __RCC_MPUDIV__: specifies the MPU division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_MPU_DIV_OFF: The MPUDIV is disabled (default after reset)
+ * @arg RCC_MPU_DIV2: ck_mpuss divided by 2
+ * @arg RCC_MPU_DIV4: ck_mpuss divided by 4
+ * @arg RCC_MPU_DIV8: ck_mpuss divided by 8
+ * @arg RCC_MPU_DIV16: ck_mpuss divided by 16
+ *
+ * @note Warning: Do not set RCC_MPU_DIV_OFF if the MPUSRC = RCC_MPUSOURCE_MPUDIV,
+ * otherwise the processor will no longer be clocked
+ */
+#define __HAL_RCC_MPU_DIV(__RCC_MPUDIV__) \
+ do{ MODIFY_REG( RCC->MPCKDIVR, RCC_MPCKDIVR_MPUDIV , __RCC_MPUDIV__ );\
+ } while(0)
+
+/** @brief Macro to get the MPU clock division factor.
+ * @retval The MPU clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_MPU_DIV_OFF: The MPUDIV is disabled (default after reset)
+ * - RCC_MPU_DIV2: ck_mpuss divided by 2
+ * - RCC_MPU_DIV4: ck_mpuss divided by 4
+ * - RCC_MPU_DIV8: ck_mpuss divided by 8
+ * - RCC_MPU_DIV16: ck_mpuss divided by 16
+ */
+#define __HAL_RCC_GET_MPU_DIV() ((uint32_t)(RCC->MPCKDIVR & RCC_MPCKDIVR_MPUDIV ))
+
+
+/**
+ * @brief Macro to configure AXI Core clock divider
+ * @note Set and reset by software to control the AXI, AHB5 and AHB6 clock division factor.
+ * @note If TZEN = 1, this parameter can only be modified in secure mode.
+ * @note It is possible to change this division ratio on-the-fly. It impacts the frequency
+ * of AXI, APB4, APB5 AHB5 and AHB6 clocks.
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_axiss cycles after AXIDIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the AXIDIVRDY flag
+ *
+ * @param __RCC_AXIDIV__: specifies the AXI division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_AXI_DIV1: ck_axiss not divided (default after reset)
+ * @arg RCC_AXI_DIV2: ck_axiss divided by 2
+ * @arg RCC_AXI_DIV3: ck_axiss divided by 3
+ * @arg RCC_AXI_DIV4: ck_axiss divided by 4
+ */
+#define __HAL_RCC_AXI_DIV(__RCC_AXIDIV__) \
+ do{ MODIFY_REG( RCC->AXIDIVR, RCC_AXIDIVR_AXIDIV , __RCC_AXIDIV__ );\
+ } while(0)
+
+/** @brief Macro to get the AXI, AHB5 and AHB6 clock division factor.
+ * @retval The AXI clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_AXI_DIV1: ck_axiss not divided (default after reset)
+ * - RCC_AXI_DIV2: ck_axiss divided by 2
+ * - RCC_AXI_DIV3: ck_axiss divided by 3
+ * - RCC_AXI_DIV4: ck_axiss divided by 4
+ */
+#define __HAL_RCC_GET_AXI_DIV() ((uint32_t)(RCC->AXIDIVR & RCC_AXIDIVR_AXIDIV ))
+
+
+/**
+ * @brief Macro to configure APB4 clock divider
+ * @note Set and reset by software to control the APB4 clock division factor.
+ * @note If TZEN = 1, this parameter can only be modified in secure mode.
+ * @note It is possible to change this division ratio on-the-fly. It impacts only the APB4 clock.
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_aclk cycles after APB4DIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the APB4DIVRDY flag
+ *
+ * @param __RCC_APB4DIV__: specifies the APB4 division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_APB4_DIV1: ck_aclk not divided (default after reset)
+ * @arg RCC_APB4_DIV2: ck_aclk divided by 2
+ * @arg RCC_APB4_DIV4: ck_aclk divided by 4
+ * @arg RCC_APB4_DIV8: ck_aclk divided by 8
+ * @arg RCC_APB4_DIV16: ck_aclk divided by 16
+ */
+#define __HAL_RCC_APB4_DIV(__RCC_APB4DIV__) \
+ do{ MODIFY_REG( RCC->APB4DIVR, RCC_APB4DIVR_APB4DIV , __RCC_APB4DIV__ );\
+ } while(0)
+
+/** @brief Macro to get the APB4 clock division factor.
+ * @retval The APB4 clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_APB4_DIV1: ck_aclk not divided (default after reset)
+ * - RCC_APB4_DIV2: ck_aclk divided by 2
+ * - RCC_APB4_DIV4: ck_aclk divided by 4
+ * - RCC_APB4_DIV8: ck_aclk divided by 8
+ * - RCC_APB4_DIV16: ck_aclk divided by 16
+ */
+#define __HAL_RCC_GET_APB4_DIV() ((uint32_t)(RCC->APB4DIVR & RCC_APB4DIVR_APB4DIV ))
+
+
+/**
+ * @brief Macro to configure APB5 clock divider
+ * @note Set and reset by software to control the APB5 clock division factor.
+ * @note If TZEN = 1, this parameter can only be modified in secure mode.
+ * @note It is possible to change this division ratio on-the-fly. It impacts only the APB5 clock.
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_aclk cycles after APB5DIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the APB5DIVRDY flag
+ *
+ * @param __RCC_APB5DIV__: specifies the APB5 division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_APB5_DIV1: ck_aclk not divided (default after reset)
+ * @arg RCC_APB5_DIV2: ck_aclk divided by 2
+ * @arg RCC_APB5_DIV4: ck_aclk divided by 4
+ * @arg RCC_APB5_DIV8: ck_aclk divided by 8
+ * @arg RCC_APB5_DIV16: ck_aclk divided by 16
+ */
+#define __HAL_RCC_APB5_DIV(__RCC_APB5DIV__) \
+ do{ MODIFY_REG( RCC->APB5DIVR, RCC_APB5DIVR_APB5DIV , __RCC_APB5DIV__ );\
+ } while(0)
+
+/** @brief Macro to get the APB5 clock division factor.
+ * @retval The APB5 clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_APB5_DIV1: ck_aclk not divided (default after reset)
+ * - RCC_APB5_DIV2: ck_aclk divided by 2
+ * - RCC_APB5_DIV4: ck_aclk divided by 4
+ * - RCC_APB5_DIV8: ck_aclk divided by 8
+ * - RCC_APB5_DIV16: ck_aclk divided by 16
+ */
+#define __HAL_RCC_GET_APB5_DIV() ((uint32_t)(RCC->APB5DIVR & RCC_APB5DIVR_APB5DIV ))
+
+
+/**
+ * @brief Macro to configure MCU clock divider
+ * @note Set and reset by software to control the MCU clock division factor.
+ * @note If TZEN = 1, this parameter can only be modified in secure mode.
+ * @note Changing this division ratio has an impact on the frequency of MCU clock, and all bus matrix clocks.
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_mcuss cycles after MCUDIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the MCUDIVRDY flag
+ *
+ * @param __RCC_MCUDIV__: specifies the MCU division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_MCU_DIV1: ck_mcuss not divided (default after reset)
+ * @arg RCC_MCU_DIV2: ck_mcuss divided by 2
+ * @arg RCC_MCU_DIV4: ck_mcuss divided by 4
+ * @arg RCC_MCU_DIV8: ck_mcuss divided by 8
+ * @arg RCC_MCU_DIV16: ck_mcuss divided by 16
+ * @arg RCC_MCU_DIV32: ck_mcuss divided by 32
+ * @arg RCC_MCU_DIV64: ck_mcuss divided by 64
+ * @arg RCC_MCU_DIV128: ck_mcuss divided by 128
+ * @arg RCC_MCU_DIV256: ck_mcuss divided by 256
+ * @arg RCC_MCU_DIV512: ck_mcuss divided by 512
+ */
+#define __HAL_RCC_MCU_DIV(__RCC_MCUDIV__) \
+ do{ MODIFY_REG( RCC->MCUDIVR, RCC_MCUDIVR_MCUDIV , __RCC_MCUDIV__ );\
+ } while(0)
+
+/** @brief Macro to get the MCU clock division factor.
+ * @retval The MCU clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_MCU_DIV1: ck_mcuss not divided (default after reset)
+ * - RCC_MCU_DIV2: ck_mcuss divided by 2
+ * - RCC_MCU_DIV4: ck_mcuss divided by 4
+ * - RCC_MCU_DIV8: ck_mcuss divided by 8
+ * - RCC_MCU_DIV16: ck_mcuss divided by 16
+ * - RCC_MCU_DIV32: ck_mcuss divided by 32
+ * - RCC_MCU_DIV64: ck_mcuss divided by 64
+ * - RCC_MCU_DIV128: ck_mcuss divided by 128
+ * - RCC_MCU_DIV256: ck_mcuss divided by 256
+ * - RCC_MCU_DIV512: ck_mcuss divided by 512
+ */
+#define __HAL_RCC_GET_MCU_DIV() ((uint32_t)(RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV ))
+
+/**
+ * @brief Macro to configure APB1 clock divider
+ * @note Set and reset by software to control the APB1 clock division factor.
+ * @note It is possible to change this division ratio on-the-fly. It impacts only the APB1 clock.
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB1DIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the APB1DIVRDY flag
+ *
+ * @param __RCC_APB1DIV__: specifies the APB1 division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_APB1_DIV1: ck_hclk not divided (default after reset)
+ * @arg RCC_APB1_DIV2: ck_hclk divided by 2
+ * @arg RCC_APB1_DIV4: ck_hclk divided by 4
+ * @arg RCC_APB1_DIV8: ck_hclk divided by 8
+ * @arg RCC_APB1_DIV16: ck_hclk divided by 16
+ */
+#define __HAL_RCC_APB1_DIV(__RCC_APB1DIV__) \
+ do{ MODIFY_REG( RCC->APB1DIVR, RCC_APB1DIVR_APB1DIV , __RCC_APB1DIV__ );\
+ } while(0)
+
+/** @brief Macro to get the APB1 clock division factor.
+ * @retval The APB1 clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_APB1_DIV1: ck_hclk not divided (default after reset)
+ * - RCC_APB1_DIV2: ck_hclk divided by 2
+ * - RCC_APB1_DIV4: ck_hclk divided by 4
+ * - RCC_APB1_DIV8: ck_hclk divided by 8
+ * - RCC_APB1_DIV16: ck_hclk divided by 16
+ */
+#define __HAL_RCC_GET_APB1_DIV() ((uint32_t)(RCC->APB1DIVR & RCC_APB1DIVR_APB1DIV ))
+
+
+/**
+ * @brief Macro to configure APB2 clock divider
+ * @note Set and reset by software to control the APB2 clock division factor.
+ * @note It is possible to change this division ratio on-the-fly. It impacts only the APB2 clock.
+
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB2DIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the APB2DIVRDY flag
+ *
+ * @param __RCC_APB2DIV__: specifies the APB2 division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_APB2_DIV1: ck_hclk not divided (default after reset)
+ * @arg RCC_APB2_DIV2: ck_hclk divided by 2
+ * @arg RCC_APB2_DIV4: ck_hclk divided by 4
+ * @arg RCC_APB2_DIV8: ck_hclk divided by 8
+ * @arg RCC_APB2_DIV16: ck_hclk divided by 16
+ */
+#define __HAL_RCC_APB2_DIV(__RCC_APB2DIV__) \
+ do{ MODIFY_REG( RCC->APB2DIVR, RCC_APB2DIVR_APB2DIV , __RCC_APB2DIV__ );\
+ } while(0)
+
+/** @brief Macro to get the APB2 clock division factor.
+ * @retval The APB2 clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_APB2_DIV1: ck_hclk not divided (default after reset)
+ * - RCC_APB2_DIV2: ck_hclk divided by 2
+ * - RCC_APB2_DIV4: ck_hclk divided by 4
+ * - RCC_APB2_DIV8: ck_hclk divided by 8
+ * - RCC_APB2_DIV16: ck_hclk divided by 16
+ */
+#define __HAL_RCC_GET_APB2_DIV() ((uint32_t)(RCC->APB2DIVR & RCC_APB2DIVR_APB2DIV ))
+
+
+/**
+ * @brief Macro to configure APB3 clock divider
+ * @note Set and reset by software to control the APB3 clock division factor.
+ * @note It is possible to change this division ratio on-the-fly. It impacts only the APB3 clock.
+
+ * @note The clocks are divided with the new prescaler factor, from 1 to 16 ck_hclk cycles after APB3DIV update.
+ * @note The application can check if the new division factor is taken into account by reading back the APB3DIVRDY flag
+ *
+ * @param __RCC_APB3DIV__: specifies the APB3 division factor
+ * This parameter can be one of the following values:
+ * @arg RCC_APB3_DIV1: ck_hclk not divided (default after reset)
+ * @arg RCC_APB3_DIV2: ck_hclk divided by 2
+ * @arg RCC_APB3_DIV4: ck_hclk divided by 4
+ * @arg RCC_APB3_DIV8: ck_hclk divided by 8
+ * @arg RCC_APB3_DIV16: ck_hclk divided by 16
+ */
+#define __HAL_RCC_APB3_DIV(__RCC_APB3DIV__) \
+ do{ MODIFY_REG( RCC->APB3DIVR, RCC_APB3DIVR_APB3DIV , __RCC_APB3DIV__ );\
+ } while(0)
+
+/** @brief Macro to get the APB3 clock division factor.
+ * @retval The APB3 clock division factor. The returned value can be one
+ * of the following:
+ * - RCC_APB3_DIV1: ck_hclk not divided (default after reset)
+ * - RCC_APB3_DIV2: ck_hclk divided by 2
+ * - RCC_APB3_DIV4: ck_hclk divided by 4
+ * - RCC_APB3_DIV8: ck_hclk divided by 8
+ * - RCC_APB3_DIV16: ck_hclk divided by 16
+ */
+#define __HAL_RCC_GET_APB3_DIV() ((uint32_t)(RCC->APB3DIVR & RCC_APB3DIVR_APB3DIV ))
+
+
+/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR bits to enable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_CSIRDY: CSI ready interrupt
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt
+ * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt
+ * @arg RCC_IT_LSECSS: LSE Clock security system interrupt
+ * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt
+ * @arg RCC_IT_ALL: All RCC interrupts
+ */
+#ifdef CORE_CM4
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MC_CIER, (__INTERRUPT__))
+#endif /* CORE_CM4 */
+#ifdef CORE_CA7
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->MP_CIER, (__INTERRUPT__))
+#endif /* CORE_CA7 */
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+ * the selected interrupts).
+ * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_CSIRDY: CSI ready interrupt
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt
+ * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt
+ * @arg RCC_IT_LSECSS: LSE Clock security system interrupt
+ * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt
+ * @arg RCC_IT_ALL: All RCC interrupts
+ */
+#ifdef CORE_CM4
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MC_CIER, (__INTERRUPT__))
+#endif /* CORE_CM4 */
+#ifdef CORE_CA7
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->MP_CIER, (__INTERRUPT__))
+#endif /* CORE_CA7 */
+
+
+/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+ * bits to clear the selected interrupt pending bits.
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_CSIRDY: CSI ready interrupt
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt
+ * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt
+ * @arg RCC_IT_LSECSS: LSE Clock security system interrupt
+ * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt
+ * @arg RCC_IT_ALL: All RCC interrupts
+ */
+#ifdef CORE_CM4
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MC_CIFR = (__INTERRUPT__))
+#endif /* CORE_CM4 */
+#ifdef CORE_CA7
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->MP_CIFR = (__INTERRUPT__))
+#endif /* CORE_CA7 */
+
+/** @brief Check the RCC's interrupt has occurred or not.
+ * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_CSIRDY: CSI ready interrupt
+ * @arg RCC_IT_PLLRDY: Main PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2RDY ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3RDY ready interrupt
+ * @arg RCC_IT_PLL4RDY: PLL4RDY ready interrupt
+ * @arg RCC_IT_LSECSS: LSE Clock security system interrupt
+ * @arg RCC_IT_WKUP: Wake-up from CSTOP Interrupt
+ * @arg RCC_IT_ALL: All RCC interrupts
+ * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ */
+#ifdef CORE_CM4
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MC_CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#endif /* CORE_CM4 */
+#ifdef CORE_CA7
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->MP_CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#endif /* CORE_CA7 */
+/**
+ * @}
+ */
+/* Include RCC HAL Extension module */
+#include "stm32mp1xx_hal_rcc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_HSEConfig(uint32_t State);
+HAL_StatusTypeDef HAL_RCC_LSEConfig(uint32_t State);
+
+HAL_StatusTypeDef RCC_PLL1_Config(RCC_PLLInitTypeDef *pll1);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct);
+HAL_StatusTypeDef HAL_RCC_LSEDriveConfig(uint32_t LseDriveValue);
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+void HAL_RCC_WAKEUP_IRQHandler(void);
+void HAL_RCC_WAKEUP_Callback(void);
+void HAL_RCC_IRQHandler(void);
+void HAL_RCC_Callback(uint32_t Flags);
+void HAL_RCC_EnableHSECSS(void);
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
+/* Peripheral Control functions ************************************************/
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+/* Get frequency functions *****************************************************/
+void HAL_RCC_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks);
+void HAL_RCC_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks);
+void HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks);
+void HAL_RCC_GetPLL4ClockFreq(PLL4_ClocksTypeDef *PLL4_Clocks);
+
+uint32_t HAL_RCC_GetMPUSSFreq(void);
+uint32_t HAL_RCC_GetAXISSFreq(void);
+uint32_t HAL_RCC_GetMCUSSFreq(void);
+uint32_t HAL_RCC_GetACLKFreq(void);
+uint32_t HAL_RCC_GetHCLK1Freq(void);
+uint32_t HAL_RCC_GetHCLK2Freq(void);
+uint32_t HAL_RCC_GetHCLK3Freq(void);
+uint32_t HAL_RCC_GetHCLK4Freq(void);
+uint32_t HAL_RCC_GetHCLK5Freq(void);
+uint32_t HAL_RCC_GetHCLK6Freq(void);
+uint32_t HAL_RCC_GetMCUFreq(void);
+uint32_t HAL_RCC_GetFCLKFreq(void);
+uint32_t HAL_RCC_GetMLHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+uint32_t HAL_RCC_GetPCLK3Freq(void);
+uint32_t HAL_RCC_GetPCLK4Freq(void);
+uint32_t HAL_RCC_GetPCLK5Freq(void);
+
+uint32_t HAL_RCC_GetSystemCoreClockFreq(void);
+
+uint32_t RCC_GetCKPERFreq(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+ * @{
+ */
+
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE (100U) /* 100 ms */
+#define CSI_TIMEOUT_VALUE (100U) /* 100 ms */
+#define LSI_TIMEOUT_VALUE (100U) /* 100 ms */
+#define PLL_TIMEOUT_VALUE (100U) /* 100 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE (1000U) /* 1 s */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Macros RCC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h
new file mode 100644
index 0000000..2895578
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h
@@ -0,0 +1,2028 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_rcc_ex.h
+ * @author MCD Application Team
+ * @brief Header file of RCC HAL Extension module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_RCC_EX_H
+#define __STM32MP1xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup RCCEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+/**
+ * @brief RCC extended clocks structure definition
+ */
+typedef struct
+{
+ uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+ This parameter can be a value of @ref
+ RCCEx_Periph_Clock_Selection */
+
+ RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters.
+ This parameter will be used only when
+ PLL2 is selected as Clock Source */
+
+ RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters.
+ This parameter will be used only when
+ PLL3 is selected as Clock Source */
+
+ RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters.
+ This parameter will be used only when
+ PLL3 is selected as Clock Source */
+
+ uint32_t I2c12ClockSelection; /*!< Specifies I2C12 clock source
+ This parameter can be a value of
+ @ref RCCEx_I2C12_Clock_Source */
+
+ uint32_t I2c35ClockSelection; /*!< Specifies I2C35 clock source
+ This parameter can be a value of
+ @ref RCCEx_I2C35_Clock_Source */
+
+ uint32_t I2c46ClockSelection; /*!< Specifies I2C46 clock source
+ This parameter can be a value of
+ @ref RCCEx_I2C46_Clock_Source */
+
+ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source
+ This parameter can be a value of @ref
+ RCCEx_SAI1_Clock_Source */
+
+ uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source
+ This parameter can be a value of @ref
+ RCCEx_SAI2_Clock_Source */
+
+ uint32_t Sai3ClockSelection; /*!< Specifies SAI3 clock source
+ This parameter can be a value of @ref
+ RCCEx_SAI3_Clock_Source */
+
+ uint32_t Sai4ClockSelection; /*!< Specifies SAI4 clock source
+ This parameter can be a value of @ref
+ RCCEx_SAI4_Clock_Source */
+
+ uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source
+ This parameter can be a value of @ref
+ RCCEx_SPI1_Clock_Source */
+
+ uint32_t Spi23ClockSelection; /*!< Specifies SPI23 clock source
+ This parameter can be a value of @ref
+ RCCEx_SPI23_Clock_Source */
+
+ uint32_t Spi45ClockSelection; /*!< Specifies SPI45 clock source
+ This parameter can be a value of @ref
+ RCCEx_SPI45_Clock_Source */
+
+ uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source
+ This parameter can be a value of @ref
+ RCCEx_SPI6_Clock_Source */
+
+ uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source
+ This parameter can be a value of @ref
+ RCCEx_USART1_Clock_Source */
+
+ uint32_t Uart24ClockSelection; /*!< Specifies UART24 clock source
+ This parameter can be a value of @ref
+ RCCEx_UART24_Clock_Source */
+
+ uint32_t Uart35ClockSelection; /*!< Specifies UART35 clock source
+ This parameter can be a value of @ref
+ RCCEx_UART35_Clock_Source */
+
+ uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source
+ This parameter can be a value of @ref
+ RCCEx_USART6_Clock_Source */
+
+ uint32_t Uart78ClockSelection; /*!< Specifies UART78 clock source
+ This parameter can be a value of @ref
+ RCCEx_UART78_Clock_Source */
+
+ uint32_t Sdmmc12ClockSelection; /*!< Specifies SDMMC12 clock source
+ This parameter can be a value of @ref
+ RCCEx_SDMMC12_Clock_Source */
+
+ uint32_t Sdmmc3ClockSelection; /*!< Specifies SDMMC3 clock source
+ This parameter can be a value of @ref
+ RCCEx_SDMMC3_Clock_Source */
+
+ uint32_t EthClockSelection; /*!< Specifies ETH clock source
+ This parameter can be a value of @ref
+ RCCEx_ETH_Clock_Source */
+
+ uint32_t FmcClockSelection; /*!< Specifies FMC clock source
+ This parameter can be a value of @ref
+ RCCEx_FMC_Clock_Source */
+
+ uint32_t QspiClockSelection; /*!< Specifies QSPI clock source
+ This parameter can be a value of @ref
+ RCCEx_QSPI_Clock_Source */
+
+ uint32_t DsiClockSelection; /*!< Specifies DSI clock source
+ This parameter can be a value of @ref
+ RCCEx_DSI_Clock_Source */
+
+ uint32_t CkperClockSelection; /*!< Specifies CKPER clock source
+ This parameter can be a value of @ref
+ RCCEx_CKPER_Clock_Source */
+
+ uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source
+ This parameter can be a value of @ref
+ RCCEx_SPDIFRX_Clock_Source */
+
+ uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source
+ This parameter can be a value of @ref
+ RCCEx_FDCAN_Clock_Source */
+
+ uint32_t Rng1ClockSelection; /*!< Specifies RNG1 clock source
+ This parameter can be a value of @ref
+ RCCEx_RNG1_Clock_Source */
+
+ uint32_t Rng2ClockSelection; /*!< Specifies RNG2 clock source
+ This parameter can be a value of @ref
+ RCCEx_RNG2_Clock_Source */
+
+ uint32_t StgenClockSelection; /*!< Specifies STGEN clock source
+ This parameter can be a value of @ref
+ RCCEx_STGEN_Clock_Source */
+
+ uint32_t UsbphyClockSelection; /*!< Specifies USB PHY clock source
+ This parameter can be a value of @ref
+ RCCEx_USBPHY_Clock_Source */
+
+ uint32_t UsboClockSelection; /*!< Specifies USB OTG clock source
+ This parameter can be a value of @ref
+ RCCEx_USBO_Clock_Source */
+
+ uint32_t CecClockSelection; /*!< Specifies CEC clock source
+ This parameter can be a value of @ref
+ RCCEx_CEC_Clock_Source */
+
+ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
+ This parameter can be a value of @ref
+ RCCEx_LPTIM1_Clock_Source */
+
+ uint32_t Lptim23ClockSelection; /*!< Specifies LPTIM23 clock source
+ This parameter can be a value of @ref
+ RCCEx_LPTIM23_Clock_Source */
+
+ uint32_t Lptim45ClockSelection; /*!< Specifies LPTIM45 clock source
+ This parameter can be a value of @ref
+ RCCEx_LPTIM45_Clock_Source */
+
+ uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source
+ This parameter can be a value of @ref
+ RCCEx_ADC_Clock_Source */
+
+ uint32_t RTCClockSelection; /*!< Specifies RTC clock source
+ This parameter can be a value of @ref
+ RCC_RTC_Clock_Source */
+
+ uint32_t TIMG1PresSelection; /*!< Specifies TIM Group 1 Clock Prescalers
+ Selection.
+ This parameter can be a value of @ref
+ RCCEx_TIMG1_Prescaler_Selection */
+
+ uint32_t TIMG2PresSelection; /*!< Specifies TIM Group 2 Clock Prescalers
+ Selection.
+ This parameter can be a value of @ref
+ RCCEx_TIMG2_Prescaler_Selection */
+} RCC_PeriphCLKInitTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+ * @{
+ */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCCEx_Periph_Clock_Selection
+ * @{
+ */
+#define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001)
+#define RCC_PERIPHCLK_UART24 ((uint64_t)0x00000002)
+#define RCC_PERIPHCLK_UART35 ((uint64_t)0x00000004)
+#define RCC_PERIPHCLK_ADC ((uint64_t)0x00000008)
+#define RCC_PERIPHCLK_I2C12 ((uint64_t)0x00000010)
+#define RCC_PERIPHCLK_I2C35 ((uint64_t)0x00000020)
+#define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00000040)
+#define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00000080)
+#define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00000100)
+#define RCC_PERIPHCLK_USBPHY ((uint64_t)0x00000200)
+#define RCC_PERIPHCLK_TIMG1 ((uint64_t)0x00000400)
+#define RCC_PERIPHCLK_TIMG2 ((uint64_t)0x00000800)
+#define RCC_PERIPHCLK_RTC ((uint64_t)0x00001000)
+#define RCC_PERIPHCLK_CEC ((uint64_t)0x00002000)
+#define RCC_PERIPHCLK_USART6 ((uint64_t)0x00004000)
+#define RCC_PERIPHCLK_UART78 ((uint64_t)0x00008000)
+#define RCC_PERIPHCLK_LPTIM23 ((uint64_t)0x00010000)
+#define RCC_PERIPHCLK_LPTIM45 ((uint64_t)0x00020000)
+#define RCC_PERIPHCLK_SAI3 ((uint64_t)0x00040000)
+#define RCC_PERIPHCLK_USBO ((uint64_t)0x00080000)
+#define RCC_PERIPHCLK_FMC ((uint64_t)0x00100000)
+#define RCC_PERIPHCLK_QSPI ((uint64_t)0x00200000)
+#define RCC_PERIPHCLK_DSI ((uint64_t)0x00400000)
+#define RCC_PERIPHCLK_CKPER ((uint64_t)0x00800000)
+#define RCC_PERIPHCLK_SPDIFRX ((uint64_t)0x01000000)
+#define RCC_PERIPHCLK_FDCAN ((uint64_t)0x02000000)
+#define RCC_PERIPHCLK_SPI1 ((uint64_t)0x04000000)
+#define RCC_PERIPHCLK_SPI23 ((uint64_t)0x08000000)
+#define RCC_PERIPHCLK_SPI45 ((uint64_t)0x10000000)
+#define RCC_PERIPHCLK_SPI6 ((uint64_t)0x20000000)
+#define RCC_PERIPHCLK_SAI4 ((uint64_t)0x40000000)
+#define RCC_PERIPHCLK_SDMMC12 ((uint64_t)0x80000000)
+#define RCC_PERIPHCLK_SDMMC3 ((uint64_t)0x100000000)
+#define RCC_PERIPHCLK_ETH ((uint64_t)0x200000000)
+#define RCC_PERIPHCLK_RNG1 ((uint64_t)0x400000000)
+#define RCC_PERIPHCLK_RNG2 ((uint64_t)0x800000000)
+#define RCC_PERIPHCLK_STGEN ((uint64_t)0x1000000000)
+#define RCC_PERIPHCLK_I2C46 ((uint64_t)0x2000000000)
+
+#define IS_RCC_PERIPHCLOCK(SELECTION) \
+ ((((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((SELECTION) & RCC_PERIPHCLK_UART24) == RCC_PERIPHCLK_UART24) || \
+ (((SELECTION) & RCC_PERIPHCLK_UART35) == RCC_PERIPHCLK_UART35) || \
+ (((SELECTION) & RCC_PERIPHCLK_I2C12) == RCC_PERIPHCLK_I2C12) || \
+ (((SELECTION) & RCC_PERIPHCLK_I2C35) == RCC_PERIPHCLK_I2C35) || \
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
+ (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
+ (((SELECTION) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY) || \
+ (((SELECTION) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
+ (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
+ (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
+ (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
+ (((SELECTION) & RCC_PERIPHCLK_UART78) == RCC_PERIPHCLK_UART78) || \
+ (((SELECTION) & RCC_PERIPHCLK_I2C46) == RCC_PERIPHCLK_I2C46) || \
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM23) == RCC_PERIPHCLK_LPTIM23) || \
+ (((SELECTION) & RCC_PERIPHCLK_LPTIM45) == RCC_PERIPHCLK_LPTIM45) || \
+ (((SELECTION) & RCC_PERIPHCLK_SAI3) == RCC_PERIPHCLK_SAI3) || \
+ (((SELECTION) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) || \
+ (((SELECTION) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
+ (((SELECTION) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) || \
+ (((SELECTION) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) || \
+ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
+ (((SELECTION) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((SELECTION) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) || \
+ (((SELECTION) & RCC_PERIPHCLK_SPI23) == RCC_PERIPHCLK_SPI23) || \
+ (((SELECTION) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) || \
+ (((SELECTION) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) || \
+ (((SELECTION) & RCC_PERIPHCLK_SAI4) == RCC_PERIPHCLK_SAI4) || \
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC12) == RCC_PERIPHCLK_SDMMC12) || \
+ (((SELECTION) & RCC_PERIPHCLK_SDMMC3) == RCC_PERIPHCLK_SDMMC3) || \
+ (((SELECTION) & RCC_PERIPHCLK_ETH) == RCC_PERIPHCLK_ETH) || \
+ (((SELECTION) & RCC_PERIPHCLK_RNG1) == RCC_PERIPHCLK_RNG1) || \
+ (((SELECTION) & RCC_PERIPHCLK_RNG2) == RCC_PERIPHCLK_RNG2) || \
+ (((SELECTION) & RCC_PERIPHCLK_USBO) == RCC_PERIPHCLK_USBO) || \
+ (((SELECTION) & RCC_PERIPHCLK_STGEN) == RCC_PERIPHCLK_STGEN) || \
+ (((SELECTION) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \
+ (((SELECTION) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Periph_One_Clock RCCEx_Periph_One_Clock
+ * @{
+ */
+#define RCC_PERIPHCLK_DAC ((uint64_t)0x4000000000)
+#define RCC_PERIPHCLK_LTDC ((uint64_t)0x8000000000)
+#define RCC_PERIPHCLK_DFSDM1 ((uint64_t)0x10000000000)
+#define RCC_PERIPHCLK_TEMP ((uint64_t)0x20000000000)
+#define RCC_PERIPHCLK_IWDG1 ((uint64_t)0x40000000000)
+#define RCC_PERIPHCLK_DDRPHYC ((uint64_t)0x80000000000)
+#define RCC_PERIPHCLK_IWDG2 ((uint64_t)0x100000000000)
+#define RCC_PERIPHCLK_GPU ((uint64_t)0x200000000000)
+#define RCC_PERIPHCLK_WWDG ((uint64_t)0x400000000000)
+#define RCC_PERIPHCLK_TIM2 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM3 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM4 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM5 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM6 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM7 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM12 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM13 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM14 RCC_PERIPHCLK_TIMG1
+#define RCC_PERIPHCLK_TIM1 RCC_PERIPHCLK_TIMG2
+#define RCC_PERIPHCLK_TIM8 RCC_PERIPHCLK_TIMG2
+#define RCC_PERIPHCLK_TIM15 RCC_PERIPHCLK_TIMG2
+#define RCC_PERIPHCLK_TIM16 RCC_PERIPHCLK_TIMG2
+#define RCC_PERIPHCLK_TIM17 RCC_PERIPHCLK_TIMG2
+
+#define IS_RCC_PERIPHONECLOCK(PERIPH) \
+ ((((PERIPH) & RCC_PERIPHCLK_DAC) == RCC_PERIPHCLK_DAC) || \
+ (((PERIPH) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
+ (((PERIPH) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
+ (((PERIPH) & RCC_PERIPHCLK_TEMP) == RCC_PERIPHCLK_TEMP) || \
+ (((PERIPH) & RCC_PERIPHCLK_IWDG1) == RCC_PERIPHCLK_IWDG1) || \
+ (((PERIPH) & RCC_PERIPHCLK_IWDG2) == RCC_PERIPHCLK_IWDG2) || \
+ (((PERIPH) & RCC_PERIPHCLK_WWDG) == RCC_PERIPHCLK_WWDG) || \
+ (((PERIPH) & RCC_PERIPHCLK_DDRPHYC) == RCC_PERIPHCLK_DDRPHYC) || \
+ (((PERIPH) & RCC_PERIPHCLK_GPU) == RCC_PERIPHCLK_GPU) || \
+ (((PERIPH) & RCC_PERIPHCLK_TIMG1) == RCC_PERIPHCLK_TIMG1) || \
+ (((PERIPH) & RCC_PERIPHCLK_TIMG2) == RCC_PERIPHCLK_TIMG2))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C12_Clock_Source I2C12 Clock Source
+ * @{
+ */
+#define RCC_I2C12CLKSOURCE_PCLK1 RCC_I2C12CKSELR_I2C12SRC_0
+#define RCC_I2C12CLKSOURCE_PLL4 RCC_I2C12CKSELR_I2C12SRC_1
+#define RCC_I2C12CLKSOURCE_HSI RCC_I2C12CKSELR_I2C12SRC_2
+#define RCC_I2C12CLKSOURCE_CSI RCC_I2C12CKSELR_I2C12SRC_3
+
+#define IS_RCC_I2C12CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_I2C12CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_I2C12CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_I2C12CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C12CLKSOURCE_CSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2C35_Clock_Source I2C35 Clock Source
+ * @{
+ */
+#define RCC_I2C35CLKSOURCE_PCLK1 RCC_I2C35CKSELR_I2C35SRC_0
+#define RCC_I2C35CLKSOURCE_PLL4 RCC_I2C35CKSELR_I2C35SRC_1
+#define RCC_I2C35CLKSOURCE_HSI RCC_I2C35CKSELR_I2C35SRC_2
+#define RCC_I2C35CLKSOURCE_CSI RCC_I2C35CKSELR_I2C35SRC_3
+
+#define IS_RCC_I2C35CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_I2C35CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_I2C35CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_I2C35CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C35CLKSOURCE_CSI))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_I2C46_Clock_Source I2C46 Clock Source
+ * @{
+ */
+#define RCC_I2C46CLKSOURCE_PCLK5 RCC_I2C46CKSELR_I2C46SRC_0
+#define RCC_I2C46CLKSOURCE_PLL3 RCC_I2C46CKSELR_I2C46SRC_1
+#define RCC_I2C46CLKSOURCE_HSI RCC_I2C46CKSELR_I2C46SRC_2
+#define RCC_I2C46CLKSOURCE_CSI RCC_I2C46CKSELR_I2C46SRC_3
+
+#define IS_RCC_I2C46CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_I2C46CLKSOURCE_PCLK5) || \
+ ((SOURCE) == RCC_I2C46CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_I2C46CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_I2C46CLKSOURCE_CSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
+ * @{
+ */
+#define RCC_SAI1CLKSOURCE_PLL4 RCC_SAI1CKSELR_SAI1SRC_0
+#define RCC_SAI1CLKSOURCE_PLL3_Q RCC_SAI1CKSELR_SAI1SRC_1
+#define RCC_SAI1CLKSOURCE_I2SCKIN RCC_SAI1CKSELR_SAI1SRC_2
+#define RCC_SAI1CLKSOURCE_PER RCC_SAI1CKSELR_SAI1SRC_3
+#define RCC_SAI1CLKSOURCE_PLL3_R RCC_SAI1CKSELR_SAI1SRC_4
+
+#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3_Q) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_I2SCKIN) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PER) || \
+ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3_R))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
+ * @{
+ */
+#define RCC_SAI2CLKSOURCE_PLL4 RCC_SAI2CKSELR_SAI2SRC_0
+#define RCC_SAI2CLKSOURCE_PLL3_Q RCC_SAI2CKSELR_SAI2SRC_1
+#define RCC_SAI2CLKSOURCE_I2SCKIN RCC_SAI2CKSELR_SAI2SRC_2
+#define RCC_SAI2CLKSOURCE_PER RCC_SAI2CKSELR_SAI2SRC_3
+#define RCC_SAI2CLKSOURCE_SPDIF RCC_SAI2CKSELR_SAI2SRC_4
+#define RCC_SAI2CLKSOURCE_PLL3_R RCC_SAI2CKSELR_SAI2SRC_5
+
+
+#define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3_Q) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_I2SCKIN) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PER) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_SPDIF) || \
+ ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3_R))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
+ * @{
+ */
+#define RCC_SAI3CLKSOURCE_PLL4 RCC_SAI3CKSELR_SAI3SRC_0
+#define RCC_SAI3CLKSOURCE_PLL3_Q RCC_SAI3CKSELR_SAI3SRC_1
+#define RCC_SAI3CLKSOURCE_I2SCKIN RCC_SAI3CKSELR_SAI3SRC_2
+#define RCC_SAI3CLKSOURCE_PER RCC_SAI3CKSELR_SAI3SRC_3
+#define RCC_SAI3CLKSOURCE_PLL3_R RCC_SAI3CKSELR_SAI3SRC_4
+
+#define IS_RCC_SAI3CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3_Q) || \
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_I2SCKIN) || \
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PER) || \
+ ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3_R))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_SAI4_Clock_Source SAI4 Clock Source
+ * @{
+ */
+#define RCC_SAI4CLKSOURCE_PLL4 RCC_SAI4CKSELR_SAI4SRC_0
+#define RCC_SAI4CLKSOURCE_PLL3_Q RCC_SAI4CKSELR_SAI4SRC_1
+#define RCC_SAI4CLKSOURCE_I2SCKIN RCC_SAI4CKSELR_SAI4SRC_2
+#define RCC_SAI4CLKSOURCE_PER RCC_SAI4CKSELR_SAI4SRC_3
+#define RCC_SAI4CLKSOURCE_PLL3_R RCC_SAI4CKSELR_SAI4SRC_4
+
+#define IS_RCC_SAI4CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL3_Q) || \
+ ((__SOURCE__) == RCC_SAI4CLKSOURCE_I2SCKIN) || \
+ ((__SOURCE__) == RCC_SAI4CLKSOURCE_PER) || \
+ ((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL3_R))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_SPI1_Clock_Source SPI/I2S1 Clock Source
+ * @{
+ */
+#define RCC_SPI1CLKSOURCE_PLL4 RCC_SPI2S1CKSELR_SPI1SRC_0
+#define RCC_SPI1CLKSOURCE_PLL3_Q RCC_SPI2S1CKSELR_SPI1SRC_1
+#define RCC_SPI1CLKSOURCE_I2SCKIN RCC_SPI2S1CKSELR_SPI1SRC_2
+#define RCC_SPI1CLKSOURCE_PER RCC_SPI2S1CKSELR_SPI1SRC_3
+#define RCC_SPI1CLKSOURCE_PLL3_R RCC_SPI2S1CKSELR_SPI1SRC_4
+
+#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3_Q) || \
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_I2SCKIN) || \
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_PER) || \
+ ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3_R))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SPI23_Clock_Source SPI/I2S2,3 Clock Source
+ * @{
+ */
+#define RCC_SPI23CLKSOURCE_PLL4 RCC_SPI2S23CKSELR_SPI23SRC_0
+#define RCC_SPI23CLKSOURCE_PLL3_Q RCC_SPI2S23CKSELR_SPI23SRC_1
+#define RCC_SPI23CLKSOURCE_I2SCKIN RCC_SPI2S23CKSELR_SPI23SRC_2
+#define RCC_SPI23CLKSOURCE_PER RCC_SPI2S23CKSELR_SPI23SRC_3
+#define RCC_SPI23CLKSOURCE_PLL3_R RCC_SPI2S23CKSELR_SPI23SRC_4
+
+#define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3_Q) || \
+ ((__SOURCE__) == RCC_SPI23CLKSOURCE_I2SCKIN) || \
+ ((__SOURCE__) == RCC_SPI23CLKSOURCE_PER) || \
+ ((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL3_R))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SPI45_Clock_Source SPI45 Clock Source
+ * @{
+ */
+#define RCC_SPI45CLKSOURCE_PCLK2 RCC_SPI45CKSELR_SPI45SRC_0
+#define RCC_SPI45CLKSOURCE_PLL4 RCC_SPI45CKSELR_SPI45SRC_1
+#define RCC_SPI45CLKSOURCE_HSI RCC_SPI45CKSELR_SPI45SRC_2
+#define RCC_SPI45CLKSOURCE_CSI RCC_SPI45CKSELR_SPI45SRC_3
+#define RCC_SPI45CLKSOURCE_HSE RCC_SPI45CKSELR_SPI45SRC_4
+
+#define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \
+ ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
+ * @{
+ */
+#define RCC_SPI6CLKSOURCE_PCLK5 RCC_SPI6CKSELR_SPI6SRC_0
+#define RCC_SPI6CLKSOURCE_PLL4 RCC_SPI6CKSELR_SPI6SRC_1
+#define RCC_SPI6CLKSOURCE_HSI RCC_SPI6CKSELR_SPI6SRC_2
+#define RCC_SPI6CLKSOURCE_CSI RCC_SPI6CKSELR_SPI6SRC_3
+#define RCC_SPI6CLKSOURCE_HSE RCC_SPI6CKSELR_SPI6SRC_4
+#define RCC_SPI6CLKSOURCE_PLL3 RCC_SPI6CKSELR_SPI6SRC_5
+
+#define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK5) || \
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL4) || \
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
+ * @{
+ */
+#define RCC_USART1CLKSOURCE_PCLK5 RCC_UART1CKSELR_UART1SRC_0
+#define RCC_USART1CLKSOURCE_PLL3 RCC_UART1CKSELR_UART1SRC_1
+#define RCC_USART1CLKSOURCE_HSI RCC_UART1CKSELR_UART1SRC_2
+#define RCC_USART1CLKSOURCE_CSI RCC_UART1CKSELR_UART1SRC_3
+#define RCC_USART1CLKSOURCE_PLL4 RCC_UART1CKSELR_UART1SRC_4
+#define RCC_USART1CLKSOURCE_HSE RCC_UART1CKSELR_UART1SRC_5
+
+#define IS_RCC_USART1CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_USART1CLKSOURCE_PCLK5) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_USART1CLKSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART24_Clock_Source UART24 Clock Source
+ * @{
+ */
+#define RCC_UART24CLKSOURCE_PCLK1 RCC_UART24CKSELR_UART24SRC_0
+#define RCC_UART24CLKSOURCE_PLL4 RCC_UART24CKSELR_UART24SRC_1
+#define RCC_UART24CLKSOURCE_HSI RCC_UART24CKSELR_UART24SRC_2
+#define RCC_UART24CLKSOURCE_CSI RCC_UART24CKSELR_UART24SRC_3
+#define RCC_UART24CLKSOURCE_HSE RCC_UART24CKSELR_UART24SRC_4
+
+#define IS_RCC_UART24CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_UART24CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART24CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_UART24CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_UART24CLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_UART24CLKSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART35_Clock_Source UART35 Clock Source
+ * @{
+ */
+#define RCC_UART35CLKSOURCE_PCLK1 RCC_UART35CKSELR_UART35SRC_0
+#define RCC_UART35CLKSOURCE_PLL4 RCC_UART35CKSELR_UART35SRC_1
+#define RCC_UART35CLKSOURCE_HSI RCC_UART35CKSELR_UART35SRC_2
+#define RCC_UART35CLKSOURCE_CSI RCC_UART35CKSELR_UART35SRC_3
+#define RCC_UART35CLKSOURCE_HSE RCC_UART35CKSELR_UART35SRC_4
+
+#define IS_RCC_UART35CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_UART35CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART35CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_UART35CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_UART35CLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_UART35CLKSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source
+ * @{
+ */
+#define RCC_USART6CLKSOURCE_PCLK2 RCC_UART6CKSELR_UART6SRC_0
+#define RCC_USART6CLKSOURCE_PLL4 RCC_UART6CKSELR_UART6SRC_1
+#define RCC_USART6CLKSOURCE_HSI RCC_UART6CKSELR_UART6SRC_2
+#define RCC_USART6CLKSOURCE_CSI RCC_UART6CKSELR_UART6SRC_3
+#define RCC_USART6CLKSOURCE_HSE RCC_UART6CKSELR_UART6SRC_4
+
+#define IS_RCC_USART6CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
+ ((SOURCE) == RCC_USART6CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_USART6CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_USART6CLKSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_UART78_Clock_Source UART78 Clock Source
+ * @{
+ */
+#define RCC_UART78CLKSOURCE_PCLK1 RCC_UART78CKSELR_UART78SRC_0
+#define RCC_UART78CLKSOURCE_PLL4 RCC_UART78CKSELR_UART78SRC_1
+#define RCC_UART78CLKSOURCE_HSI RCC_UART78CKSELR_UART78SRC_2
+#define RCC_UART78CLKSOURCE_CSI RCC_UART78CKSELR_UART78SRC_3
+#define RCC_UART78CLKSOURCE_HSE RCC_UART78CKSELR_UART78SRC_4
+
+#define IS_RCC_UART78CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_UART78CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_UART78CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_UART78CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_UART78CLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_UART78CLKSOURCE_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC12 Clock Source
+ * @{
+ */
+#define RCC_SDMMC12CLKSOURCE_HCLK6 RCC_SDMMC12CKSELR_SDMMC12SRC_0
+#define RCC_SDMMC12CLKSOURCE_PLL3 RCC_SDMMC12CKSELR_SDMMC12SRC_1
+#define RCC_SDMMC12CLKSOURCE_PLL4 RCC_SDMMC12CKSELR_SDMMC12SRC_2
+#define RCC_SDMMC12CLKSOURCE_HSI RCC_SDMMC12CKSELR_SDMMC12SRC_3
+
+#define IS_RCC_SDMMC12CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_SDMMC12CLKSOURCE_HCLK6) || \
+ ((SOURCE) == RCC_SDMMC12CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_SDMMC12CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_SDMMC12CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_SDMMC3_Clock_Source SDMMC3 Clock Source
+ * @{
+ */
+#define RCC_SDMMC3CLKSOURCE_HCLK2 RCC_SDMMC3CKSELR_SDMMC3SRC_0
+#define RCC_SDMMC3CLKSOURCE_PLL3 RCC_SDMMC3CKSELR_SDMMC3SRC_1
+#define RCC_SDMMC3CLKSOURCE_PLL4 RCC_SDMMC3CKSELR_SDMMC3SRC_2
+#define RCC_SDMMC3CLKSOURCE_HSI RCC_SDMMC3CKSELR_SDMMC3SRC_3
+
+#define IS_RCC_SDMMC3CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_SDMMC3CLKSOURCE_HCLK2) || \
+ ((SOURCE) == RCC_SDMMC3CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_SDMMC3CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_SDMMC3CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_ETH_Clock_Source ETH Clock Source
+ * @{
+ */
+#define RCC_ETHCLKSOURCE_PLL4 RCC_ETHCKSELR_ETHSRC_0
+#define RCC_ETHCLKSOURCE_PLL3 RCC_ETHCKSELR_ETHSRC_1
+#define RCC_ETHCLKSOURCE_OFF RCC_ETHCKSELR_ETHSRC_2
+
+
+#define IS_RCC_ETHCLKSOURCE(SOURCE) (((SOURCE) == RCC_ETHCLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_ETHCLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_ETHCLKSOURCE_OFF))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_ETH_PrecisionTimeProtocol_Divider ETH PrecisionTimeProtocol Divider
+ * @{
+ */
+#define RCC_ETHPTPDIV_1 RCC_ETHCKSELR_ETHPTPDIV_0 /*Bypass (default after reset*/
+#define RCC_ETHPTPDIV_2 RCC_ETHCKSELR_ETHPTPDIV_1 /*Division by 2*/
+#define RCC_ETHPTPDIV_3 RCC_ETHCKSELR_ETHPTPDIV_2 /*Division by 3*/
+#define RCC_ETHPTPDIV_4 RCC_ETHCKSELR_ETHPTPDIV_3 /*Division by 4*/
+#define RCC_ETHPTPDIV_5 RCC_ETHCKSELR_ETHPTPDIV_4 /*Division by 5*/
+#define RCC_ETHPTPDIV_6 RCC_ETHCKSELR_ETHPTPDIV_5 /*Division by 6*/
+#define RCC_ETHPTPDIV_7 RCC_ETHCKSELR_ETHPTPDIV_6 /*Division by 7*/
+#define RCC_ETHPTPDIV_8 RCC_ETHCKSELR_ETHPTPDIV_7 /*Division by 8*/
+#define RCC_ETHPTPDIV_9 RCC_ETHCKSELR_ETHPTPDIV_8 /*Division by 9*/
+#define RCC_ETHPTPDIV_10 RCC_ETHCKSELR_ETHPTPDIV_9 /*Division by 10*/
+#define RCC_ETHPTPDIV_11 RCC_ETHCKSELR_ETHPTPDIV_10 /*Division by 11*/
+#define RCC_ETHPTPDIV_12 RCC_ETHCKSELR_ETHPTPDIV_11 /*Division by 12*/
+#define RCC_ETHPTPDIV_13 RCC_ETHCKSELR_ETHPTPDIV_12 /*Division by 13*/
+#define RCC_ETHPTPDIV_14 RCC_ETHCKSELR_ETHPTPDIV_13 /*Division by 14*/
+#define RCC_ETHPTPDIV_15 RCC_ETHCKSELR_ETHPTPDIV_14 /*Division by 15*/
+#define RCC_ETHPTPDIV_16 RCC_ETHCKSELR_ETHPTPDIV_15 /*Division by 16*/
+
+
+#define IS_RCC_ETHPTPDIV(SOURCE) (((SOURCE) == RCC_ETHPTPDIV_1) || \
+ ((SOURCE) == RCC_ETHPTPDIV_2) || \
+ ((SOURCE) == RCC_ETHPTPDIV_3) || \
+ ((SOURCE) == RCC_ETHPTPDIV_4) || \
+ ((SOURCE) == RCC_ETHPTPDIV_5) || \
+ ((SOURCE) == RCC_ETHPTPDIV_6) || \
+ ((SOURCE) == RCC_ETHPTPDIV_7) || \
+ ((SOURCE) == RCC_ETHPTPDIV_8) || \
+ ((SOURCE) == RCC_ETHPTPDIV_9) || \
+ ((SOURCE) == RCC_ETHPTPDIV_10) || \
+ ((SOURCE) == RCC_ETHPTPDIV_11) || \
+ ((SOURCE) == RCC_ETHPTPDIV_12) || \
+ ((SOURCE) == RCC_ETHPTPDIV_13) || \
+ ((SOURCE) == RCC_ETHPTPDIV_14) || \
+ ((SOURCE) == RCC_ETHPTPDIV_15) || \
+ ((SOURCE) == RCC_ETHPTPDIV_16))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_QSPI_Clock_Source QSPI Clock Source
+ * @{
+ */
+#define RCC_QSPICLKSOURCE_ACLK RCC_QSPICKSELR_QSPISRC_0
+#define RCC_QSPICLKSOURCE_PLL3 RCC_QSPICKSELR_QSPISRC_1
+#define RCC_QSPICLKSOURCE_PLL4 RCC_QSPICKSELR_QSPISRC_2
+#define RCC_QSPICLKSOURCE_PER RCC_QSPICKSELR_QSPISRC_3
+
+#define IS_RCC_QSPICLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_QSPICLKSOURCE_ACLK) || \
+ ((SOURCE) == RCC_QSPICLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_QSPICLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_QSPICLKSOURCE_PER))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source
+ * @{
+ */
+#define RCC_FMCCLKSOURCE_ACLK RCC_FMCCKSELR_FMCSRC_0
+#define RCC_FMCCLKSOURCE_PLL3 RCC_FMCCKSELR_FMCSRC_1
+#define RCC_FMCCLKSOURCE_PLL4 RCC_FMCCKSELR_FMCSRC_2
+#define RCC_FMCCLKSOURCE_PER RCC_FMCCKSELR_FMCSRC_3
+
+#define IS_RCC_FMCCLKSOURCE(SOURCE) (((SOURCE) == RCC_FMCCLKSOURCE_ACLK) || \
+ ((SOURCE) == RCC_FMCCLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_FMCCLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_FMCCLKSOURCE_PER))
+/**
+ * @}
+ */
+
+#if defined(FDCAN1)
+/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
+ * @{
+ */
+#define RCC_FDCANCLKSOURCE_HSE RCC_FDCANCKSELR_FDCANSRC_0
+#define RCC_FDCANCLKSOURCE_PLL3 RCC_FDCANCKSELR_FDCANSRC_1
+#define RCC_FDCANCLKSOURCE_PLL4_Q RCC_FDCANCKSELR_FDCANSRC_2
+#define RCC_FDCANCLKSOURCE_PLL4_R RCC_FDCANCKSELR_FDCANSRC_3
+
+
+
+#define IS_RCC_FDCANCLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_FDCANCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_FDCANCLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_FDCANCLKSOURCE_PLL4_Q) || \
+ ((SOURCE) == RCC_FDCANCLKSOURCE_PLL4_R))
+/**
+ * @}
+ */
+#endif /*FDCAN1*/
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source
+ * @{
+ */
+#define RCC_SPDIFRXCLKSOURCE_PLL4 RCC_SPDIFCKSELR_SPDIFSRC_0
+#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_SPDIFCKSELR_SPDIFSRC_1
+#define RCC_SPDIFRXCLKSOURCE_HSI RCC_SPDIFCKSELR_SPDIFSRC_2
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source
+ * @{
+ */
+#define RCC_CECCLKSOURCE_LSE RCC_CECCKSELR_CECSRC_0
+#define RCC_CECCLKSOURCE_LSI RCC_CECCKSELR_CECSRC_1
+#define RCC_CECCLKSOURCE_CSI122 RCC_CECCKSELR_CECSRC_2
+
+#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
+ ((SOURCE) == RCC_CECCLKSOURCE_CSI122))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_USBPHY_Clock_Source USBPHY Clock Source
+ * @{
+ */
+#define RCC_USBPHYCLKSOURCE_HSE RCC_USBCKSELR_USBPHYSRC_0
+#define RCC_USBPHYCLKSOURCE_PLL4 RCC_USBCKSELR_USBPHYSRC_1
+#define RCC_USBPHYCLKSOURCE_HSE2 RCC_USBCKSELR_USBPHYSRC_2
+
+#define IS_RCC_USBPHYCLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_USBPHYCLKSOURCE_HSE) || \
+ ((SOURCE) ==RCC_USBPHYCLKSOURCE_PLL4) || \
+ ((SOURCE) ==RCC_USBPHYCLKSOURCE_HSE2))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_USBO_Clock_Source USBO Clock Source
+ * @{
+ */
+#define RCC_USBOCLKSOURCE_PLL4 RCC_USBCKSELR_USBOSRC_0
+#define RCC_USBOCLKSOURCE_PHY RCC_USBCKSELR_USBOSRC_1
+
+#define IS_RCC_USBOCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBOCLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_USBOCLKSOURCE_PHY))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_RNG1_Clock_Source RNG1 Clock Source
+ * @{
+ */
+#define RCC_RNG1CLKSOURCE_CSI RCC_RNG1CKSELR_RNG1SRC_0
+#define RCC_RNG1CLKSOURCE_PLL4 RCC_RNG1CKSELR_RNG1SRC_1
+#define RCC_RNG1CLKSOURCE_LSE RCC_RNG1CKSELR_RNG1SRC_2
+#define RCC_RNG1CLKSOURCE_LSI RCC_RNG1CKSELR_RNG1SRC_3
+
+#define IS_RCC_RNG1CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG1CLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_RNG1CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_RNG1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_RNG1CLKSOURCE_LSI))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_RNG2_Clock_Source RNG2 Clock Source
+ * @{
+ */
+#define RCC_RNG2CLKSOURCE_CSI RCC_RNG2CKSELR_RNG2SRC_0
+#define RCC_RNG2CLKSOURCE_PLL4 RCC_RNG2CKSELR_RNG2SRC_1
+#define RCC_RNG2CLKSOURCE_LSE RCC_RNG2CKSELR_RNG2SRC_2
+#define RCC_RNG2CLKSOURCE_LSI RCC_RNG2CKSELR_RNG2SRC_3
+
+#define IS_RCC_RNG2CLKSOURCE(SOURCE) (((SOURCE) == RCC_RNG2CLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_RNG2CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_RNG2CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_RNG2CLKSOURCE_LSI))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_CKPER_Clock_Source CKPER Clock Source
+ * @{
+ */
+#define RCC_CKPERCLKSOURCE_HSI RCC_CPERCKSELR_CKPERSRC_0
+#define RCC_CKPERCLKSOURCE_CSI RCC_CPERCKSELR_CKPERSRC_1
+#define RCC_CKPERCLKSOURCE_HSE RCC_CPERCKSELR_CKPERSRC_2
+#define RCC_CKPERCLKSOURCE_OFF RCC_CPERCKSELR_CKPERSRC_3 /*Clock disabled*/
+
+#define IS_RCC_CKPERCLKSOURCE(SOURCE) (((SOURCE) == RCC_CKPERCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_CKPERCLKSOURCE_CSI) || \
+ ((SOURCE) == RCC_CKPERCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_CKPERCLKSOURCE_OFF))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_STGEN_Clock_Source STGEN Clock Source
+ * @{
+ */
+#define RCC_STGENCLKSOURCE_HSI RCC_STGENCKSELR_STGENSRC_0
+#define RCC_STGENCLKSOURCE_HSE RCC_STGENCKSELR_STGENSRC_1
+#define RCC_STGENCLKSOURCE_OFF RCC_STGENCKSELR_STGENSRC_2
+
+#define IS_RCC_STGENCLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_STGENCLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_STGENCLKSOURCE_HSE) || \
+ ((SOURCE) == RCC_STGENCLKSOURCE_OFF))
+/**
+ * @}
+ */
+
+#if defined(DSI)
+/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source
+ * @{
+ */
+#define RCC_DSICLKSOURCE_PHY RCC_DSICKSELR_DSISRC_0
+#define RCC_DSICLKSOURCE_PLL4 RCC_DSICKSELR_DSISRC_1
+
+#define IS_RCC_DSICLKSOURCE(__SOURCE__) \
+ (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \
+ ((__SOURCE__) == RCC_DSICLKSOURCE_PLL4))
+/**
+ * @}
+ */
+#endif /*DSI*/
+
+/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
+ * @{
+ */
+#define RCC_ADCCLKSOURCE_PLL4 RCC_ADCCKSELR_ADCSRC_0
+#define RCC_ADCCLKSOURCE_PER RCC_ADCCKSELR_ADCSRC_1
+#define RCC_ADCCLKSOURCE_PLL3 RCC_ADCCKSELR_ADCSRC_2
+
+#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_ADCCLKSOURCE_PER) || \
+ ((SOURCE) == RCC_ADCCLKSOURCE_PLL3))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
+ * @{
+ */
+#define RCC_LPTIM1CLKSOURCE_PCLK1 RCC_LPTIM1CKSELR_LPTIM1SRC_0
+#define RCC_LPTIM1CLKSOURCE_PLL4 RCC_LPTIM1CKSELR_LPTIM1SRC_1
+#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_LPTIM1CKSELR_LPTIM1SRC_2
+#define RCC_LPTIM1CLKSOURCE_LSE RCC_LPTIM1CKSELR_LPTIM1SRC_3
+#define RCC_LPTIM1CLKSOURCE_LSI RCC_LPTIM1CKSELR_LPTIM1SRC_4
+#define RCC_LPTIM1CLKSOURCE_PER RCC_LPTIM1CKSELR_LPTIM1SRC_5
+#define RCC_LPTIM1CLKSOURCE_OFF RCC_LPTIM1CKSELR_LPTIM1SRC_6
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_PER) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_OFF))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM23 Clock Source
+ * @{
+ */
+#define RCC_LPTIM23CLKSOURCE_PCLK3 RCC_LPTIM23CKSELR_LPTIM23SRC_0
+#define RCC_LPTIM23CLKSOURCE_PLL4 RCC_LPTIM23CKSELR_LPTIM23SRC_1
+#define RCC_LPTIM23CLKSOURCE_PER RCC_LPTIM23CKSELR_LPTIM23SRC_2
+#define RCC_LPTIM23CLKSOURCE_LSE RCC_LPTIM23CKSELR_LPTIM23SRC_3
+#define RCC_LPTIM23CLKSOURCE_LSI RCC_LPTIM23CKSELR_LPTIM23SRC_4
+#define RCC_LPTIM23CLKSOURCE_OFF RCC_LPTIM23CKSELR_LPTIM23SRC_5
+
+
+#define IS_RCC_LPTIM23CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_LPTIM23CLKSOURCE_PCLK3) || \
+ ((SOURCE) == RCC_LPTIM23CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_LPTIM23CLKSOURCE_PER) || \
+ ((SOURCE) == RCC_LPTIM23CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_LPTIM23CLKSOURCE_LSI) || \
+ ((SOURCE) == RCC_LPTIM23CLKSOURCE_OFF))
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM45 Clock Source
+ * @{
+ */
+#define RCC_LPTIM45CLKSOURCE_PCLK3 RCC_LPTIM45CKSELR_LPTIM45SRC_0
+#define RCC_LPTIM45CLKSOURCE_PLL4 RCC_LPTIM45CKSELR_LPTIM45SRC_1
+#define RCC_LPTIM45CLKSOURCE_PLL3 RCC_LPTIM45CKSELR_LPTIM45SRC_2
+#define RCC_LPTIM45CLKSOURCE_LSE RCC_LPTIM45CKSELR_LPTIM45SRC_3
+#define RCC_LPTIM45CLKSOURCE_LSI RCC_LPTIM45CKSELR_LPTIM45SRC_4
+#define RCC_LPTIM45CLKSOURCE_PER RCC_LPTIM45CKSELR_LPTIM45SRC_5
+#define RCC_LPTIM45CLKSOURCE_OFF RCC_LPTIM45CKSELR_LPTIM45SRC_6
+
+
+
+#define IS_RCC_LPTIM45CLKSOURCE(SOURCE) \
+ (((SOURCE) == RCC_LPTIM45CLKSOURCE_PCLK3) || \
+ ((SOURCE) == RCC_LPTIM45CLKSOURCE_PLL4) || \
+ ((SOURCE) == RCC_LPTIM45CLKSOURCE_PLL3) || \
+ ((SOURCE) == RCC_LPTIM45CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_LPTIM45CLKSOURCE_LSI) || \
+ ((SOURCE) == RCC_LPTIM45CLKSOURCE_PER) || \
+ ((SOURCE) == RCC_LPTIM45CLKSOURCE_OFF))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_TIMG1_Prescaler_Selection TIMG1 Prescaler Selection
+ * @{
+ */
+#define RCC_TIMG1PRES_DEACTIVATED RCC_TIMG1PRER_TIMG1PRE_0
+#define RCC_TIMG1PRES_ACTIVATED RCC_TIMG1PRER_TIMG1PRE_1
+
+#define IS_RCC_TIMG1PRES(PRES) (((PRES) == RCC_TIMG1PRES_DEACTIVATED) || \
+ ((PRES) == RCC_TIMG1PRES_ACTIVATED))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_TIMG2_Prescaler_Selection TIMG2 Prescaler Selection
+ * @{
+ */
+#define RCC_TIMG2PRES_DEACTIVATED RCC_TIMG2PRER_TIMG2PRE_0
+#define RCC_TIMG2PRES_ACTIVATED RCC_TIMG2PRER_TIMG2PRE_1
+
+#define IS_RCC_TIMG2PRES(PRES) (((PRES) == RCC_TIMG2PRES_DEACTIVATED) || \
+ ((PRES) == RCC_TIMG2PRES_ACTIVATED))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_RCC_BootCx RCC BootCx
+ * @{
+ */
+#define RCC_BOOT_C1 RCC_MP_BOOTCR_MPU_BEN
+#define RCC_BOOT_C2 RCC_MP_BOOTCR_MCU_BEN
+
+#define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \
+ ((CORE) == RCC_BOOT_C2) || \
+ ((CORE) == (RCC_BOOT_C1 ||RCC_BOOT_C2) ))
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+ * @{
+ */
+/** @brief macro to configure the I2C12 clock (I2C12CLK).
+ *
+ * @param __I2C12CLKSource__: specifies the I2C12 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2C12CLKSOURCE_PCLK1: PCLK1 selected as I2C12 clock (default after reset)
+ * @arg RCC_I2C12CLKSOURCE_PLL4: PLL4_R selected as I2C12 clock
+ * @arg RCC_I2C12CLKSOURCE_HSI: HSI selected as I2C12 clock
+ * @arg RCC_I2C12CLKSOURCE_CSI: CSI selected as I2C12 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C12_CONFIG(__I2C12CLKSource__) \
+ MODIFY_REG(RCC->I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, (uint32_t)(__I2C12CLKSource__))
+
+/** @brief macro to get the I2C12 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2C12CLKSOURCE_PCLK1: PCLK1 selected as I2C12 clock
+ * @arg RCC_I2C12CLKSOURCE_PLL4: PLL4_R selected as I2C12 clock
+ * @arg RCC_I2C12CLKSOURCE_HSI: HSI selected as I2C12 clock
+ * @arg RCC_I2C12CLKSOURCE_CSI: CSI selected as I2C12 clock
+ */
+#define __HAL_RCC_GET_I2C12_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC)))
+
+/** @brief macro to configure the I2C35 clock (I2C35CLK).
+ *
+ * @param __I2C35CLKSource__: specifies the I2C35 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2C35CLKSOURCE_PCLK1: PCLK1 selected as I2C35 clock (default after reset)
+ * @arg RCC_I2C35CLKSOURCE_PLL4: PLL4_R selected as I2C35 clock
+ * @arg RCC_I2C35CLKSOURCE_HSI: HSI selected as I2C35 clock
+ * @arg RCC_I2C35CLKSOURCE_CSI: CSI selected as I2C35 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C35_CONFIG(__I2C35CLKSource__) \
+ MODIFY_REG(RCC->I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, (uint32_t)(__I2C35CLKSource__))
+
+/** @brief macro to get the I2C35 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2C35CLKSOURCE_PCLK1: PCLK1 selected as I2C35 clock
+ * @arg RCC_I2C35CLKSOURCE_PLL4: PLL4_R selected as I2C35 clock
+ * @arg RCC_I2C35CLKSOURCE_HSI: HSI selected as I2C35 clock
+ * @arg RCC_I2C35CLKSOURCE_CSI: CSI selected as I2C35 clock
+ */
+#define __HAL_RCC_GET_I2C35_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC)))
+
+/** @brief macro to configure the I2C46 clock (I2C46CLK).
+ *
+ * @param __I2C46CLKSource__: specifies the I2C46 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2C46CLKSOURCE_PCLK5: PCLK5 selected as I2C46 clock (default after reset)
+ * @arg RCC_I2C46CLKSOURCE_PLL3: PLL3_Q selected as I2C46 clock
+ * @arg RCC_I2C46CLKSOURCE_HSI: HSI selected as I2C46 clock
+ * @arg RCC_I2C46CLKSOURCE_CSI: CSI selected as I2C46 clock
+ * @retval None
+ */
+#define __HAL_RCC_I2C46_CONFIG(__I2C46CLKSource__) \
+ MODIFY_REG(RCC->I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, (uint32_t)(__I2C46CLKSource__))
+
+/** @brief macro to get the I2C46 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_I2C46CLKSOURCE_PCLK5: PCLK5 selected as I2C46 clock
+ * @arg RCC_I2C46CLKSOURCE_PLL3: PLL3_Q selected as I2C46 clock
+ * @arg RCC_I2C46CLKSOURCE_HSI: HSI selected as I2C46 clock
+ * @arg RCC_I2C46CLKSOURCE_CSI: CSI selected as I2C46 clock
+ */
+#define __HAL_RCC_GET_I2C46_SOURCE() ((uint32_t)(READ_BIT(RCC->I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC)))
+
+/**
+ * @brief Macro to Configure the SAI1 clock source.
+ * @param __RCC_SAI1CLKSource__: defines the SAI1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLL4: SAI1 clock = PLL4Q
+ * @arg RCC_SAI1CLKSOURCE_PLL3_Q: SAI1 clock = PLL3Q
+ * @arg RCC_SAI1CLKSOURCE_I2SCKIN: SAI1 clock = I2SCKIN
+ * @arg RCC_SAI1CLKSOURCE_PER: SAI1 clock = PER
+ * @arg RCC_SAI1CLKSOURCE_PLL3_R: SAI1 clock = PLL3R
+ * @retval None
+ */
+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ ) \
+ MODIFY_REG(RCC->SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, (uint32_t)(__RCC_SAI1CLKSource__))
+
+/** @brief Macro to get the SAI1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI1CLKSOURCE_PLL4: SAI1 clock = PLL4Q
+ * @arg RCC_SAI1CLKSOURCE_PLL3_Q: SAI1 clock = PLL3Q
+ * @arg RCC_SAI1CLKSOURCE_I2SCKIN: SAI1 clock = I2SCKIN
+ * @arg RCC_SAI1CLKSOURCE_PER: SAI1 clock = PER
+ * @arg RCC_SAI1CLKSOURCE_PLL3_R: SAI1 clock = PLL3R
+ */
+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC)))
+
+
+/**
+ * @brief Macro to Configure the SAI2 clock source.
+ * @param __RCC_SAI2CLKSource__: defines the SAI2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLL4: SAI2 clock = PLL4Q
+ * @arg RCC_SAI2CLKSOURCE_PLL3_Q: SAI2 clock = PLL3Q
+ * @arg RCC_SAI2CLKSOURCE_I2SCKIN: SAI2 clock = I2SCKIN
+ * @arg RCC_SAI2CLKSOURCE_PER: SAI2 clock = PER
+ * @arg RCC_SAI2CLKSOURCE_SPDIF: SAI2 clock = SPDIF_CK_SYMB
+ * @arg RCC_SAI2CLKSOURCE_PLL3_R: SAI2 clock = PLL3R
+ * @retval None
+ */
+#define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ ) \
+ MODIFY_REG(RCC->SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (uint32_t)(__RCC_SAI2CLKSource__))
+
+/** @brief Macro to get the SAI2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI2CLKSOURCE_PLL4: SAI2 clock = PLL4Q
+ * @arg RCC_SAI2CLKSOURCE_PLL3_Q: SAI2 clock = PLL3Q
+ * @arg RCC_SAI2CLKSOURCE_I2SCKIN: SAI2 clock = I2SCKIN
+ * @arg RCC_SAI2CLKSOURCE_PER: SAI2 clock = PER
+ * @arg RCC_SAI2CLKSOURCE_SPDIF: SAI2 clock = SPDIF_CK_SYMB
+ * @arg RCC_SAI2CLKSOURCE_PLL3_R: SAI2 clock = PLL3R
+ */
+#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC)))
+
+
+/**
+ * @brief Macro to Configure the SAI3 clock source.
+ * @param __RCC_SAI3CLKSource__: defines the SAI3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI3CLKSOURCE_PLL4: SAI3 clock = PLL4Q
+ * @arg RCC_SAI3CLKSOURCE_PLL3_Q: SAI3 clock = PLL3Q
+ * @arg RCC_SAI3CLKSOURCE_I2SCKIN: SAI3 clock = I2SCKIN
+ * @arg RCC_SAI3CLKSOURCE_PER: SAI3 clock = PER
+ * @arg RCC_SAI3CLKSOURCE_PLL3_R: SAI3 clock = PLL3R
+ * @retval None
+ */
+#define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ ) \
+ MODIFY_REG(RCC->SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, (uint32_t)(__RCC_SAI3CLKSource__))
+
+/** @brief Macro to get the SAI3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI3CLKSOURCE_PLL4: SAI3 clock = PLL4Q
+ * @arg RCC_SAI3CLKSOURCE_PLL3_Q: SAI3 clock = PLL3Q
+ * @arg RCC_SAI3CLKSOURCE_I2SCKIN: SAI3 clock = I2SCKIN
+ * @arg RCC_SAI3CLKSOURCE_PER: SAI3 clock = PER
+ * @arg RCC_SAI3CLKSOURCE_PLL3_R: SAI3 clock = PLL3R
+ */
+#define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC)))
+
+
+/**
+ * @brief Macro to Configure the SAI4 clock source.
+ * @param __RCC_SAI4CLKSource__: defines the SAI4 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAI4CLKSOURCE_PLL4: SAI4 clock = PLL4Q
+ * @arg RCC_SAI4CLKSOURCE_PLL3_Q: SAI4 clock = PLL3Q
+ * @arg RCC_SAI4CLKSOURCE_I2SCKIN: SAI4 clock = I2SCKIN
+ * @arg RCC_SAI4CLKSOURCE_PER: SAI4 clock = PER
+ * @arg RCC_SAI4CLKSOURCE_PLL3_R: SAI4 clock = PLL3R
+ * @retval None
+ */
+#define __HAL_RCC_SAI4_CONFIG(__RCC_SAI4CLKSource__ ) \
+ MODIFY_REG(RCC->SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, (uint32_t)(__RCC_SAI4CLKSource__))
+
+/** @brief Macro to get the SAI4 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SAI4CLKSOURCE_PLL4: SAI4 clock = PLL4Q
+ * @arg RCC_SAI4CLKSOURCE_PLL3_Q: SAI4 clock = PLL3Q
+ * @arg RCC_SAI4CLKSOURCE_I2SCKIN: SAI4 clock = I2SCKIN
+ * @arg RCC_SAI4CLKSOURCE_PER: SAI4 clock = PER
+ * @arg RCC_SAI4CLKSOURCE_PLL3_R: SAI4 clock = PLL3R
+ */
+#define __HAL_RCC_GET_SAI4_SOURCE() ((uint32_t)(READ_BIT(RCC->SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC)))
+
+
+/**
+ * @brief Macro to Configure the SPI/I2S1 clock source.
+ * @param __RCC_SPI1CLKSource__: defines the SPI/I2S1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPI1CLKSOURCE_PLL4: SPI1 clock = PLL4P
+ * @arg RCC_SPI1CLKSOURCE_PLL3_Q: SPI1 clock = PLL3Q
+ * @arg RCC_SPI1CLKSOURCE_I2SCKIN: SPI1 clock = I2SCKIN
+ * @arg RCC_SPI1CLKSOURCE_PER: SPI1 clock = PER
+ * @arg RCC_SPI1CLKSOURCE_PLL3_R: SPI1 clock = PLL3R
+ * @retval None
+ */
+#define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__) \
+ MODIFY_REG(RCC->SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, (uint32_t)(__RCC_SPI1CLKSource__))
+
+/** @brief Macro to get the SPI/I2S1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI1CLKSOURCE_PLL4: SPI1 clock = PLL4P
+ * @arg RCC_SPI1CLKSOURCE_PLL3_Q: SPI1 clock = PLL3Q
+ * @arg RCC_SPI1CLKSOURCE_I2SCKIN: SPI1 clock = I2SCKIN
+ * @arg RCC_SPI1CLKSOURCE_PER: SPI1 clock = PER
+ * @arg RCC_SPI1CLKSOURCE_PLL3_R: SPI1 clock = PLL3R
+ */
+#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC)))
+
+
+/**
+ * @brief Macro to Configure the SPI/I2S2,3 clock source.
+ * @param __RCC_SPI23CLKSource__: defines the SPI/I2S2,3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPI23CLKSOURCE_PLL4: SPI23 clock = PLL4P
+ * @arg RCC_SPI23CLKSOURCE_PLL3_Q: SPI23 clock = PLL3Q
+ * @arg RCC_SPI23CLKSOURCE_I2SCKIN: SPI23 clock = I2SCKIN
+ * @arg RCC_SPI23CLKSOURCE_PER: SPI23 clock = PER
+ * @arg RCC_SPI23CLKSOURCE_PLL3_R: SPI23 clock = PLL3R
+ * @retval None
+ */
+#define __HAL_RCC_SPI23_CONFIG(__RCC_SPI23CLKSource__ ) \
+ MODIFY_REG(RCC->SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, (uint32_t)(__RCC_SPI23CLKSource__))
+
+/** @brief Macro to get the SPI/I2S2,3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI23CLKSOURCE_PLL4: SPI23 clock = PLL4P
+ * @arg RCC_SPI23CLKSOURCE_PLL3_Q: SPI23 clock = PLL3Q
+ * @arg RCC_SPI23CLKSOURCE_I2SCKIN: SPI23 clock = I2SCKIN
+ * @arg RCC_SPI23CLKSOURCE_PER: SPI23 clock = PER
+ * @arg RCC_SPI23CLKSOURCE_PLL3_R: SPI23 clock = PLL3R
+ */
+#define __HAL_RCC_GET_SPI23_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC)))
+
+/**
+ * @brief Macro to Configure the SPI45 clock source.
+ * @param __RCC_SPI45CLKSource__: defines the SPI45 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPI45CLKSOURCE_PCLK2: SPI45 clock = PCLK2
+ * @arg RCC_SPI45CLKSOURCE_PLL4: SPI45 clock = PLL4Q
+ * @arg RCC_SPI45CLKSOURCE_HSI: SPI45 clock = HSI
+ * @arg RCC_SPI45CLKSOURCE_CSI: SPI45 clock = CSI
+ * @arg RCC_SPI45CLKSOURCE_HSE: SPI45 clock = HSE
+ * @retval None
+ */
+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ ) \
+ MODIFY_REG(RCC->SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, (uint32_t)(__RCC_SPI45CLKSource__))
+
+/** @brief Macro to get the SPI45 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI45CLKSOURCE_PCLK2: SPI45 clock = PCLK2
+ * @arg RCC_SPI45CLKSOURCE_PLL4: SPI45 clock = PLL4Q
+ * @arg RCC_SPI45CLKSOURCE_HSI: SPI45 clock = HSI
+ * @arg RCC_SPI45CLKSOURCE_CSI: SPI45 clock = CSI
+ * @arg RCC_SPI45CLKSOURCE_HSE: SPI45 clock = HSE
+ */
+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC)))
+
+/**
+ * @brief Macro to Configure the SPI6 clock source.
+ * @param __RCC_SPI6CLKSource__: defines the SPI6 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPI6CLKSOURCE_PCLK5: SPI6 clock = PCLK5
+ * @arg RCC_SPI6CLKSOURCE_PLL4: SPI6 clock = PLL4Q
+ * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
+ * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
+ * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
+ * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3Q
+ * @retval None
+ */
+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ ) \
+ MODIFY_REG(RCC->SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (uint32_t)(__RCC_SPI6CLKSource__))
+
+/** @brief Macro to get the SPI6 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPI6CLKSOURCE_PCLK5: SPI6 clock = PCLK5
+ * @arg RCC_SPI6CLKSOURCE_PLL4: SPI6 clock = PLL4Q
+ * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
+ * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
+ * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
+ * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3Q
+ */
+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC)))
+
+
+/** @brief macro to configure the USART1 clock (USART1CLK).
+ *
+ * @param __USART1CLKSource__: specifies the USART1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USART1CLKSOURCE_PCLK5: PCLK5 Clock selected as USART1 clock (default after reset)
+ * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock USART1
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI Clock selected as USART1 clock USART1
+ * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock USART1
+ * @arg RCC_USART1CLKSOURCE_PLL4: PLL4_Q Clock selected as USART1 clock USART1
+ * @arg RCC_USART1CLKSOURCE_HSE: HSE Clock selected as USART1 clock USART1
+ * @retval None
+ */
+#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
+ MODIFY_REG(RCC->UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (uint32_t)(__USART1CLKSource__))
+
+/** @brief macro to get the USART1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USART1CLKSOURCE_PCLK5: PCLK5 Clock selected as USART1 clock (default after reset)
+ * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_HSI: HSI Clock selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_PLL4: PLL4_Q Clock selected as USART1 clock
+ * @arg RCC_USART1CLKSOURCE_HSE: HSE Clock selected as USART1 clock
+ */
+#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->UART1CKSELR, RCC_UART1CKSELR_UART1SRC)))
+
+/** @brief macro to configure the UART24 clock (UART24CLK).
+ *
+ * @param __UART24CLKSource__: specifies the UART24 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_UART24CLKSOURCE_PCLK1: PCLK1 Clock selected as UART24
+ * clock (default after reset)
+ * @arg RCC_UART24CLKSOURCE_PLL4: PLL4_Q Clock selected as UART24 clock
+ * @arg RCC_UART24CLKSOURCE_HSI: HSI selected as UART24 clock
+ * @arg RCC_UART24CLKSOURCE_CSI: CSI Clock selected as UART24 clock
+ * @arg RCC_UART24CLKSOURCE_HSE: HSE selected as UART24 clock
+ * @retval None
+ */
+#define __HAL_RCC_UART24_CONFIG(__UART24CLKSource__) \
+ MODIFY_REG(RCC->UART24CKSELR, RCC_UART24CKSELR_UART24SRC, (uint32_t)(__UART24CLKSource__))
+
+/** @brief macro to get the UART24 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_UART24CLKSOURCE_PCLK1: PCLK1 Clock selected as UART24 clock
+ * @arg RCC_UART24CLKSOURCE_PLL4: PLL4_Q Clock selected as UART24 clock
+ * @arg RCC_UART24CLKSOURCE_HSI: HSI selected as UART24 clock
+ * @arg RCC_UART24CLKSOURCE_CSI: CSI Clock selected as UART24 clock
+ * @arg RCC_UART24CLKSOURCE_HSE: HSE selected as UART24 clock
+ */
+#define __HAL_RCC_GET_UART24_SOURCE() ((uint32_t)(READ_BIT(RCC->UART24CKSELR, RCC_UART24CKSELR_UART24SRC)))
+
+
+/** @brief macro to configure the UART35 clock (UART35CLK).
+ *
+ * @param __UART35CLKSource__: specifies the UART35 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_UART35CLKSOURCE_PCLK1: PCLK1 Clock selected as UART35
+ * clock (default after reset)
+ * @arg RCC_UART35CLKSOURCE_PLL4: PLL4_Q Clock selected as UART35 clock
+ * @arg RCC_UART35CLKSOURCE_HSI: HSI selected as UART35 clock
+ * @arg RCC_UART35CLKSOURCE_CSI: CSI Clock selected as UART35 clock
+ * @arg RCC_UART35CLKSOURCE_HSE: HSE selected as UART35 clock
+ * @retval None
+ */
+#define __HAL_RCC_UART35_CONFIG(__UART35CLKSource__) \
+ MODIFY_REG(RCC->UART35CKSELR, RCC_UART35CKSELR_UART35SRC, (uint32_t)(__UART35CLKSource__))
+
+/** @brief macro to get the UART35 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_UART35CLKSOURCE_PCLK1: PCLK1 Clock selected as UART35 clock
+ * @arg RCC_UART35CLKSOURCE_PLL4: PLL4_Q Clock selected as UART35 clock
+ * @arg RCC_UART35CLKSOURCE_HSI: HSI selected as UART35 clock
+ * @arg RCC_UART35CLKSOURCE_CSI: CSI Clock selected as UART35 clock
+ * @arg RCC_UART35CLKSOURCE_HSE: HSE selected as UART35 clock
+ */
+#define __HAL_RCC_GET_UART35_SOURCE() ((uint32_t)(READ_BIT(RCC->UART35CKSELR, RCC_UART35CKSELR_UART35SRC)))
+
+
+/** @brief macro to configure the USART6 clock (USART6CLK).
+ *
+ * @param __USART6CLKSource__: specifies the USART6 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USART6CLKSOURCE_PCLK2: PCLK2 Clock selected as USART6 clock (default after reset)
+ * @arg RCC_USART6CLKSOURCE_PLL4: PLL4_Q Clock selected as USART6 clock
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+ * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+ * @arg RCC_USART6CLKSOURCE_HSE: HSE selected as USART6 clock
+ * @retval None
+ */
+#define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \
+ MODIFY_REG(RCC->UART6CKSELR, RCC_UART6CKSELR_UART6SRC, (uint32_t)(__USART6CLKSource__))
+
+/** @brief macro to get the USART6 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USART6CLKSOURCE_PCLK2: PCLK2 Clock selected as USART6 clock
+ * @arg RCC_USART6CLKSOURCE_PLL4: PLL4_Q Clock selected as USART6 clock
+ * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
+ * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
+ * @arg RCC_USART6CLKSOURCE_HSE: HSE selected as USART6 clock
+ */
+#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->UART6CKSELR, RCC_UART6CKSELR_UART6SRC)))
+
+/** @brief macro to configure the UART78clock (UART78CLK).
+ *
+ * @param __UART78CLKSource__: specifies the UART78 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_UART78CLKSOURCE_PCLK1: PCLK1 Clock selected as UART78 clock (default after reset)
+ * @arg RCC_UART78CLKSOURCE_PLL4: PLL4_Q Clock selected as UART78 clock
+ * @arg RCC_UART78CLKSOURCE_HSI: HSI selected as UART78 clock
+ * @arg RCC_UART78CLKSOURCE_CSI: CSI Clock selected as UART78 clock
+ * @arg RCC_UART78CLKSOURCE_HSE: HSE selected as UART78 clock
+ * @retval None
+ */
+#define __HAL_RCC_UART78_CONFIG(__UART78CLKSource__) \
+ MODIFY_REG(RCC->UART78CKSELR, RCC_UART78CKSELR_UART78SRC, (uint32_t)(__UART78CLKSource__))
+
+/** @brief macro to get the UART78 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_UART78CLKSOURCE_PCLK1: PCLK1 Clock selected as UART78 clock
+ * @arg RCC_UART78CLKSOURCE_PLL4: PLL4_Q Clock selected as UART78 clock
+ * @arg RCC_UART78CLKSOURCE_HSI: HSI selected as UART78 clock
+ * @arg RCC_UART78CLKSOURCE_CSI: CSI Clock selected as UART78 clock
+ * @arg RCC_UART78CLKSOURCE_HSE: HSE selected as UART78 clock
+ */
+#define __HAL_RCC_GET_UART78_SOURCE() ((uint32_t)(READ_BIT(RCC->UART78CKSELR, RCC_UART78CKSELR_UART78SRC)))
+
+/** @brief macro to configure the SDMMC12 clock (SDMMC12CLK).
+ *
+ * @param __SDMMC12CLKSource__: specifies the SDMMC12 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDMMC12CLKSOURCE_HCLK6: HCLK6 Clock selected as SDMMC12 clock (default after reset)
+ * @arg RCC_SDMMC12CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC12 clock
+ * @arg RCC_SDMMC12CLKSOURCE_PLL4: PLL4_P selected as SDMMC12 clock
+ * @arg RCC_SDMMC12CLKSOURCE_HSI: HSI selected as SDMMC12 clock
+ * @retval None
+ */
+#define __HAL_RCC_SDMMC12_CONFIG(__SDMMC12CLKSource__) \
+ MODIFY_REG(RCC->SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, (uint32_t)(__SDMMC12CLKSource__))
+
+/** @brief macro to get the SDMMC12 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDMMC12CLKSOURCE_HCLK6: HCLK6 Clock selected as SDMMC12 clock (default after reset)
+ * @arg RCC_SDMMC12CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC12 clock
+ * @arg RCC_SDMMC12CLKSOURCE_PLL4: PLL4_P selected as SDMMC12 clock
+ * @arg RCC_SDMMC12CLKSOURCE_HSI: HSI selected as SDMMC12 clock
+ */
+#define __HAL_RCC_GET_SDMMC12_SOURCE() ((uint32_t)(READ_BIT(RCC->SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC)))
+
+
+/** @brief macro to configure the SDMMC3 clock (SDMMC3CLK).
+ *
+ * @param __SDMMC3CLKSource__: specifies the SDMMC3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDMMC3CLKSOURCE_HCLK2: HCLK2 Clock selected as SDMMC3 clock (default after reset)
+ * @arg RCC_SDMMC3CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC3 clock
+ * @arg RCC_SDMMC3CLKSOURCE_PLL4: PLL4_P selected as SDMMC3 clock
+ * @arg RCC_SDMMC3CLKSOURCE_HSI: HSI selected as SDMMC3 clock
+ *
+ * @retval None
+ */
+#define __HAL_RCC_SDMMC3_CONFIG(__SDMMC3CLKSource__) \
+ MODIFY_REG(RCC->SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, (uint32_t)(__SDMMC3CLKSource__))
+
+/** @brief macro to get the SDMMC3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SDMMC3CLKSOURCE_HCLK2: HCLK2 Clock selected as SDMMC3 clock (default after reset)
+ * @arg RCC_SDMMC3CLKSOURCE_PLL3: PLL3_R Clock selected as SDMMC3 clock
+ * @arg RCC_SDMMC3CLKSOURCE_PLL4: PLL4_P selected as SDMMC3 clock
+ * @arg RCC_SDMMC3CLKSOURCE_HSI: HSI selected as SDMMC3 clock
+ */
+#define __HAL_RCC_GET_SDMMC3_SOURCE() ((uint32_t)(READ_BIT(RCC->SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC)))
+
+
+/** @brief macro to configure the ETH clock (ETHCLK).
+ *
+ * @param __ETHCLKSource__: specifies the ETH clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_ETHCLKSOURCE_PLL4: PLL4_P selected as ETH clock (default after reset)
+ * @arg RCC_ETHCLKSOURCE_PLL3: PLL3_Q Clock selected as ETH clock
+ * @arg RCC_ETHCLKSOURCE_OFF: the kernel clock is disabled
+ * @retval None
+ */
+#define __HAL_RCC_ETH_CONFIG(__ETHCLKSource__) \
+ MODIFY_REG(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC, (uint32_t)(__ETHCLKSource__))
+
+/** @brief macro to get the ETH clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_ETHCLKSOURCE_PLL4: PLL4_P selected as ETH clock (default after reset)
+ * @arg RCC_ETHCLKSOURCE_PLL3: PLL3_Q Clock selected as ETH clock
+ * @arg RCC_ETHCLKSOURCE_OFF: the kernel clock is disabled
+ */
+#define __HAL_RCC_GET_ETH_SOURCE() ((uint32_t)(READ_BIT(RCC->ETHCKSELR, RCC_ETHCKSELR_ETHSRC)))
+
+
+/** @brief macro to configure the QSPI clock (QSPICLK).
+ *
+ * @param __QSPICLKSource__: specifies the QSPI clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_QSPICLKSOURCE_ACLK: ACLK Clock selected as QSPI clock (default after reset)
+ * @arg RCC_QSPICLKSOURCE_PLL3: PLL3_R Clock selected as QSPI clock
+ * @arg RCC_QSPICLKSOURCE_PLL4: PLL4_P selected as QSPI clock
+ * @arg RCC_QSPICLKSOURCE_PER: PER selected as QSPI clock
+ * @retval None
+ */
+#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
+ MODIFY_REG(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC, (uint32_t)(__QSPICLKSource__))
+
+/** @brief macro to get the QSPI clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_QSPICLKSOURCE_ACLK: ACLK Clock selected as QSPI clock (default after reset)
+ * @arg RCC_QSPICLKSOURCE_PLL3: PLL3_R Clock selected as QSPI clock
+ * @arg RCC_QSPICLKSOURCE_PLL4: PLL4_P selected as QSPI clock
+ * @arg RCC_QSPICLKSOURCE_PER: PER selected as QSPI clock
+ */
+#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->QSPICKSELR, RCC_QSPICKSELR_QSPISRC)))
+
+
+/** @brief macro to configure the FMC clock (FMCCLK).
+ *
+ * @param __FMCCLKSource__: specifies the FMC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMCCLKSOURCE_ACLK: ACLK Clock selected as FMC clock (default after reset)
+ * @arg RCC_FMCCLKSOURCE_PLL3: PLL3_R Clock selected as FMC clock
+ * @arg RCC_FMCCLKSOURCE_PLL4: PLL4_P selected as FMC clock
+ * @arg RCC_FMCCLKSOURCE_PER: PER selected as FMC clock
+ * @retval None
+ */
+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
+ MODIFY_REG(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC, (uint32_t)(__FMCCLKSource__))
+
+/** @brief macro to get the FMC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FMCCLKSOURCE_ACLK: ACLK Clock selected as FMC clock (default after reset)
+ * @arg RCC_FMCCLKSOURCE_PLL3: PLL3_R Clock selected as FMC clock
+ * @arg RCC_FMCCLKSOURCE_PLL4: PLL4_P selected as FMC clock
+ * @arg RCC_FMCCLKSOURCE_PER: PER selected as FMC clock
+ */
+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->FMCCKSELR, RCC_FMCCKSELR_FMCSRC)))
+
+#if defined(FDCAN1)
+/** @brief macro to configure the FDCAN clock (FDCANCLK).
+ *
+ * @param __FDCANCLKSource__: specifies the FDCAN clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FDCANCLKSOURCE_HSE: HSE Clock selected as FDCAN clock (default after reset)
+ * @arg RCC_FDCANCLKSOURCE_PLL3: PLL3_Q Clock selected as FDCAN clock
+ * @arg RCC_FDCANCLKSOURCE_PLL4_Q: PLL4_Q selected as FDCAN clock
+ * @arg RCC_FDCANCLKSOURCE_PLL4_R: PLL4_R selected as FDCAN clock
+ * @retval None
+ */
+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
+ MODIFY_REG(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC, (uint32_t)(__FDCANCLKSource__))
+
+/** @brief macro to get the FDCAN clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_FDCANCLKSOURCE_HSE: HSE Clock selected as FDCAN clock (default after reset)
+ * @arg RCC_FDCANCLKSOURCE_PLL3: PLL3_Q Clock selected as FDCAN clock
+ * @arg RCC_FDCANCLKSOURCE_PLL4_Q: PLL4_Q selected as FDCAN clock
+ * @arg RCC_FDCANCLKSOURCE_PLL4_R: PLL4_R selected as FDCAN clock
+ */
+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->FDCANCKSELR, RCC_FDCANCKSELR_FDCANSRC)))
+#endif /*FDCAN1*/
+
+/** @brief macro to configure the SPDIFRX clock (SPDIFCLK).
+ *
+ * @param __SPDIFCLKSource__: specifies the SPDIF clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLL4: PLL4_P Clock selected as SPDIF clock (default after reset)
+ * @arg RCC_SPDIFRXCLKSOURCE_PLL3: PLL3_Q Clock selected as SPDIF clock
+ * @arg RCC_SPDIFRXCLKSOURCE_HSI: HSI selected as SPDIF clock
+ * @retval None
+ */
+#define __HAL_RCC_SPDIFRX_CONFIG(__SPDIFCLKSource__) \
+ MODIFY_REG(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC, (uint32_t)(__SPDIFCLKSource__))
+
+/** @brief macro to get the SPDIFRX clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSOURCE_PLL4: PLL4_P Clock selected as SPDIF clock (default after reset)
+ * @arg RCC_SPDIFRXCLKSOURCE_PLL3: PLL3_Q Clock selected as SPDIF clock
+ * @arg RCC_SPDIFRXCLKSOURCE_HSI: HSI selected as SPDIF clock
+ */
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->SPDIFCKSELR, RCC_SPDIFCKSELR_SPDIFSRC)))
+
+
+/** @brief macro to configure the CEC clock (CECCLK).
+ *
+ * @param __CECCLKSource__: specifies the CEC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_LSE: LSE Clock selected as CEC clock (default after reset)
+ * @arg RCC_CECCLKSOURCE_LSI: LSI Clock selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_CSI122: CSI/122 Clock selected as CEC clock
+ * @retval None
+ */
+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
+ MODIFY_REG(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC, (uint32_t)(__CECCLKSource__))
+
+/** @brief macro to get the CEC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CECCLKSOURCE_LSE: LSE Clock selected as CEC clock (default after reset)
+ * @arg RCC_CECCLKSOURCE_LSI: LSI Clock selected as CEC clock
+ * @arg RCC_CECCLKSOURCE_CSI122: CSI/122 Clock selected as CEC clock
+ */
+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CECCKSELR, RCC_CECCKSELR_CECSRC)))
+
+
+/** @brief macro to configure the USB PHY clock (USBPHYCLK).
+ *
+ * @param __USBPHYCLKSource__: specifies the USB PHY clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBPHYCLKSOURCE_HSE: HSE_KER Clock selected as USB PHY clock (default after reset)
+ * @arg RCC_USBPHYCLKSOURCE_PLL4: PLL4_R Clock selected as USB PHY clock
+ * @arg RCC_USBPHYCLKSOURCE_HSE2: HSE_KER/2 Clock selected as USB PHY clock
+ * @retval None
+ */
+#define __HAL_RCC_USBPHY_CONFIG(__USBPHYCLKSource__) \
+ MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC, (uint32_t)(__USBPHYCLKSource__))
+
+/** @brief macro to get the USB PHY PLL clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USBPHYCLKSOURCE_HSE: HSE_KER Clock selected as USB PHY clock (default after reset)
+ * @arg RCC_USBPHYCLKSOURCE_PLL4: PLL4_R Clock selected as USB PHY clock
+ * @arg RCC_USBPHYCLKSOURCE_HSE2: HSE_KER/2 Clock selected as USB PHY clock
+ */
+#define __HAL_RCC_GET_USBPHY_SOURCE() ((uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBPHYSRC)))
+
+
+/** @brief macro to configure the USB OTG clock (USBOCLK).
+ *
+ * @param __USBOCLKSource__: specifies the USB OTG clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBOCLKSOURCE_PLL4: PLL4_R Clock selected as USB OTG clock (default after reset)
+ * @arg RCC_USBOCLKSOURCE_PHY: USB PHY Clock selected as USB OTG clock
+ * @retval None
+ */
+#define __HAL_RCC_USBO_CONFIG(__USBOCLKSource__) \
+ MODIFY_REG(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC, (uint32_t)(__USBOCLKSource__))
+
+/** @brief macro to get the USB OTG PLL clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USBOCLKSOURCE_PLL4: PLL4_R Clock selected as USB OTG clock (default after reset)
+ * @arg RCC_USBOCLKSOURCE_PHY: USB PHY Clock selected as USB OTG clock
+ */
+#define __HAL_RCC_GET_USBO_SOURCE() ((uint32_t)(READ_BIT(RCC->USBCKSELR, RCC_USBCKSELR_USBOSRC)))
+
+
+/** @brief macro to configure the RNG1 clock (RNG1CLK).
+ *
+ * @param __RNG1CLKSource__: specifies the RNG1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RNG1CLKSOURCE_CSI: CSI Clock selected as RNG1 clock (default after reset)
+ * @arg RCC_RNG1CLKSOURCE_PLL4: PLL4_R Clock selected as RNG1 clock
+ * @arg RCC_RNG1CLKSOURCE_LSE: LSE Clock selected as RNG1 clock
+ * @arg RCC_RNG1CLKSOURCE_LSI: LSI Clock selected as RNG1 clock
+ * @retval None
+ */
+#define __HAL_RCC_RNG1_CONFIG(__RNG1CLKSource__) \
+ MODIFY_REG(RCC->RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, (uint32_t)(__RNG1CLKSource__))
+
+/** @brief macro to get the RNG1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_RNG1CLKSOURCE_CSI: CSI Clock selected as RNG1 clock (default after reset)
+ * @arg RCC_RNG1CLKSOURCE_PLL4: PLL4_R Clock selected as RNG1 clock
+ * @arg RCC_RNG1CLKSOURCE_LSE: LSE Clock selected as RNG1 clock
+ * @arg RCC_RNG1CLKSOURCE_LSI: LSI Clock selected as RNG1 clock
+ */
+#define __HAL_RCC_GET_RNG1_SOURCE() ((uint32_t)(READ_BIT(RCC->RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC)))
+
+
+/** @brief macro to configure the RNG2 clock (RNG2CLK).
+ *
+ * @param __RNG2CLKSource__: specifies the RNG2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RNG2CLKSOURCE_CSI: CSI Clock selected as RNG2 clock (default after reset)
+ * @arg RCC_RNG2CLKSOURCE_PLL4: PLL4_R Clock selected as RNG2 clock
+ * @arg RCC_RNG2CLKSOURCE_LSE: LSE Clock selected as RNG2 clock
+ * @arg RCC_RNG2CLKSOURCE_LSI: LSI Clock selected as RNG2 clock
+ * @retval None
+ */
+#define __HAL_RCC_RNG2_CONFIG(__RNG2CLKSource__) \
+ MODIFY_REG(RCC->RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, (uint32_t)(__RNG2CLKSource__))
+
+/** @brief macro to get the RNG2 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_RNG2CLKSOURCE_CSI: CSI Clock selected as RNG2 clock (default after reset)
+ * @arg RCC_RNG2CLKSOURCE_PLL4: PLL4_R Clock selected as RNG2 clock
+ * @arg RCC_RNG2CLKSOURCE_LSE: LSE Clock selected as RNG2 clock
+ * @arg RCC_RNG2CLKSOURCE_LSI: LSI Clock selected as RNG2 clock
+ */
+#define __HAL_RCC_GET_RNG2_SOURCE() ((uint32_t)(READ_BIT(RCC->RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC)))
+
+
+/** @brief macro to configure the CK_PER clock (CK_PERCLK).
+ *
+ * @param __CKPERCLKSource__: specifies the CPER clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CKPERCLKSOURCE_HSI: HSI Clock selected as CK_PER clock (default after reset)
+ * @arg RCC_CKPERCLKSOURCE_CSI: CSI Clock selected as CK_PER clock
+ * @arg RCC_CKPERCLKSOURCE_HSE: HSE Clock selected as CK_PER clock
+ * @arg RCC_CKPERCLKSOURCE_OFF: Clock disabled for CK_PER
+ * @retval None
+ */
+#define __HAL_RCC_CKPER_CONFIG(__CKPERCLKSource__) \
+ MODIFY_REG(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC, (uint32_t)(__CKPERCLKSource__))
+
+/** @brief macro to get the CPER clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_CKPERCLKSOURCE_HSI: HSI Clock selected as CK_PER clock (default after reset)
+ * @arg RCC_CKPERCLKSOURCE_CSI: CSI Clock selected as CK_PER clock
+ * @arg RCC_CKPERCLKSOURCE_HSE: HSE Clock selected as CK_PER clock
+ * @arg RCC_CKPERCLKSOURCE_OFF: Clock disabled for CK_PER
+ */
+#define __HAL_RCC_GET_CKPER_SOURCE() ((uint32_t)(READ_BIT(RCC->CPERCKSELR, RCC_CPERCKSELR_CKPERSRC)))
+
+
+/** @brief macro to configure the STGEN clock (STGENCLK).
+ *
+ * @param __STGENCLKSource__: specifies the STGEN clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_STGENCLKSOURCE_HSI: HSI Clock selected as STGEN clock (default after reset)
+ * @arg RCC_STGENCLKSOURCE_HSE: HSE Clock selected as STGEN clock
+ * @arg RCC_STGENCLKSOURCE_OFF: Clock disabled
+ *
+ * @retval None
+ */
+#define __HAL_RCC_STGEN_CONFIG(__STGENCLKSource__) \
+ MODIFY_REG(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC, (uint32_t)(__STGENCLKSource__))
+
+/** @brief macro to get the STGEN clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_STGENCLKSOURCE_HSI: HSI Clock selected as STGEN clock (default after reset)
+ * @arg RCC_STGENCLKSOURCE_HSE: HSE Clock selected as STGEN clock
+ * @arg RCC_STGENCLKSOURCE_OFF: Clock disabled
+ */
+#define __HAL_RCC_GET_STGEN_SOURCE() ((uint32_t)(READ_BIT(RCC->STGENCKSELR, RCC_STGENCKSELR_STGENSRC)))
+
+#if defined(DSI)
+/** @brief macro to configure the DSI clock (DSICLK).
+ *
+ * @param __DSICLKSource__: specifies the DSI clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DSICLKSOURCE_PHY: DSIHOST clock from PHY is selected as DSI byte lane clock (default after reset)
+ * @arg RCC_DSICLKSOURCE_PLL4: PLL4_P Clock selected as DSI byte lane clock
+ * @retval None
+ */
+#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
+ MODIFY_REG(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC, (uint32_t)(__DSICLKSource__))
+
+/** @brief macro to get the DSI clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_DSICLKSOURCE_PHY: DSIHOST clock from PHY is selected as DSI byte lane clock (default after reset)
+ * @arg RCC_DSICLKSOURCE_PLL4: PLL4_P Clock selected as DSI byte lane clock
+ */
+#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->DSICKSELR, RCC_DSICKSELR_DSISRC)))
+#endif /*DSI*/
+
+/** @brief macro to configure the ADC clock (ADCCLK).
+ *
+ * @param __ADCCLKSource__: specifies the ADC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_ADCCLKSOURCE_PLL4: PLL4_R Clock selected as ADC clock (default after reset)
+ * @arg RCC_ADCCLKSOURCE_PER: PER Clock selected as ADC clock
+ * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_Q Clock selected as ADC clock
+ * @retval None
+ */
+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
+ MODIFY_REG(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC, (uint32_t)(__ADCCLKSource__))
+
+/** @brief macro to get the ADC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_ADCCLKSOURCE_PLL4: PLL4_R Clock selected as ADC clock (default after reset)
+ * @arg RCC_ADCCLKSOURCE_PER: PER Clock selected as ADC clock
+ * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_Q Clock selected as ADC clock
+ */
+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->ADCCKSELR, RCC_ADCCKSELR_ADCSRC)))
+
+
+/** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
+ *
+ * @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 Clock selected as LPTIM1 clock (default after reset)
+ * @arg RCC_LPTIM1CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_PER: PER Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_OFF: The kernel clock is disabled
+ *
+ * @retval None
+ */
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
+ MODIFY_REG(RCC->LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (uint32_t)(__LPTIM1CLKSource__))
+
+/** @brief macro to get the LPTIM1 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 Clock selected as LPTIM1 clock (default after reset)
+ * @arg RCC_LPTIM1CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_PER: PER Clock selected as LPTIM1 clock
+ * @arg RCC_LPTIM1CLKSOURCE_OFF: The kernel clock is disabled
+ */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC)))
+
+/** @brief macro to configure the LPTIM23 clock (LPTIM23CLK).
+ *
+ * @param __LPTIM23CLKSource__: specifies the LPTIM23 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM23CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM23 clock (default after reset)
+ * @arg RCC_LPTIM23CLKSOURCE_PLL4: PLL4_Q Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_PER: PER Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_LSE: LSE Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_LSI: LSI Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_OFF: The kernel clock is disabled
+ * @retval None
+ */
+#define __HAL_RCC_LPTIM23_CONFIG(__LPTIM23CLKSource__) \
+ MODIFY_REG(RCC->LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (uint32_t)(__LPTIM23CLKSource__))
+
+/** @brief macro to get the LPTIM23 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_LPTIM23CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM23 clock (default after reset)
+ * @arg RCC_LPTIM23CLKSOURCE_PLL4: PLL4_Q Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_PER: PER Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_LSE: LSE Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_LSI: LSI Clock selected as LPTIM23 clock
+ * @arg RCC_LPTIM23CLKSOURCE_OFF: The kernel clock is disabled
+ */
+#define __HAL_RCC_GET_LPTIM23_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC)))
+
+/** @brief macro to configure the LPTIM45 clock (LPTIM45CLK).
+ *
+ * @param __LPTIM45CLKSource__: specifies the LPTIM45 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM45CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM45 clock (default after reset)
+ * @arg RCC_LPTIM45CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_LSE: LSE Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_LSI: LSI Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_PER: PER Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_OFF: The kernel clock is disabled
+ * @retval None
+ */
+#define __HAL_RCC_LPTIM45_CONFIG(__LPTIM45CLKSource__) \
+ MODIFY_REG(RCC->LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (uint32_t)(__LPTIM45CLKSource__))
+
+/** @brief macro to get the LPTIM45 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_LPTIM45CLKSOURCE_PCLK3: PCLK3 Clock selected as LPTIM45 clock (default after reset)
+ * @arg RCC_LPTIM45CLKSOURCE_PLL4: PLL4_P Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_PLL3: PLL3_Q Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_LSE: LSE Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_LSI: LSI Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_PER: PER Clock selected as LPTIM45 clock
+ * @arg RCC_LPTIM45CLKSOURCE_OFF: The kernel clock is disabled
+ */
+#define __HAL_RCC_GET_LPTIM45_SOURCE() ((uint32_t)(READ_BIT(RCC->LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC)))
+
+
+
+/**
+ * @brief Macro to set the APB1 timer clock prescaler
+ * @note Set and reset by software to control the clock frequency of all the timers connected to APB1 domain.
+ * It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14.
+ * @param __RCC_TIMG1PRES__: specifies the Timers clocks prescaler selection
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMG1PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding
+ * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset)
+ * @arg RCC_TIMG1PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding
+ * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1
+ */
+#define __HAL_RCC_TIMG1PRES(__RCC_TIMG1PRES__) \
+ do{ MODIFY_REG( RCC->TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE , __RCC_TIMG1PRES__ );\
+ } while(0)
+
+/** @brief Macro to get the APB1 timer clock prescaler.
+ * @retval The APB1 timer clock prescaler. The returned value can be one
+ * of the following:
+ * - RCC_TIMG1PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding
+ * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset)
+ * - RCC_TIMG1PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB1DIV is corresponding
+ * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1
+ */
+#define __HAL_RCC_GET_TIMG1PRES() ((uint32_t)(RCC->TIMG1PRER & RCC_TIMG1PRER_TIMG1PRE))
+
+/**
+ * @brief Macro to set the APB2 timers clocks prescaler
+ * @note Set and reset by software to control the clock frequency of all the timers connected to APB2 domain.
+ * It concerns TIM1, TIM8, TIM15, TIM16, and TIM17.
+ * @param __RCC_TIMG2PRES__: specifies the timers clocks prescaler selection
+ * This parameter can be one of the following values:
+ * @arg RCC_TIMG2PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding
+ * to a division by 1 or 2, else it is equal to 2 x Fck_pclk2 (default after reset)
+ * @arg RCC_TIMG2PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding
+ * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1
+ */
+#define __HAL_RCC_TIMG2PRES(__RCC_TIMG2PRES__) \
+ do{ MODIFY_REG( RCC->TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE , __RCC_TIMG2PRES__ );\
+ } while(0)
+
+/** @brief Macro to get the APB2 timer clock prescaler.
+ * @retval The APB2 timer clock prescaler. The returned value can be one
+ * of the following:
+ * - RCC_TIMG2PRES_DEACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding
+ * to a division by 1 or 2, else it is equal to 2 x Fck_pclk1 (default after reset)
+ * - RCC_TIMG2PRES_ACTIVATED: The Timers kernel clock is equal to ck_hclk if APB2DIV is corresponding
+ * to division by 1, 2 or 4, else it is equal to 4 x Fck_pclk1
+ */
+#define __HAL_RCC_GET_TIMG2PRES() ((uint32_t)(RCC->TIMG2PRER & RCC_TIMG2PRER_TIMG2PRE))
+
+
+
+#define USB_PHY_VALUE ((uint32_t)48000000) /*!< Value of the USB_PHY_VALUE signal in Hz
+ It is equal to rcc_hsphy_CLK_48M which is
+ a constant value */
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk);
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
+HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLLInitTypeDef *pll2);
+HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLLInitTypeDef *pll3);
+HAL_StatusTypeDef RCCEx_PLL4_Config(RCC_PLLInitTypeDef *pll4);
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group2
+ * @{
+ */
+
+void HAL_RCCEx_EnableLSECSS(void);
+void HAL_RCCEx_DisableLSECSS(void);
+
+#ifdef CORE_CA7
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
+void HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx);
+void HAL_RCCEx_HoldBootMCU(void);
+void HAL_RCCEx_BootMCU(void);
+#endif /* CORE_CA7 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_RCC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
new file mode 100644
index 0000000..11d8982
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
@@ -0,0 +1,1092 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_spi.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_SPI_H
+#define STM32MP1xx_HAL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+ * @{
+ */
+
+/**
+ * @brief SPI Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_Mode */
+
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ This parameter can be a value of @ref SPI_Direction */
+
+ uint32_t DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_Data_Size */
+
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_Management */
+
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
+
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
+ This parameter can be a value of @ref SPI_TI_Mode */
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_CRC_Calculation */
+
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
+
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ This parameter can be a value of @ref SPI_CRC_length */
+
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ This parameter can be a value of @ref SPI_NSSP_Mode
+ This mode is activated by the SSOM bit in the SPIx_CR2 register and
+ it takes effect only if the SPI interface is configured as Motorola SPI
+ master (FRF=0). */
+
+ uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is
+ considered as active one.
+ This parameter can be a value of @ref SPI_NSS_Polarity */
+
+ uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref SPI_Fifo_Threshold */
+
+ uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
+ This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
+
+ uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
+ This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
+
+ uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
+ additionally between active edge of SS and first data transaction start in master mode.
+ This parameter can be a value of @ref SPI_Master_SS_Idleness */
+
+ uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
+ two consecutive data frames in master mode
+ This parameter can be a value of @ref SPI_Master_InterData_Idleness */
+
+ uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management
+ in order to avoid overrun condition.
+ This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
+
+ uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
+ This parameter can be a value of @ref SPI_Master_Keep_IO_State */
+
+ uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
+ This parameter can be a value of @ref SPI_IO_Swap */
+
+} SPI_InitTypeDef;
+
+/**
+ * @brief HAL SPI State structure definition
+ */
+typedef enum
+{
+ HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */
+} HAL_SPI_StateTypeDef;
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+/**
+ * @brief SPI Reload Structure definition
+ */
+typedef struct
+{
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size to reload */
+
+ uint32_t Requested; /*!< SPI reload request */
+
+} SPI_ReloadTypeDef;
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+/**
+ * @brief SPI handle Structure definition
+ */
+typedef struct __SPI_HandleTypeDef
+{
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
+
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
+
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
+
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
+
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
+#ifdef HAL_DMA_MODULE_ENABLED
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
+#endif
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
+
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+
+ SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */
+
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
+ void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
+ void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
+ void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
+ void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
+ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
+ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
+ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
+ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+} SPI_HandleTypeDef;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+/**
+ * @brief HAL SPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */
+ HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */
+ HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */
+ HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */
+ HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */
+ HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */
+ HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */
+ HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */
+ HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */
+ HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */
+
+} HAL_SPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SPI Callback pointer definition
+ */
+typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_FIFO_Type SPI FIFO Type
+ * @{
+ */
+#define SPI_LOWEND_FIFO_SIZE 8UL
+#define SPI_HIGHEND_FIFO_SIZE 16UL
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Error_Code SPI Error Codes
+ * @{
+ */
+#define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */
+#define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */
+#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */
+#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */
+#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknow error */
+#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Mode SPI Mode
+ * @{
+ */
+#define SPI_MODE_SLAVE (0x00000000UL)
+#define SPI_MODE_MASTER SPI_CFG2_MASTER
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+ * @{
+ */
+#define SPI_DIRECTION_2LINES (0x00000000UL)
+#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
+#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
+#define SPI_DIRECTION_1LINE SPI_CFG2_COMM
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+ * @{
+ */
+#define SPI_DATASIZE_4BIT (0x00000003UL)
+#define SPI_DATASIZE_5BIT (0x00000004UL)
+#define SPI_DATASIZE_6BIT (0x00000005UL)
+#define SPI_DATASIZE_7BIT (0x00000006UL)
+#define SPI_DATASIZE_8BIT (0x00000007UL)
+#define SPI_DATASIZE_9BIT (0x00000008UL)
+#define SPI_DATASIZE_10BIT (0x00000009UL)
+#define SPI_DATASIZE_11BIT (0x0000000AUL)
+#define SPI_DATASIZE_12BIT (0x0000000BUL)
+#define SPI_DATASIZE_13BIT (0x0000000CUL)
+#define SPI_DATASIZE_14BIT (0x0000000DUL)
+#define SPI_DATASIZE_15BIT (0x0000000EUL)
+#define SPI_DATASIZE_16BIT (0x0000000FUL)
+#define SPI_DATASIZE_17BIT (0x00000010UL)
+#define SPI_DATASIZE_18BIT (0x00000011UL)
+#define SPI_DATASIZE_19BIT (0x00000012UL)
+#define SPI_DATASIZE_20BIT (0x00000013UL)
+#define SPI_DATASIZE_21BIT (0x00000014UL)
+#define SPI_DATASIZE_22BIT (0x00000015UL)
+#define SPI_DATASIZE_23BIT (0x00000016UL)
+#define SPI_DATASIZE_24BIT (0x00000017UL)
+#define SPI_DATASIZE_25BIT (0x00000018UL)
+#define SPI_DATASIZE_26BIT (0x00000019UL)
+#define SPI_DATASIZE_27BIT (0x0000001AUL)
+#define SPI_DATASIZE_28BIT (0x0000001BUL)
+#define SPI_DATASIZE_29BIT (0x0000001CUL)
+#define SPI_DATASIZE_30BIT (0x0000001DUL)
+#define SPI_DATASIZE_31BIT (0x0000001EUL)
+#define SPI_DATASIZE_32BIT (0x0000001FUL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+ * @{
+ */
+#define SPI_POLARITY_LOW (0x00000000UL)
+#define SPI_POLARITY_HIGH SPI_CFG2_CPOL
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+ * @{
+ */
+#define SPI_PHASE_1EDGE (0x00000000UL)
+#define SPI_PHASE_2EDGE SPI_CFG2_CPHA
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
+ * @{
+ */
+#define SPI_NSS_SOFT SPI_CFG2_SSM
+#define SPI_NSS_HARD_INPUT (0x00000000UL)
+#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+ * @{
+ */
+#define SPI_NSS_PULSE_DISABLE (0x00000000UL)
+#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+ * @{
+ */
+#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
+#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
+#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
+#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
+#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
+#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
+#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
+#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
+ * @{
+ */
+#define SPI_FIRSTBIT_MSB (0x00000000UL)
+#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
+/**
+ * @}
+ */
+
+/** @defgroup SPI_TI_Mode SPI TI Mode
+ * @{
+ */
+#define SPI_TIMODE_DISABLE (0x00000000UL)
+#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+ * @{
+ */
+#define SPI_CRCCALCULATION_DISABLE (0x00000000UL)
+#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+ * @{
+ */
+#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
+#define SPI_CRC_LENGTH_4BIT (0x00030000UL)
+#define SPI_CRC_LENGTH_5BIT (0x00040000UL)
+#define SPI_CRC_LENGTH_6BIT (0x00050000UL)
+#define SPI_CRC_LENGTH_7BIT (0x00060000UL)
+#define SPI_CRC_LENGTH_8BIT (0x00070000UL)
+#define SPI_CRC_LENGTH_9BIT (0x00080000UL)
+#define SPI_CRC_LENGTH_10BIT (0x00090000UL)
+#define SPI_CRC_LENGTH_11BIT (0x000A0000UL)
+#define SPI_CRC_LENGTH_12BIT (0x000B0000UL)
+#define SPI_CRC_LENGTH_13BIT (0x000C0000UL)
+#define SPI_CRC_LENGTH_14BIT (0x000D0000UL)
+#define SPI_CRC_LENGTH_15BIT (0x000E0000UL)
+#define SPI_CRC_LENGTH_16BIT (0x000F0000UL)
+#define SPI_CRC_LENGTH_17BIT (0x00100000UL)
+#define SPI_CRC_LENGTH_18BIT (0x00110000UL)
+#define SPI_CRC_LENGTH_19BIT (0x00120000UL)
+#define SPI_CRC_LENGTH_20BIT (0x00130000UL)
+#define SPI_CRC_LENGTH_21BIT (0x00140000UL)
+#define SPI_CRC_LENGTH_22BIT (0x00150000UL)
+#define SPI_CRC_LENGTH_23BIT (0x00160000UL)
+#define SPI_CRC_LENGTH_24BIT (0x00170000UL)
+#define SPI_CRC_LENGTH_25BIT (0x00180000UL)
+#define SPI_CRC_LENGTH_26BIT (0x00190000UL)
+#define SPI_CRC_LENGTH_27BIT (0x001A0000UL)
+#define SPI_CRC_LENGTH_28BIT (0x001B0000UL)
+#define SPI_CRC_LENGTH_29BIT (0x001C0000UL)
+#define SPI_CRC_LENGTH_30BIT (0x001D0000UL)
+#define SPI_CRC_LENGTH_31BIT (0x001E0000UL)
+#define SPI_CRC_LENGTH_32BIT (0x001F0000UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
+ * @{
+ */
+#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
+#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
+#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
+#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
+#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
+#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
+#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
+#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
+#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
+#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
+#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
+#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
+#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
+#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
+#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
+#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
+ * @{
+ */
+#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
+#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSS_Polarity SPI NSS Polarity
+ * @{
+ */
+#define SPI_NSS_POLARITY_LOW (0x00000000UL)
+#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_Keep_IO_State Keep IO State
+ * @{
+ */
+#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
+#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
+/**
+ * @}
+ */
+
+/** @defgroup SPI_IO_Swap Control SPI IO Swap
+ * @{
+ */
+#define SPI_IO_SWAP_DISABLE (0x00000000UL)
+#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness
+ * @{
+ */
+#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
+#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
+#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
+#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
+#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
+#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
+#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
+#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
+#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
+#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
+#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
+#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
+#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
+#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
+#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
+#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness
+ * @{
+ */
+#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
+#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
+ * @{
+ */
+#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
+#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
+ * @{
+ */
+#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
+#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
+#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
+ * @{
+ */
+#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
+#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
+#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
+ * @{
+ */
+#define SPI_IT_RXP SPI_IER_RXPIE
+#define SPI_IT_TXP SPI_IER_TXPIE
+#define SPI_IT_DXP SPI_IER_DXPIE
+#define SPI_IT_EOT SPI_IER_EOTIE
+#define SPI_IT_TXTF SPI_IER_TXTFIE
+#define SPI_IT_UDR SPI_IER_UDRIE
+#define SPI_IT_OVR SPI_IER_OVRIE
+#define SPI_IT_CRCERR SPI_IER_CRCEIE
+#define SPI_IT_FRE SPI_IER_TIFREIE
+#define SPI_IT_MODF SPI_IER_MODFIE
+#define SPI_IT_TSERF SPI_IER_TSERFIE
+#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Flags_definition SPI Flags Definition
+ * @{
+ */
+#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
+#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
+#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
+#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
+#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
+#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
+#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
+#define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
+#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
+#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
+#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
+#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+ * @{
+ */
+#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
+#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
+#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
+#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @retval None
+ */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif
+
+/** @brief Enable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_RXP : Rx-Packet available interrupt
+ * @arg SPI_IT_TXP : Tx-Packet space available interrupt
+ * @arg SPI_IT_DXP : Duplex Packet interrupt
+ * @arg SPI_IT_EOT : End of transfer interrupt
+ * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
+ * @arg SPI_IT_UDR : Underrun interrupt
+ * @arg SPI_IT_OVR : Overrun interrupt
+ * @arg SPI_IT_CRCERR : CRC error interrupt
+ * @arg SPI_IT_FRE : TI mode frame format error interrupt
+ * @arg SPI_IT_MODF : Mode fault interrupt
+ * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
+ * @arg SPI_IT_ERR : Error interrupt
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_RXP : Rx-Packet available interrupt
+ * @arg SPI_IT_TXP : Tx-Packet space available interrupt
+ * @arg SPI_IT_DXP : Duplex Packet interrupt
+ * @arg SPI_IT_EOT : End of transfer interrupt
+ * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
+ * @arg SPI_IT_UDR : Underrun interrupt
+ * @arg SPI_IT_OVR : Overrun interrupt
+ * @arg SPI_IT_CRCERR : CRC error interrupt
+ * @arg SPI_IT_FRE : TI mode frame format error interrupt
+ * @arg SPI_IT_MODF : Mode fault interrupt
+ * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
+ * @arg SPI_IT_ERR : Error interrupt
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_RXP : Rx-Packet available interrupt
+ * @arg SPI_IT_TXP : Tx-Packet space available interrupt
+ * @arg SPI_IT_DXP : Duplex Packet interrupt
+ * @arg SPI_IT_EOT : End of transfer interrupt
+ * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
+ * @arg SPI_IT_UDR : Underrun interrupt
+ * @arg SPI_IT_OVR : Overrun interrupt
+ * @arg SPI_IT_CRCERR : CRC error interrupt
+ * @arg SPI_IT_FRE : TI mode frame format error interrupt
+ * @arg SPI_IT_MODF : Mode fault interrupt
+ * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
+ * @arg SPI_IT_ERR : Error interrupt
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXP : Rx-Packet available flag
+ * @arg SPI_FLAG_TXP : Tx-Packet space available flag
+ * @arg SPI_FLAG_DXP : Duplex Packet flag
+ * @arg SPI_FLAG_EOT : End of transfer flag
+ * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag
+ * @arg SPI_FLAG_UDR : Underrun flag
+ * @arg SPI_FLAG_OVR : Overrun flag
+ * @arg SPI_FLAG_CRCERR : CRC error flag
+ * @arg SPI_FLAG_FRE : TI mode frame format error flag
+ * @arg SPI_FLAG_MODF : Mode fault flag
+ * @arg SPI_FLAG_TSERF : Additional number of data reloaded flag
+ * @arg SPI_FLAG_SUSP : Transfer suspend complete flag
+ * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag
+ * @arg SPI_FLAG_FRLVL : Fifo reception level flag
+ * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
+
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
+
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
+
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
+
+/** @brief Clear the SPI UDR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
+
+/** @brief Clear the SPI EOT pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
+
+/** @brief Clear the SPI UDR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
+
+/** @brief Clear the SPI SUSP pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
+
+/** @brief Clear the SPI TSERF pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
+
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
+
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
+/**
+ * @}
+ */
+
+
+/* Include SPI HAL Extension module */
+#include "stm32mp1xx_hal_spi_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @{
+ */
+
+/* Peripheral State and Error functions ***************************************/
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
+ ((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
+ ((MODE) == SPI_DIRECTION_2LINES)|| \
+ ((MODE) == SPI_DIRECTION_1LINE) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_31BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_30BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_29BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_28BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_27BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_26BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_25BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_24BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_23BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_22BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_21BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_20BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_22BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_19BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_18BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_17BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_9BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_7BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_6BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_5BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
+ ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+ ((NSSP) == SPI_NSS_PULSE_DISABLE))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+ ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
+ ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
+
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
+ ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
+ ((LENGTH) == SPI_CRC_LENGTH_4BIT))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
+
+#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
+ ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
+ ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
+
+#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
+ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
+ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_SPI_H */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h
new file mode 100644
index 0000000..1bd7fc2
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi_ex.h
@@ -0,0 +1,77 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_spi_ex.h
+ * @author MCD Application Team
+ * @brief Header file of SPI HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_SPI_EX_H
+#define STM32MP1xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup SPIEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_SPI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
new file mode 100644
index 0000000..3bd6d92
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
@@ -0,0 +1,2222 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_tim.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_TIM_H
+#define STM32MP1xx_HAL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIM_Exported_Types TIM Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time base Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint32_t Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_ClockDivision */
+
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
+ This parameter can be a value of @ref TIM_AutoReloadPreload */
+} TIM_Base_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ This parameter can be a value of @ref TIM_Output_Fast_State
+ @note This parameter is valid only in PWM1 and PWM2 mode. */
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+} TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM One Pulse Mode Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for timer instances supporting break feature. */
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_OnePulse_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_IC_InitTypeDef;
+
+/**
+ * @brief TIM Encoder Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Encoder_Mode */
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC2Selection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC2Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_Encoder_InitTypeDef;
+
+/**
+ * @brief Clock Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockSource; /*!< TIM clock sources
+ This parameter can be a value of @ref TIM_Clock_Source */
+ uint32_t ClockPolarity; /*!< TIM clock polarity
+ This parameter can be a value of @ref TIM_Clock_Polarity */
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ This parameter can be a value of @ref TIM_Clock_Prescaler */
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
+
+/**
+ * @brief TIM Clear Input Configuration Handle Structure definition
+ */
+typedef struct
+{
+ uint32_t ClearInputState; /*!< TIM clear Input state
+ This parameter can be ENABLE or DISABLE */
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ This parameter can be a value of @ref TIM_ClearInput_Polarity */
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
+
+/**
+ * @brief TIM Master configuration Structure definition
+ * @note Advanced timers provide TRGO2 internal line which is redirected
+ * to the ADC
+ */
+typedef struct
+{
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the effect of
+ an event on the trigger input (TRGI) is delayed to allow a
+ perfect synchronization between the current timer and its
+ slaves (through TRGO). It is not mandatory in case of timer
+ synchronization mode. */
+} TIM_MasterConfigTypeDef;
+
+/**
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t BreakFilter; /*!< Specifies the break input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
+ This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
+ uint32_t Break2State; /*!< TIM Break2 State
+ This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+ uint32_t Break2Polarity; /*!< TIM Break2 input polarity
+ This parameter can be a value of @ref TIM_Break2_Polarity */
+ uint32_t Break2Filter; /*!< TIM break2 input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
+ This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
+} HAL_TIM_StateTypeDef;
+
+/**
+ * @brief HAL Active channel structures definition
+ */
+typedef enum
+{
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
+ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
+
+/**
+ * @brief TIM Time Base Handle Structure definition
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+{
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+#endif
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
+ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
+ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
+ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
+ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
+ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
+ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+
+ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
+ * @{
+ */
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_DCR 0x00000012U
+#define TIM_DMABASE_DMAR 0x00000013U
+#define TIM_DMABASE_CCMR3 0x00000015U
+#define TIM_DMABASE_CCR5 0x00000016U
+#define TIM_DMABASE_CCR6 0x00000017U
+#define TIM_DMABASE_AF1 0x00000018U
+#define TIM_DMABASE_AF2 0x00000019U
+#define TIM_DMABASE_TISEL 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
+ * @{
+ */
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
+ * @{
+ */
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode TIM Counter Mode
+ * @{
+ */
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClockDivision TIM Clock Division
+ * @{
+ */
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+ * @{
+ */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Fast_State TIM Output Fast State
+ * @{
+ */
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
+ * @{
+ */
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
+ * @{
+ */
+#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
+ * @{
+ */
+#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
+ * @{
+ */
+#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
+ * @{
+ */
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
+ * @{
+ */
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
+ * @{
+ */
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
+ * @{
+ */
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
+ * @{
+ */
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
+ * @{
+ */
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Commutation_Source TIM Commutation Source
+ * @{
+ */
+#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources TIM DMA Sources
+ * @{
+ */
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flag_definition TIM Flag Definition
+ * @{
+ */
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
+#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
+#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
+#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel TIM Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
+#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
+#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Source TIM Clock Source
+ * @{
+ */
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
+ * @{
+ */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
+ * @{
+ */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
+ * @{
+ */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
+ * @{
+ */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
+ * @{
+ */
+#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
+ * @{
+ */
+#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+ * @}
+ */
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
+ * @{
+ */
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
+ * @{
+ */
+#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
+#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
+ * @{
+ */
+#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
+#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
+ * @{
+ */
+#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
+#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
+ * @{
+ */
+#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
+#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
+ * @{
+ */
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+ (if none of the break inputs BRK and BRK2 is active) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+ * @{
+ */
+#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
+ * @{
+ */
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
+ * @{
+ */
+#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
+#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
+#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
+ * @{
+ */
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode TIM Slave mode
+ * @{
+ */
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
+#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
+#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
+#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
+#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
+#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
+ * @{
+ */
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
+ * @{
+ */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
+ * @{
+ */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
+ * @{
+ */
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
+ * @{
+ */
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
+ * @{
+ */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
+/**
+ * @}
+ */
+
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
+ * @{
+ */
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Break_System TIM Break System
+ * @{
+ */
+#define TIM_BREAK_SYSTEM_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup TIM_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @brief Reset TIM handle state.
+ * @param __HANDLE__ TIM handle.
+ * @retval None
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @brief Enable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
+
+/**
+ * @brief Enable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
+
+/**
+ * @brief Disable the TIM peripheral.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+ */
+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__ TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled unconditionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
+
+/** @brief Enable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
+
+/** @brief Disable the specified TIM interrupt.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief Enable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief Disable the specified DMA request.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief Check whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified TIM interrupt flag.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
+ * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/**
+ * @brief Check whether the specified TIM interrupt source is enabled or not.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval The state of TIM_IT (SET or RESET).
+ */
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+ == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.
+ * @param __HANDLE__ TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+ */
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
+
+/**
+ * @brief Set the TIM Prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __PRESC__ specifies the Prescaler new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
+
+/**
+ * @brief Set the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __COUNTER__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
+
+/**
+ * @brief Get the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
+ */
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
+
+/**
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __AUTORELOAD__ specifies the Counter register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
+
+/**
+ * @brief Get the TIM Autoreload Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
+ */
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
+
+/**
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CKD__ specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ * @retval None
+ */
+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
+
+/**
+ * @brief Get the TIM Clock Division value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval The clock division can be one of the following values:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
+ */
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+
+/**
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
+
+/**
+ * @brief Get the TIM Input Capture prescaler on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
+ * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
+ * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
+ * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
+ * @retval The input capture prescaler can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ */
+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
+
+/**
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
+
+/**
+ * @brief Get the TIM Capture Compare Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @arg TIM_CHANNEL_5: get capture/compare 5 register value
+ * @arg TIM_CHANNEL_6: get capture/compare 6 register value
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
+ ((__HANDLE__)->Instance->CCR6))
+
+/**
+ * @brief Set the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Reset the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * _ Counter overflow underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+ * @brief Set the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__ Polarity for TIx source
+ * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
+ * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
+ * @retval None
+ */
+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
+
+/**
+ * @}
+ */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR5) || \
+ ((__BASE__) == TIM_DMABASE_CCR6) || \
+ ((__BASE__) == TIM_DMABASE_TISEL))
+
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
+ ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \
+ ((__CHANNEL__) == TIM_CHANNEL_6) || \
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
+ ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
+ ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
+ ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
+ ((__STATE__) == TIM_BREAK2_DISABLE))
+
+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+
+#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
+ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO_OC1) || \
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
+ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO2_OC1) || \
+ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
+ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
+
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
+ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
+ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
+ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
+#include "stm32mp1xx_hal_tim_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ * @{
+ */
+/* Time Base functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ * @{
+ */
+/* Timer Output Compare functions *********************************************/
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ * @{
+ */
+/* Timer PWM functions ********************************************************/
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ * @{
+ */
+/* Timer Input Capture functions **********************************************/
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ * @{
+ */
+/* Timer One Pulse functions **************************************************/
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ * @{
+ */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ * @{
+ */
+/* Interrupt Handler functions ***********************************************/
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Control functions *********************************************************/
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ * @{
+ */
+/* Callback in non blocking modes (Interrupt and DMA) *************************/
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions ************************************************/
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+#ifdef HAL_DMA_MODULE_ENABLED
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_TIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
new file mode 100644
index 0000000..e0d9e6b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
@@ -0,0 +1,449 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_tim_ex.h
+ * @author MCD Application Team
+ * @brief Header file of TIM HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_TIM_EX_H
+#define STM32MP1xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup TIMEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+ * @{
+ */
+
+/**
+ * @brief TIM Hall sensor Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint32_t IC1Filter; /*!< Specifies the input capture filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+} TIM_HallSensor_InitTypeDef;
+
+/**
+ * @brief TIM Break/Break2 input configuration
+ */
+typedef struct
+{
+ uint32_t Source; /*!< Specifies the source of the timer break input.
+ This parameter can be a value of @ref TIMEx_Break_Input_Source */
+ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+ uint32_t Polarity; /*!< Specifies the break input source polarity.
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+ Not relevant when analog watchdog output of the DFSDM1 used as break input source */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+/**
+ * @}
+ */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup TIMEx_Remap TIM Extended Remapping
+ * @{
+ */
+#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
+#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC2_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */
+#if defined(TIM8)
+#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
+#define TIM_TIM8_ETR_ADC1_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM8_ETR_ADC1_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM8_ETR_ADC1_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */
+#endif
+#if defined(TIM2)
+#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
+#define TIM_TIM2_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_2) /* !< TIM2_ETR is connected to SAI1 FS_A */
+#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
+#define TIM_TIM2_ETR_ETH_PPS (TIM2_AF1_ETRSEL_2 | TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to ETH PPS */
+#endif
+#if defined(TIM3)
+#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_ETH_PPS (TIM3_AF1_ETRSEL_2 | TIM3_AF1_ETRSEL_1) /* !< TIM3_ETR is connected to ETH PPS */
+#endif
+#if defined(TIM4)
+#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< TIM4_ETR is connected to GPIO */
+#endif
+#if defined(TIM5)
+#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */
+#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */
+#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_OTG_SOF (TIM5_AF1_ETRSEL_1 | TIM5_AF1_ETRSEL_0) /* !< TIM5_ETR is connected to OTG SOF */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input TIM Extended Break input
+ * @{
+ */
+#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
+#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
+#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
+ * @{
+ */
+
+#define TIM_TIM1_TI1_GPIO 0x00000000UL /* !< TIM1_TI1 is connected to GPIO */
+#define TIM_TIM1_TI2_GPIO 0x00000000UL /* !< TIM1_TI2 is connected to GPIO */
+#define TIM_TIM1_TI3_GPIO 0x00000000UL /* !< TIM1_TI3 is connected to GPIO */
+#define TIM_TIM1_TI4_GPIO 0x00000000UL /* !< TIM1_TI4 is connected to GPIO */
+
+#define TIM_TIM8_TI1_GPIO 0x00000000UL /* !< TIM8_TI1 is connected to GPIO */
+#define TIM_TIM8_TI2_GPIO 0x00000000UL /* !< TIM8_TI2 is connected to GPIO */
+#define TIM_TIM8_TI3_GPIO 0x00000000UL /* !< TIM8_TI3 is connected to GPIO */
+#define TIM_TIM8_TI4_GPIO 0x00000000UL /* !< TIM8_TI4 is connected to GPIO */
+
+#define TIM_TIM2_TI1_GPIO 0x00000000UL /* !< TIM2_TI1 is connected to GPIO */
+#define TIM_TIM2_TI2_GPIO 0x00000000UL /* !< TIM2_TI2 is connected to GPIO */
+#define TIM_TIM2_TI3_GPIO 0x00000000UL /* !< TIM2_TI3 is connected to GPIO */
+#define TIM_TIM2_TI4_GPIO 0x00000000UL /* !< TIM2_TI4 is connected to GPIO */
+
+#define TIM_TIM3_TI1_GPIO 0x00000000UL /* !< TIM3_TI1 is connected to GPIO */
+#define TIM_TIM3_TI2_GPIO 0x00000000UL /* !< TIM3_TI2 is connected to GPIO */
+#define TIM_TIM3_TI3_GPIO 0x00000000UL /* !< TIM3_TI3 is connected to GPIO */
+#define TIM_TIM3_TI4_GPIO 0x00000000UL /* !< TIM3_TI4 is connected to GPIO */
+
+#define TIM_TIM4_TI1_GPIO 0x00000000UL /* !< TIM4_TI1 is connected to GPIO */
+#define TIM_TIM4_TI2_GPIO 0x00000000UL /* !< TIM4_TI2 is connected to GPIO */
+#define TIM_TIM4_TI3_GPIO 0x00000000UL /* !< TIM4_TI3 is connected to GPIO */
+#define TIM_TIM4_TI4_GPIO 0x00000000UL /* !< TIM4_TI4 is connected to GPIO */
+
+#define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_FDCAN1_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to FDCAN1 TMP */
+#define TIM_TIM5_TI1_FDCAN1_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to FDCAN1 RTP */
+#define TIM_TIM5_TI2_GPIO 0x00000000UL /* !< TIM5_TI2 is connected to GPIO */
+#define TIM_TIM5_TI3_GPIO 0x00000000UL /* !< TIM5_TI3 is connected to GPIO */
+#define TIM_TIM5_TI4_GPIO 0x00000000UL /* !< TIM5_TI4 is connected to GPIO */
+
+#define TIM_TIM12_TI1_GPIO 0x00000000UL /* !< TIM12_TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_HSI_CAL_CK TIM_TISEL_TI1SEL_0 /* !< TIM12_TI1 is connected to HSI CAL CK */
+#define TIM_TIM12_TI1_CSI_CAL_CK TIM_TISEL_TI1SEL_1 /* !< TIM12_TI1 is connected to CSI CAL CK */
+#define TIM_TIM12_TI2_GPIO 0x00000000UL /* !< TIM12_TI2 is connected to GPIO */
+
+#define TIM_TIM13_TI1_GPIO 0x00000000UL /* !< TIM13_TI1 is connected to GPIO */
+
+#define TIM_TIM14_TI1_GPIO 0x00000000UL /* !< TIM14_TI1 is connected to GPIO */
+
+#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */
+#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
+#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */
+#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */
+#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
+#define TIM_TIM15_TI1_HSI_CAL_CK (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to HSI CAL CK */
+#define TIM_TIM15_TI1_CSI_CAL_CK TIM_TISEL_TI1SEL_3 /* !< TIM15_TI1 is connected to CSI CAL CK */
+
+#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */
+#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
+
+#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */
+#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */
+#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
+
+#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_SPDIFRX_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_RCC_HSE_RTC TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE RTC */
+#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+ * @{
+ */
+#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
+ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
+ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
+#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
+
+
+/**
+ * @}
+ */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
+/* Timer Hall Sensor functions **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
+/* Timer Complementary Output Compare functions *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
+/* Timer Complementary PWM functions ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
+/* Timer Complementary One Pulse functions **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+#ifdef HAL_DMA_MODULE_ENABLED
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+#endif
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ * @{
+ */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ * @{
+ */
+/* Extended Peripheral State functions ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+#if defined(HAL_DMA_MODULE_ENABLED)
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
+/**
+ * @}
+ */
+/* End of private functions --------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32MP1xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
new file mode 100644
index 0000000..9a6e822
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
@@ -0,0 +1,1631 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_uart.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_UART_H
+#define STM32MP1xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
+ The baud rate register is computed using the following formula:
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+ - If oversampling is 8,
+ Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref UARTEx_Word_Length. */
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref UART_Stop_Bits. */
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref UART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref UART_Mode. */
+
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
+ This parameter can be a value of @ref UART_Over_Sampling. */
+
+ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
+ Selecting the single sample method increases the receiver tolerance to clock
+ deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+ uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
+ This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+ * @brief UART Advanced Features initialization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
+ Advanced Features may be initialized at the same time .
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref UART_Tx_Inv. */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref UART_Rx_Inv. */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref UART_Data_Inv. */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref UART_Overrun_Disable. */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+ uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+ uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
+ detection is carried out.
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+ * @brief HAL UART State definition
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
+ * - gState contains UART state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+ * @brief UART clock sources definition
+ */
+typedef enum
+{
+ UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ UART_CLOCKSOURCE_PCLK5 = 0x02U, /*!< PCLK5 clock source (only used by UART1) */
+ UART_CLOCKSOURCE_PLL3Q = 0x04U, /*!< PLL3Q clock source (only used by UART1) */
+ UART_CLOCKSOURCE_PLL4Q = 0x08U, /*!< PLL4Q clock source */
+ UART_CLOCKSOURCE_HSI = 0x10U, /*!< HSI clock source */
+ UART_CLOCKSOURCE_CSI = 0x20U, /*!< CSI clock source */
+ UART_CLOCKSOURCE_HSE = 0x40U, /*!< HSE clock source */
+ UART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */
+} UART_ClockSourceTypeDef;
+
+/**
+ * @brief UART handle Structure definition
+ */
+typedef struct __UART_HandleTypeDef
+{
+ USART_TypeDef *Instance; /*!< UART registers base address */
+
+ UART_InitTypeDef Init; /*!< UART communication parameters */
+
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+
+ uint16_t Mask; /*!< UART Rx RDR register mask */
+
+ uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used.
+ This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
+
+ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+
+ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+#endif
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ MDMA_HandleTypeDef *hmdmatx; /*!< UART Tx MDMA Handle parameters */
+
+ MDMA_HandleTypeDef *hmdmarx; /*!< UART Rx MDMA Handle parameters */
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
+ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
+ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
+ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
+ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
+ void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
+ void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
+
+ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
+ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL UART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
+ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
+ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */
+ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */
+
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL UART Callback pointer definition
+ */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+ * @{
+ */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+ * @{
+ */
+#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Error_Definition UART Error Definition
+ * @{
+ */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+ * @{
+ */
+#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
+#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */
+#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Parity UART Parity
+ * @{
+ */
+#define UART_PARITY_NONE 0x00000000U /*!< No parity */
+#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+ * @{
+ */
+#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */
+#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */
+#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mode UART Transfer Mode
+ * @{
+ */
+#define UART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define UART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup UART_State UART State
+ * @{
+ */
+#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */
+#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+ * @{
+ */
+#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+ * @{
+ */
+#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_ClockPrescaler UART Clock Prescaler
+ * @{
+ */
+#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
+#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
+#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
+#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
+#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
+#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
+#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
+#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
+#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
+#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
+#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+ * @{
+ */
+#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN UART Local Interconnection Network mode
+ * @{
+ */
+#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Tx UART DMA Tx
+ * @{
+ */
+#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Rx UART DMA Rx
+ * @{
+ */
+#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
+ * @{
+ */
+#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
+ * @{
+ */
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+ * @{
+ */
+#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
+ * @{
+ */
+#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
+ * @{
+ */
+#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+ * @{
+ */
+#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
+ * @{
+ */
+#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
+ * @{
+ */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
+ * @{
+ */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_MSB_First UART Advanced Feature MSB First
+ * @{
+ */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
+ * @{
+ */
+#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
+/**
+ * @}
+ */
+
+/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
+ * @{
+ */
+#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+ * @{
+ */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
+ * @{
+ */
+#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */
+/**
+ * @}
+ */
+
+/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
+ * @{
+ */
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART Status Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */
+#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */
+#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */
+#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */
+#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */
+#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
+#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */
+#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
+#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
+#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
+#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
+#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
+#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
+#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
+#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
+#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
+#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */
+#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */
+#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */
+#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */
+#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */
+#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */
+#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */
+#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */
+#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */
+#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
+#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */
+#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
+#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */
+#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
+#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
+#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
+#define UART_IT_CM 0x112EU /*!< UART character match interruption */
+#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
+#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */
+#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
+#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
+#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
+#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
+
+#define UART_IT_ERR 0x0060U /*!< UART error interruption */
+
+#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
+#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
+#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
+ * @{
+ */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+ * @{
+ */
+
+/** @brief Reset UART handle states.
+ * @param __HANDLE__ UART handle.
+ * @retval None
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief Flush the UART Data registers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
+
+/** @brief Clear the specified UART pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the UART PE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief Clear the UART FE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief Clear the UART NE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief Clear the UART ORE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief Clear the UART IDLE pending flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief Clear the UART TX FIFO empty clear flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief Check whether the specified UART flag is set or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag
+ * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag
+ * @arg @ref UART_FLAG_RXFF RXFIFO Full flag
+ * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag
+ * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
+ * @arg @ref UART_FLAG_SBKF Send Break flag
+ * @arg @ref UART_FLAG_CMF Character match flag
+ * @arg @ref UART_FLAG_BUSY Busy flag
+ * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref UART_FLAG_CTS CTS Change flag
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag
+ * @arg @ref UART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+ * @arg @ref UART_FLAG_TC Transmission Complete flag
+ * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+ * @arg @ref UART_FLAG_RTOF Receiver Timeout flag
+ * @arg @ref UART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref UART_FLAG_ORE Overrun Error flag
+ * @arg @ref UART_FLAG_NE Noise Error flag
+ * @arg @ref UART_FLAG_FE Framing Error flag
+ * @arg @ref UART_FLAG_PE Parity Error flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Enable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+
+/** @brief Disable the specified UART interrupt.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval None
+ */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief Check whether the specified UART interrupt has occurred or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief Check whether the specified UART interrupt source is enabled or not.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_IT_RXFF RXFIFO Full interrupt
+ * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
+ * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
+ * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
+ */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
+
+/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+ * to clear the corresponding interrupt
+ * This parameter can be one of the following values:
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+ * @retval None
+ */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief Set a specific UART request flag.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __REQ__ specifies the request flag to set
+ * This parameter can be one of the following values:
+ * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+ * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+ * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+ * @retval None
+ */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief Enable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief Disable the UART one bit sample method.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief Enable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief Disable UART.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief Enable CTS flow control.
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
+ } while(0U)
+
+/** @brief Disable CTS flow control.
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
+ } while(0U)
+
+/** @brief Enable RTS flow control.
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
+ } while(0U)
+
+/** @brief Disable RTS flow control.
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,
+ * without need to call HAL_UART_Init() function.
+ * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+ * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+ * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+ * - UART instance should have already been initialised (through call of HAL_UART_Init() )
+ * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
+ do{ \
+ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
+ } while(0U)
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+/** @brief Get UART clok division factor from clock prescaler value.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval UART clock division factor
+ */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+ (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+
+
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+ + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ UART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @retval Division result
+ */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+ + ((__BAUD__)/2U)) / (__BAUD__))
+
+
+/** @brief Check UART Baud rate.
+ * @param __BAUDRATE__ Baudrate specified by the user.
+ * The maximum Baud Rate is derived from the maximum clock on MP1 (i.e. 100 MHz)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+ */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
+
+/** @brief Check UART assertion time.
+ * @param __TIME__ 5-bit value assertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/** @brief Check UART deassertion time.
+ * @param __TIME__ 5-bit value deassertion time.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+ * @brief Ensure that UART frame number of stop bits is valid.
+ * @param __STOPBITS__ UART frame number of stop bits.
+ * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+ */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_1) || \
+ ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+ ((__STOPBITS__) == UART_STOPBITS_2))
+
+
+/**
+ * @brief Ensure that UART frame parity is valid.
+ * @param __PARITY__ UART frame parity.
+ * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+ */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+ ((__PARITY__) == UART_PARITY_EVEN) || \
+ ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+ * @brief Ensure that UART hardware flow control is valid.
+ * @param __CONTROL__ UART hardware flow control.
+ * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+ */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+ * @brief Ensure that UART communication mode is valid.
+ * @param __MODE__ UART communication mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+ * @brief Ensure that UART state is valid.
+ * @param __STATE__ UART state.
+ * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+ */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+ ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+ * @brief Ensure that UART oversampling is valid.
+ * @param __SAMPLING__ UART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+ * @brief Ensure that UART frame sampling is valid.
+ * @param __ONEBIT__ UART frame sampling.
+ * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+ */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+ ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__ UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+ * @brief Ensure that UART receiver timeout setting is valid.
+ * @param __TIMEOUT__ UART receiver timeout setting.
+ * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+ */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum UART receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__ UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
+ ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__ UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+ * @brief Ensure that UART DMA TX state is valid.
+ * @param __DMATX__ UART DMA TX state.
+ * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+ */
+#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+ ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA RX state is valid.
+ * @param __DMARX__ UART DMA RX state.
+ * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+ */
+#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+ ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+ * @brief Ensure that UART half-duplex state is valid.
+ * @param __HDSEL__ UART half-duplex state.
+ * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+ */
+#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+ ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up method is valid.
+ * @param __WAKEUP__ UART wake-up method .
+ * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+ */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__ UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+ * @brief Ensure that UART advanced features initialization is valid.
+ * @param __INIT__ UART advanced features initialization.
+ * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
+ UART_ADVFEATURE_TXINVERT_INIT | \
+ UART_ADVFEATURE_RXINVERT_INIT | \
+ UART_ADVFEATURE_DATAINVERT_INIT | \
+ UART_ADVFEATURE_SWAP_INIT | \
+ UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
+ UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+ UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
+ UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+ * @brief Ensure that UART frame TX inversion setting is valid.
+ * @param __TXINV__ UART frame TX inversion setting.
+ * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+ ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX inversion setting is valid.
+ * @param __RXINV__ UART frame RX inversion setting.
+ * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+ ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame data inversion setting is valid.
+ * @param __DATAINV__ UART frame data inversion setting.
+ * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+ ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+ * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ UART frame RX/TX pins swap setting.
+ * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+ ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+ * @brief Ensure that UART frame overrun setting is valid.
+ * @param __OVERRUN__ UART frame overrun setting.
+ * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+ */
+#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+ ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+ * @brief Ensure that UART auto Baud rate state is valid.
+ * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+ * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+ ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+ * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ UART DMA enabling or disabling on error setting.
+ * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+ ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+ * @brief Ensure that UART frame MSB first setting is valid.
+ * @param __MSBFIRST__ UART frame MSB first setting.
+ * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__ UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART mute mode state is valid.
+ * @param __MUTE__ UART mute mode state.
+ * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+ */
+#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__ UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+ * @brief Ensure that UART driver enable polarity is valid.
+ * @param __POLARITY__ UART driver enable polarity.
+ * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+ */
+#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+ ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+ * @brief Ensure that UART Prescaler is valid.
+ * @param __CLOCKPRESCALER__ UART Prescaler value.
+ * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+ */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+ * @}
+ */
+
+/* Include UART HAL Extended module */
+#include "stm32mp1xx_hal_uart_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* Peripheral Control functions ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @{
+ */
+
+/* Peripheral State and Errors functions **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h
new file mode 100644
index 0000000..f7514fd
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart_ex.h
@@ -0,0 +1,509 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_uart_ex.h
+ * @author MCD Application Team
+ * @brief Header file of UART HAL Extended module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_HAL_UART_EX_H
+#define STM32MP1xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup UARTEx
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+ * @{
+ */
+
+/**
+ * @brief UART wake up from stop mode parameters
+ */
+typedef struct
+{
+ uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+ This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+ If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+ be filled up. */
+
+ uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
+ This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
+
+ uint8_t Address; /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+ * @{
+ */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+ * @{
+ */
+#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+ * @{
+ */
+#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+ * @brief UART FIFO mode
+ * @{
+ */
+#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+ * @brief UART TXFIFO threshold level
+ * @{
+ */
+#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+ * @brief UART RXFIFO threshold level
+ * @{
+ */
+#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+ * @{
+ */
+
+/** @brief Report the UART clock source.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval UART clocking source, written in __CLOCKSOURCE__.
+ */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK5: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK5; \
+ break; \
+ case RCC_USART1CLKSOURCE_PLL3: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3Q; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_UART24_SOURCE()) \
+ { \
+ case RCC_UART24CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART24CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART24CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART24CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART24CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_UART35_SOURCE()) \
+ { \
+ case RCC_UART35CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART35CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART35CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART35CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART35CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART24_SOURCE()) \
+ { \
+ case RCC_UART24CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART24CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART24CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART24CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART24CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if ((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART35_SOURCE()) \
+ { \
+ case RCC_UART35CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART35CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART35CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART35CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART35CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ switch(__HAL_RCC_GET_USART6_SOURCE()) \
+ { \
+ case RCC_USART6CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART6CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_USART6CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART7) \
+ { \
+ switch(__HAL_RCC_GET_UART78_SOURCE()) \
+ { \
+ case RCC_UART78CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART78CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART78CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART78CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART78CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART8) \
+ { \
+ switch(__HAL_RCC_GET_UART78_SOURCE()) \
+ { \
+ case RCC_UART78CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART78CLKSOURCE_PLL4: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL4Q; \
+ break; \
+ case RCC_UART78CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART78CLKSOURCE_CSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
+ break; \
+ case RCC_UART78CLKSOURCE_HSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+
+/** @brief Report the UART mask to apply to retrieve the received data
+ * according to the word length and to the parity bits activation.
+ * @note If PCE = 1, the parity bit is not included in the data extracted
+ * by the reception API().
+ * This masking operation is not carried out in the case of
+ * DMA transfers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+ */
+#define UART_MASK_COMPUTATION(__HANDLE__) \
+ do { \
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU ; \
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+
+/**
+ * @brief Ensure that UART frame length is valid.
+ * @param __LENGTH__ UART frame length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+ ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+ * @brief Ensure that UART wake-up address length is valid.
+ * @param __ADDRESS__ UART wake-up address length.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+ */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+ * @brief Ensure that UART TXFIFO threshold level is valid.
+ * @param __THRESHOLD__ UART TXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+ * @brief Ensure that UART RXFIFO threshold level is valid.
+ * @param __THRESHOLD__ UART RXFIFO threshold level.
+ * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+ */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+ ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h
new file mode 100644
index 0000000..33832b7
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h
@@ -0,0 +1,7207 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_ll_adc.h
+ * @author MCD Application Team
+ * @brief Header file of ADC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32MP1xx_LL_ADC_H
+#define STM32MP1xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx.h"
+
+/** @addtogroup STM32MP1xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC calibration: */
+/* Internal register offset for ADC calibration factors configuration */
+
+/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - ADC calibration configuration: configuration before calibration start */
+/* - ADC calibration factors: register offset */
+#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
+#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
+#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
+#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
+#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
+
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET (0x00000000UL)
+#define ADC_SQR2_REGOFFSET (0x00000100UL)
+#define ADC_SQR3_REGOFFSET (0x00000200UL)
+#define ADC_SQR4_REGOFFSET (0x00000300UL)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
+
+
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET (0x00000000UL)
+#define ADC_JDR2_REGOFFSET (0x00000100UL)
+#define ADC_JDR3_REGOFFSET (0x00000200UL)
+#define ADC_JDR4_REGOFFSET (0x00000300UL)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition. */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
+
+
+
+/* Internal mask for ADC group regular trigger: */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
+/* - regular trigger source */
+/* - regular trigger edge */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
+
+/* Definition of ADC group regular trigger bits information. */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
+
+
+
+/* Internal mask for ADC group injected trigger: */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
+/* - injected trigger source */
+/* - injected trigger edge */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
+
+/* Definition of ADC group injected trigger bits information. */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
+
+
+
+
+
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel identifier defined by bitfield */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET (0x00000000UL)
+#define ADC_SMPR2_REGOFFSET (0x02000000UL)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
+#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
+#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
+#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
+#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+
+/* Definition of channels ID bitfield information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
+#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
+#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
+#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
+
+
+/* Internal mask for ADC mode single or differential ended: */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - ADC calibration: calibration start, calibration factor get or set */
+/* - ADC channels: set each ADC channel ending mode */
+#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
+/* selection on groups. */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
+#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
+#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
+
+/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
+/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
+
+/* Internal mask for ADC offset: */
+/* Internal register offset for ADC offset number configuration */
+#define ADC_OFR1_REGOFFSET (0x00000000UL)
+#define ADC_OFR2_REGOFFSET (0x00000001UL)
+#define ADC_OFR3_REGOFFSET (0x00000002UL)
+#define ADC_OFR4_REGOFFSET (0x00000003UL)
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) (0x5C005250UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x5C00525CUL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32MP1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x5C00525EUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32MP1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+
+#define ADC_LINEAR_CALIB_REG_COUNT (6UL)
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC common parameters
+ * and multimode
+ * (all ADC instances belonging to the same ADC common instance).
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
+ * is conditioned to ADC instances state (all ADC instances
+ * sharing the same ADC common instance):
+ * All ADC instances sharing the same ADC common instance must be
+ * disabled.
+ */
+typedef struct
+{
+ uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
+ This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+ @note On this STM32 serie, if ADC group injected is used, some
+ clock ratio constraints between ADC clock and AHB clock
+ must be respected. Refer to reference manual.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+
+ uint32_t MultiDMATransfer; /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
+
+ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t Resolution; /*!< Set ADC resolution.
+ This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+ uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
+ This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
+
+ uint32_t LowPowerMode; /*!< Set ADC low power mode.
+ This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+ In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */
+
+ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
+ data preserved or overwritten.
+ This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+ In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
+#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
+#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
+#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
+#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
+#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
+#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
+#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
+#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
+#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
+#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
+#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
+#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
+#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
+#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
+#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
+#define LL_ADC_PATH_INTERNAL_VDDCORE (ADC2_OR_VDDCOREEN) /*!< ADC measurement path to internal channel Vddcore */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode
+ * @{
+ */
+#define LL_ADC_BOOST_MODE_DISABLE (0x00000000UL) /*!< ADC boost mode disable: can be used when ADC clock < 20 MHz to save power at lower clock frequency */
+#define LL_ADC_BOOST_MODE_ENABLE (ADC_CR_BOOST) /*!< ADC boost mode enable: must be used when ADC clock > 20 MHz. Note: In multimode, boost setting of ADC slave is discarded are applies setting of ADC master. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
+ * @{
+ */
+#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */
+#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET) /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */
+#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD ADC instance - Calibration linearity words
+ * @{
+ */
+#define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1) /*!< ADC calibration linearity word 1 */
+#define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2) /*!< ADC calibration linearity word 2 */
+#define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3) /*!< ADC calibration linearity word 3 */
+#define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4) /*!< ADC calibration linearity word 4 */
+#define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5) /*!< ADC calibration linearity word 5 */
+#define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6) /*!< ADC calibration linearity word 6 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */
+#define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
+ * @{
+ */
+#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC convesion data */
+#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC convesion data */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
+ * @{
+ */
+#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
+ * @{
+ */
+#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift
+ * @{
+ */
+#define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
+#define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VddCore. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
+#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
+#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+ * @{
+ */
+#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+ * @{
+ */
+#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
+ * @{
+ */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
+#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 8.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 32.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 387.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
+ * @{
+ */
+#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VddCore, converted by group regular only */
+#define LL_ADC_AWD_CH_VCORE_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VddCore, converted by group injected only */
+#define LL_ADC_AWD_CH_VCORE_REG_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VddCore, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
+ * @{
+ */
+#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
+ * @{
+ */
+#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
+ * @{
+ */
+#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
+ * @{
+ */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
+#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 14 bits resolution */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5 (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 8.5 ADC clock cycles for 16 bits resolution */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
+ * @{
+ */
+#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 serie: */
+/* - ADC calibration time: maximum delay is 16384/fADC. */
+/* (refer to device datasheet, parameter "tCAL") */
+/* - ADC enable time: maximum delay is 1 conversion cycle. */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC disable time: maximum delay should be a few ADC clock cycles */
+/* - ADC stop conversion time: maximum delay should be a few ADC clock */
+/* cycles */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tADCVREG_STUP"). */
+/* Unit: us */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time. */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "ts_vrefint"). */
+/* Unit: us */
+#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART_RUN"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
+
+/* Delay required between ADC end of calibration and ADC enable. */
+/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* are required between ADC end of calibration and ADC enable. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
+
+/* Fixed timeout value for ADC linearity word bit set/clear delay. */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+/* Example of profile low frequency (minimum value */
+/* according to Data sheet): ADC frequency at 15.625kHz (ADC clock */
+/* source PLL4_Q 4MHz, ADC clock prescaler 256), */
+/* linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
+/* 6 / 15625 = 0,384ms */
+/* At maximum CPU speed (650 MHz), this means */
+/* 3.58 * 650 MHz = 524400 CPU cycles */
+#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
+ ? ( \
+ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+ ) \
+ : \
+ ( \
+ (uint32_t)POSITION_VAL((__CHANNEL__)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9UL) \
+ ? ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ : \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC2) \
+ &&( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VCORE) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VCORE_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VCORE_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VCORE_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (1)
+ *
+ * (0) On STM32MP1, parameter available only on analog watchdog number: AWD1.\n
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 16 bits.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 18 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
+ * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
+ */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 16 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 18 bits):
+ * < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @param __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
+ * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
+ */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \
+ ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+ * @brief Helper macro to set the ADC calibration value with both single ended
+ * and differential modes calibration factors concatenated.
+ * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
+ * Example, to set calibration factors single ended to 0x55
+ * and differential ended to 0x2A:
+ * LL_ADC_SetCalibrationOffsetFactor(
+ * ADC1,
+ * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+ * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
+ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to select, from a ADC instance, to which ADC instance
+ * it has a dependence in multimode (ADC master of the corresponding
+ * ADC common instance).
+ * @note In case of device with multimode available and a mix of
+ * ADC instances compliant and not compliant with multimode feature,
+ * ADC instances not compliant with multimode feature are
+ * considered as master instances (do not depend to
+ * any other ADC instance).
+ * @param __ADCx__ ADC instance
+ * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+ */
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+ ( ( ((__ADCx__) == ADC2) \
+ )? \
+ (ADC1) \
+ : \
+ (__ADCx__) \
+ )
+#endif
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC12_COMMON)
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) )
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+ (((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+ )
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ )
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 serie, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 16 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 16 bits.
+ * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_16B))
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 16 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 16 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_16B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 16 bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 16 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32MP1, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32MP1, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((( ( \
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000UL) \
+ - \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000UL) \
+ ) \
+ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+ *
+ * (1) Available on devices with several ADC instances.
+ * @retval ADC register address
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ register uint32_t data_reg_addr;
+
+ if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+ {
+ /* Retrieve address of register DR */
+ data_reg_addr = (uint32_t) &(ADCx->DR);
+ }
+ else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+ {
+ /* Retrieve address of register CDR */
+ data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+ }
+
+ return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ /* Prevent unused argument(s) compilation warning */
+ (void)(Register);
+
+ /* Retrieve address of register DR */
+ return (uint32_t) &(ADCx->DR);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: Clock source and prescaler.
+ * @note On this STM32 serie, if ADC group injected is used, some
+ * clock ratio constraints between ADC clock and AHB clock
+ * must be respected.
+ * Refer to reference manual.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
+ * CCR PRESC LL_ADC_SetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param CommonClock This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+ * @brief Get parameter common to several ADC: Clock source and prescaler.
+ * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
+ * CCR PRESC LL_ADC_GetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Configure all paths (overwrite current configuration).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * The values not selected are removed from configuration.
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
+ * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
+ * CCR VBATEN LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE)
+ {
+ /* Feature limited to ADC instance ADC2 */
+ SET_BIT(ADC2->OR, ADC2_OR_VDDCOREEN);
+ }
+ else
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
+ }
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Add paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
+ * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE)
+ {
+ /* Feature limited to ADC instance ADC2 */
+ SET_BIT(ADC2->OR, ADC2_OR_VDDCOREEN);
+ }
+ else
+ {
+ SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+ }
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to
+ * internal channels (VrefInt, temperature sensor, ...).
+ * Remove paths to the current configuration.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
+ * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
+ * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE)
+ {
+ /* Feature limited to ADC instance ADC2 */
+ CLEAR_BIT(ADC2->OR, ADC2_OR_VDDCOREEN);
+ }
+ else
+ {
+ CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+ }
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
+ * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
+ * CCR VBATEN LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note This function is intended to set calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration factor must be specified for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * Calibration of linearity is common to both
+ * single-ended and differential modes
+ * (calibration factor can be specified only once).
+ * @note In case of setting calibration factors of both modes single ended
+ * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+ * both calibration factors must be concatenated.
+ * To perform this processing, use helper macro
+ * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor\n
+ * CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+ MODIFY_REG(ADCx->CALFACT,
+ SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+ CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
+}
+
+/**
+ * @brief Get ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * Calibration of linearity is common to both
+ * single-ended and differential modes
+ * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor\n
+ * CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+ /* Retrieve bits with position in register depending on parameter */
+ /* "SingleDiff". */
+ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+}
+
+/**
+ * @brief Set ADC Linear calibration factor in the mode single-ended.
+ * @note This function is intended to set linear calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n
+ * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
+ * @param ADCx ADC instance
+ * @param LinearityWord This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
+{
+ register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
+ MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
+ MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
+ while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))
+ {
+ timeout_cpu_cycles--;
+ }
+}
+
+/**
+ * @brief Get ADC Linear calibration factor in the mode single-ended.
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n
+ * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
+ * @param ADCx ADC instance
+ * @param LinearityWord This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
+ * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
+{
+ register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
+ CLEAR_BIT(ADCx->CR, LinearityWord);
+ while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))
+ {
+ timeout_cpu_cycles--;
+ }
+ return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
+}
+/**
+ * @brief Set ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR RES LL_ADC_SetResolution
+ * @param ADCx ADC instance
+ * @param Resolution This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+}
+
+/**
+ * @brief Get ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR RES LL_ADC_GetResolution
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_16B
+ * @arg @ref LL_ADC_RESOLUTION_14B
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+}
+
+/**
+ * @brief Set ADC low power mode.
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - Do not use with interruption or DMA since these modes
+ * have to clear immediately the EOC flag to free the
+ * IRQ vector sequencer.
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
+ * @param ADCx ADC instance
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+}
+
+/**
+ * @brief Get ADC low power mode:
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - Do not use with interruption or DMA since these modes
+ * have to clear immediately the EOC flag to free the
+ * IRQ vector sequencer.
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+}
+
+/**
+ * @brief Set ADC selected offset number 1, 2, 3 or 4.
+ * @note This function set the 2 items of offset configuration:
+ * - ADC channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note This function enables the offset, by default. It can be forced
+ * to disable state using function LL_ADC_SetOffsetState().
+ * @note If a channel is mapped on several offsets numbers, only the offset
+ * with the lowest value is considered for the subtraction.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @note On STM32MP1, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
+ * OFR1 OFFSET1 LL_ADC_SetOffset\n
+ * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
+ * OFR2 OFFSET2 LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
+ * OFR3 OFFSET3 LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
+ * OFR4 OFFSET4 LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffset
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @note On STM32MP1, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
+ * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
+ * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
+ * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
+ * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
+ * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
+ * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+
+/**
+ * @brief Set data right shift for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll CFGR2 RSHIFT LL_ADC_SetDataRightShift\n
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param RigthShift This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
+ * @retval Returned None
+ */
+__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
+{
+ MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
+}
+
+/**
+ * @brief Get data right shift for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll CFGR2 RSHIFT LL_ADC_GetDataRightShift\n
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
+ * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
+}
+
+/**
+ * @brief Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll OFR1 SSATE LL_ADC_SetOffsetSignedSaturation\n
+ * OFR2 SSATE LL_ADC_SetOffsetSignedSaturation\n
+ * OFR3 SSATE LL_ADC_SetOffsetSignedSaturation\n
+ * OFR4 SSATE LL_ADC_SetOffsetSignedSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetSignedSaturation This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
+ * @retval Returned None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
+{
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
+}
+
+/**
+ * @brief Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:
+ * signed offset saturation if enabled or disabled.
+ * @rmtoll OFR1 SSATE LL_ADC_GetOffsetSignedSaturation\n
+ * OFR2 SSATE LL_ADC_GetOffsetSignedSaturation\n
+ * OFR3 SSATE LL_ADC_GetOffsetSignedSaturation\n
+ * OFR4 SSATE LL_ADC_GetOffsetSignedSaturation
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
+ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_REG_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
+ * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
+ | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ * or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+}
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+ return (uint32_t)((READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+ );
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+}
+/**
+ * @brief Set ADC data transfer mode
+ * @note Conversion data can be either:
+ * - Available in Data Register
+ * - Transfered by DMA in one shot mode
+ * - Transfered by DMA in circular mode
+ * - Transfered to DFSDM data register
+ * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
+ * @param ADCx ADC instance
+ * @param DataTransferMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DR_TRANSFER
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @arg @ref LL_ADC_REG_DFSDM_TRANSFER
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
+}
+
+
+/**
+ * @brief Get ADC data transfer mode
+ * @note Conversion data can be either:
+ * - Available in Data Register
+ * - Transfered by DMA in one shot mode
+ * - Transfered by DMA in circular mode
+ * - Transfered to DFSDM data register
+ * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DR_TRANSFER
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @arg @ref LL_ADC_REG_DFSDM_TRANSFER
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));
+}
+
+
+/**
+ * @brief Set ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @note Compatibility with devices without feature overrun:
+ * other devices without this feature have a behavior
+ * equivalent to data overwritten.
+ * The default setting of overrun is data preserved.
+ * Therefore, for compatibility with all devices, parameter
+ * overrun should be set to data overwritten.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
+ * @param ADCx ADC instance
+ * @param Overrun This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+}
+
+/**
+ * @brief Get ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_INJ_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external peripheral (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+ /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
+ | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32MP1, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->JSQR,
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+ ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ return (uint32_t)((READ_BIT(ADCx->JSQR,
+ (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected contexts queue mode.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * If contexts queue is disabled:
+ * - only 1 sequence can be configured
+ * and is active perpetually.
+ * If contexts queue is enabled:
+ * - up to 2 contexts can be queued
+ * and are checked in and out as a FIFO stack (first-in, first-out).
+ * - If a new context is set when queues is full, error is triggered
+ * by interruption "Injected Queue Overflow".
+ * - Two behaviors are possible when all contexts have been processed:
+ * the contexts queue can maintain the last context active perpetually
+ * or can be empty and injected group triggers are disabled.
+ * - Triggers can be only external (not internal SW start)
+ * - Caution: The sequence must be fully configured in one time
+ * (one write of register JSQR makes a check-in of a new context
+ * into the queue).
+ * Therefore functions to set separately injected trigger and
+ * sequencer channels cannot be used, register JSQR must be set
+ * using function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note This parameter can be modified only when no conversion is on going
+ * on either groups regular or injected.
+ * @note A modification of the context mode (bit JQDIS) causes the contexts
+ * queue to be flushed and the register JSQR is cleared.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
+ * CFGR JQDIS LL_ADC_INJ_SetQueueMode
+ * @param ADCx ADC instance
+ * @param QueueMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
+}
+
+/**
+ * @brief Get ADC group injected context queue mode.
+ * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
+ * CFGR JQDIS LL_ADC_INJ_GetQueueMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
+}
+
+/**
+ * @brief Set one context on ADC group injected that will be checked in
+ * contexts queue.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * This function is intended to be used when contexts queue is enabled,
+ * because the sequence must be fully configured in one time
+ * (functions to set separately injected trigger and sequencer channels
+ * cannot be used):
+ * Refer to function @ref LL_ADC_INJ_SetQueueMode().
+ * @note In the contexts queue, only the active context can be read.
+ * The parameters of this function can be read using functions:
+ * @arg @ref LL_ADC_INJ_GetTriggerSource()
+ * @arg @ref LL_ADC_INJ_GetTriggerEdge()
+ * @arg @ref LL_ADC_INJ_GetSequencerRanks()
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On STM32MP1, some fast channels are available: fast analog inputs
+ * coming from GPIO pads (ADC_IN0..5).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ *
+ * Note: This parameter is discarded in case of SW start:
+ * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @param Rank1_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param Rank2_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param Rank3_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param Rank4_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+ uint32_t TriggerSource,
+ uint32_t ExternalTriggerEdge,
+ uint32_t SequencerNbRanks,
+ uint32_t Rank1_Channel,
+ uint32_t Rank2_Channel,
+ uint32_t Rank3_Channel,
+ uint32_t Rank4_Channel)
+{
+ /* Set bits with content of parameter "Rankx_Channel" with bits position */
+ /* in register depending on literal "LL_ADC_INJ_RANK_x". */
+ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
+ /* because containing other bits reserved for other purpose. */
+ /* If parameter "TriggerSource" is set to SW start, then parameter */
+ /* "ExternalTriggerEdge" is discarded. */
+ register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+ MODIFY_REG(ADCx->JSQR,
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JL,
+ (TriggerSource & ADC_JSQR_JEXTSEL) |
+ (ExternalTriggerEdge * (is_trigger_not_sw)) |
+ (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+ SequencerNbRanks
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
+ SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0 (3)
+ * @arg @ref LL_ADC_CHANNEL_1 (3)
+ * @arg @ref LL_ADC_CHANNEL_2 (3)
+ * @arg @ref LL_ADC_CHANNEL_3 (3)
+ * @arg @ref LL_ADC_CHANNEL_4 (3)
+ * @arg @ref LL_ADC_CHANNEL_5 (3)
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_19
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_VCORE (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
+ * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
+ *
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+ * Other channels are slow channels (conversion rate: refer to reference manual).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
+ >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
+ );
+}
+
+/**
+ * @brief Set mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note Channel ending is on channel scope: independently of channel mapped
+ * on ADC group regular or injected.
+ * In differential mode: Differential measurement is carried out
+ * between the selected channel 'i' (positive input) and
+ * channel 'i+1' (negative input). Only channel 'i' has to be
+ * configured, channel 'i+1' is configured automatically.
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32MP1, some channels are internally fixed to single-ended inputs
+ * configuration:
+ * - ADC1: Channels 0, 6, 7, 8, 9, 14, 15, 16, 17, 19
+ * - ADC2: Channels 0, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 19
+ * @note For ADC channels configured in differential mode, both inputs
+ * should be biased at (Vref+)/2 +/-200mV.
+ * (Vref+ is the analog voltage reference)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @param SingleDiff This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+ /* Bits of channels in single or differential mode are set only for */
+ /* differential mode (for single mode, mask of bits allowed to be set is */
+ /* shifted out of range of bits of channels in single or differential mode. */
+ MODIFY_REG(ADCx->DIFSEL,
+ Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+ * @brief Get mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * Therefore, to ensure a channel is configured in single-ended mode,
+ * the configuration of channel itself and the channel 'i-1' must be
+ * read back (to ensure that the selected channel channel has not been
+ * configured in differential mode by the previous channel).
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32MP1, some channels are internally fixed to single-ended inputs
+ * configuration:
+ * - ADC1: Channels 0, 6, 7, 8, 9, 14, 15, 16, 17, 19
+ * - ADC2: Channels 0, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 19
+ * @note One or several values can be selected. In this case, the value
+ * returned is null if all channels are in single ended-mode.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @retval 0: channel in single-ended mode, else: channel in differential mode
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel, multiple channels or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VCORE_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VCORE_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VCORE_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (1)
+ *
+ * (0) On STM32MP1, parameter available only on analog watchdog number: AWD1.\n
+ * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+ /* Set bits with content of parameter "AWDChannelGroup" with bits position */
+ /* in register and register position depending on parameter "AWDy". */
+ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ MODIFY_REG(*preg,
+ (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ AWDChannelGroup & AWDy);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On this AWD number, monitored channel can be retrieved
+ * if only 1 channel is programmed (or none or all channels).
+ * This function cannot retrieve monitored channel if
+ * multiple channels are programmed simultaneously
+ * by bitfield.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
+ *
+ * (0) On STM32MP1, parameter available only on analog watchdog number: AWD1.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+ /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
+ /* (parameter value LL_ADC_AWD_DISABLE). */
+ /* Else, the selected AWD is enabled and is monitoring a group of channels */
+ /* or a single channel. */
+ if (AnalogWDMonitChannels != 0UL)
+ {
+ if (AWDy == LL_ADC_AWD1)
+ {
+ if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
+ {
+ /* AWD monitoring a group of channels */
+ AnalogWDMonitChannels = ((AnalogWDMonitChannels
+ | (ADC_AWD_CR23_CHANNEL_MASK)
+ )
+ & (~(ADC_CFGR_AWD1CH))
+ );
+ }
+ else
+ {
+ /* AWD monitoring a single channel */
+ AnalogWDMonitChannels = (AnalogWDMonitChannels
+ | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
+ );
+ }
+ }
+ else
+ {
+ if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+ {
+ /* AWD monitoring a group of channels */
+ AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
+ | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
+ );
+ }
+ else
+ {
+ /* AWD monitoring a single channel */
+ /* AWD monitoring a group of channels */
+ AnalogWDMonitChannels = (AnalogWDMonitChannels
+ | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+ | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
+ );
+ }
+ }
+ }
+
+ return AnalogWDMonitChannels;
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
+ * impacted: the comparison of analog watchdog thresholds is done
+ * on oversampling intermediate computation (after ratio, before shift
+ * application): intermediate register bitfield [32:7]
+ * (26 most significant bits).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either ADC groups regular or injected.
+ * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
+ uint32_t AWDThresholdValue)
+{
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */
+ /* position in register and register position depending on parameters */
+ /* "AWDThresholdsHighLow" and "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ + (AWDThresholdsHighLow));
+
+ MODIFY_REG(*preg, ADC_LTR1_LT1, AWDThresholdValue);
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high,
+ * threshold low or raw data with ADC thresholds high and low
+ * concatenated.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ + (AWDThresholdsHighLow));
+
+ return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LT1));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+ * @{
+ */
+
+/**
+ * @brief Set ADC oversampling scope: ADC groups regular and-or injected
+ * (availability of ADC group injected depends on STM32 families).
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
+ * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
+ * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
+ * @param ADCx ADC instance
+ * @param OvsScope This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_DISABLE
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+}
+
+/**
+ * @brief Get ADC oversampling scope: ADC groups regular and-or injected
+ * (availability of ADC group injected depends on STM32 families).
+ * @note If both groups regular and injected are selected,
+ * specify behavior of ADC group injected interrupting
+ * group regular: when ADC group injected is triggered,
+ * the oversampling on ADC group regular is either
+ * temporary stopped and continued, or resumed from start
+ * (oversampler buffer reset).
+ * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
+ * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
+ * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OVS_DISABLE
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+ * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+ * @arg @ref LL_ADC_OVS_GRP_INJECTED
+ * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+}
+
+/**
+ * @brief Set ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @note On this STM32 serie, oversampling discontinuous mode
+ * (triggered mode) can be used only when oversampling is
+ * set on group regular only and in resumed mode.
+ * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
+ * @param ADCx ADC instance
+ * @param OverSamplingDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_REG_CONT
+ * @arg @ref LL_ADC_OVS_REG_DISCONT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+}
+
+/**
+ * @brief Get ADC oversampling discontinuous mode (triggered mode)
+ * on the selected ADC group.
+ * @note Number of oversampled conversions are done either in:
+ * - continuous mode (all conversions of oversampling ratio
+ * are done from 1 trigger)
+ * - discontinuous mode (each conversion of oversampling ratio
+ * needs a trigger)
+ * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OVS_REG_CONT
+ * @arg @ref LL_ADC_OVS_REG_DISCONT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+}
+
+/**
+ * @brief Set ADC oversampling
+ * (impacting both ADC groups regular and injected)
+ * @note This function set the 2 items of oversampling configuration:
+ * - ratio
+ * - shift
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
+ * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
+ * @param ADCx ADC instance
+ * @param Ratio This parameter can be in the range from 1 to 1024.
+ * @param Shift This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+ MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OSR_Pos))));
+}
+
+/**
+ * @brief Get ADC oversampling ratio
+ * (impacting both ADC groups regular and injected)
+ * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
+ * @param ADCx ADC instance
+ * @retval Ratio This parameter can be in the from 1 to 1024.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+{
+ return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OSR))+(1UL << ADC_CFGR2_OSR_Pos)) >> ADC_CFGR2_OSR_Pos);
+}
+
+/**
+ * @brief Get ADC oversampling shift
+ * (impacting both ADC groups regular and injected)
+ * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
+ * @param ADCx ADC instance
+ * @retval Shift This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OVS_SHIFT_NONE
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
+ * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+ * @{
+ */
+/**
+ * @brief Set ADC boost mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC boost must be configured, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CR BOOST LL_ADC_SetBoostMode
+ * @param ADCx ADC instance
+ * @param BoostMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_BOOST_MODE_DISABLE
+ * @arg @ref LL_ADC_BOOST_MODE_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
+{
+ MODIFY_REG(ADCx->CR, ADC_CR_BOOST, BoostMode);
+}
+
+/**
+ * @brief Get ADC boost mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC boost must be configured, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CR BOOST LL_ADC_GetBoostMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_BOOST_MODE_DISABLE
+ * @arg @ref LL_ADC_BOOST_MODE_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_BOOST));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Set ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DUAL LL_ADC_SetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param Multimode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+ * @brief Get ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CCR DUAL LL_ADC_GetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+ * @brief Set ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled
+ * or enabled without conversion on going on group regular.
+ * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiDMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
+}
+
+/**
+ * @brief Get ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
+}
+
+/**
+ * @brief Set ADC multimode delay between 2 sampling phases.
+ * @note The sampling delay range depends on ADC resolution:
+ * - ADC resolution 12 bits can have maximum delay of 12 cycles.
+ * - ADC resolution 10 bits can have maximum delay of 10 cycles.
+ * - ADC resolution 8 bits can have maximum delay of 8 cycles.
+ * - ADC resolution 6 bits can have maximum delay of 6 cycles.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiTwoSamplingDelay This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (4)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5 (5)
+ *
+ * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
+ * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
+ * (3) Parameter available only if ADC resolution is 16 or 14 bits.
+ * (4) Parameter available only if ADC resolution is 16 bits.
+ * (5) Parameter available only if ADC resolution is 16 bits.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+ * @brief Get ADC multimode delay between 2 sampling phases.
+ * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (4)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5 (5)
+ *
+ * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
+ * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
+ * (3) Parameter available only if ADC resolution is 16 or 14 bits.
+ * (4) Parameter available only if ADC resolution is 16 bits.
+ * (5) Parameter available only if ADC resolution is 16 bits.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Put ADC instance in deep power down state.
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down
+ * state, the internal analog calibration is lost. After exiting from
+ * deep power down, calibration must be relaunched or calibration factor
+ * (preliminarily saved) must be set back into calibration register.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_DEEPPWD);
+}
+
+/**
+ * @brief Disable ADC deep power down mode.
+ * @note In case of ADC calibration necessary: When ADC is in deep-power-down
+ * state, the internal analog calibration is lost. After exiting from
+ * deep power down, calibration must be relaunched or calibration factor
+ * (preliminarily saved) must be set back into calibration register.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance deep power down state.
+ * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
+ * @param ADCx ADC instance
+ * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable ADC instance internal voltage regulator.
+ * @note On this STM32 serie, after ADC internal voltage regulator enable,
+ * a delay for ADC internal voltage regulator stabilization
+ * is required before performing a ADC calibration or ADC enable.
+ * Refer to device datasheet, parameter tADCVREG_STUP.
+ * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADVREGEN);
+}
+
+/**
+ * @brief Disable ADC internal voltage regulator.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance internal voltage regulator state.
+ * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
+ * @param ADCx ADC instance
+ * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 serie, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled and ADC internal voltage regulator enabled.
+ * @rmtoll CR ADEN LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADEN);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be not disabled. Must be enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CR ADDIS LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADDIS);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll CR ADEN LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get the selected ADC instance disable state.
+ * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no ADC disable command on going.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * are required between ADC end of calibration and ADC enable.
+ * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+ * @note Calibration duration:
+ * - Calibration of offset: 520 ADC clock cycles
+ * - Calibration of linearity: 131072 ADC clock cycles
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration run must be performed for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * Calibration of linearity is common to both
+ * single-ended and differential modes
+ * (calibration run can be performed only once).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
+ * CR ADCALDIF LL_ADC_StartCalibration\n
+ * CR ADCALLIN LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @param CalibrationMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CALIB_OFFSET
+ * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADSTART);
+}
+
+/**
+ * @brief Stop ADC group regular conversion.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADSTP);
+}
+
+/**
+ * @brief Get ADC group regular conversion state.
+ * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group regular command of conversion stop state
+ * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 16 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 14 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave
+ * or raw data with ADC master and slave concatenated.
+ * @note If raw data with ADC master and slave concatenated is retrieved,
+ * a macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * (however this macro is mainly intended for multimode
+ * transfer by DMA, because this function can do the same
+ * by getting multimode conversion data of ADC master or ADC slave
+ * separately).
+ * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
+ * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ConversionData This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+ ConversionData)
+ >> (POSITION_VAL(ConversionData) & 0x1FUL)
+ );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group injected,
+ * without conversion stop command on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_JADSTART);
+}
+
+/**
+ * @brief Stop ADC group injected conversion.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_JADSTP);
+}
+
+/**
+ * @brief Get ADC group injected conversion state.
+ * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group injected command of conversion stop state
+ * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 16 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData16
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 14 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData14
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+ return (uint8_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC ready.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear flag ADC ready.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+ * @brief Clear flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get flag multimode ADC ready of the ADC master.
+ * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC ready of the ADC slave.
+ * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+ * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+ * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+ * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+ * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC master.
+ * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC slave.
+ * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
+ * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
+ * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+ * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+ * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+ * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+ * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
+ * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
+ * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
+ * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave.
+ * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
+ * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
+ * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
+ * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
+ * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Enable ADC group regular interruption overrun.
+ * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Disable interruption ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Disable interruption ADC group regular overrun.
+ * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Get state of interruption ADC ready
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular overrun
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sampling
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC group injected context queue overflow interrupt state
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 2
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 3
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
+{
+ return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32MP1xx_LL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c
new file mode 100644
index 0000000..ccd36e0
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c
@@ -0,0 +1,941 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal.c
+ * @author MCD Application Team
+ * @brief HAL module driver.
+ * This is the common part of the HAL initialization
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The common HAL driver contains a set of generic and common APIs that can be
+ used by the PPP peripheral drivers and the user to start using the HAL.
+ [..]
+ The HAL contains two APIs' categories:
+ (+) Common HAL APIs
+ (+) Services HAL APIs
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL HAL
+ * @brief HAL module driver.
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HAL_Private_Defines HAL Private Defines
+ * @{
+ */
+
+/**
+ * @brief STM32MP1xx HAL Driver version number
+ */
+#define __STM32MP1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32MP1xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
+#define __STM32MP1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32MP1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32MP1xx_HAL_VERSION ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\
+ |(__STM32MP1xx_HAL_VERSION_SUB1 << 16)\
+ |(__STM32MP1xx_HAL_VERSION_SUB2 << 8 )\
+ |(__STM32MP1xx_HAL_VERSION_RC))
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+#define SYSCFG_DEFAULT_TIMEOUT 100U
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Exported variables --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+ * @{
+ */
+__IO uint32_t uwTick;
+#if defined(CORE_CM4)
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+#else /* CA7 */
+uint32_t uwTickPrio = (1UL << 4); /* Invalid PRIO */
+#endif
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Private_Functions HAL Private Functions
+ * @{
+ */
+
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initializes the Flash interface the NVIC allocation and initial clock
+ configuration. It initializes the systick also when timeout is needed
+ and the backup domain when enabled.
+ (+) De-Initializes common part of the HAL.
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
+ can eventually implement his proper time base source (a general purpose
+ timer for example or other time source), keeping in mind that Time base
+ duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+ handled in milliseconds basis.
+ (++) Time base configuration function (HAL_InitTick ()) is called automatically
+ at the beginning of the program after reset by HAL_Init() or at any time
+ when clock is configured, by HAL_RCC_ClockConfig().
+ (++) Source of time base is configured to generate interrupts at regular
+ time intervals. Care must be taken if HAL_Delay() is called from a
+ peripheral ISR process, the Tick interrupt line must have higher priority
+ (numerically lower) than the peripheral interrupt. Otherwise the caller
+ ISR process will be blocked.
+ (++) functions affecting time base configurations are declared as __weak
+ to make override possible in case of other implementations in user file.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is used to initialize the HAL Library; it must be the first
+ * instruction to be executed in the main program (before to call any other
+ * HAL function), it performs the following:
+ * Configures the SysTick to generate an interrupt each 1 millisecond,
+ * which is clocked by the HSI (at this stage, the clock is not yet
+ * configured and thus the system is running from the internal HSI at 64 MHz).
+ * Set NVIC Group Priority to 4.
+ * Calls the HAL_MspInit() callback function defined in user file
+ * "stm32mp1xx_hal_msp.c" to do the global low level hardware initialization
+ *
+ * @note SysTick is used as time base for the HAL_Delay() function, the application
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct HAL operation.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ /* Set Interrupt Group Priority */
+#if defined (CORE_CM4)
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+#endif
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
+
+ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Init the low level hardware */
+ HAL_MspInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief This function de-Initializes common part of the HAL and stops the systick.
+ * This function is optional.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+ /* Reset of all peripherals */
+
+
+ /* De-Init the low level hardware */
+ HAL_MspDeInit();
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the MSP.
+ * @retval None
+ */
+__weak void HAL_MspDeInit(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief This function configures the source of the time base.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
+ * @note In the default implementation, SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals.
+ * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+ * The the SysTick interrupt must have higher priority (numerically lower)
+ * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+ * The function is declared as __weak to be overwritten in case of other
+ * implementation in user file.
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ /*Configure the Tick to have interrupt in 1ms time basis*/
+#if defined (CORE_CA7)
+
+#if defined(USE_ST_CASIS)
+ HAL_SYSTICK_Config(SystemCoreClock/1000);
+#elif defined (USE_PL1_SecurePhysicalTimer_IRQ)
+ /* Stop Timer */
+ PL1_SetControl(0x0);
+
+ PL1_SetCounterFrequency(HSI_VALUE);
+
+ /* Initialize Counter */
+ PL1_SetLoadValue(HSI_VALUE/1000);
+
+ /* Disable corresponding IRQ */
+ IRQ_Disable(SecurePhysicalTimer_IRQn);
+ IRQ_ClearPending(SecurePhysicalTimer_IRQn);
+
+ /* Set timer priority to lowest (Only bit 7:3 are implemented in MP1 CA7 GIC) */
+ /* TickPriority is based on 16 level priority (from MCUs) so set it in 7:4 and leave bit 3=0 */
+ if (TickPriority < (1UL << 4))
+ {
+ IRQ_SetPriority(SecurePhysicalTimer_IRQn, TickPriority << 4);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set edge-triggered IRQ */
+ IRQ_SetMode(SecurePhysicalTimer_IRQn, IRQ_MODE_TRIG_EDGE);
+
+ /* Enable corresponding interrupt */
+ IRQ_Enable(SecurePhysicalTimer_IRQn);
+
+ /* Kick start Timer */
+ PL1_SetControl(0x1);
+#else
+ /*Set Counter Frequency */
+ PL1_SetCounterFrequency(HSI_VALUE);
+ // __set_CNTFRQ(HSI_VALUE);
+ /* Initialize Counter */
+ PL1_SetLoadValue(0x1);
+ // __set_CNTP_TVAL(0x1);
+#endif
+
+#endif /* CORE_CA7 */
+
+
+#if defined (CORE_CM4)
+ if ((uint32_t)uwTickFreq == 0U)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock /(1000U / uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+#endif /* CORE_CM4 */
+
+
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HAL_Group2 HAL Control functions
+ * @brief HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### HAL Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Provide a tick value in millisecond
+ (+) Provide a blocking delay in millisecond
+ (+) Suspend the time base source interrupt
+ (+) Resume the time base source interrupt
+ (+) Get the HAL API driver version
+ (+) Get the device identifier
+ (+) Get the device revision identifier
+ (+) Enable/Disable Debug module during SLEEP mode
+ (+) Enable/Disable Debug module during STOP mode
+ (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief This function is called to increment a global variable "uwTick"
+ * used as application time base.
+ * @note In the default implementation, this variable is incremented each 1ms
+ * in Systick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ uwTick += (uint32_t)uwTickFreq;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+#if defined (CORE_CA7)
+
+#if defined (USE_ST_CASIS)
+ return ( Gen_Timer_Get_PhysicalCount() / (HSI_VALUE/1000));
+#elif defined (USE_PL1_SecurePhysicalTimer_IRQ)
+ /* tick is incremented in SecurePhysicalTimer_IRQ handler */
+ return uwTick;
+#else
+ /* tick value directly got from 64bits CA7 register*/
+ return ( PL1_GetCurrentPhysicalValue() / (HSI_VALUE/1000));
+#endif
+
+#endif /* CORE_CA7 */
+
+
+#if defined (CORE_CM4)
+ /* tick is incremented in systick handler */
+ return uwTick;
+#endif /* CORE_CM4 */
+
+}
+
+#if defined (CORE_CM4)
+/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval Status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_TickFreqTypeDef prevTickFreq;
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+
+ if (status != HAL_OK)
+ {
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+#endif
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on variable incremented.
+ * @note In the default implementation , SysTick timer is the source of time base.
+ * It is used to generate interrupts at regular time intervals where uwTick
+ * is incremented.
+ * @note ThiS function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while ((HAL_GetTick() - tickstart) < wait)
+ {
+ }
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+ * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is suspended.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_SuspendTick(void)
+{
+#if defined (CORE_CA7)
+#elif defined (CORE_CM4)
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+#endif
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note In the default implementation , SysTick timer is the source of time base. It is
+ * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+ * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is resumed.
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_ResumeTick(void)
+{
+#if defined (CORE_CA7)
+#elif defined (CORE_CM4)
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+#endif
+}
+
+/**
+ * @brief Returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32MP1xx_HAL_VERSION;
+}
+
+/**
+ * @brief Returns the device revision identifier.
+ * @retval Device revision identifier
+ */
+uint32_t HAL_GetREVID(void)
+{
+ return((DBGMCU->IDCODE) >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @retval Device identifier
+ */
+uint32_t HAL_GetDEVID(void)
+{
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Enable DBG wake up on AIEC
+ * @retval None
+ */
+void HAL_EnableDBGWakeUp(void)
+{
+#if defined (CORE_CA7)
+ SET_BIT(EXTI_C1->IMR3, EXTI_IMR3_IM75);
+#elif defined (CORE_CM4)
+ SET_BIT(EXTI_C2->IMR3, EXTI_IMR3_IM75);
+#endif
+}
+
+/**
+ * @brief Disable DBG wake up on AIEC
+ * @retval None
+ */
+void HAL_DisableDBGWakeUp(void)
+{
+#if defined (CORE_CA7)
+ CLEAR_BIT(EXTI_C1->IMR3, EXTI_IMR3_IM75);
+#elif defined (CORE_CM4)
+ CLEAR_BIT(EXTI_C2->IMR3, EXTI_IMR3_IM75);
+#endif
+}
+
+/**
+ * @brief Enable the Debug Module during Domain1 SLEEP mode
+ * @retval None
+ */
+void HAL_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during Domain1 SLEEP mode
+ * @retval None
+ */
+void HAL_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during Domain1 STOP mode
+ * @retval None
+ */
+void HAL_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during Domain1 STOP mode
+ * @retval None
+ */
+void HAL_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during Domain1 STANDBY mode
+ * @retval None
+ */
+void HAL_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during Domain1 STANDBY mode
+ * @retval None
+ */
+void HAL_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+
+/**
+ * @brief Configure the internal voltage reference buffer voltage scale.
+ * @param VoltageScaling specifies the output voltage to achieve
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
+ * This requires VDDA equal to or higher than 2.4 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
+ * This requires VDDA equal to or higher than 2.8 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
+ * This requires VDDA equal to or higher than 1.8 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
+ * This requires VDDA equal to or higher than 2.1 V.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+ * @brief Configure the internal voltage reference buffer high impedance mode.
+ * @param Mode specifies the high impedance mode
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+ * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+
+ MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+ * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
+ * @retval None
+ */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+
+ MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+ * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
+ * @retval HAL_OK/HAL_TIMEOUT
+ */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+ uint32_t tickstart = 0;
+
+ SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait for VRR bit */
+ while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
+ {
+ if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
+ *
+ * @retval None
+ */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+ CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+
+/**
+ * @brief Ethernet PHY Interface Selection either MII or RMII
+ * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_ETH_MII : Select the Media Independent Interface
+ * @arg SYSCFG_ETH_GMII : Select the Gigabit Media Independent Interface
+ * @arg SYSCFG_ETH_RGMII: Select the Gigabit Reduced Media Independent Interface
+ * @arg SYSCFG_ETH_RMII : Select the Reduced Media Independent Interface
+ * @retval None
+ */
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
+ SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCSETR_ETH_SEL|SYSCFG_PMCSETR_ETH_SELMII_SEL);
+ SET_BIT(SYSCFG->PMCSETR, (uint32_t)(SYSCFG_ETHInterface));
+}
+
+/**
+ * @brief Analog Switch control for dual analog pads.
+ * @param SYSCFG_AnalogSwitch: Selects the analog pad
+ * This parameter can be one or a combination of the following values:
+ * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
+ * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch
+ * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (
+ * This parameter can be one or a combination of the following values:
+ * @arg SYSCFG_SWITCH_PA0_OPEN
+ * @arg SYSCFG_SWITCH_PA0_CLOSE
+ * @arg SYSCFG_SWITCH_PA1_OPEN
+ * @arg SYSCFG_SWITCH_PA1_CLOSE
+ * @retval None
+ */
+
+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
+ assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
+ SET_BIT(SYSCFG->PMCCLRR, SYSCFG_AnalogSwitch);
+ SET_BIT(SYSCFG->PMCSETR, (uint32_t)(SYSCFG_SwitchState));
+
+}
+
+
+/**
+ * @brief Enables the booster to reduce the total harmonic distortion of the analog
+ * switch when the supply voltage is lower than 2.7 V.
+ * @note Activating the booster allows to guaranty the analog switch AC performance
+ * when the supply voltage is below 2.7 V: in this case, the analog switch
+ * performance is the same on the full voltage range
+ * @retval None
+ */
+void HAL_SYSCFG_EnableBOOST(void)
+{
+ SET_BIT(SYSCFG->PMCSETR, SYSCFG_PMCSETR_EN_BOOSTER) ;
+}
+
+/**
+ * @brief Disables the booster
+ * @note Activating the booster allows to guaranty the analog switch AC performance
+ * when the supply voltage is below 2.7 V: in this case, the analog switch
+ * performance is the same on the full voltage range
+ * @retval None
+ */
+void HAL_SYSCFG_DisableBOOST(void)
+{
+ SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCCLRR_EN_BOOSTER) ;
+}
+
+
+/**
+ * @brief Enables the I/O Compensation Cell.
+ * @note The I/O compensation cell can be used only when the device supply
+ * voltage ranges from 2.4 to 3.6 V.
+ * @retval None
+ */
+void HAL_EnableCompensationCell(void)
+{
+#if defined(CORE_CM4)
+ SET_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MCU_EN) ;
+#elif defined(CORE_CA7)
+ SET_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MPU_EN) ;
+#endif
+}
+
+/**
+ * @brief Power-down the I/O Compensation Cell.
+ * @note The I/O compensation cell can be used only when the device supply
+ * voltage ranges from 2.4 to 3.6 V.
+ * @retval None
+ */
+void HAL_DisableCompensationCell(void)
+{
+#if defined(CORE_CM4)
+ SET_BIT(SYSCFG->CMPENCLRR, SYSCFG_CMPENCLRR_MCU_EN) ;
+#elif defined(CORE_CA7)
+ SET_BIT(SYSCFG->CMPENCLRR, SYSCFG_CMPENCLRR_MPU_EN) ;
+#endif
+}
+
+
+/**
+ * @brief To Enable optimize the I/O speed when the product voltage is low.
+ * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+ * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+ * higher than 2.5 V might be destructive.
+ * @param SYSCFG_HighSpeedSignal: Signal selection (TRACE, QUADSPI...)
+ * This parameter can be one or a combination of the following values:
+ * @arg SYSCFG_HIGHSPEED_TRACE_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_QUADSPI_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_ETH_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_SDMMC_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_SPI_SIGNAL
+ * @retval None
+ */
+void HAL_SYSCFG_EnableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal )
+{
+ SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_HighSpeedSignal) ;
+}
+
+/**
+ * @brief To Disable optimize the I/O speed when the product voltage is low.
+ * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
+ * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
+ * higher than 2.5 V might be destructive.
+ * @param SYSCFG_HighSpeedSignal: Signal selection (TRACE, QUADSPI...)
+ * This parameter can be one or a combination of the following values:
+ * @arg SYSCFG_HIGHSPEED_TRACE_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_QUADSPI_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_ETH_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_SDMMC_SIGNAL
+ * @arg SYSCFG_HIGHSPEED_SPI_SIGNAL
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal )
+{
+ SET_BIT(SYSCFG->IOCTRLCLRR, SYSCFG_HighSpeedSignal) ;
+}
+
+/**
+ * @brief Code selection for the I/O Compensation cell
+ * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
+ * This parameter can be one of the following values:
+ * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
+ * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
+ * @retval None
+ */
+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
+ MODIFY_REG(SYSCFG->CMPCR, SYSCFG_CMPCR_SW_CTRL, (uint32_t)(SYSCFG_CompCode));
+}
+
+/**
+ * @brief Code selection for the I/O Compensation cell
+ * @param SYSCFG_PMOSCode: PMOS compensation code
+ * This code is applied to the I/O compensation cell when the CS bit of the
+ * SYSCFG_CMPCR is set
+ * @param SYSCFG_NMOSCode: NMOS compensation code
+ * This code is applied to the I/O compensation cell when the CS bit of the
+ * SYSCFG_CMPCR is set
+ * @retval None
+ */
+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
+ assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
+ MODIFY_REG(SYSCFG->CMPCR, SYSCFG_CMPCR_RANSRC|SYSCFG_CMPCR_RAPSRC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
+}
+
+/**
+ * @brief Disable IO compensation mechanism
+ * E.g. before going into STOP
+ * @retval None
+ */
+void HAL_SYSCFG_DisableIOCompensation(void)
+{
+ uint32_t pmos_val = 0;
+ uint32_t nmos_val = 0;
+
+ /* Get I/O compensation cell values for PMOS and NMOS transistors */
+ pmos_val = __HAL_SYSCFG_GET_PMOS_CMP();
+ nmos_val = __HAL_SYSCFG_GET_NMOS_CMP();
+
+ /* Copy actual value of SYSCFG_CMPCR.APSRC[3:0]/ANSRC[3:0] in
+ * SYSCFG_CMPCR.RAPSRC[3:0]/RANSRC[3:0]
+ */
+ HAL_SYSCFG_CompensationCodeConfig(pmos_val, nmos_val);
+
+ /* Set SYSCFG_CMPCR.SW_CTRL = 1 */
+ HAL_SYSCFG_CompensationCodeSelect(SYSCFG_REGISTER_CODE);
+
+ /* Disable the Compensation Cell */
+ HAL_DisableCompensationCell();
+}
+
+/**
+ * @brief Enable IO compensation mechanism
+ * By default the I/O compensation cell is not used. However when the
+ * I/O output buffer speed is configured in 50 MHz mode and above, it
+ * is recommended to use the compensation cell for a slew rate control
+ * on I/O tf(IO)out/tr(IO)out commutation to reduce the I/O noise on
+ * the power supply.
+ * @note Use polling mode for timeout as code could be used on critical
+ * section (IRQs disabled)
+ * @retval HAL_StatusTypeDef value
+ */
+HAL_StatusTypeDef HAL_SYSCFG_EnableIOCompensation(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t count = SYSCFG_DEFAULT_TIMEOUT * (SystemCoreClock / 20U / 1000U);
+
+ /* Set SYSCFG_CMPENSETR.MCU_EN */
+ HAL_EnableCompensationCell();
+
+ /* Wait SYSCFG_CMPCR.READY = 1 */
+ do
+ {
+ if (count-- == 0U)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ while (__HAL_SYSCFG_CMP_CELL_GET_FLAG() == 0U);
+
+ /* Set SYSCFG_CMPCR.SW_CTRL = 0 */
+ HAL_SYSCFG_CompensationCodeSelect(SYSCFG_CELL_CODE);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
new file mode 100644
index 0000000..afc9859
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
@@ -0,0 +1,3740 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_adc.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Initialization and de-initialization functions
+ * ++ Initialization and Configuration of ADC
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of regular
+ * group, using 3 possible modes: polling, interruption or DMA.
+ * + Control functions
+ * ++ Channels configuration on regular group
+ * ++ Analog Watchdog configuration
+ * + State functions
+ * ++ ADC state machine management
+ * ++ Interrupts and flags management
+ * Other functions (extended functions) are available in file
+ * "stm32mp1xx_hal_adc_ex.c".
+ *
+ @verbatim
+ ==============================================================================
+ ##### ADC peripheral features #####
+ ==============================================================================
+ [..]
+ (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
+
+ (+) Interrupt generation at the end of regular conversion and in case of
+ analog watchdog or overrun events.
+
+ (+) Single and continuous conversion modes.
+
+ (+) Scan mode for conversion of several channels sequentially.
+
+ (+) Data alignment with in-built data coherency.
+
+ (+) Programmable sampling time (channel wise)
+
+ (+) External trigger (timer or EXTI) with configurable polarity
+
+ (+) DMA request generation for transfer of conversions data of regular group.
+
+ (+) Configurable delay between conversions in Dual interleaved mode.
+
+ (+) ADC channels selectable single/differential input.
+
+ (+) ADC offset shared on 4 offset instances.
+ (+) ADC calibration
+
+ (+) ADC conversion of regular group.
+
+ (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+ (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+ Vdda or to an external voltage reference).
+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ *** Configuration of top level parameters related to ADC ***
+ ============================================================
+ [..]
+
+ (#) Enable the ADC interface
+ (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+ (++) Two clock settings are mandatory:
+ (+++) ADC clock (core clock, also possibly conversion clock).
+
+ (+++) ADC clock (conversions clock).
+ Two possible clock sources: synchronous clock derived from AHB clock
+ or asynchronous clock derived from system clock, the PLL4 or the PLL3.
+
+ (+++) Example:
+ Into HAL_ADC_MspInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
+
+ RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected)
+ (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
+ (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
+ (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+ (++) ADC clock source and clock prescaler are configured at ADC level with
+ parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+ (#) ADC pins configuration
+ (++) Enable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Configure these ADC pins in analog mode
+ using function HAL_GPIO_Init()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Configure the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding ADC interruption vector
+ ADCx_IRQHandler().
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+ using function HAL_DMA_Init().
+ (++) Configure the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+ into the function of corresponding DMA interruption vector
+ DMAx_Channelx_IRQHandler().
+
+ *** Configuration of ADC, group regular, channels parameters ***
+ ================================================================
+ [..]
+
+ (#) Configure the ADC parameters (resolution, data alignment, ...)
+ and regular group parameters (conversion trigger, sequencer, ...)
+ using function HAL_ADC_Init().
+
+ (#) Configure the channels for regular group parameters (channel number,
+ channel rank into sequencer, ..., into regular group)
+ using function HAL_ADC_ConfigChannel().
+
+ (#) Optionally, configure the analog watchdog parameters (channels
+ monitored, thresholds, ...)
+ using function HAL_ADC_AnalogWDGConfig().
+
+ *** Execution of ADC conversions ***
+ ====================================
+ [..]
+
+ (#) Optionally, perform an automatic ADC calibration to improve the
+ conversion accuracy
+ using function HAL_ADCEx_Calibration_Start().
+
+ (#) ADC driver can be used among three modes: polling, interruption,
+ transfer by DMA.
+
+ (++) ADC conversion by polling:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start()
+ (+++) Wait for ADC conversion completion
+ using function HAL_ADC_PollForConversion()
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop()
+
+ (++) ADC conversion by interruption:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_IT()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback()
+ (this function must be implemented in user program)
+ (+++) Retrieve conversion results
+ using function HAL_ADC_GetValue()
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_IT()
+
+ (++) ADC conversion with transfer by DMA:
+ (+++) Activate the ADC peripheral and start conversions
+ using function HAL_ADC_Start_DMA()
+ (+++) Wait for ADC conversion completion by call of function
+ HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+ (these functions must be implemented in user program)
+ (+++) Conversion results are automatically transferred by DMA into
+ destination variable address.
+ (+++) Stop conversion and disable the ADC peripheral
+ using function HAL_ADC_Stop_DMA()
+
+ [..]
+
+ (@) Callback functions must be implemented in user program:
+ (+@) HAL_ADC_ErrorCallback()
+ (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+ (+@) HAL_ADC_ConvCpltCallback()
+ (+@) HAL_ADC_ConvHalfCpltCallback
+
+ *** Deinitialization of ADC ***
+ ============================================================
+ [..]
+
+ (#) Disable the ADC interface
+ (++) ADC clock can be hard reset and disabled at RCC top level.
+ (++) Hard reset of ADC peripherals
+ using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+ (++) ADC clock disable
+ using the equivalent macro/functions as configuration step.
+ (+++) Example:
+ Into HAL_ADC_MspDeInit() (recommended code location) or with
+ other device clock parameters configuration:
+ (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+ (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+ (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+ (#) ADC pins configuration
+ (++) Disable the clock for the ADC GPIOs
+ using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+ (#) Optionally, in case of usage of ADC with interruptions:
+ (++) Disable the NVIC for ADC
+ using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+ (#) Optionally, in case of usage of DMA:
+ (++) Deinitialize the DMA
+ using function HAL_DMA_Init().
+ (++) Disable the NVIC for DMA
+ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+ [..]
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
+ (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
+ (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
+ (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
+ (+) EndOfSamplingCallback : ADC end of sampling callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADC ADC
+ * @brief ADC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+ * @{
+ */
+#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES |\
+ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
+ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
+ when no regular conversion is on-going */
+
+#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\
+ ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
+ ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
+ (neither regular nor injected) is on-going */
+
+/* Timeout values for ADC operations (enable settling time, */
+/* disable settling time, ...). */
+/* Values defined to be higher than worst cases: low clock frequency, */
+/* maximum prescalers. */
+#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
+#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
+
+/* Timeout to wait for current conversion on going to be completed. */
+/* Timeout fixed to worst case, for 1 channel. */
+/* - maximum sampling time (830.5 adc_clk) */
+/* - ADC resolution (Tsar 16 bits= 16.5 adc_clk) */
+/* - ADC clock with prescaler 256 */
+/* 823 * 256 = 210688 clock cycles max */
+/* Unit: cycles of CPU clock. */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief ADC Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the ADC.
+ (+) De-initialize the ADC.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the ADC peripheral and regular group according to
+ * parameters specified in structure "ADC_InitTypeDef".
+ * @note As prerequisite, ADC clock must be configured at RCC top level
+ * (refer to description of RCC configuration for ADC
+ * in header of this file).
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+ * coming from ADC state reset. Following calls to this function can
+ * be used to reconfigure some parameters of ADC_InitTypeDef
+ * structure on the fly, without modifying MSP configuration. If ADC
+ * MSP has to be modified again, HAL_ADC_DeInit() must be called
+ * before HAL_ADC_Init().
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_InitTypeDef".
+ * @note This function configures the ADC within 2 scopes: scope of entire
+ * ADC and scope of regular group. For parameters details, see comments
+ * of structure "ADC_InitTypeDef".
+ * @note Parameters related to common ADC registers (ADC clock mode) are set
+ * only if all ADCs are disabled.
+ * If this is not the case, these common parameters setting are
+ * bypassed without error reporting: it can be the intended behaviour in
+ * case of update of a parameter of ADC_InitTypeDef on the fly,
+ * without disabling the other ADCs.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpCFGR;
+ uint32_t tmp_adc_reg_is_conversion_on_going;
+ __IO uint32_t wait_loop_index = 0UL;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+ assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+ assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+ assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+ assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+ assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+ }
+ }
+
+ /* DISCEN and CONT bits cannot be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+ /* Actions performed only if ADC is coming from state reset: */
+ /* - Initialization of ADC MSP */
+ if (hadc->State == HAL_ADC_STATE_RESET)
+ {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
+ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
+
+ if (hadc->MspInitCallback == NULL)
+ {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
+ /* Init the low level hardware */
+ HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Initialize Lock */
+ hadc->Lock = HAL_UNLOCKED;
+ }
+
+ /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+ {
+ /* Disable ADC deep power down mode */
+ LL_ADC_DisableDeepPowerDown(hadc->Instance);
+
+ /* System was in deep power down mode, calibration must
+ be relaunched or a previously saved calibration factor
+ re-applied once the ADC voltage regulator is enabled */
+ }
+
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ {
+ /* Enable ADC internal voltage regulator */
+ LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Configuration of ADC parameters if previous preliminary actions are */
+ /* correctly completed and if there is no conversion on going on regular */
+ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
+ /* called to update a parameter on the fly). */
+ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+ if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ )
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Configuration of common ADC parameters */
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - clock configuration */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ /* Reset configuration of ADC common register CCR: */
+ /* */
+ /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
+ /* according to adc->Init.ClockPrescaler. It selects the clock */
+ /* source and sets the clock division factor. */
+ /* */
+ /* Some parameters of this register are not reset, since they are set */
+ /* by other functions and must be kept in case of usage of this */
+ /* function on the fly (update of a parameter of ADC_InitTypeDef */
+ /* without needing to reconfigure all other ADC groups/channels */
+ /* parameters): */
+ /* - when multimode feature is available, multimode-related */
+ /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
+ /* HAL_ADCEx_MultiModeConfigChannel() ) */
+ /* - internal measurement paths: Vbat, temperature sensor, Vref */
+ /* (set into HAL_ADC_ConfigChannel() or */
+ /* HAL_ADCEx_InjectedConfigChannel() ) */
+ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
+ }
+ }
+
+ /* Configuration of ADC: */
+ /* - resolution Init.Resolution */
+ /* - external trigger to start conversion Init.ExternalTrigConv */
+ /* - external trigger polarity Init.ExternalTrigConvEdge */
+ /* - continuous conversion mode Init.ContinuousConvMode */
+ /* - overrun Init.Overrun */
+ /* - discontinuous mode Init.DiscontinuousConvMode */
+ /* - discontinuous mode channel count Init.NbrOfDiscConversion */
+ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ hadc->Init.Overrun |
+ hadc->Init.Resolution |
+ ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+
+ if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ {
+ tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+ }
+
+ /* Enable external trigger if trigger selection is different of software */
+ /* start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ {
+ tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
+ | hadc->Init.ExternalTrigConvEdge
+ );
+ }
+
+ /* Update Configuration Register CFGR */
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Conversion data management Init.ConversionDataManagement */
+ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
+ /* - Oversampling parameters Init.Oversampling */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ tmpCFGR = (
+ ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
+
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+ assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+ assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+ assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+
+ if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
+ || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
+ {
+ /* Multi trigger is not applicable to software-triggered conversions */
+ assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
+ }
+
+ /* Configuration of Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+ /* - Left bit shift */
+ /* - Triggered mode */
+ /* - Oversampling mode (continued/resumed) */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
+ ADC_CFGR2_ROVSE |
+ ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) |
+ hadc->Init.Oversampling.RightBitShift |
+ hadc->Init.Oversampling.TriggeredMode |
+ hadc->Init.Oversampling.OversamplingStopReset);
+
+ }
+ else
+ {
+ /* Disable ADC oversampling scope on ADC group regular */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+ }
+
+ /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
+ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
+
+ /* Configure the BOOST Mode */
+ ADC_ConfigureBoostMode(hadc);
+ }
+
+ /* Configuration of regular group sequencer: */
+ /* - if scan mode is disabled, regular channels sequence length is set to */
+ /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* Parameter "NbrOfConversion" is discarded. */
+ /* Note: Scan mode is not present by hardware on this device, but */
+ /* emulated by software for alignment over all STM32 devices. */
+ /* - if scan mode is enabled, regular channels sequence length is set to */
+ /* parameter "NbrOfConversion". */
+
+ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ {
+ /* Set number of ranks in regular group sequencer */
+ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ }
+
+ /* Initialize the ADC state */
+ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Deinitialize the ADC peripheral registers to their default reset
+ * values, with deinitialization of the ADC MSP.
+ * @note For devices with several ADCs: reset of ADC common registers is done
+ * only if all ADCs sharing the same common group are disabled.
+ * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+ * all ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * If this is not the case, reset of these common parameters reset is
+ * bypassed without error reporting: it can be the intended behavior in
+ * case of reset of a single ADC while the other ADCs sharing the same
+ * common group is still running.
+ * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+ * this saves more power by reducing leakage currents
+ * and is particularly interesting before entering MCU low-power modes.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check ADC handle */
+ if (hadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Stop potential conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ /* Flush register JSQR: reset the queue sequencer when injected */
+ /* queue sequencer is enabled and ADC disabled. */
+ /* The software and hardware triggers of the injected sequence are both */
+ /* internally disabled just after the completion of the last valid */
+ /* injected sequence. */
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Change ADC state */
+ hadc->State = HAL_ADC_STATE_READY;
+ }
+ }
+
+ /* Note: HAL ADC deInit is done independently of ADC conversion stop */
+ /* and disable return status. In case of status fail, attempt to */
+ /* perform deinitialization anyway and it is up user code in */
+ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
+ /* system RCC hard reset. */
+
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
+ ADC_IT_JQOVF | ADC_IT_OVR |
+ ADC_IT_JEOS | ADC_IT_JEOC |
+ ADC_IT_EOS | ADC_IT_EOC |
+ ADC_IT_EOSMP | ADC_IT_RDY));
+
+ /* Reset register ISR */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+ ADC_FLAG_JQOVF | ADC_FLAG_OVR |
+ ADC_FLAG_JEOS | ADC_FLAG_JEOC |
+ ADC_FLAG_EOS | ADC_FLAG_EOC |
+ ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+ /* Reset register CR */
+ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+ ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+ no direct reset applicable.
+ Update CR register to reset value where doable by software */
+ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+ SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
+ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
+ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
+ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL |
+ ADC_CFGR_RES | ADC_CFGR_DMNGT);
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ /* Reset register CFGR2 */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
+ ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+ ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+ ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+ /* Reset register LTR1 and HTR1 */
+ CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1);
+ CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1);
+
+ /* Reset register LTR2 and HTR2*/
+ CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2);
+ CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2);
+
+ /* Reset register LTR3 and HTR3 */
+ CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LT2);
+ CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HT2);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+ ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+ ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+ ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Register JSQR was reset when the ADC was disabled */
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable*/
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+
+ /* ========== Reset common ADC registers ========== */
+
+ /* Software is allowed to change common parameters only when all the other
+ ADCs are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ /* Reset configuration of ADC common register CCR:
+ - clock mode: CKMODE, PRESCEN
+ - multimode related parameters(when this feature is available): DELAY, DUAL
+ (set into HAL_ADCEx_MultiModeConfigChannel() API)
+ - internal measurement paths: Vbat, temperature sensor, Vref (set into
+ HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+ */
+ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+ }
+
+ /* DeInit the low level hardware.
+
+ For example:
+ __HAL_RCC_ADC_FORCE_RESET();
+ __HAL_RCC_ADC_RELEASE_RESET();
+ __HAL_RCC_ADC_CLK_DISABLE();
+
+ Keep in mind that all ADCs use the same clock: disabling
+ the clock will reset all ADCs.
+
+ */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware: RCC clock, NVIC */
+ HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+
+ /* Reset injected channel configuration parameters */
+ hadc->InjectionConfig.ContextQueue = 0;
+ hadc->InjectionConfig.ChannelCount = 0;
+
+ /* Set ADC state */
+ hadc->State = HAL_ADC_STATE_RESET;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Initialize the ADC MSP.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspInit must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief DeInitialize the ADC MSP.
+ * @param hadc ADC handle
+ * @note All ADC instances use the same core clock at RCC level, disabling
+ * the core clock reset all ADC instances).
+ * @retval None
+ */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_MspDeInit must be implemented in the user file.
+ */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+ hadc->InjectedQueueOverflowCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = pCallback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
+ * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+ break;
+
+ case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+ break;
+
+ case HAL_ADC_END_OF_SAMPLING_CB_ID :
+ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+ * @brief ADC IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Start conversion of regular group.
+ (+) Stop conversion of regular group.
+ (+) Poll for conversion complete on regular group.
+ (+) Poll for conversion event.
+ (+) Get result of regular channel conversion.
+ (+) Start conversion of regular group and enable interruptions.
+ (+) Stop conversion of regular group and disable interruptions.
+ (+) Handle ADC interrupt request
+ (+) Start conversion of regular group and enable DMA transfer.
+ (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable ADC, start conversion of regular group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * if ADC is Slave, ADC is enabled but conversion is not started,
+ * if ADC is master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif
+
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ /* if Master ADC JAUTO bit is set, update Slave State in setting
+ HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ }
+#else
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+#endif
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on injected group. If injected group is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for regular group conversion to be completed.
+ * @note ADC conversion flags EOS (end of sequence) and EOC (end of
+ * conversion) are cleared by this function, with an exception:
+ * if low power feature "LowPowerAutoWait" is enabled, flags are
+ * not cleared to not interfere with this feature until data register
+ * is read using function HAL_ADC_GetValue().
+ * @note This function cannot be used in a particular setup: ADC configured
+ * in DMA mode and polling for end of each conversion (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+ * In this case, DMA resets the flag EOC and polling cannot be
+ * performed on each conversion. Nevertheless, polling can still
+ * be performed on the complete sequence (ADC init
+ * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_End;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of conversion selected to end of sequence conversions */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_End = ADC_FLAG_EOS;
+ }
+ /* If end of conversion selected to end of unitary conversion */
+ else /* ADC_EOC_SINGLE_CONV */
+ {
+ /* Verification that ADC configuration is compliant with polling for */
+ /* each conversion: */
+ /* Particular case is ADC configured in DMA mode and ADC sequencer with */
+ /* several ranks and polling for end of each conversion. */
+ /* For code simplicity sake, this particular case is generalized to */
+ /* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* Check DMNGT bit in handle ADC CFGR register */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+ }
+ else
+ {
+ /* Check ADC DMA mode in multimode on ADC group regular */
+ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+ }
+#else
+ /* Check ADC DMA mode */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+ else
+ {
+ tmp_Flag_End = (ADC_FLAG_EOC);
+ }
+#endif
+ }
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of unitary conversion or sequence conversions flag is raised */
+ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going. */
+ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ && (hadc->Init.ContinuousConvMode == DISABLE)
+ )
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* Retrieve handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ /* Retrieve Master ADC CFGR register */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ /* Retrieve handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+ /* Clear polled flag */
+ if (tmp_Flag_End == ADC_FLAG_EOS)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+ }
+ else
+ {
+ /* Clear end of conversion EOC flag of regular group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
+ /* until data register is read using function HAL_ADC_GetValue(). */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Poll for ADC event.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
+ * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
+ * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
+ * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
+ * @arg @ref ADC_OVR_EVENT ADC Overrun event
+ * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
+ * @param Timeout Timeout value in millisecond.
+ * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+ * Indeed, the latter is reset only if hadc->Init.Overrun field is set
+ * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+ * by a new converted data as soon as OVR is cleared.
+ * To reset OVR flag once the preserved data is retrieved, the user can resort
+ * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ /* Check selected event flag */
+ while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ switch (EventType)
+ {
+ /* End Of Sampling event */
+ case ADC_EOSMP_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+ /* Clear the End Of Sampling flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+ break;
+
+ /* Analog watchdog (level out of window) event */
+ /* Note: In case of several analog watchdog enabled, if needed to know */
+ /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
+ /* For example: */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
+ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
+
+ /* Check analog watchdog 1 flag */
+ case ADC_AWD_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+ break;
+
+ /* Check analog watchdog 2 flag */
+ case ADC_AWD2_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+ break;
+
+ /* Check analog watchdog 3 flag */
+ case ADC_AWD3_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+ break;
+
+ /* Injected context queue overflow event */
+ case ADC_JQOVF_EVENT:
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear ADC Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ break;
+
+ /* Overrun event */
+ default: /* Case ADC_OVR_EVENT */
+ /* If overrun is set to overwrite previous data, overrun event is not */
+ /* considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+ }
+ else
+ {
+ /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+ otherwise, data register is potentially overwritten by new converted data as soon
+ as OVR is cleared. */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+ break;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of regular group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : EOC (end of conversion), EOS (end of sequence),
+ * OVR overrun.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+ * ADC Master.
+ * For ADC Slave, ADC is enabled only (conversion is not started).
+ * For ADC Master, ADC is enabled and multimode conversion is started.
+ * @note To guarantee a proper reset of all interruptions once all the needed
+ * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+ * a correct stop of the IT-based conversions.
+ * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+ * interruption. If required (e.g. in case of oversampling with trigger
+ * mode), the user must:
+ * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+ * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+ * before calling HAL_ADC_Start_IT().
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif
+
+ /* Set ADC error code */
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Clear ADC group regular conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Disable all interruptions before enabling the desired ones */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+ break;
+ }
+
+ /* Enable ADC overrun interrupt */
+ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+ ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+ behavior and no CPU time is lost for a non-processed interruption */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+ }
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* - if ADC is slave and dual regular conversions are enabled, ADC is */
+ /* enabled only (conversion is not started), */
+ /* - if ADC is master, ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+ /* Enable as well injected interruptions in case
+ HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+ allows to start regular and injected conversions when JAUTO is
+ set with a single call to HAL_ADC_Start_IT() */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ /* if Master ADC JAUTO bit is set, Slave injected interruptions
+ are enabled nevertheless (for same reason as above) */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ {
+ /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
+ and in resetting HAL_ADC_STATE_INJ_EOC bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+ /* Next, set Slave injected interruptions */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+ }
+#else
+ /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+ {
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+ /* Enable as well injected interruptions in case
+ HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+ allows to start regular and injected conversions when JAUTO is
+ set with a single call to HAL_ADC_Start_IT() */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+ }
+
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+#endif
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable interrution of
+ * end-of-conversion, disable ADC peripheral.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for regular group */
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
+ * @note Interruptions enabled in this function:
+ * overrun (if applicable), DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
+ * is designed for single-ADC mode only. For multimode, the dedicated
+ * HAL_ADCEx_MultiModeStart_DMA() function must be used.
+ * @param hadc ADC handle
+ * @param pData Destination Buffer address.
+ * @param Length Number of data to be transferred from ADC peripheral to memory
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Perform ADC enable and conversion start if no conversion is on going */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Ensure that multimode regular conversions are not enabled. */
+ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
+ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+#endif
+ {
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ /* - Clear state bitfield related to regular group conversion results */
+ /* - Set state bitfield related to regular operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+ HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif
+
+ /* Check if a conversion is on going on ADC group injected */
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+ {
+ /* Reset ADC error code fields related to regular conversions only */
+ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+ }
+ else
+ {
+ /* Reset all ADC error code fields */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
+ /* ADC start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC */
+ /* operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* With DMA, overrun event is always considered as an error even if
+ hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+ ADC_IT_OVR is enabled. */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Enable ADC DMA mode*/
+ LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
+
+ /* Start the DMA channel */
+ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ }
+#if defined(ADC_MULTIMODE_SUPPORT)
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+#endif
+ }
+ else
+ {
+ tmp_hal_status = HAL_BUSY;
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral.
+ * @note: ADC peripheral disable is forcing stop of potential
+ * conversion on ADC group injected. If ADC group injected is under use, it
+ * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+ * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential ADC group regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+ {
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif
+
+/**
+ * @brief Get ADC regular group conversion result.
+ * @note Reading register DR automatically clears ADC flag EOC
+ * (ADC group regular end of unitary conversion).
+ * @note This function does not clear ADC flag EOS
+ * (ADC group regular end of sequence conversion).
+ * Occurrence of flag EOS rising:
+ * - If sequencer is composed of 1 rank, flag EOS is equivalent
+ * to flag EOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag EOC only is raised, at the end of the scan sequence
+ * both flags EOC and EOS are raised.
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADC_PollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+ * @param hadc ADC handle
+ * @retval ADC group regular conversion data
+ */
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Note: EOC flag is not cleared here by software because automatically */
+ /* cleared by hardware when reading register DR. */
+
+ /* Return ADC converted value */
+ return hadc->Instance->DR;
+}
+
+/**
+ * @brief Handle ADC interrupt request.
+ * @param hadc ADC handle
+ * @retval None
+ */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+ uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+ uint32_t tmp_isr = hadc->Instance->ISR;
+ uint32_t tmp_ier = hadc->Instance->IER;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+ /* ========== Check End of Sampling flag for ADC group regular ========== */
+ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+ {
+ /* Update state machine on end of sampling status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+ }
+
+ /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->EndOfSamplingCallback(hadc);
+#else
+ HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+ }
+
+ /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+ (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+ }
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ {
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+ )
+ {
+ /* check CONT bit directly in handle ADC CFGR register */
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ /* else need to check Master ADC CONT bit */
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+ /* Carry on if continuous mode is disabled */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+ {
+ /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
+ /* ADSTART==0 (no conversion on going) */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ /* Note: Overrun interrupt was enabled with EOC interrupt in */
+ /* HAL_Start_IT(), but is not disabled here because can be used */
+ /* by overrun IRQ process below. */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
+ /* to determine if conversion has been triggered from EOC or EOS, */
+ /* possibility to use: */
+ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear regular group conversion flag */
+ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
+ /* conversion flags clear induces the release of the preserved data.*/
+ /* Therefore, if the preserved data value is needed, it must be */
+ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+ }
+
+ /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
+ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+ (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+ {
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+ /* Disable interruption if no further conversion upcoming by injected */
+ /* external trigger or by automatic injected conversion with regular */
+ /* group having no further conversion upcoming (same conditions as */
+ /* regular group interruption disabling above), */
+ /* and if injected scan sequence is completed. */
+ if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
+ ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ {
+ /* If End of Sequence is reached, disable interrupts */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+ {
+ /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
+ /* JADSTART==0 (no conversion on going) */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* Disable ADC end of sequence conversion interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ }
+ }
+ }
+ }
+
+ /* Injected Conversion complete callback */
+ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
+ if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+ if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+ interruption has been triggered by end of conversion or end of
+ sequence. */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedConvCpltCallback(hadc);
+#else
+ HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear injected group conversion flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+ }
+
+ /* ========== Check Analog watchdog 1 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
+ HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+ }
+
+ /* ========== Check analog watchdog 2 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow2Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+ }
+
+ /* ========== Check analog watchdog 3 flag ========== */
+ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindow3Callback(hadc);
+#else
+ HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+ /* Clear ADC analog watchdog flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+ }
+
+ /* ========== Check Overrun flag ========== */
+ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+ {
+ /* If overrun is set to overwrite previous data (default setting), */
+ /* overrun event is not considered as an error. */
+ /* (cf ref manual "Managing conversions without using the DMA and without */
+ /* overrun ") */
+ /* Exception for usage with DMA overrun event always considered as an */
+ /* error. */
+ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+ {
+ overrun_error = 1UL;
+ }
+ else
+ {
+ /* Check DMA configuration */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
+ {
+ /* Multimode (when feature is available) is enabled,
+ Common Control Register MDMA bits must be checked. */
+ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
+ {
+ overrun_error = 1UL;
+ }
+ }
+ else
+#endif
+ {
+ /* Multimode not set or feature not available or ADC independent */
+ if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
+ {
+ overrun_error = 1UL;
+ }
+ }
+ }
+
+ if (overrun_error == 1UL)
+ {
+ /* Change ADC state to error state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+ /* Set ADC error code to overrun */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+ /* Error callback */
+ /* Note: In case of overrun, ADC conversion data is preserved until */
+ /* flag OVR is reset. */
+ /* Therefore, old ADC conversion data can be retrieved in */
+ /* function "HAL_ADC_ErrorCallback()". */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+ /* Clear ADC overrun flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+ }
+
+ /* ========== Check Injected context queue overflow flag ========== */
+ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
+ {
+ /* Change ADC state to overrun state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ /* Set ADC error code to Injected context queue overflow */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+ /* Clear the Injected context queue overflow flag */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+ /* Injected context queue overflow callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->InjectedQueueOverflowCallback(hadc);
+#else
+ HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+
+}
+
+/**
+ * @brief Conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Conversion DMA half-transfer callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 1 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief ADC error callback in non-blocking mode
+ * (ADC conversion with interruption or transfer by DMA).
+ * @note In case of error due to overrun when using ADC with DMA transfer
+ * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+ * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+ * - If needed, restart a new ADC conversion using function
+ * "HAL_ADC_Start_DMA()"
+ * (this function is also clearing overrun flag)
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADC_ErrorCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on regular group
+ (+) Configure the analog watchdog
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group regular.
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor/VddCore.
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Possibility to update parameters on the fly:
+ * This function initializes channel into ADC group regular,
+ * following calls to this function can be used to reconfigure
+ * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+ * without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_ChannelConfTypeDef".
+ * @param hadc ADC handle
+ * @param sConfig Structure of ADC channel assigned to ADC group regular.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpOffsetShifted;
+ uint32_t tmp_config_internal_channel;
+ __IO uint32_t wait_loop_index = 0;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
+ assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
+ /* Check offset range according to oversampling setting */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
+ }
+ else
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
+ }
+
+ /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+ ignored (considered as reset) */
+ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
+
+ /* Verification of channel number */
+ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+ }
+ else
+ {
+ if (hadc->Instance == ADC1)
+ {
+ assert_param(IS_ADC1_DIFF_CHANNEL(sConfig->Channel));
+ }
+ if (hadc->Instance == ADC2)
+ {
+ assert_param(IS_ADC2_DIFF_CHANNEL(sConfig->Channel));
+ }
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel number */
+ /* - Channel rank */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* ADC channels preselection */
+ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
+
+ /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
+
+ if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
+ {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
+
+ assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
+ /* Set ADC selected offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+
+ assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
+ /* Set ADC selected offset right shift */
+ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
+
+ }
+ else
+ {
+ /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
+ If this is the case, offset OFRx is disabled since
+ sConfig->OffsetNumber = ADC_OFFSET_NONE. */
+ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
+ }
+ if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
+ }
+ if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
+ }
+ if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ {
+ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
+ }
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor/VddCore */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Set mode single-ended or differential input of the selected ADC channel */
+ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
+
+ /* Configuration of differential mode */
+ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Set sampling time of the selected ADC channel */
+ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
+ sConfig->SamplingTime);
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore. */
+ /* If internal channel selected, enable dedicated internal buffers and */
+ /* paths. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ {
+ /* Configuration of common ADC parameters */
+
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ while(wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ if (ADC_VREFINT_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ }
+ else if ((sConfig->Channel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL))
+ {
+ if (ADC_VDDCORE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_internal_channel);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ /* If the requested internal measurement path has already been */
+ /* enabled and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* If a conversion is on going on regular group, no update on regular */
+ /* channel could be done on neither of the channel configuration structure */
+ /* parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Configure the analog watchdog.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes the selected analog watchdog, successive
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+ * the ADC.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_AnalogWDGConfTypeDef".
+ * @note On this STM32 serie, analog watchdog thresholds cannot be modified
+ * while ADC conversion is on going.
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpAWDHighThresholdShifted;
+ uint32_t tmpAWDLowThresholdShifted;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+ assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+ assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+ if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
+ (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+ {
+ assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+ }
+
+ /* Verify thresholds range */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ /* Case of oversampling enabled: thresholds are compared to oversampling
+ intermediate computation (after ratio, before shift application) */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
+ }
+ else
+ {
+ /* Verify if thresholds are within the selected ADC resolution */
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on ADC groups regular and injected: */
+ /* - Analog watchdog channels */
+ /* - Analog watchdog thresholds */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Analog watchdog configuration */
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+ {
+ /* Configuration of analog watchdog: */
+ /* - Set the analog watchdog enable mode: one or overall group of */
+ /* channels, on groups regular and-or injected. */
+ switch (AnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
+ LL_ADC_GROUP_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
+ LL_ADC_GROUP_REGULAR_INJECTED));
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ /* Shift the offset in function of the selected ADC resolution: */
+ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
+ /* are set to 0 */
+ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ /* Set the high and low thresholds */
+ MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmpAWDHighThresholdShifted);
+
+ /* Update state, clear previous result related to AWD1 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (AnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD1(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD1(hadc->Instance);
+ }
+ }
+ /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+ else
+ {
+ switch (AnalogWDGConfig->WatchdogMode)
+ {
+ case ADC_ANALOGWATCHDOG_SINGLE_REG:
+ case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+ case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ else
+ {
+ SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ break;
+
+ case ADC_ANALOGWATCHDOG_ALL_REG:
+ case ADC_ANALOGWATCHDOG_ALL_INJEC:
+ case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+ /* Update AWD by bitfield to keep the possibility to monitor */
+ /* several channels by successive calls of this function. */
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ else
+ {
+ SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
+ }
+ break;
+
+ default: /* ADC_ANALOGWATCHDOG_NONE */
+ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+ break;
+ }
+
+ /* Shift the thresholds in function of the selected ADC resolution */
+ /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
+ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+ tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmpAWDHighThresholdShifted);
+ }
+ else
+ {
+ /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+ MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmpAWDLowThresholdShifted);
+ MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmpAWDHighThresholdShifted);
+ }
+
+ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+ {
+ /* Update state, clear previous result related to AWD2 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (AnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD2(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD2(hadc->Instance);
+ }
+ }
+ /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+ else
+ {
+ /* Update state, clear previous result related to AWD3 */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+ /* Clear flag ADC analog watchdog */
+ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
+ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
+ /* (in case left enabled by previous ADC operations). */
+ LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+ /* Configure ADC analog watchdog interrupt */
+ if (AnalogWDGConfig->ITMode == ENABLE)
+ {
+ LL_ADC_EnableIT_AWD3(hadc->Instance);
+ }
+ else
+ {
+ LL_ADC_DisableIT_AWD3(hadc->Instance);
+ }
+ }
+ }
+
+ }
+ /* If a conversion is on going on ADC group regular or injected, no update */
+ /* could be done on neither of the AWD configuration structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+ * @brief ADC Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral state and errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions to get in run-time the status of the
+ peripheral.
+ (+) Check the ADC state
+ (+) Check the ADC error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the ADC handle state.
+ * @note ADC state machine is managed by bitfields, ADC status must be
+ * compared with states bits.
+ * For example:
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+ * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+ * @param hadc ADC handle
+ * @retval ADC handle state (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Return ADC handle state */
+ return hadc->State;
+}
+
+/**
+ * @brief Return the ADC error code.
+ * @param hadc ADC handle
+ * @retval ADC error code (bitfield on 32 bits)
+ */
+uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ return hadc->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+ * @{
+ */
+
+/**
+ * @brief Stop ADC conversion.
+ * @param hadc ADC handle
+ * @param ConversionGroup ADC group regular and/or injected.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
+ * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
+ * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
+{
+ uint32_t tickstart;
+ uint32_t Conversion_Timeout_CPU_cycles = 0UL;
+ uint32_t conversion_group_reassigned = ConversionGroup;
+ uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+ /* Verification if ADC is not already stopped (on regular and injected */
+ /* groups) to bypass this function if not needed. */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ if ((tmp_adc_is_conversion_on_going_regular != 0UL)
+ || (tmp_adc_is_conversion_on_going_injected != 0UL)
+ )
+ {
+ /* Particular case of continuous auto-injection mode combined with */
+ /* auto-delay mode. */
+ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
+ /* injected group stop ADC_CR_JADSTP). */
+ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
+ /* (see reference manual). */
+ if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
+ && (hadc->Init.ContinuousConvMode == ENABLE)
+ && (hadc->Init.LowPowerAutoWait == ENABLE)
+ )
+ {
+ /* Use stop of regular group */
+ conversion_group_reassigned = ADC_REGULAR_GROUP;
+
+ /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
+ {
+ if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ Conversion_Timeout_CPU_cycles ++;
+ }
+
+ /* Clear JEOS */
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+ }
+
+ /* Stop potential conversion on going on ADC group regular */
+ if (conversion_group_reassigned != ADC_INJECTED_GROUP)
+ {
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group regular conversion */
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Stop potential conversion on going on ADC group injected */
+ if (conversion_group_reassigned != ADC_REGULAR_GROUP)
+ {
+ /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+ {
+ /* Stop ADC group injected conversion */
+ LL_ADC_INJ_StopConversion(hadc->Instance);
+ }
+ }
+ }
+
+ /* Selection of start and stop bits with respect to the regular or injected group */
+ switch (conversion_group_reassigned)
+ {
+ case ADC_REGULAR_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+ break;
+ case ADC_INJECTED_GROUP:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+ break;
+ /* Case ADC_REGULAR_GROUP only*/
+ default:
+ tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+ break;
+ }
+
+ /* Wait for conversion effectively stopped */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief Enable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC must be disabled
+ * and voltage regulator must be enabled (done into HAL_ADC_Init()).
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+
+ /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
+ /* enabling phase not yet completed: flag ADC ready not yet set). */
+ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
+ /* causes: ADC clock not running, ...). */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Check if conditions to enable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripheral */
+ LL_ADC_Enable(hadc->Instance);
+
+ /* Wait for ADC effectively enabled */
+ tickstart = HAL_GetTick();
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Poll for ADC ready flag raised except case of multimode enabled
+ and ADC slave selected. */
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+ {
+ /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+ has been cleared (after a calibration), ADEN bit is reset by the
+ calibration logic.
+ The workaround is to continue setting ADEN until ADRDY is becomes 1.
+ Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+ 4 ADC clock cycle duration */
+ /* Note: Test of ADC enabled required due to hardware constraint to */
+ /* not enable ADC if already enabled. */
+ if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_Enable(hadc->Instance);
+ }
+
+ if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+#endif
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+ uint32_t tickstart;
+ const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+ /* Verification if ADC is not already disabled: */
+ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
+ /* disabled. */
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ && (tmp_adc_is_disable_on_going == 0UL)
+ )
+ {
+ /* Check if conditions to disable the ADC are fulfilled */
+ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+ {
+ /* Disable the ADC peripheral */
+ LL_ADC_Disable(hadc->Instance);
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+ }
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+
+ /* Wait for ADC effectively disabled */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Return HAL status */
+ return HAL_OK;
+}
+
+#ifdef HAL_DMA_MODULE_ENABLED
+/**
+ * @brief DMA transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Update state machine on conversion status if not in error state */
+ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+ /* Determine whether any further conversion upcoming on group regular */
+ /* by external trigger, continuous mode or scan sequence on going */
+ /* to disable interruption. */
+ /* Is it the end of the regular sequence ? */
+ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
+ {
+ /* Are conversions software-triggered ? */
+ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+ {
+ /* Is CONT bit set ? */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
+ {
+ /* CONT bit is not set, no more conversions expected */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* DMA End of Transfer interrupt was triggered but conversions sequence
+ is not over. If DMACFG is set to 0, conversions are stopped. */
+ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
+ {
+ /* DMACFG bit is not set, conversions are stopped. */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+
+ /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else /* DMA and-or internal error occurred */
+ {
+ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+ {
+ /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Call ADC DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback(hdma);
+ }
+ }
+}
+
+/**
+ * @brief DMA half transfer complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
+ HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA error callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ /* Retrieve ADC handle corresponding to current DMA handle */
+ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+ /* Set ADC error code to DMA error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+ /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
+ HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+#endif
+
+/**
+ * @brief Configure boost mode of selected ADC.
+ * @note Prerequisite condition to use this function: ADC conversions must be
+ * stopped.
+ * @param hadc ADC handle
+ * @retval None.
+ */
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
+{
+ uint32_t freq;
+ if(ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
+ {
+ freq = HAL_RCC_GetHCLK2Freq();
+ switch(hadc->Init.ClockPrescaler)
+ {
+ case ADC_CLOCK_SYNC_PCLK_DIV1:
+ case ADC_CLOCK_SYNC_PCLK_DIV2:
+ freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
+ break;
+ case ADC_CLOCK_SYNC_PCLK_DIV4:
+ freq /= 4UL;
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
+ switch(hadc->Init.ClockPrescaler)
+ {
+ case ADC_CLOCK_ASYNC_DIV2:
+ case ADC_CLOCK_ASYNC_DIV4:
+ case ADC_CLOCK_ASYNC_DIV6:
+ case ADC_CLOCK_ASYNC_DIV8:
+ case ADC_CLOCK_ASYNC_DIV10:
+ case ADC_CLOCK_ASYNC_DIV12:
+ freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
+ break;
+ case ADC_CLOCK_ASYNC_DIV16:
+ freq /= 16UL;
+ break;
+ case ADC_CLOCK_ASYNC_DIV32:
+ freq /= 32UL;
+ break;
+ case ADC_CLOCK_ASYNC_DIV64:
+ freq /= 64UL;
+ break;
+ case ADC_CLOCK_ASYNC_DIV128:
+ freq /= 128UL;
+ break;
+ case ADC_CLOCK_ASYNC_DIV256:
+ freq /= 256UL;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if(freq > 20000000UL)
+ {
+ SET_BIT(hadc->Instance->CR, ADC_CR_BOOST);
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->CR, 0);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
new file mode 100644
index 0000000..98e6970
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
@@ -0,0 +1,2466 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_adc_ex.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Analog to Digital Convertor (ADC)
+ * peripheral:
+ * + Operation functions
+ * ++ Start, stop, get result of conversions of ADC group injected,
+ * using 2 possible modes: polling, interruption.
+ * ++ Calibration
+ * +++ ADC automatic self-calibration
+ * +++ Calibration factors get or set
+ * ++ Multimode feature when available
+ * + Control functions
+ * ++ Channels configuration on ADC group injected
+ * + State functions
+ * ++ ADC group injected contexts queue management
+ * Other functions (generic functions) are available in file
+ * "stm32mp1xx_hal_adc.c".
+ *
+ @verbatim
+ [..]
+ (@) Sections "ADC peripheral features" and "How to use this driver" are
+ available in file of generic functions "stm32mp1xx_hal_adc.c".
+ [..]
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup ADCEx ADCEx
+ * @brief ADC Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+ * @{
+ */
+
+#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
+ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
+ once the ADC is enabled */
+
+/* Fixed timeout value for ADC calibration. */
+/* Values defined to be higher than worst cases: maximum ratio between ADC */
+/* and CPU clock frequencies. */
+/* Example of profile low frequency : ADC frequency at 15.625kHz (ADC clock */
+/* source PLL4_Q 4MHz, ADC clock prescaler 256), CPU frequency 650MHz. */
+/* Calibration time max = 16384 / fADC (refer to datasheet) */
+/* = 682000000 CPU cycles */
+#define ADC_CALIBRATION_TIMEOUT (682000000U) /*!< ADC calibration time-out value */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+ * @brief Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+
+ (+) Perform the ADC self-calibration for single or differential ending.
+ (+) Get calibration factors for single or differential ending.
+ (+) Set calibration factors for single or differential ending.
+
+ (+) Start conversion of ADC group injected.
+ (+) Stop conversion of ADC group injected.
+ (+) Poll for conversion complete on ADC group injected.
+ (+) Get result of ADC group injected channel conversion.
+ (+) Start conversion of ADC group injected and enable interruptions.
+ (+) Stop conversion of ADC group injected and disable interruptions.
+
+ (+) When multimode feature is available, start multimode and enable DMA transfer.
+ (+) Stop multimode and disable ADC DMA transfer.
+ (+) Get result of multimode conversion.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Perform an ADC automatic self-calibration
+ * Calibration prerequisite: ADC must be disabled (execute this
+ * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+ * @param hadc ADC handle
+* @param CalibrationMode Selection of calibration offset or
+ * linear calibration offset.
+ * @arg ADC_CALIB_OFFSET Channel in mode calibration offset
+ * @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
+ * @param SingleDiff Selection of single-ended or differential input
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ __IO uint32_t wait_loop_index = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Calibration prerequisite: ADC must be disabled. */
+
+ /* Disable the ADC (if not already disabled) */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_BUSY_INTERNAL);
+
+ /* Start ADC calibration in mode single-ended or differential */
+ LL_ADC_StartCalibration(hadc->Instance , CalibrationMode, SingleDiff );
+
+ /* Wait for calibration completion */
+ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+ {
+ wait_loop_index++;
+ if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_BUSY_INTERNAL,
+ HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Note: No need to update variable "tmp_hal_status" here: already set */
+ /* to state "HAL_ERROR" by function disabling the ADC. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Get the calibration factor.
+ * @param hadc ADC handle.
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @retval Calibration value.
+ */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+ /* Return the selected ADC calibration value */
+ return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
+}
+
+/**
+ * @brief Get the calibration factor from automatic conversion result
+ * @param hadc ADC handle
+ * @param LinearCalib_Buffer: Linear calibration factor
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer)
+{
+ uint32_t cnt;
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t temp_REG_IsConversionOngoing = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
+ if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Enable(hadc);
+ }
+
+ if (tmp_hal_status == HAL_OK)
+ {
+ if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ LL_ADC_REG_StopConversion(hadc->Instance);
+ temp_REG_IsConversionOngoing = 1UL;
+ }
+ for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--)
+ {
+ LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt));
+ }
+ if(temp_REG_IsConversionOngoing != 0UL)
+ {
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Set the calibration factor to overwrite automatic conversion result.
+ * ADC must be enabled and no conversion is ongoing.
+ * @param hadc ADC handle
+ * @param SingleDiff This parameter can be only:
+ * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
+ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+ assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Verification of hardware constraints before modifying the calibration */
+ /* factors register: ADC must be enabled, no conversion on going. */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ && (tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* Set the selected ADC calibration value */
+ LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+ }
+ else
+ {
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ /* Update ADC error code */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ /* Update ADC state machine to error */
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Set the linear calibration factor
+ * @param hadc ADC handle
+ * @param LinearCalib_Buffer: Linear calibration factor
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer)
+{
+ uint32_t cnt;
+ __IO uint32_t wait_loop_index = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* - Exit from deep-power-down mode and ADC voltage regulator enable */
+ /* Exit deep power down mode if still in that state */
+ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
+ {
+ /* Exit deep power down mode */
+ CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+ /* System was in deep power down mode, calibration must
+ be relaunched or a previously saved calibration factor
+ re-applied once the ADC voltage regulator is enabled */
+ }
+
+
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+ {
+ /* Enable ADC internal voltage regulator */
+ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
+ /* Delay for ADC stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles. */
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
+ while(wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+
+
+ /* Verification that ADC voltage regulator is correctly enabled, whether */
+ /* or not ADC is coming from state reset (if any potential problem of */
+ /* clocking, voltage regulator would not be enabled). */
+ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ for(cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++)
+ {
+ LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt, LinearCalib_Buffer[cnt]);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of injected group.
+ * @note Interruptions enabled in this function: None.
+ * @note Case of multimode enabled when multimode feature is available:
+ * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ return HAL_BUSY;
+ }
+ else
+ {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+ && (tmp_config_injected_queue == 0UL)
+ )
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+ {
+ /* Reset ADC error code field related to injected conversions only */
+ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ }
+ else
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable conversion of injected group, if automatic injected conversion */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ /* Start ADC group injected conversion */
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif
+
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop conversion of injected channels. Disable ADC peripheral if
+ * no regular conversion is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note In case of multimode enabled (when multimode feature is available),
+ * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @param hadc ADC handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on regular group is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Wait for injected group conversion to be completed.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
+ * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+ * checked and cleared depending on AUTDLY bit status.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ uint32_t tmp_Flag_End;
+ uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+ uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+ uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ const ADC_TypeDef *tmpADC_Master;
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* If end of sequence selected */
+ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+ {
+ tmp_Flag_End = ADC_FLAG_JEOS;
+ }
+ else /* end of conversion selected */
+ {
+ tmp_Flag_End = ADC_FLAG_JEOC;
+ }
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait until End of Conversion or Sequence flag is raised */
+ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+ {
+ /* Check if timeout is disabled (set to infinite wait) */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+ {
+ /* Update ADC state machine to timeout */
+ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Retrieve ADC configuration */
+ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+ tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+ /* Get relevant register CFGR in ADC instance of ADC master or slave */
+ /* in function of multimode state (for devices with multimode */
+ /* available). */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+ }
+ else
+ {
+ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+ tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+ }
+#else
+ tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif
+
+ /* Update ADC state machine */
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+ /* Determine whether any further conversion upcoming on group injected */
+ /* by external trigger or by automatic injected conversion */
+ /* from group regular. */
+ if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
+ ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
+ ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+ (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+ {
+ /* Check whether end of sequence is reached */
+ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+ {
+ /* Particular case if injected contexts queue is enabled: */
+ /* when the last context has been fully processed, JSQR is reset */
+ /* by the hardware. Even if no injected conversion is planned to come */
+ /* (queue empty, triggers are ignored), it can start again */
+ /* immediately after setting a new context (JADSTART is still set). */
+ /* Therefore, state of HAL ADC injected group is kept to busy. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+ }
+ }
+ }
+ }
+
+ /* Clear polled flag */
+ if (tmp_Flag_End == ADC_FLAG_JEOS)
+ {
+ /* Clear end of sequence JEOS flag of injected group if low power feature */
+ /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
+ /* For injected groups, no new conversion will start before JEOS is */
+ /* cleared. */
+ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+ }
+ }
+ else
+ {
+ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+ }
+
+ /* Return API HAL status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable ADC, start conversion of injected group with interruption.
+ * @note Interruptions enabled in this function according to initialization
+ * setting : JEOC (end of conversion) or JEOS (end of sequence)
+ * @note Case of multimode enabled (when multimode feature is enabled):
+ * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+ * then for ADC master.
+ * For ADC slave, ADC is enabled only (conversion is not started).
+ * For ADC master, ADC is enabled and multimode conversion is started.
+ * @param hadc ADC handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ return HAL_BUSY;
+ }
+ else
+ {
+ /* In case of software trigger detection enabled, JQDIS must be set
+ (which can be done only if ADSTART and JADSTART are both cleared).
+ If JQDIS is not set at that point, returns an error
+ - since software trigger detection is disabled. User needs to
+ resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+ - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+ the queue is empty */
+ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+ && (tmp_config_injected_queue == 0UL)
+ )
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Enable the ADC peripheral */
+ tmp_hal_status = ADC_Enable(hadc);
+
+ /* Start conversion if ADC is effectively enabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Check if a regular conversion is ongoing */
+ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+ {
+ /* Reset ADC error code field related to injected conversions only */
+ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+ }
+ else
+ {
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+ }
+
+ /* Set ADC state */
+ /* - Clear state bitfield related to injected group conversion results */
+ /* - Set state bitfield related to injected operation */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+ HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+ - if ADC instance is master or if multimode feature is not available
+ - if multimode setting is disabled (ADC instance slave in independent mode) */
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ )
+ {
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#endif
+
+ /* Clear ADC group injected group conversion flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC Injected context queue overflow interrupt if this feature */
+ /* is enabled. */
+ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
+ {
+ __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+ }
+
+ /* Enable ADC end of conversion interrupt */
+ switch (hadc->Init.EOCSelection)
+ {
+ case ADC_EOC_SEQ_CONV:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+ break;
+ /* case ADC_EOC_SINGLE_CONV */
+ default:
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+ break;
+ }
+
+ /* Enable conversion of injected group, if automatic injected conversion */
+ /* is disabled. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Case of multimode enabled (when multimode feature is available): */
+ /* if ADC is slave, */
+ /* - ADC is enabled only (conversion is not started), */
+ /* - if multimode only concerns regular conversion, ADC is enabled */
+ /* and conversion is started. */
+ /* If ADC is master or independent, */
+ /* - ADC is enabled and conversion is started. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+ || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+ || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+ )
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+ }
+ else
+ {
+ /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+ }
+#else
+ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+ {
+ /* Start ADC group injected conversion */
+ LL_ADC_INJ_StartConversion(hadc->Instance);
+ }
+#endif
+
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop conversion of injected channels, disable interruption of
+ * end-of-conversion. Disable ADC peripheral if no regular conversion
+ * is on going.
+ * @note If ADC must be disabled and if conversion is on going on
+ * regular group, function HAL_ADC_Stop must be used to stop both
+ * injected and regular groups, and disable the ADC.
+ * @note If injected group mode auto-injection is enabled,
+ * function HAL_ADC_Stop must be used.
+ * @note Case of multimode enabled (when multimode feature is available):
+ * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+ * then for ADC slave.
+ * For ADC master, conversion is stopped and ADC is disabled.
+ * For ADC slave, ADC is disabled only (conversion stop of ADC master
+ * has already stopped conversion of ADC slave).
+ * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential conversion on going on injected group only. */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if injected conversions are effectively stopped */
+ /* and if no conversion on the other group (regular group) is intended to */
+ /* continue. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Disable ADC end of conversion interrupt for injected channels */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ /* Set ADC state */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+ * @note Multimode must have been previously configured using
+ * HAL_ADCEx_MultiModeConfigChannel() function.
+ * Interruptions enabled in this function:
+ * overrun, DMA half transfer, DMA transfer complete.
+ * Each of these interruptions has its dedicated callback function.
+ * @note State field of Slave ADC handle is not updated in this configuration:
+ * user should not rely on it for information related to Slave regular
+ * conversions.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData Destination Buffer address.
+ * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ ADC_HandleTypeDef tmphadcSlave;
+ ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+ assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+
+ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+ {
+ return HAL_BUSY;
+ }
+ else
+ {
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Set ADC state */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Enable the ADC peripherals: master and slave (in case if not already */
+ /* enabled previously) */
+ tmp_hal_status = ADC_Enable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Enable(&tmphadcSlave);
+ }
+
+ /* Start multimode conversion of ADCs pair */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
+ HAL_ADC_STATE_REG_BUSY);
+
+ /* Set ADC error code to none */
+ ADC_CLEAR_ERRORCODE(hadc);
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Set the DMA transfer complete callback */
+ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+ /* Set the DMA half transfer complete callback */
+ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+ /* Set the DMA error callback */
+ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+#endif
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
+ /* start (in case of SW start): */
+
+ /* Clear regular group conversion flag and overrun flag */
+ /* (To ensure of no unknown state from potential previous ADC operations) */
+ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+ /* Process unlocked */
+ /* Unlock before starting ADC conversions: in case of potential */
+ /* interruption, to let the process to ADC IRQ Handler. */
+ __HAL_UNLOCK(hadc);
+
+ /* Enable ADC overrun interrupt */
+ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+ /* Start the DMA channel */
+ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+
+ /* Enable conversion of regular group. */
+ /* If software start has been selected, conversion starts immediately. */
+ /* If external trigger has been selected, conversion will start at next */
+ /* trigger event. */
+ /* Start ADC group regular conversion */
+ LL_ADC_REG_StartConversion(hadc->Instance);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+ }
+
+ /* Return function status */
+ return tmp_hal_status;
+ }
+}
+
+/**
+ * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+ * @note Multimode is kept enabled after this function. MultiMode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+ * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+ * resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADC_Stop_DMA() must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+ uint32_t tmphadcSlave_conversion_on_going;
+ HAL_StatusTypeDef tmphadcSlave_disable_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADC_Stop_DMA() API. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status == HAL_ERROR)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
+ if ((ADC_Disable(hadc) == HAL_OK) &&
+ (tmphadcSlave_disable_status == HAL_OK))
+ {
+ tmp_hal_status = HAL_OK;
+ }
+ }
+ else
+ {
+ /* In case of error, attempt to disable ADC master and slave without status assert */
+ (void) ADC_Disable(hadc);
+ (void) ADC_Disable(&tmphadcSlave);
+ }
+
+ /* Set ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif
+
+/**
+ * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
+ * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+ * @retval The converted data values.
+ */
+uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
+{
+ const ADC_Common_TypeDef *tmpADC_Common;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Prevent unused argument(s) compilation warning if no assert_param check */
+ /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
+ UNUSED(hadc);
+
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* Return the multi mode conversion value */
+ return tmpADC_Common->CDR;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Get ADC injected group conversion result.
+ * @note Reading register JDRx automatically clears ADC flag JEOC
+ * (ADC group injected end of unitary conversion).
+ * @note This function does not clear ADC flag JEOS
+ * (ADC group injected end of sequence conversion)
+ * Occurrence of flag JEOS rising:
+ * - If sequencer is composed of 1 rank, flag JEOS is equivalent
+ * to flag JEOC.
+ * - If sequencer is composed of several ranks, during the scan
+ * sequence flag JEOC only is raised, at the end of the scan sequence
+ * both flags JEOC and EOS are raised.
+ * Flag JEOS must not be cleared by this function because
+ * it would not be compliant with low power features
+ * (feature low power auto-wait, not available on all STM32 families).
+ * To clear this flag, either use function:
+ * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+ * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+ * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
+ * This parameter can be one of the following values:
+ * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+ * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+ * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+ * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+ * @retval ADC group injected conversion data
+ */
+uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+ uint32_t tmp_jdr;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+ /* Get ADC converted value */
+ switch (InjectedRank)
+ {
+ case ADC_INJECTED_RANK_4:
+ tmp_jdr = hadc->Instance->JDR4;
+ break;
+ case ADC_INJECTED_RANK_3:
+ tmp_jdr = hadc->Instance->JDR3;
+ break;
+ case ADC_INJECTED_RANK_2:
+ tmp_jdr = hadc->Instance->JDR2;
+ break;
+ case ADC_INJECTED_RANK_1:
+ default:
+ tmp_jdr = hadc->Instance->JDR1;
+ break;
+ }
+
+ /* Return ADC converted value */
+ return tmp_jdr;
+}
+
+/**
+ * @brief Injected conversion complete callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Injected context queue overflow callback.
+ * @note This callback is called if injected context queue is enabled
+ (parameter "QueueInjectedContext" in injected channel configuration)
+ and if a new injected context is set when queue is full (maximum 2
+ contexts).
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 2 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Analog watchdog 3 callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+ */
+}
+
+
+/**
+ * @brief End Of Sampling callback in non-blocking mode.
+ * @param hadc ADC handle
+ * @retval None
+ */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hadc);
+
+ /* NOTE : This function should not be modified. When the callback is needed,
+ function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Stop ADC conversion of regular group (and injected channels in
+ * case of auto_injection mode), disable ADC peripheral if no
+ * conversion is on going on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if regular conversions are effectively stopped
+ and if no injected conversions are on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* 2. Disable the ADC peripheral */
+ tmp_hal_status = ADC_Disable(hadc);
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ /* Conversion on injected group is stopped, but ADC not disabled since */
+ /* conversion on regular group is still running. */
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+
+/**
+ * @brief Stop ADC conversion of ADC groups regular and injected,
+ * disable interrution of end-of-conversion,
+ * disable ADC peripheral if no conversion is on going
+ * on injected group.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable all regular-related interrupts */
+ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+ /* 2. Disable ADC peripheral if no injected conversions are on-going */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ /* if no issue reported */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Stop ADC conversion of regular group (and injected group in
+ * case of auto_injection mode), disable ADC DMA transfer, disable
+ * ADC peripheral if no conversion is on going
+ * on injected group.
+ * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
+ * For multimode (when multimode feature is available),
+ * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+ * @param hadc ADC handle
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* 1. Stop potential regular conversion on going */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped
+ and if no injected conversion is on-going */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+ /* while DMA transfer is on going) */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripheral */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, */
+ /* to keep in memory a potential failing status. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ if (tmp_hal_status == HAL_OK)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ }
+ else
+ {
+ (void)ADC_Disable(hadc);
+ }
+
+ /* Check if ADC is effectively disabled */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Set ADC state */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
+ }
+ }
+ else
+ {
+ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
+ * @note Multimode is kept enabled after this function. Multimode DMA bits
+ * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+ * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+ * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+ * resort to HAL_ADCEx_DisableMultiMode() API.
+ * @note In case of DMA configured in circular mode, function
+ * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+ * ADC slave, to properly disable the DMA channel.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tickstart;
+ ADC_HandleTypeDef tmphadcSlave;
+ uint32_t tmphadcSlave_conversion_on_going;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+
+ /* 1. Stop potential multimode conversion on going, on regular groups */
+ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+ /* Disable ADC peripheral if conversions are effectively stopped */
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Clear HAL_ADC_STATE_REG_BUSY bit */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+ /* Set a temporary handle of the ADC slave associated to the ADC master */
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Procedure to disable the ADC peripheral: wait for conversions */
+ /* effectively stopped (ADC master and ADC slave), then disable ADC */
+
+ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+ tickstart = HAL_GetTick();
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+ || (tmphadcSlave_conversion_on_going == 1UL)
+ )
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ }
+
+ /* Disable the DMA channel (in case of DMA in circular mode or stop */
+ /* while DMA transfer is on going) */
+ /* Note: DMA channel of ADC slave should be stopped after this function */
+ /* with HAL_ADCEx_RegularStop_DMA() API. */
+ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+ /* Check if DMA channel effectively disabled */
+ if (tmp_hal_status != HAL_OK)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+ }
+
+ /* Disable ADC overrun interrupt */
+ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+ /* 2. Disable the ADC peripherals: master and slave if no injected */
+ /* conversion is on-going. */
+ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+ /* memory a potential failing status. */
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(hadc);
+ if (tmp_hal_status == HAL_OK)
+ {
+ if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
+ {
+ tmp_hal_status = ADC_Disable(&tmphadcSlave);
+ }
+ }
+ }
+
+ if (tmp_hal_status == HAL_OK)
+ {
+ /* Both Master and Slave ADC's could be disabled. Update Master State */
+ /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+ }
+ else
+ {
+ /* injected (Master or Slave) conversions are still on-going,
+ no Master State change */
+ }
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+ * @brief ADC Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure channels on injected group
+ (+) Configure multimode when multimode feature is available
+ (+) Enable or Disable Injected Queue
+ (+) Disable ADC voltage regulator
+ (+) Enter ADC deep-power-down mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure a channel to be assigned to ADC group injected.
+ * @note Possibility to update parameters on the fly:
+ * This function initializes injected group, following calls to this
+ * function can be used to reconfigure some parameters of structure
+ * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+ * The setting of these parameters is conditioned to ADC state:
+ * Refer to comments of structure "ADC_InjectionConfTypeDef".
+ * @note In case of usage of internal measurement channels:
+ * Vbat/VrefInt/TempSensor/VddCore.
+ * These internal paths can be disabled using function
+ * HAL_ADC_DeInit().
+ * @note Caution: For Injected Context Queue use, a context must be fully
+ * defined before start of injected conversion. All channels are configured
+ * consecutively for the same ADC instance. Therefore, the number of calls to
+ * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
+ * InjectedNbrOfConversion for each context.
+ * - Example 1: If 1 context is intended to be used (or if there is no use of the
+ * Injected Queue Context feature) and if the context contains 3 injected ranks
+ * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
+ * called once for each channel (i.e. 3 times) before starting a conversion.
+ * This function must not be called to configure a 4th injected channel:
+ * it would start a new context into context queue.
+ * - Example 2: If 2 contexts are intended to be used and each of them contains
+ * 3 injected ranks (InjectedNbrOfConversion = 3),
+ * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+ * for each context (3 channels x 2 contexts = 6 calls). Conversion can
+ * start once the 1st context is set, that is after the first three
+ * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
+ * @param hadc ADC handle
+ * @param sConfigInjected Structure of ADC injected group and ADC channel for
+ * injected group.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ uint32_t tmpOffsetShifted;
+ uint32_t tmp_config_internal_channel;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+ __IO uint32_t wait_loop_index = 0;
+
+ uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
+ assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
+ assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
+ assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
+ assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
+
+ if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ {
+ assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
+ assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
+ assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
+ }
+
+ /* Check offset range according to oversampling setting */
+ if (hadc->Init.OversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset/(hadc->Init.Oversampling.Ratio+1U)));
+ }
+ else
+ {
+ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
+ }
+
+ /* JDISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
+
+ /* DISCEN and JAUTO bits can't be set at the same time */
+ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
+
+ /* Verification of channel number */
+ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+ {
+ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+ else
+ {
+ if (hadc->Instance == ADC1)
+ {
+ assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+ if (hadc->Instance == ADC2)
+ {
+ assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
+ }
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ /* Configuration of injected group sequencer: */
+ /* Hardware constraint: Must fully define injected context register JSQR */
+ /* before make it entering into injected sequencer queue. */
+ /* */
+ /* - if scan mode is disabled: */
+ /* * Injected channels sequence length is set to 0x00: 1 channel */
+ /* converted (channel on injected rank 1) */
+ /* Parameter "InjectedNbrOfConversion" is discarded. */
+ /* * Injected context register JSQR setting is simple: register is fully */
+ /* defined on one call of this function (for injected rank 1) and can */
+ /* be entered into queue directly. */
+ /* - if scan mode is enabled: */
+ /* * Injected channels sequence length is set to parameter */
+ /* "InjectedNbrOfConversion". */
+ /* * Injected context register JSQR setting more complex: register is */
+ /* fully defined over successive calls of this function, for each */
+ /* injected channel rank. It is entered into queue only when all */
+ /* injected ranks have been set. */
+ /* Note: Scan mode is not present by hardware on this device, but used */
+ /* by software for alignment over all STM32 devices. */
+
+ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
+ (sConfigInjected->InjectedNbrOfConversion == 1U))
+ {
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer: fixed to 1st rank */
+ /* (scan mode disabled, only rank 1 used) */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+
+ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+ {
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
+ | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+ | sConfigInjected->ExternalTrigInjecConvEdge
+ );
+ }
+ else
+ {
+ tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
+ }
+
+ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
+ /* For debug and informative reasons, hadc handle saves JSQR setting */
+ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
+
+ }
+ }
+ else
+ {
+ /* Case of scan mode enabled, several channels to set into injected group */
+ /* sequencer. */
+ /* */
+ /* Procedure to define injected context register JSQR over successive */
+ /* calls of this function, for each injected channel rank: */
+ /* 1. Start new context and set parameters related to all injected */
+ /* channels: injected sequence length and trigger. */
+
+ /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
+ /* call of the context under setting */
+ if (hadc->InjectionConfig.ChannelCount == 0U)
+ {
+ /* Initialize number of channels that will be configured on the context */
+ /* being built */
+ hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
+ /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
+ call, this context will be written in JSQR register at the last call.
+ At this point, the context is merely reset */
+ hadc->InjectionConfig.ContextQueue = 0x00000000U;
+
+ /* Configuration of context register JSQR: */
+ /* - number of ranks in injected group sequencer */
+ /* - external trigger to start conversion */
+ /* - external trigger polarity */
+
+ /* Enable external trigger if trigger selection is different of */
+ /* software start. */
+ /* Note: This configuration keeps the hardware feature of parameter */
+ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
+ /* software start. */
+ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+ {
+ tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
+ | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+ | sConfigInjected->ExternalTrigInjecConvEdge
+ );
+ }
+ else
+ {
+ tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
+ }
+
+ }
+
+ /* 2. Continue setting of context under definition with parameter */
+ /* related to each channel: channel rank sequence */
+ /* Clear the old JSQx bits for the selected rank */
+ tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
+
+ /* Set the JSQx bits for the selected rank */
+ tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
+
+ /* Decrease channel count */
+ hadc->InjectionConfig.ChannelCount--;
+
+ /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
+ call, aggregate the setting to those already built during the previous
+ HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
+ hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
+
+ /* 4. End of context setting: if this is the last channel set, then write context
+ into register JSQR and make it enter into queue */
+ if (hadc->InjectionConfig.ChannelCount == 0U)
+ {
+ MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
+ }
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on injected group: */
+ /* - Injected context queue: Queue disable (active context is kept) or */
+ /* enable (context decremented, up to 2 contexts queued) */
+ /* - Injected discontinuous mode: can be enabled only if auto-injected */
+ /* mode is disabled. */
+ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+ {
+ /* ADC channels preselection */
+ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
+
+ /* If auto-injected mode is disabled: no constraint */
+ if (sConfigInjected->AutoInjectedConv == DISABLE)
+ {
+ MODIFY_REG(hadc->Instance->CFGR,
+ ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
+ ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
+ }
+ /* If auto-injected mode is enabled: Injected discontinuous setting is */
+ /* discarded. */
+ else
+ {
+ MODIFY_REG(hadc->Instance->CFGR,
+ ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+ ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
+ }
+
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular and injected groups: */
+ /* - Automatic injected conversion: can be enabled if injected group */
+ /* external triggers are disabled. */
+ /* - Channel sampling time */
+ /* - Channel offset */
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ /* If injected group external triggers are disabled (set to injected */
+ /* software start): no constraint */
+ if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+ || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+ {
+ if (sConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+ }
+ }
+ /* If Automatic injected conversion was intended to be set and could not */
+ /* due to injected group external triggers enabled, error is reported. */
+ else
+ {
+ if (sConfigInjected->AutoInjectedConv == ENABLE)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ else
+ {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+ }
+ }
+
+ if (sConfigInjected->InjecOversamplingMode == ENABLE)
+ {
+ assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+ assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
+
+ /* JOVSE must be reset in case of triggered regular mode */
+ assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
+
+ /* Configuration of Injected Oversampler: */
+ /* - Oversampling Ratio */
+ /* - Right bit shift */
+
+ /* Enable OverSampling mode */
+ MODIFY_REG(hadc->Instance->CFGR2,
+ ADC_CFGR2_JOVSE |
+ ADC_CFGR2_OVSR |
+ ADC_CFGR2_OVSS,
+ ADC_CFGR2_JOVSE |
+ ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) |
+ sConfigInjected->InjecOversampling.RightBitShift
+ );
+ }
+ else
+ {
+ /* Disable Regular OverSampling */
+ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+ }
+
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
+
+ /* Configure the offset: offset enable/disable, channel, offset value */
+
+ /* Shift the offset with respect to the selected ADC resolution. */
+ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
+
+ if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+ {
+ /* Set ADC selected offset number */
+ LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
+ tmpOffsetShifted);
+
+ /* Set ADC selected offset signed saturation */
+ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+
+ /* Set ADC selected offset right shift */
+ LL_ADC_SetDataRightShift(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetRightShift == (uint32_t)ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
+
+ }
+ else
+ {
+ /* Scan each offset register to check if the selected channel is targeted. */
+ /* If this is the case, the corresponding offset number is disabled. */
+ if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ {
+ LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ }
+ }
+
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Single or differential mode */
+ /* - Internal measurement channels: Vbat/VrefInt/TempSensor/VddCore */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ /* Set mode single-ended or differential input of the selected ADC channel */
+ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
+
+ /* Configuration of differential mode */
+ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
+ {
+ /* Set sampling time of the selected ADC channel */
+ LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
+ }
+
+ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore */
+ /* internal measurement paths enable: If internal channel selected, */
+ /* enable dedicated internal buffers and path. */
+ /* Note: these internal measurement paths can be disabled using */
+ /* HAL_ADC_DeInit(). */
+
+ if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
+ {
+ /* Configuration of common ADC parameters (continuation) */
+ /* Software is allowed to change common parameters only when all ADCs */
+ /* of the common group are disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ /* If the requested internal measurement path has already been enabled, */
+ /* bypass the configuration processing. */
+ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ {
+ if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+ /* Delay for temperature sensor stabilization time */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially */
+ /* CPU processing cycles, scaling in us split to not */
+ /* exceed 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ while(wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
+ }
+ }
+ else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ {
+ if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ }
+ }
+ else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ {
+ if (ADC_VREFINT_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ }
+ }
+ else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL))
+ {
+ if (ADC_VDDCORE_INSTANCE(hadc))
+ {
+ LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_internal_channel);
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ }
+ /* If the requested internal measurement path has already been enabled */
+ /* and other ADC of the common group are enabled, internal */
+ /* measurement paths cannot be enabled. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+ }
+
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Enable ADC multimode and configure multimode parameters
+ * @note Possibility to update parameters on the fly:
+ * This function initializes multimode parameters, following
+ * calls to this function can be used to reconfigure some parameters
+ * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+ * the ADCs.
+ * The setting of these parameters is conditioned to ADC state.
+ * For parameters constraints, see comments of structure
+ * "ADC_MultiModeTypeDef".
+ * @note To move back configuration from multimode to single mode, ADC must
+ * be reset (using function HAL_ADC_Init() ).
+ * @param hadc Master ADC handle
+ * @param multimode Structure of ADC multimode configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
+{
+ HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ ADC_Common_TypeDef *tmpADC_Common;
+ ADC_HandleTypeDef tmphadcSlave;
+ uint32_t tmphadcSlave_conversion_on_going;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+ assert_param(IS_ADC_MULTIMODE(multimode->Mode));
+ if (multimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
+ assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
+
+ ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+ if (tmphadcSlave.Instance == NULL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ return HAL_ERROR;
+ }
+
+ /* Parameters update conditioned to ADC state: */
+ /* Parameters that can be updated when ADC is disabled or enabled without */
+ /* conversion on going on regular group: */
+ /* - Multimode DATA Format configuration */
+ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
+ if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ && (tmphadcSlave_conversion_on_going == 0UL))
+ {
+ /* Pointer to the common control register */
+ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+ /* If multimode is selected, configure all multimode parameters. */
+ /* Otherwise, reset multimode parameters (can be used in case of */
+ /* transition from multimode to independent mode). */
+ if (multimode->Mode != ADC_MODE_INDEPENDENT)
+ {
+ MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ /* Note: Delay range depends on selected resolution: */
+ /* from 1 to 9 clock cycles for 16 bits */
+ /* from 1 to 9 clock cycles for 14 bits, */
+ /* from 1 to 8 clock cycles for 12 bits */
+ /* from 1 to 6 clock cycles for 10 and 8 bits */
+ /* If a higher delay is selected, it will be clipped to maximum delay */
+ /* range */
+
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ MODIFY_REG(tmpADC_Common->CCR,
+ ADC_CCR_DUAL |
+ ADC_CCR_DELAY,
+ multimode->Mode |
+ multimode->TwoSamplingDelay
+ );
+ }
+ }
+ else /* ADC_MODE_INDEPENDENT */
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
+
+ /* Parameters that can be updated only when ADC is disabled: */
+ /* - Multimode mode selection */
+ /* - Multimode delay */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ {
+ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+ }
+ }
+ }
+ /* If one of the ADC sharing the same common group is enabled, no update */
+ /* could be done on neither of the multimode structure parameters. */
+ else
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hadc);
+
+ /* Return function status */
+ return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @brief Enable Injected Queue
+ * @note This function resets CFGR register JQDIS bit in order to enable the
+ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+ * are both equal to 0 to ensure that no regular nor injected
+ * conversion is ongoing.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ /* Parameter can be set only if no conversion is on-going */
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+ /* Update state, clear previous result related to injected queue overflow */
+ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Disable Injected Queue
+ * @note This function sets CFGR register JQDIS bit in order to disable the
+ * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+ * are both equal to 0 to ensure that no regular nor injected
+ * conversion is ongoing.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+ uint32_t tmp_adc_is_conversion_on_going_regular;
+ uint32_t tmp_adc_is_conversion_on_going_injected;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+ /* Parameter can be set only if no conversion is on-going */
+ if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ )
+ {
+ LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Disable ADC voltage regulator.
+ * @note Disabling voltage regulator allows to save power. This operation can
+ * be carried out only when ADC is disabled.
+ * @note To enable again the voltage regulator, the user is expected to
+ * resort to HAL_ADC_Init() API.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_DisableInternalRegulator(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @brief Enter ADC deep-power-down mode
+ * @note This mode is achieved in setting DEEPPWD bit and allows to save power
+ * in reducing leakage currents. It is particularly interesting before
+ * entering stop modes.
+ * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+ * ADC voltage regulator. This means that this API encompasses
+ * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+ * calibration is lost.
+ * @note To exit the ADC deep-power-down mode, the user is expected to
+ * resort to HAL_ADC_Init() API as well as to relaunch a calibration
+ * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+ * saved calibration factor.
+ * @param hadc ADC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
+{
+ HAL_StatusTypeDef tmp_hal_status;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+ /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ {
+ LL_ADC_EnableDeepPowerDown(hadc->Instance);
+ tmp_hal_status = HAL_OK;
+ }
+ else
+ {
+ tmp_hal_status = HAL_ERROR;
+ }
+
+ return tmp_hal_status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c
new file mode 100644
index 0000000..1a6e6e6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cortex.c
@@ -0,0 +1,439 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_cortex.c
+ * @author MCD Application Team
+ * @brief CORTEX HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the CORTEX:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+
+ [..]
+ *** How to configure Interrupts using CORTEX HAL driver ***
+ ===========================================================
+ [..]
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
+ The Cortex-M exceptions are managed by CMSIS functions.
+
+ (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+ function according to the following table.
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+ (#) please refer to programming manual for details in how to configure priority.
+
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
+ The pending IRQ priority will be managed only by the sub priority.
+
+ -@- IRQ priority order (sorted by highest to lowest priority):
+ (+@) Lowest preemption priority
+ (+@) Lowest sub priority
+ (+@) Lowest hardware priority (IRQ number)
+
+ [..]
+ *** How to configure Systick using CORTEX HAL driver ***
+ ========================================================
+ [..]
+ Setup SysTick Timer for time base.
+
+ (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+ is a CMSIS function that:
+ (++) Configures the SysTick Reload register with value passed as function parameter.
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Resets the SysTick Counter register.
+ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+ (++) Enables the SysTick Interrupt.
+ (++) Starts the SysTick Counter.
+
+ (+) You can change the SysTick IRQ priority by calling the
+ HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+ call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+ (+) To adjust the SysTick time base, use the following formula:
+
+ Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
+ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+ (++) Reload Value should not exceed 0xFFFFFF
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX CORTEX
+ * @brief CORTEX HAL module driver
+ * @{
+ */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+ Systick functionalities
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Sets the priority grouping field (preemption priority and subpriority)
+ * using the required unlock sequence.
+ * @param PriorityGroup: The priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ * 0 bits for subpriority
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+ * The pending IRQ priority will be managed only by the subpriority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+ NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+ * @brief Sets the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @param PreemptPriority: The preemption priority for the IRQn channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority
+ * @param SubPriority: the subpriority level for the IRQ channel.
+ * This parameter can be a value between 0 and 15
+ * A lower priority value indicates a higher priority.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t prioritygroup = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+ prioritygroup = NVIC_GetPriorityGrouping();
+
+ NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+ * @brief Enables a device specific interrupt in the NVIC interrupt controller.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Enable interrupt */
+ NVIC_EnableIRQ(IRQn);
+}
+
+/**
+ * @brief Disables a device specific interrupt in the NVIC interrupt controller.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Disable interrupt */
+ NVIC_DisableIRQ(IRQn);
+}
+
+/**
+ * @brief Initiates a system reset request to reset the MCU.
+ * @retval None
+ */
+void HAL_NVIC_SystemReset(void)
+{
+ /* System Reset */
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ * Counter is in free running mode to generate periodic interrupts.
+ * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ return SysTick_Config(TicksNumb);
+}
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Cortex control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the CORTEX
+ (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+ * @{
+ */
+#if (__MPU_PRESENT == 1)
+/**
+ * @brief Initializes and configures the Region and the memory to be protected.
+ * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
+ * @retval None
+ */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+ assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+ /* Set the Region number */
+ MPU->RNR = MPU_Init->Number;
+
+ if ((MPU_Init->Enable) != RESET)
+ {
+ /* Check the parameters */
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
+ }
+ else
+ {
+ MPU->RBAR = 0x00;
+ MPU->RASR = 0x00;
+ }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+ * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
+ * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+ */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+ /* Get the PRIGROUP[10:8] field value */
+ return NVIC_GetPriorityGrouping();
+}
+
+/**
+ * @brief Gets the priority of an interrupt.
+ * @param IRQn: External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @param PriorityGroup: the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+ * 0 bits for subpriority
+ * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @retval None
+ */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+ * @brief Sets Pending bit of an external interrupt.
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Set interrupt pending */
+ NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * and returns the pending bit for the specified interrupt).
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if pending else 0 */
+ return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @retval None
+ */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Clear pending interrupt */
+ NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+ * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+ * @param IRQn External interrupt number
+ * This parameter can be an enumerator of IRQn_Type enumeration
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
+ * @retval status: - 0 Interrupt status is not pending.
+ * - 1 Interrupt status is pending.
+ */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+ /* Return 1 if active else 0 */
+ return NVIC_GetActive(IRQn);
+}
+
+
+/**
+ * @brief This function handles SYSTICK interrupt request.
+ * @retval None
+ */
+void HAL_SYSTICK_IRQHandler(void)
+{
+ HAL_SYSTICK_Callback();
+}
+
+/**
+ * @brief SYSTICK callback.
+ * @retval None
+ */
+__weak void HAL_SYSTICK_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SYSTICK_Callback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c
new file mode 100644
index 0000000..a2e94d5
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma.c
@@ -0,0 +1,1591 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_dma.c
+ * @author MCD Application Team
+ * @brief DMA HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and errors functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the DMA Stream
+ (except for internal SRAM/FLASH memories: no initialization is
+ necessary) please refer to Reference manual for connection between peripherals
+ and DMA requests .
+
+ (#) For a given Stream, program the required configuration through the following parameters:
+ Transfer Direction, Source and Destination data formats,
+ Circular, Normal or peripheral flow control mode, Stream Priority level,
+ Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
+ Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred. In this
+ case the DMA interrupt is configured
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of DMA handle structure).
+ [..]
+ (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
+ detection.
+
+ (#) Use HAL_DMA_Abort() function to abort the current transfer
+
+ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+ -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+ possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+ Half-Word data size for the peripheral to access its data register and set Word data size
+ for the Memory to gain in access time. Each two half words will be packed and written in
+ a single access to a Word in the Memory).
+
+ -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+ and Destination. In this case the Peripheral Data Size will be applied to both Source
+ and Destination.
+
+ *** DMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in DMA HAL driver.
+
+ (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+ (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+ (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
+ (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
+ (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
+ (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
+
+ [..]
+ (@) You can refer to the DMA HAL driver header file for more useful macros.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMA DMA
+ * @brief DMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register */
+ __IO uint32_t Reserved0;
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */
+
+
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize the DMA Stream source
+ and destination incrementation and data sizes, transfer direction,
+ circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+ [..]
+ The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+ reference manual.
+ The HAL_DMA_DeInit function allows to deinitialize the DMA stream.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ uint32_t registerValue;
+ uint32_t tickstart = HAL_GetTick();
+ DMA_Base_Registers *regs;
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+ assert_param(IS_DMA_MODE(hdma->Init.Mode));
+ assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+
+ if (IS_DMA_INSTANCE(hdma) != RESET) /*DMA2/DMA1 stream */
+ {
+
+// assert_param(IS_DMA_REQUEST(hdma->Init.Request));
+ assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+ /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+ when FIFO mode is enabled */
+ if (hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+ {
+ assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+ assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+ assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+ }
+
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hdma);
+
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA Stream is effectively disabled */
+ while ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the CR register value */
+ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR;
+
+ /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
+ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
+ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
+
+ /* Prepare the DMA Stream configuration */
+ registerValue |= hdma->Init.Direction |
+ hdma->Init.PeriphInc | hdma->Init.MemInc |
+ hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ hdma->Init.Mode | hdma->Init.Priority;
+
+ /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+ if (hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ {
+ /* Get memory burst and peripheral burst */
+ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+ }
+
+ /* Write to DMA Stream CR register */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue;
+
+ /* Get the FCR register value */
+ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR;
+
+ /* Clear Direct mode and FIFO threshold bits */
+ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+ /* Prepare the DMA Stream FIFO configuration */
+ registerValue |= hdma->Init.FIFOMode;
+
+ /* the FIFO threshold is not used when the FIFO mode is disabled */
+ if (hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ {
+ /* Get the FIFO threshold */
+ registerValue |= hdma->Init.FIFOThreshold;
+
+ /* Check compatibility between FIFO threshold level and size of the memory burst */
+ /* for INCR4, INCR8, INCR16 */
+ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+ {
+ if (DMA_CheckFifoParam(hdma) != HAL_OK)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Write to DMA Stream FCR */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue;
+
+ /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+ DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all interrupt flags */
+ regs->IFCR = 0x3FUL << hdma->StreamIndex;
+ }
+ else
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Initialize parameters for DMAMUX channel :
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+ */
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ {
+ /* if memory to memory force the request to 0*/
+ hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+ }
+
+
+ /* Set peripheral request to DMAMUX channel */
+ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Initialize parameters for DMAMUX request generator :
+ if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
+ */
+
+ if ((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+ {
+ /* Initialize parameters for DMAMUX request generator :
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ */
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+ /* Reset the DMAMUX request generator register*/
+ hdma->DMAmuxRequestGen->RGCR = 0U;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+ else
+ {
+ hdma->DMAmuxRequestGen = 0U;
+ hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGenStatusMask = 0U;
+ }
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the DMA peripheral
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+ DMA_Base_Registers *regs;
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the DMA peripheral state */
+ if (hdma->State == HAL_DMA_STATE_BUSY)
+ {
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+
+ /* Disable the selected DMA Streamx */
+ __HAL_DMA_DISABLE(hdma);
+
+
+ /* Reset DMA Streamx control register */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U;
+
+ /* Reset DMA Streamx number of data to transfer register */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U;
+
+ /* Reset DMA Streamx peripheral address register */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U;
+
+ /* Reset DMA Streamx memory 0 address register */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U;
+
+ /* Reset DMA Streamx memory 1 address register */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U;
+
+ /* Reset DMA Streamx FIFO control register */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U;
+
+ /* Get DMA steam Base Address */
+ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FUL << hdma->StreamIndex;
+ /* Initialize parameters for DMAMUX channel :
+ DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
+ DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+
+ if(hdma->DMAmuxChannel != NULL)
+ {
+ /* Resett he DMAMUX channel that corresponds to the DMA stream */
+ hdma->DMAmuxChannel->CCR = 0U;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ }
+
+ if ((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+ {
+ /* Initialize parameters for DMAMUX request generator :
+ DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
+ */
+ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+
+ /* Reset the DMAMUX request generator register*/
+ hdma->DMAmuxRequestGen->RGCR = 0U;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ hdma->DMAmuxRequestGen = 0U;
+ hdma->DMAmuxRequestGenStatus = 0U;
+ hdma->DMAmuxRequestGenStatusMask = 0U;
+
+ /* Clean callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferM1CpltCallback = NULL;
+ hdma->XferM1HalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the DMA state */
+ hdma->State = HAL_DMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start DMA transfer with interrupt
+ (+) Register and Unregister DMA callbacks
+ (+) Abort DMA transfer
+ (+) Poll for transfer complete
+ (+) Handle DMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Start the DMA Transfer with interrupt enabled.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable Common interrupts*/
+ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
+
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /*Enable Half Transfer IT if corresponding Callback is set*/
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
+ }
+
+ /* Check if DMAMUX Synchronization is enabled*/
+ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+ {
+ /* Enable DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+ }
+
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+ /* enable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+
+ }
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Aborts the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ *
+ * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
+ * effectively disabled is added. If a Stream is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Stream will be effectively disabled only after the transfer of
+ * this single data is finished.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = NULL;
+ const __IO uint32_t *enableRegister;
+
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the DMA peripheral state */
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable DMA All Interrupts */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+ regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR));
+
+ /* disable the DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Check if the DMA Stream is effectively disabled */
+ while (((*enableRegister) & DMA_SxCR_EN) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+ regs->IFCR = 0x3FUL << hdma->StreamIndex;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+ /* disable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the DMA Transfer in Interrupt mode.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set Abort State */
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CompleteLevel: Specifies the DMA level complete.
+ * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
+ * This model could be used for debug purpose.
+ * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t cpltlevel_mask;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* IT status register */
+ const __IO uint32_t *isr_reg;
+ /* IT clear flag register */
+ __IO uint32_t *ifcr_reg;
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* No transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ /* Polling mode not supported in circular mode and double buffering mode */
+ if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U)
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ /* Get the level transfer complete flag */
+ if (CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Transfer Complete flag */
+ cpltlevel_mask = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+ }
+ else
+ {
+ /* Half Transfer Complete flag */
+ cpltlevel_mask = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+ }
+
+ isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR);
+ ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR);
+
+ while ((((*isr_reg) & cpltlevel_mask) == 0U) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == 0U))
+ {
+ /* Check for the Timeout (Not applicable in circular mode)*/
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+
+ /* if timeout then abort the current transfer */
+ if (HAL_DMA_Abort(hdma) == HAL_OK)
+ {
+ /*
+ Note that the Abort function will
+ - Clear the transfer error flags
+ - Unlock
+ - Set the State
+ */
+ }
+
+ return HAL_ERROR;
+ }
+ }
+
+ /*Check for DMAMUX Request generator (if used) overrun status */
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
+ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+ {
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+ }
+ }
+
+ /* Check for DMAMUX Synchronization overrun */
+ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+ {
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+ }
+
+ if (((*isr_reg) & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+ /* Clear the transfer error flag */
+ (*ifcr_reg) = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+ }
+
+ if (((*isr_reg) & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+
+ /* Clear the FIFO error flag */
+ (*ifcr_reg) = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+ }
+
+ if (((*isr_reg) & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+
+ /* Clear the Direct Mode error flag */
+ (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+ }
+ }
+
+
+ if (hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ {
+ if ((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+ {
+ if (IS_DMA_INSTANCE(hdma) != RESET) /* DMA : DMA1 or DMA2 */
+ {
+ if (HAL_DMA_Abort(hdma) == HAL_OK)
+ {
+ /*
+ Note that the Abort function will
+ - Clear the transfer error flags
+ - Unlock
+ - Set the State
+ */
+ }
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the level transfer complete flag */
+ if (CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ {
+ /* Clear the half transfer and transfer complete flags */
+ (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
+ {
+ /* Clear the half transfer and transfer complete flags */
+ (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Handles DMA interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
+ */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ uint32_t tmpisr;
+ __IO uint32_t count = 0U;
+ uint32_t timeout = SystemCoreClock / 9600U;
+
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+ tmpisr = regs->ISR;
+
+ if (IS_DMA_INSTANCE(hdma) != RESET) /*D2 domain DMA : DMA1 or DMA2*/
+ {
+ /* Transfer Error Interrupt management ***************************************/
+ if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
+ {
+ /* Disable the transfer error interrupt */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE);
+
+ /* Clear the transfer error flag */
+ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+ }
+ }
+ /* FIFO Error Interrupt management ******************************************/
+ if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
+ {
+ /* Clear the FIFO error flag */
+ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+ }
+ }
+ /* Direct Mode Error Interrupt management ***********************************/
+ if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
+ {
+ /* Clear the direct mode error flag */
+ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ }
+ }
+ /* Half Transfer Complete Interrupt management ******************************/
+ if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+ {
+ /* Clear the half transfer complete flag */
+ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+
+ /* Multi_Buffering mode enabled */
+ if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+ {
+ /* Current memory buffer used is Memory 0 */
+ if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+ {
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ /* Current memory buffer used is Memory 1 */
+ else
+ {
+ if (hdma->XferM1HalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferM1HalfCpltCallback(hdma);
+ }
+ }
+ }
+ else
+ {
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ /* Disable the half transfer interrupt */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);
+ }
+
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+ }
+ }
+ /* Transfer Complete Interrupt management ***********************************/
+ if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != 0U)
+ {
+ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+ {
+ /* Clear the transfer complete flag */
+ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+
+ if (HAL_DMA_STATE_ABORT == hdma->State)
+ {
+ /* Disable all the transfer interrupts */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+
+ if ((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ {
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT);
+ }
+
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FUL << hdma->StreamIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ if (hdma->XferAbortCallback != NULL)
+ {
+ hdma->XferAbortCallback(hdma);
+ }
+ return;
+ }
+
+ if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+ {
+ /* Current memory buffer used is Memory 0 */
+ if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+ {
+ if (hdma->XferM1CpltCallback != NULL)
+ {
+ /* Transfer complete Callback for memory1 */
+ hdma->XferM1CpltCallback(hdma);
+ }
+ }
+ /* Current memory buffer used is Memory 1 */
+ else
+ {
+ if (hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete Callback for memory0 */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+ /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+ else
+ {
+ if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+ {
+ /* Disable the transfer complete interrupt */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ if (hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+ }
+ }
+
+ /* manage error case */
+ if (hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ {
+ if ((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+ {
+ hdma->State = HAL_DMA_STATE_ABORT;
+
+ /* Disable the stream */
+ __HAL_DMA_DISABLE(hdma);
+
+ do
+ {
+ if (++count > timeout)
+ {
+ break;
+ }
+ }
+ while ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ {
+ /* Change the DMA state to error if DMA disable fails */
+ hdma->State = HAL_DMA_STATE_ERROR;
+ }
+ else
+ {
+ /* Change the DMA state to Ready if DMA disable success */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+ }
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+ else
+ {
+ /* Nothing To Do */
+ }
+}
+
+/**
+ * @brief Register callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID: User Callback identifer
+ * a DMA_HandleTypeDef structure as parameter.
+ * @param pCallback: pointer to private callbacsk function which has pointer to
+ * a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_M1CPLT_CB_ID:
+ hdma->XferM1CpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+ hdma->XferM1HalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID: User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the DMA peripheral handle */
+ if (hdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_M1CPLT_CB_ID:
+ hdma->XferM1CpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+ hdma->XferM1HalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferM1CpltCallback = NULL;
+ hdma->XferM1HalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the DMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the DMA state.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL state
+ */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ return hdma->State;
+}
+
+/**
+ * @brief Return the DMA error code
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval DMA Error Code
+ */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+ return hdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* calculate DMA base and stream number */
+ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+ /* Clear all interrupt flags at correct offset within the register */
+ regs->IFCR = 0x3FUL << hdma->StreamIndex;
+
+ /* Clear DBM bit */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+ /* Configure DMA Stream data length */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Stream destination address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
+
+ /* Configure DMA Stream source address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Stream source address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
+
+ /* Configure DMA Stream destination address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
+ }
+}
+
+/**
+ * @brief Returns the DMA Stream base address depending on stream number
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval Stream base address
+ */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+ uint32_t stream_number = (((uint32_t)((uint32_t *)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+ /* lookup table for necessary bitshift of flags within status registers */
+ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+ hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
+
+ if (stream_number > 3U)
+ {
+ /* return pointer to HISR and HIFCR */
+ hdma->StreamBaseAddress = (((uint32_t)((uint32_t *)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
+ }
+ else
+ {
+ /* return pointer to LISR and LIFCR */
+ hdma->StreamBaseAddress = ((uint32_t)((uint32_t *)hdma->Instance) & (uint32_t)(~0x3FFU));
+ }
+
+ return hdma->StreamBaseAddress;
+}
+
+/**
+ * @brief Check compatibility between FIFO threshold level and size of the memory burst
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Memory Data size equal to Byte */
+ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+ {
+ switch (hdma->Init.FIFOThreshold)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case DMA_FIFO_THRESHOLD_FULL:
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ /* Memory Data size equal to Half-Word */
+ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ switch (hdma->Init.FIFOThreshold)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ status = HAL_ERROR;
+ break;
+
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case DMA_FIFO_THRESHOLD_FULL:
+ if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ /* Memory Data size equal to Word */
+ else
+ {
+ switch (hdma->Init.FIFOThreshold)
+ {
+ case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+ case DMA_FIFO_THRESHOLD_HALFFULL:
+ case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+ status = HAL_ERROR;
+ break;
+
+ case DMA_FIFO_THRESHOLD_FULL:
+ if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ uint32_t stream_number;
+ uint32_t stream_baseaddress = (uint32_t)((uint32_t *)hdma->Instance);
+ /*DMA1/DMA2 Streams are connected to DMAMUX1 channels*/
+ stream_number = (((uint32_t)((uint32_t *)hdma->Instance) & 0xFFU) - 16U) / 24U;
+
+ if ((stream_baseaddress <= ((uint32_t)DMA2_Stream7)) && \
+ (stream_baseaddress >= ((uint32_t)DMA2_Stream0)))
+ {
+ stream_number += 8U;
+ }
+ hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+ hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+ hdma->DMAmuxChannelStatusMask = 1UL << stream_number;
+}
+
+/**
+ * @brief Updates the DMA handle with the DMAMUX request generator params
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+
+ if ((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
+ {
+
+ /*DMA1 and DMA2 Streams use DMAMUX1 request generator blocks*/
+ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+ hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+ hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c
new file mode 100644
index 0000000..5f044b3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dma_ex.c
@@ -0,0 +1,603 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_dma_ex.c
+ * @author MCD Application Team
+ * @brief DMA Extension HAL module driver
+ * This file provides firmware functions to manage the following
+ * functionalities of the DMA Extension peripheral:
+ * + Extended features functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The DMA Extension HAL driver can be used as follows:
+ (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+ for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+ Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+ to respectively enable/disable the request generator.
+
+ (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
+ the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
+ As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
+ called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
+ (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
+
+ -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+ -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
+ -@- In Multi (Double) buffer mode, it is possible to update the base address for
+ the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
+ -@- Multi (Double) buffer mode is only possible with D2 DMAs i.e DMA1 or DMA2. not BDMA.
+ Multi (Double) buffer mode is not possible with D3 BDMA.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup DMAEx DMAEx
+ * @brief DMA Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+#define DMAMUX_POSITION_CxCR_SE (uint32_t)POSITION_VAL(DMAMUX_CxCR_SE) /*!< Required for left shift of the DMAMUX SYNC enable/disable */
+#define DMAMUX_POSITION_CxCR_EGE (uint32_t)POSITION_VAL(DMAMUX_CxCR_EGE) /*!< Required for left shift of the DMAMUX SYNC EVENT enable/disable */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
+
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+ * @{
+ */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended features functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and
+ Start MultiBuffer DMA transfer
+ (+) Configure the source, destination address and data length and
+ Start MultiBuffer DMA transfer with interrupt
+ (+) Change on the fly the memory0 or memory1 address.
+ (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
+ (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
+ (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
+ to respectively enable/disable the request generator.
+ (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
+ the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Starts the multi_buffer DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Memory-to-memory transfer not supported in double buffering mode */
+ /* double buffering mode not supported for BDMA (D3 DMA) */
+ if ((IS_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Enable the double buffer mode */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= (uint32_t)DMA_SxCR_DBM;
+
+ /* Configure DMA Stream destination address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
+
+ /* Configure the source, destination address and the data length */
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Calculate the interrupt clear flag register (IFCR) base address */
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+ /* Clear all flags */
+ *ifcRegister_Base = 0x3FUL << hdma->StreamIndex;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Enable the peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+ /* Memory-to-memory transfer not supported in double buffering mode */
+ if ((IS_DMA_INSTANCE(hdma) == 0U) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if (HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Enable the Double buffer mode */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= (uint32_t)DMA_SxCR_DBM;
+
+ /* Configure DMA Stream destination address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
+
+ /* Configure the source, destination address and the data length */
+ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Calculate the interrupt clear flag register (IFCR) base address */
+ ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
+
+ /* Clear all flags */
+ *ifcRegister_Base = 0x3FUL << hdma->StreamIndex;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ }
+
+ /* Enable Common interrupts*/
+ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
+
+ if (hdma->XferHalfCpltCallback != NULL)
+ {
+ /*Enable Half Transfer IT if corresponding Callback is set*/
+ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
+ }
+
+ /* Check if DMAMUX Synchronization is enabled*/
+ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+ {
+ /* Enable DMAMUX sync overrun IT*/
+ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+ }
+
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+ /* enable the request gen overrun IT*/
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+ }
+
+ /* Enable the peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Change the memory0 or memory1 address on the fly.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param Address: The new address
+ * @param memory: the memory to be changed, This parameter can be one of
+ * the following values:
+ * MEMORY0 /
+ * MEMORY1
+ * @note The MEMORY0 address can be changed only when the current transfer use
+ * MEMORY1 and the MEMORY1 address can be changed only when the current
+ * transfer use MEMORY0.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+ if (memory == MEMORY0)
+ {
+ /* change the memory0 address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;
+ }
+ else
+ {
+ /* change the memory1 address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
+{
+ uint32_t syncSignalID = 0;
+ uint32_t syncPolarity = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+ assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
+ assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
+ assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
+
+ if (pSyncConfig->SyncEnable == ENABLE)
+ {
+ assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
+ assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
+ syncSignalID = pSyncConfig->SyncSignalID;
+ syncPolarity = pSyncConfig->SyncPolarity;
+ }
+
+ /*Check if the DMA state is ready */
+ if (hdma->State == HAL_DMA_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ /* Disable the synchronization and event generation before applying a new config */
+ CLEAR_BIT(hdma->DMAmuxChannel->CCR, (DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
+
+ /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
+ MODIFY_REG(hdma->DMAmuxChannel->CCR, \
+ (~DMAMUX_CxCR_DMAREQ_ID), \
+ (syncSignalID << POSITION_VAL(DMAMUX_CxCR_SYNC_ID)) | \
+ ((pSyncConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_CxCR_NBREQ)) | \
+ syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_POSITION_CxCR_SE) | \
+ ((uint32_t)pSyncConfig->EventEnable << DMAMUX_POSITION_CxCR_EGE));
+
+ /* Process Locked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* Return error status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
+ * contains the request generator parameters.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
+ assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
+
+ assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
+ assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if(hdma->DMAmuxRequestGen == NULL)
+ {
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+
+ /* error status */
+ status = HAL_ERROR;
+ }
+ else if ((hdma->State == HAL_DMA_STATE_READY) && ((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U))
+ {
+ /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
+
+ /* Process Locked */
+ __HAL_LOCK(hdma);
+
+ /* Set the request generator new parameters*/
+ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
+ ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ)) | \
+ pRequestGeneratorConfig->Polarity;
+ /* Process Locked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set the error code to busy */
+ hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+
+ /* error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != NULL))
+ {
+
+ /* Enable the request generator*/
+ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
+ /* check if the DMA state is ready
+ and DMA is using a DMAMUX request generator block
+ */
+ if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != NULL))
+ {
+
+ /* Disable the request generator*/
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles DMAMUX interrupt request.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
+ */
+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ /* Check for DMAMUX Synchronization overrun */
+ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
+ {
+ /* Disable the synchro overrun interrupt */
+ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+
+ /* Clear the DMAMUX synchro overrun flag */
+ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+
+ if(hdma->DMAmuxRequestGen != NULL)
+ {
+ /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
+ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
+ {
+ /* Disable the request gen overrun interrupt */
+ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+
+ /* Clear the DMAMUX request generator overrun flag */
+ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+
+ /* Update error code */
+ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup DMAEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Set the DMA Transfer parameter.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param DataLength: The length of data to be transferred from source to destination
+ * @retval HAL status
+ */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ /* Configure DMA Stream data length */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
+
+ /* Peripheral to Memory */
+ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ {
+ /* Configure DMA Stream destination address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
+
+ /* Configure DMA Stream source address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
+ }
+ /* Memory to Peripheral */
+ else
+ {
+ /* Configure DMA Stream source address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
+
+ /* Configure DMA Stream destination address */
+ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c
new file mode 100644
index 0000000..8c98003
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c
@@ -0,0 +1,767 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_exti.c
+ * @author MCD Application Team
+ * @brief EXTI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (EXTI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### EXTI Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each Exti line can be configured within this driver.
+
+ (+) Exti line can be configured in 3 different modes
+ (++) Interrupt
+ (++) Event
+ (++) Both of them
+
+ (+) Configurable Exti lines can be configured with 3 different triggers
+ (++) Rising
+ (++) Falling
+ (++) Both of them
+
+ (+) When set in interrupt mode, configurable Exti lines have two diffenrents
+ interrupt pending registers which allow to distinguish which transition
+ occurs:
+ (++) Rising edge pending interrupt
+ (++) Falling
+
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+ be selected throught multiplexer.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Configure the configurable EXTI line using HAL_EXTI_SetConfigLine().
+ NOTE: in addition HAL_EXTI_SetInterruptAndEventMask shall be used
+ to configure interrupt and events mask of this configurable line
+ (++) Choose the interrupt line number by setting "Line" member from
+ EXTI_ConfigTypeDef structure.
+ (++) Configure the interrupt and/or event mode using "Mode" member from
+ EXTI_ConfigTypeDef structure.
+ (++) For configurable lines, configure rising and/or falling trigger
+ "Trigger" member from EXTI_ConfigTypeDef structure.
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+ member from GPIO_InitTypeDef structure.
+
+ (#) Get current Exti configuration of a dedicated line using
+ HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+
+ (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ EXTI_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+ * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+ * of bounds [0,3] in following API :
+ * HAL_EXTI_SetConfigLine
+ * HAL_EXTI_GetConfigLine
+ * HAL_EXTI_ClearConfigLine
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+#define EXTI_MODE_C1 0x10u
+#define EXTI_MODE_C2 0x20u
+#define EXTI_MODE_INTERRUPT 0x01u
+#define EXTI_MODE_EVENT 0x02u
+#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set configuration except Interrupt and Event mask of a dedicated Exti line.
+ * It is relevant only for configurable events.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+
+ /* Assign line number to handle */
+ hexti->Line = pExtiConfig->Line;
+
+ /* compute line register offset and line mask */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* Configure triggers for configurable lines */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ {
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Configure rising trigger */
+ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store rising trigger mode */
+ *regaddr = regval;
+
+ /* Configure falling trigger */
+ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store falling trigger mode */
+ *regaddr = regval;
+
+ /* Configure gpio port selection in case of gpio exti line */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[linepos >> 2u];
+ regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ EXTI->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ /*Set Interrupt And Event Mask for Core 1 if configuration for Core 1 given into parameter mode */
+ if ((pExtiConfig->Mode & EXTI_MODE_C1) != 0x00u)
+ {
+ regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset));
+
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store interrupt mode */
+ *regaddr = regval;
+
+ /* The event mode cannot be configured if the line does not support it */
+ assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
+
+ regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
+
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store event mode */
+ *regaddr = regval;
+ }
+
+ /*Set Interrupt And Event Mask for Core 2 if configuration for Core 2 given into parameter mode */
+ if ((pExtiConfig->Mode & EXTI_MODE_C2) != 0x00u)
+ {
+ regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store interrupt mode */
+ *regaddr = regval;
+
+ /* The event mode cannot be configured if the line does not support it */
+ assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
+
+ regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+
+ regval = *regaddr;
+
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+ {
+ regval |= maskline;
+ }
+ else
+ {
+ regval &= ~maskline;
+ }
+
+ /* Store event mode */
+ *regaddr = regval;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Get configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* Store handle line number to configiguration structure */
+ pExtiConfig->Line = hexti->Line;
+
+ /* compute line register offset and line mask */
+ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* 1] Get core 1 mode : interrupt */
+ regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0x00u)
+ {
+ pExtiConfig->Mode = EXTI_MODE_C1_INTERRUPT;
+ }
+ else
+ {
+ pExtiConfig->Mode = EXTI_MODE_C1_NONE;
+ }
+
+ /* Get Core 1 mode : event */
+ regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0x00u)
+ {
+ pExtiConfig->Mode |= EXTI_MODE_C1_EVENT;
+ }
+
+ /* Get core 2 mode : interrupt */
+ regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0x00u)
+ {
+ pExtiConfig->Mode |= EXTI_MODE_C2_INTERRUPT;
+ }
+ else
+ {
+ pExtiConfig->Mode |= EXTI_MODE_C2_NONE;
+ }
+
+ /* Get Core 2 mode : event */
+ regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if selected line is enable */
+ if ((regval & maskline) != 0x00u)
+ {
+ pExtiConfig->Mode |= EXTI_MODE_C2_EVENT;
+ }
+
+ /* 2] Get trigger for configurable lines : rising */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ {
+ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0x00u)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ }
+ else
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ }
+
+ /* Get falling configuration */
+ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = *regaddr;
+
+ /* Check if configuration of selected line is enable */
+ if ((regval & maskline) != 0x00u)
+ {
+ pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ }
+
+ /* Get Gpio port selection for gpio lines */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[linepos >> 2u];
+ pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+ }
+ else
+ {
+ pExtiConfig->GPIOSel = 0x00u;
+ }
+ }
+ else
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Clear whole configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* 1] Clear interrupt mode */
+ regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 2] Clear event mode */
+ regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* 3] Clear triggers in case of configurable lines */
+ if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+ {
+ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & ~maskline);
+ *regaddr = regval;
+
+ /* Get Gpio port selection for gpio lines */
+ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = EXTI->EXTICR[linepos >> 2u];
+ regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ EXTI->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Register callback for a dedicaated Exti line.
+ * @param hexti Exti handle.
+ * @param CallbackID User callback identifier.
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_EXTI_COMMON_CB_ID:
+ hexti->RisingCallback = pPendingCbfn;
+ hexti->FallingCallback = pPendingCbfn;
+ break;
+
+ case HAL_EXTI_RISING_CB_ID:
+ hexti->RisingCallback = pPendingCbfn;
+ break;
+
+ case HAL_EXTI_FALLING_CB_ID:
+ hexti->FallingCallback = pPendingCbfn;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Store line number as handle private field.
+ * @param hexti Exti handle.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Store line number as handle private field */
+ hexti->Line = ExtiLine;
+
+ return HAL_OK;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ * @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Get rising edge pending bit */
+ regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & maskline);
+
+ if (regval != 0x00u)
+ {
+ /* Clear pending bit */
+ *regaddr = maskline;
+
+ /* Call rising callback */
+ if (hexti->RisingCallback != NULL)
+ {
+ hexti->RisingCallback();
+ }
+ }
+
+ /* Get falling edge pending bit */
+ regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ regval = (*regaddr & maskline);
+
+ if (regval != 0x00u)
+ {
+ /* Clear pending bit */
+ *regaddr = maskline;
+
+ /* Call rising callback */
+ if (hexti->FallingCallback != NULL)
+ {
+ hexti->FallingCallback();
+ }
+ }
+}
+
+
+/**
+ * @brief Get interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be checked.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING
+ * @arg @ref EXTI_TRIGGER_FALLING
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ if (Edge != EXTI_TRIGGER_RISING)
+ {
+ /* Get falling edge pending bit */
+ regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+ else
+ {
+ /* Get rising edge pending bit */
+ regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+
+ /* return 1 if bit is set else 0 */
+ regval = ((*regaddr & maskline) >> linepos);
+ return regval;
+}
+
+
+/**
+ * @brief Clear interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be clear.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING
+ * @arg @ref EXTI_TRIGGER_FALLING
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ if (Edge != EXTI_TRIGGER_RISING)
+ {
+ /* Get falling edge pending register address */
+ regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+ else
+ {
+ /* Get falling edge pending register address */
+ regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
+ }
+
+ /* Clear Pending bit */
+ *regaddr = maskline;
+}
+
+
+/**
+ * @brief Generate a software interrupt for a dedicated line.
+ * @param hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+ __IO uint32_t *regaddr;
+ uint32_t maskline;
+ uint32_t offset;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+ /* compute line register offset and line mask */
+ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
+ *regaddr = maskline;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c
new file mode 100644
index 0000000..35df2e1
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_fdcan.c
@@ -0,0 +1,5097 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_fdcan.c
+ * @author MCD Application Team
+ * @brief FDCAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Flexible DataRate Controller Area Network
+ * (FDCAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Configuration and Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
+
+ (#) If needed , configure the reception filters and optional features using
+ the following configuration functions:
+ (++) HAL_FDCAN_ConfigClockCalibration
+ (++) HAL_FDCAN_ConfigFilter
+ (++) HAL_FDCAN_ConfigGlobalFilter
+ (++) HAL_FDCAN_ConfigExtendedIdMask
+ (++) HAL_FDCAN_ConfigRxFifoOverwrite
+ (++) HAL_FDCAN_ConfigFifoWatermark
+ (++) HAL_FDCAN_ConfigRamWatchdog
+ (++) HAL_FDCAN_ConfigTimestampCounter
+ (++) HAL_FDCAN_EnableTimestampCounter
+ (++) HAL_FDCAN_DisableTimestampCounter
+ (++) HAL_FDCAN_ConfigTimeoutCounter
+ (++) HAL_FDCAN_EnableTimeoutCounter
+ (++) HAL_FDCAN_DisableTimeoutCounter
+ (++) HAL_FDCAN_ConfigTxDelayCompensation
+ (++) HAL_FDCAN_EnableTxDelayCompensation
+ (++) HAL_FDCAN_DisableTxDelayCompensation
+ (++) HAL_FDCAN_EnableISOMode
+ (++) HAL_FDCAN_DisableISOMode
+ (++) HAL_FDCAN_EnableEdgeFiltering
+ (++) HAL_FDCAN_DisableEdgeFiltering
+ (++) HAL_FDCAN_TT_ConfigOperation
+ (++) HAL_FDCAN_TT_ConfigReferenceMessage
+ (++) HAL_FDCAN_TT_ConfigTrigger
+
+ (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
+ the node is active on the bus: it can send and receive messages.
+
+ (#) The following Tx control functions can only be called when the FDCAN
+ module is started:
+ (++) HAL_FDCAN_AddMessageToTxFifoQ
+ (++) HAL_FDCAN_EnableTxBufferRequest
+ (++) HAL_FDCAN_AbortTxRequest
+
+ (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
+ get Tx buffer location used to place the Tx request thanks to
+ HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
+ It is then possible to abort later on the corresponding Tx Request using
+ HAL_FDCAN_AbortTxRequest API.
+
+ (#) When a message is received into the FDCAN message RAM, it can be
+ retrieved using the HAL_FDCAN_GetRxMessage function.
+
+ (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
+ it to initialization mode and re-enabling access to configuration
+ registers through the configuration functions listed here above.
+
+ (#) All other control functions can be called any time after initialization
+ phase, no matter if the FDCAN module is started or stoped.
+
+ *** Polling mode operation ***
+ ==============================
+
+ [..]
+ (#) Reception and transmission states can be monitored via the following
+ functions:
+ (++) HAL_FDCAN_IsRxBufferMessageAvailable
+ (++) HAL_FDCAN_IsTxBufferMessagePending
+ (++) HAL_FDCAN_GetRxFifoFillLevel
+ (++) HAL_FDCAN_GetTxFifoFreeLevel
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) There are two interrupt lines: line 0 and 1.
+ By default, all interrupts are assigned to line 0. Interrupt lines
+ can be configured using HAL_FDCAN_ConfigInterruptLines function.
+
+ (#) Notifications are activated using HAL_FDCAN_ActivateNotification
+ function. Then, the process can be controlled through one of the
+ available user callbacks: HAL_FDCAN_xxxCallback.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+#if defined(FDCAN1)
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup FDCAN FDCAN
+ * @brief FDCAN HAL module driver
+ * @{
+ */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Constants
+ * @{
+ */
+#define FDCAN_TIMEOUT_VALUE 10U
+
+#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN)
+#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N)
+#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N)
+#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
+#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
+#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG)
+#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI)
+#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD)
+#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \
+ FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC)
+#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER)
+
+#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
+#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
+#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
+#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
+#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
+#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
+#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
+#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
+#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
+#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
+#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
+#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
+#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
+#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
+
+#define FDCAN_MESSAGE_RAM_SIZE 0x2800U
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FDCAN_Private_Functions_Prototypes
+ * @{
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
+ * @{
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the FDCAN.
+ (+) De-initialize the FDCAN.
+ (+) Enter FDCAN peripheral in power down mode.
+ (+) Exit power down mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the FDCAN peripheral according to the specified
+ * parameters in the FDCAN_InitTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef status;
+ const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+
+ /* Check FDCAN handle */
+ if (hfdcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check FDCAN instance */
+ if (hfdcan->Instance == FDCAN1)
+ {
+ hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+ }
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
+ assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
+ assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
+ assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
+ assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
+ assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
+ assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
+ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+ {
+ assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
+ assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
+ assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
+ assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
+ }
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U));
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U));
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U));
+ if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+ {
+ assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize));
+ }
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U));
+ if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+ {
+ assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize));
+ }
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U));
+ if (hfdcan->Init.RxBuffersNbr > 0U)
+ {
+ assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize));
+ }
+ assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U));
+ assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U));
+ if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+ {
+ assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
+ }
+ if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+ {
+ assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize));
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hfdcan->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ HAL_FDCAN_MspInit(hfdcan);
+ }
+
+ /* Exit from Sleep mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check Sleep mode acknowledge */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Request initialisation */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the INIT bit into CCCR register is set */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable configuration change */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+ /* Set the no automatic retransmission */
+ if (hfdcan->Init.AutoRetransmission == ENABLE)
+ {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ }
+ else
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ }
+
+ /* Set the transmit pause feature */
+ if (hfdcan->Init.TransmitPause == ENABLE)
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ }
+ else
+ {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ }
+
+ /* Set the Protocol Exception Handling */
+ if (hfdcan->Init.ProtocolException == ENABLE)
+ {
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ }
+ else
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ }
+
+ /* Set FDCAN Frame Format */
+ MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+
+ /* Reset FDCAN Operation Mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+ CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+ /* Set FDCAN Operating Mode:
+ | Normal | Restricted | Bus | Internal | External
+ | | Operation | Monitoring | LoopBack | LoopBack
+ CCCR.TEST | 0 | 0 | 0 | 1 | 1
+ CCCR.MON | 0 | 0 | 1 | 1 | 0
+ TEST.LBCK | 0 | 0 | 0 | 1 | 1
+ CCCR.ASM | 0 | 1 | 0 | 0 | 0
+ */
+ if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+ {
+ /* Enable Restricted Operation mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+ }
+ else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+ {
+ if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+ {
+ /* Enable write access to TEST register */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+
+ /* Enable LoopBack mode */
+ SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+
+ if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+ {
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ }
+ }
+ else
+ {
+ /* Enable bus monitoring mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ }
+ }
+ else
+ {
+ /* Nothing to do: normal mode */
+ }
+
+ /* Set the nominal bit timing register */
+ hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \
+ (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \
+ (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+
+ /* If FD operation with BRS is selected, set the data bit timing register */
+ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+ {
+ hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+ (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
+ (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
+ (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+ }
+
+ if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+ {
+ /* Select between Tx FIFO and Tx Queue operation modes */
+ SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+ }
+
+ /* Configure Tx element size */
+ if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+ {
+ MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+ }
+
+ /* Configure Rx FIFO 0 element size */
+ if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+ {
+ MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+ }
+
+ /* Configure Rx FIFO 1 element size */
+ if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+ {
+ MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+ }
+
+ /* Configure Rx buffer element size */
+ if (hfdcan->Init.RxBuffersNbr > 0U)
+ {
+ MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+ }
+
+ /* By default operation mode is set to Event-driven communication.
+ If Time-triggered communication is needed, user should call the
+ HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+ if (hfdcan->Instance == FDCAN1)
+ {
+ CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+ }
+
+ /* Initialize the Latest Tx FIFO/Queue request buffer index */
+ hfdcan->LatestTxFifoQRequest = 0U;
+
+ /* Initialize the error code */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Initialize the FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_READY;
+
+ /* Calculate each RAM block address */
+ status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Deinitializes the FDCAN peripheral registers to their default reset values.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Check FDCAN handle */
+ if (hfdcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
+
+ /* Stop the FDCAN module: return value is voluntary ignored */
+ (void)HAL_FDCAN_Stop(hfdcan);
+
+ /* Disable Interrupt lines */
+ CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ HAL_FDCAN_MspDeInit(hfdcan);
+
+ /* Reset the FDCAN ErrorCode */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_RESET;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FDCAN MSP.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the FDCAN MSP.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Enter FDCAN peripheral in sleep mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t tickstart;
+
+ /* Request clock stop */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FDCAN is ready for power down */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Exit power down mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t tickstart;
+
+ /* Reset clock stop request */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FDCAN exits sleep mode */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ {
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enter normal operation */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
+ * @brief FDCAN Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Configuration functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_ConfigClockCalibration : Configure the FDCAN clock calibration unit
+ (+) HAL_FDCAN_GetClockCalibrationState : Get the clock calibration state
+ (+) HAL_FDCAN_ResetClockCalibrationState : Reset the clock calibration state
+ (+) HAL_FDCAN_GetClockCalibrationCounter : Get the clock calibration counters values
+ (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters
+ (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter
+ (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask
+ (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode
+ (+) HAL_FDCAN_ConfigFifoWatermark : Configure the FIFO watermark
+ (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog
+ (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter
+ (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter
+ (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter
+ (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value
+ (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero
+ (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter
+ (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter
+ (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter
+ (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value
+ (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value
+ (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation
+ (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation
+ (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation
+ (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode
+ (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode
+ (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during bus integration
+ (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering during bus integration
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the FDCAN clock calibration unit according to the specified
+ * parameters in the FDCAN_ClkCalUnitTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that
+ * contains the clock calibration information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
+ if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+ {
+ assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider));
+ }
+ else
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU));
+ assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength));
+ assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U));
+ assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U));
+ assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU));
+ }
+
+ /* FDCAN1 should be initialized in order to use clock calibration */
+ if (hfdcan->Instance != FDCAN1)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE)
+ {
+ /* Bypass clock calibration */
+ SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+ /* Configure clock divider */
+ MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+ }
+ else /* sCcuConfig->ClockCalibration == ENABLE */
+ {
+ /* Clock calibration unit generates time quanta clock */
+ CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
+
+ /* Configure clock calibration unit */
+ MODIFY_REG(FDCAN_CCU->CCFG,
+ (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
+ ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+
+ /* Configure the start value of the calibration watchdog counter */
+ MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the clock calibration state.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
+ */
+uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS);
+}
+
+/**
+ * @brief Reset the clock calibration state.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* FDCAN1 should be initialized in order to use clock calibration */
+ if (hfdcan->Instance != FDCAN1)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Calibration software reset */
+ SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the clock calibration counter value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param Counter clock calibration counter.
+ * This parameter can be a value of @arg FDCAN_calibration_counter.
+ * @retval Value clock calibration counter value
+ */
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter));
+
+ if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER)
+ {
+ return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos);
+ }
+ else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER)
+ {
+ return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC);
+ }
+ else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */
+ {
+ return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos);
+ }
+}
+
+/**
+ * @brief Configure the FDCAN reception filter according to the specified
+ * parameters in the FDCAN_FilterTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
+ * contains the filter configuration information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+{
+ uint32_t FilterElementW1;
+ uint32_t FilterElementW2;
+ uint32_t *FilterAddress;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
+ assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
+ if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U));
+ }
+
+ if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
+ {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
+ if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
+ assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
+ }
+
+ /* Build filter element */
+ if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+ {
+ FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U) |
+ (sFilterConfig->FilterID1 << 16U) |
+ (sFilterConfig->IsCalibrationMsg << 8U) |
+ sFilterConfig->RxBufferIndex);
+ }
+ else
+ {
+ FilterElementW1 = ((sFilterConfig->FilterType << 30U) |
+ (sFilterConfig->FilterConfig << 27U) |
+ (sFilterConfig->FilterID1 << 16U) |
+ sFilterConfig->FilterID2);
+ }
+
+ /* Calculate filter address */
+ FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U));
+
+ /* Write filter element to the message RAM */
+ *FilterAddress = FilterElementW1;
+ }
+ else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
+ {
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
+ if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
+ assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
+ }
+
+ /* Build first word of filter element */
+ FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
+
+ /* Build second word of filter element */
+ if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER)
+ {
+ FilterElementW2 = sFilterConfig->RxBufferIndex;
+ }
+ else
+ {
+ FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
+ }
+
+ /* Calculate filter address */
+ FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U));
+
+ /* Write filter element to the message RAM */
+ *FilterAddress = FilterElementW1;
+ FilterAddress++;
+ *FilterAddress = FilterElementW2;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the FDCAN global filter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param NonMatchingStd Defines how received messages with 11-bit IDs that
+ * do not match any element of the filter list are treated.
+ * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+ * @param NonMatchingExt Defines how received messages with 29-bit IDs that
+ * do not match any element of the filter list are treated.
+ * This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
+ * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
+ * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+ * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
+ * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t NonMatchingStd,
+ uint32_t NonMatchingExt,
+ uint32_t RejectRemoteStd,
+ uint32_t RejectRemoteExt)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
+ assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
+ assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
+ assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure global filter */
+ hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos) |
+ (NonMatchingExt << FDCAN_GFC_ANFE_Pos) |
+ (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) |
+ (RejectRemoteExt << FDCAN_GFC_RRFE_Pos));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the extended ID mask.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param Mask Extended ID Mask.
+ * This parameter must be a number between 0 and 0x1FFFFFFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure the extended ID mask */
+ hfdcan->Instance->XIDAM = Mask;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the Rx FIFO operation mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be one of the following values:
+ * @arg FDCAN_RX_FIFO0: Rx FIFO 0
+ * @arg FDCAN_RX_FIFO1: Rx FIFO 1
+ * @param OperationMode operation mode.
+ * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+ assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ if (RxFifo == FDCAN_RX_FIFO0)
+ {
+ /* Select FIFO 0 Operation Mode */
+ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+ }
+ else /* RxFifo == FDCAN_RX_FIFO1 */
+ {
+ /* Select FIFO 1 Operation Mode */
+ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the FIFO watermark.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param FIFO select the FIFO to be configured.
+ * This parameter can be a value of @arg FDCAN_FIFO_watermark.
+ * @param Watermark level for FIFO watermark interrupt.
+ * This parameter must be a number between:
+ * - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO
+ * - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO));
+ if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U));
+ }
+ else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U));
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Set the level for FIFO watermark interrupt */
+ if (FIFO == FDCAN_CFG_TX_EVENT_FIFO)
+ {
+ MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos));
+ }
+ else if (FIFO == FDCAN_CFG_RX_FIFO0)
+ {
+ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos));
+ }
+ else /* FIFO == FDCAN_CFG_RX_FIFO1 */
+ {
+ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos));
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the RAM watchdog.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param CounterStartValue Start value of the Message RAM Watchdog Counter,
+ * This parameter must be a number between 0x00 and 0xFF,
+ * with the reset value of 0x00 the counter is disabled.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure the RAM watchdog counter start value */
+ MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimestampPrescaler Timestamp Counter Prescaler.
+ * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure prescaler */
+ MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimestampOperation Timestamp counter operation.
+ * This parameter can be a value of @arg FDCAN_Timestamp.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable timestamp counter */
+ MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the timestamp counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable timestamp counter */
+ CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the timestamp counter value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Value Timestamp counter value
+ */
+uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ return (uint16_t)(hfdcan->Instance->TSCV);
+}
+
+/**
+ * @brief Reset the timestamp counter to zero.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
+ {
+ /* Reset timestamp counter.
+ Actually any write operation to TSCV clears the counter */
+ CLEAR_REG(hfdcan->Instance->TSCV);
+ }
+ else
+ {
+ /* Update error code.
+ Unable to reset external counter */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimeoutOperation Timeout counter operation.
+ * This parameter can be a value of @arg FDCAN_Timeout_Operation.
+ * @param TimeoutPeriod Start value of the timeout down-counter.
+ * This parameter must be a number between 0x0000 and 0xFFFF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
+ assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Select timeout operation and configure period */
+ MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable timeout counter */
+ SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the timeout counter.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable timeout counter */
+ CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get the timeout counter value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Value Timeout counter value
+ */
+uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ return (uint16_t)(hfdcan->Instance->TOCV);
+}
+
+/**
+ * @brief Reset the timeout counter to its start value.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+{
+ if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
+ {
+ /* Reset timeout counter to start value */
+ CLEAR_REG(hfdcan->Instance->TOCV);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Unable to reset counter: controlled only by FIFO empty state */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TdcOffset Transmitter Delay Compensation Offset.
+ * This parameter must be a number between 0x00 and 0x7F.
+ * @param TdcFilter Transmitter Delay Compensation Filter Window Length.
+ * This parameter must be a number between 0x00 and 0x7F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
+ assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure TDC offset and filter window */
+ hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable transmitter delay compensation */
+ SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable the transmitter delay compensation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable transmitter delay compensation */
+ CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable ISO 11898-1 protocol mode.
+ * CAN FD frame format is according to ISO 11898-1 standard.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable Non ISO protocol mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable ISO 11898-1 protocol mode.
+ * CAN FD frame format is according to Bosch CAN FD specification V1.0.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable Non ISO protocol mode */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable edge filtering during bus integration.
+ * Two consecutive dominant tq are required to detect an edge for hard synchronization.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Enable edge filtering */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable edge filtering during bus integration.
+ * One dominant tq is required to detect an edge for hard synchronization.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Disable edge filtering */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_Start : Start the FDCAN module
+ (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers
+ (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+ (+) HAL_FDCAN_AddMessageToTxBuffer : Add a message to a dedicated Tx buffer
+ (+) HAL_FDCAN_EnableTxBufferRequest : Enable transmission request
+ (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
+ (+) HAL_FDCAN_AbortTxRequest : Abort transmission request
+ (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
+ (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+ (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
+ (+) HAL_FDCAN_GetProtocolStatus : Get protocol status
+ (+) HAL_FDCAN_GetErrorCounters : Get error counter values
+ (+) HAL_FDCAN_IsRxBufferMessageAvailable : Check if a new message is received in the selected Rx buffer
+ (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending on the selected Tx buffer
+ (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+ (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
+ (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode
+ (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Start the FDCAN module.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Change FDCAN peripheral state */
+ hfdcan->State = HAL_FDCAN_STATE_BUSY;
+
+ /* Request leave initialisation */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Reset the FDCAN ErrorCode */
+ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop the FDCAN module and enable access to configuration registers.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Request initialisation */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+
+ /* Wait until the INIT bit into CCCR register is set */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Reset counter */
+ Counter = 0U;
+
+ /* Exit from Sleep mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+
+ /* Wait until FDCAN exits sleep mode */
+ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable configuration change */
+ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+
+ /* Reset Latest Tx FIFO/Queue Request Buffer Index */
+ hfdcan->LatestTxFifoQRequest = 0U;
+
+ /* Change FDCAN peripheral state */
+ hfdcan->State = HAL_FDCAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+ * @param pTxData pointer to a buffer containing the payload of the Tx frame.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+{
+ uint32_t PutIndex;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+ if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+ }
+ else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+ }
+ assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+ assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+ assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+ assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+ assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+ assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+ if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+
+ /* Check that the Tx FIFO/Queue is not full */
+ if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Retrieve the Tx FIFO PutIndex */
+ PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+
+ /* Add the message to the Tx FIFO/Queue */
+ FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+
+ /* Activate the corresponding transmission request */
+ hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+
+ /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+ hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Add a message to a dedicated Tx buffer
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+ * @param pTxData pointer to a buffer containing the payload of the Tx frame.
+ * @param BufferIndex index of the buffer to be configured.
+ * This parameter can be a value of @arg FDCAN_Tx_location.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
+ if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
+ }
+ else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
+ }
+ assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
+ assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
+ assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
+ assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+ assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+ assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+ assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+ assert_param(IS_FDCAN_TX_LOCATION(BufferIndex));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check that the selected buffer has an allocated area into the RAM */
+ if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos))
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+
+ /* Check that there is no transmittion request pending for the selected buffer */
+ if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Add the message to the Tx buffer */
+ FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex));
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable transmission request.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndex buffer index.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Add transmission request */
+ hfdcan->Instance->TXBAR = BufferIndex;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get Tx buffer index of latest Tx FIFO/Queue request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Tx buffer index of last Tx FIFO/Queue request
+ * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
+ * - 0 if no Tx FIFO/Queue request have been submitted.
+ */
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Return Last Tx FIFO/Queue Request Buffer */
+ return hfdcan->LatestTxFifoQRequest;
+}
+
+/**
+ * @brief Abort transmission request
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndex buffer index.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
+{
+ if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Add cancellation request */
+ hfdcan->Instance->TXBCR = BufferIndex;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxLocation Location of the received message to be read.
+ * This parameter can be a value of @arg FDCAN_Rx_location.
+ * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
+ * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+ uint32_t *RxAddress;
+ uint8_t *pData;
+ uint32_t ByteCounter;
+ uint32_t GetIndex = 0;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if (state == HAL_FDCAN_STATE_BUSY)
+ {
+ if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+ if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Calculate Rx FIFO 0 element address */
+ GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+ }
+ }
+ else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+ if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Calculate Rx FIFO 1 element address */
+ GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+ }
+ }
+ else /* Rx element is assigned to a dedicated Rx buffer */
+ {
+ /* Check that the selected buffer has an allocated area into the RAM */
+ if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Calculate Rx buffer address */
+ RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+ }
+ }
+
+ /* Retrieve IdType */
+ pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+
+ /* Retrieve Identifier */
+ if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+ {
+ pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+ }
+ else /* Extended ID element */
+ {
+ pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+ }
+
+ /* Retrieve RxFrameType */
+ pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+
+ /* Retrieve ErrorStateIndicator */
+ pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+
+ /* Increment RxAddress pointer to second word of Rx FIFO element */
+ RxAddress++;
+
+ /* Retrieve RxTimestamp */
+ pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+
+ /* Retrieve DataLength */
+ pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+
+ /* Retrieve BitRateSwitch */
+ pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+
+ /* Retrieve FDFormat */
+ pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+
+ /* Retrieve FilterIndex */
+ pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+
+ /* Retrieve NonMatchingFrame */
+ pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+
+ /* Increment RxAddress pointer to payload of Rx FIFO element */
+ RxAddress++;
+
+ /* Retrieve Rx payload */
+ pData = (uint8_t *)RxAddress;
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+ {
+ pRxData[ByteCounter] = pData[ByteCounter];
+ }
+
+ if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ {
+ /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+ hfdcan->Instance->RXF0A = GetIndex;
+ }
+ else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+ {
+ /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+ hfdcan->Instance->RXF1A = GetIndex;
+ }
+ else /* Rx element is assigned to a dedicated Rx buffer */
+ {
+ /* Clear the New Data flag of the current Rx buffer */
+ if (RxLocation < FDCAN_RX_BUFFER32)
+ {
+ hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+ }
+ else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+ {
+ hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
+{
+ uint32_t *TxEventAddress;
+ uint32_t GetIndex;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U));
+
+ if (state == HAL_FDCAN_STATE_BUSY)
+ {
+ /* Check that the Tx Event FIFO has an allocated area into the RAM */
+ if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+
+ /* Check that the Tx event FIFO is not empty */
+ if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+
+ return HAL_ERROR;
+ }
+
+ /* Calculate Tx event FIFO element address */
+ GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
+ TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U));
+
+ /* Retrieve IdType */
+ pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
+
+ /* Retrieve Identifier */
+ if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+ {
+ pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+ }
+ else /* Extended ID element */
+ {
+ pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
+ }
+
+ /* Retrieve TxFrameType */
+ pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
+
+ /* Retrieve ErrorStateIndicator */
+ pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
+
+ /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
+ TxEventAddress++;
+
+ /* Retrieve TxTimestamp */
+ pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
+
+ /* Retrieve DataLength */
+ pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+
+ /* Retrieve BitRateSwitch */
+ pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
+
+ /* Retrieve FDFormat */
+ pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
+
+ /* Retrieve EventType */
+ pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
+
+ /* Retrieve MessageMarker */
+ pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+
+ /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
+ hfdcan->Instance->TXEFA = GetIndex;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get high priority message status.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+{
+ HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
+ HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
+ HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
+ HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Get protocol status.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+{
+ uint32_t StatusReg;
+
+ /* Read the protocol status register */
+ StatusReg = READ_REG(hfdcan->Instance->PSR);
+
+ /* Fill the protocol status structure */
+ ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
+ ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
+ ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
+ ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
+ ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
+ ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
+ ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
+ ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
+ ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
+ ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
+ ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Get error counter values.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+{
+ uint32_t CountersReg;
+
+ /* Read the error counters register */
+ CountersReg = READ_REG(hfdcan->Instance->ECR);
+
+ /* Fill the error counters structure */
+ ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
+ ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
+ ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
+ ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Check if a new message is received in the selected Rx buffer.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxBufferIndex Rx buffer index.
+ * This parameter must be a number between 0 and 63.
+ * @retval Status
+ * - 0 : No new message on RxBufferIndex.
+ * - 1 : New message received on RxBufferIndex.
+ */
+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U));
+ uint32_t NewData1 = hfdcan->Instance->NDAT1;
+ uint32_t NewData2 = hfdcan->Instance->NDAT2;
+
+ /* Check new message reception on the selected buffer */
+ if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) ||
+ ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U)))
+ {
+ return 0;
+ }
+
+ /* Clear the New Data flag of the current Rx buffer */
+ if (RxBufferIndex < 32U)
+ {
+ hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex);
+ }
+ else /* 32 <= RxBufferIndex <= 63 */
+ {
+ hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU));
+ }
+
+ return 1;
+}
+
+/**
+ * @brief Check if a transmission request is pending on the selected Tx buffer.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TxBufferIndex Tx buffer index.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval Status
+ * - 0 : No pending transmission request on TxBufferIndex.
+ * - 1 : Pending transmission request on TxBufferIndex.
+ */
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+{
+ /* Check pending transmittion request on the selected buffer */
+ if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
+ {
+ return 0;
+ }
+ return 1;
+}
+
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be one of the following values:
+ * @arg FDCAN_RX_FIFO0: Rx FIFO 0
+ * @arg FDCAN_RX_FIFO1: Rx FIFO 1
+ * @retval Level Rx FIFO fill level.
+ */
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+{
+ uint32_t FillLevel;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_RX_FIFO(RxFifo));
+
+ if (RxFifo == FDCAN_RX_FIFO0)
+ {
+ FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
+ }
+ else /* RxFifo == FDCAN_RX_FIFO1 */
+ {
+ FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
+ }
+
+ /* Return Rx FIFO fill level */
+ return FillLevel;
+}
+
+/**
+ * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO
+ * elements starting from Tx FIFO GetIndex.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Level Tx FIFO free level.
+ */
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t FreeLevel;
+
+ FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
+
+ /* Return Tx FIFO free level */
+ return FreeLevel;
+}
+
+/**
+ * @brief Check if the FDCAN peripheral entered Restricted Operation Mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval Status
+ * - 0 : Normal FDCAN operation.
+ * - 1 : Restricted Operation Mode active.
+ */
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t OperationMode;
+
+ /* Get Operation Mode */
+ OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
+
+ return OperationMode;
+}
+
+/**
+ * @brief Exit Restricted Operation Mode.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Exit Restricted Operation mode */
+ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
+ * @brief TT Configuration and control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TT Configuration and control functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_TT_ConfigOperation : Initialize TT operation parameters
+ (+) HAL_FDCAN_TT_ConfigReferenceMessage : Configure the reference message
+ (+) HAL_FDCAN_TT_ConfigTrigger : Configure the FDCAN trigger
+ (+) HAL_FDCAN_TT_SetGlobalTime : Schedule global time adjustment
+ (+) HAL_FDCAN_TT_SetClockSynchronization : Schedule TUR numerator update
+ (+) HAL_FDCAN_TT_ConfigStopWatch : Configure stop watch source and polarity
+ (+) HAL_FDCAN_TT_ConfigRegisterTimeMark : Configure register time mark pulse generation
+ (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse : Enable register time mark pulse generation
+ (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse : Disable register time mark pulse generation
+ (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse : Enable trigger time mark pulse generation
+ (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse : Disable trigger time mark pulse generation
+ (+) HAL_FDCAN_TT_EnableHardwareGapControl : Enable gap control by input pin fdcan1_evt
+ (+) HAL_FDCAN_TT_DisableHardwareGapControl : Disable gap control by input pin fdcan1_evt
+ (+) HAL_FDCAN_TT_EnableTimeMarkGapControl : Enable gap control (finish only) by register time mark interrupt
+ (+) HAL_FDCAN_TT_DisableTimeMarkGapControl : Disable gap control by register time mark interrupt
+ (+) HAL_FDCAN_TT_SetNextIsGap : Transmit next reference message with Next_is_Gap = "1"
+ (+) HAL_FDCAN_TT_SetEndOfGap : Finish a Gap by requesting start of reference message
+ (+) HAL_FDCAN_TT_ConfigExternalSyncPhase : Configure target phase used for external synchronization
+ (+) HAL_FDCAN_TT_EnableExternalSynchronization : Synchronize the phase of the FDCAN schedule to an external schedule
+ (+) HAL_FDCAN_TT_DisableExternalSynchronization : Disable external schedule synchronization
+ (+) HAL_FDCAN_TT_GetOperationStatus : Get TT operation status
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize TT operation parameters.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
+{
+ uint32_t tickstart;
+ uint32_t RAMcounter;
+ uint32_t StartAddress;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator));
+ assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator));
+ assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster));
+ assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U));
+ assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U));
+ assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U));
+ assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync));
+ assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel));
+ assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel));
+ if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+ {
+ assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr));
+ }
+ if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable));
+ assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U));
+ assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity));
+ assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow));
+ assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U));
+ }
+ if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+ {
+ assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator));
+ assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync));
+ assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter));
+ assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration));
+ }
+ else
+ {
+ assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator));
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Stop local time in order to enable write access to the other bits of TURCF register */
+ CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the ELT bit into TURCF register is reset */
+ while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Configure TUR (Time Unit Ratio) */
+ MODIFY_REG(hfdcan->ttcan->TURCF,
+ (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
+ (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+
+ /* Enable local time */
+ SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
+
+ /* Configure TT operation */
+ MODIFY_REG(hfdcan->ttcan->TTOCF,
+ (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO),
+ (pTTParams->OperationMode | \
+ pTTParams->TimeMaster | \
+ (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \
+ (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos)));
+ if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ MODIFY_REG(hfdcan->ttcan->TTOCF,
+ (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP),
+ (pTTParams->GapEnable | \
+ (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \
+ pTTParams->EvtTrigPolarity));
+ }
+ if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1)
+ {
+ MODIFY_REG(hfdcan->ttcan->TTOCF,
+ (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC),
+ (pTTParams->ExternalClkSync | \
+ pTTParams->GlobalTimeFilter | \
+ pTTParams->ClockCalibration));
+ }
+
+ /* Configure system matrix limits */
+ MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync);
+ if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ MODIFY_REG(hfdcan->ttcan->TTMLM,
+ (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
+ (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+ }
+ if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
+ {
+ MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr);
+ }
+
+ /* Configure input triggers: Stop watch and Event */
+ MODIFY_REG(hfdcan->ttcan->TTTS,
+ (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL),
+ (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel));
+
+ /* Configure trigger memory start address */
+ StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U;
+ MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos));
+
+ /* Trigger memory elements number */
+ MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos));
+
+ /* Recalculate End Address */
+ hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress;
+ hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U);
+
+ if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+ {
+ /* Update error code.
+ Message RAM overflow */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Flush the allocated Message RAM area */
+ for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+ {
+ *(uint32_t *)(RAMcounter) = 0x00000000;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the reference message.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param IdType Identifier Type.
+ * This parameter can be a value of @arg FDCAN_id_type.
+ * @param Identifier Reference Identifier.
+ * This parameter must be a number between:
+ * - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
+ * - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID
+ * @param Payload Enable or disable the additional payload.
+ * This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload.
+ * This parameter is ignored in case of time slaves.
+ * If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the
+ * following elements are taken from Tx Buffer 0:
+ * - MessageMarker
+ * - TxEventFifoControl
+ * - DataLength
+ * - Data Bytes (payload):
+ * - bytes 2-8, for Level 1
+ * - bytes 5-8, for Level 0 and Level 2
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
+{
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_ID_TYPE(IdType));
+ if (IdType == FDCAN_STANDARD_ID)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU));
+ }
+ else /* IdType == FDCAN_EXTENDED_ID */
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU));
+ }
+ assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload));
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Configure reference message identifier type, identifier and payload */
+ if (IdType == FDCAN_EXTENDED_ID)
+ {
+ MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
+ }
+ else /* IdType == FDCAN_STANDARD_ID */
+ {
+ MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure the FDCAN trigger according to the specified
+ * parameters in the FDCAN_TriggerTypeDef structure.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that
+ * contains the trigger configuration information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
+{
+ uint32_t CycleCode;
+ uint32_t MessageNumber;
+ uint32_t TriggerElementW1;
+ uint32_t TriggerElementW2;
+ uint32_t *TriggerAddress;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U));
+ assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU));
+ assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor));
+ if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U)));
+ }
+ assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt));
+ assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt));
+ assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType));
+ assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType));
+ if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+ (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+ (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+ (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+ {
+ assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex));
+ }
+ if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+ {
+ if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U));
+ }
+ else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U));
+ }
+ }
+
+ if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ {
+ /* Calculate cycle code */
+ if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+ {
+ CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+ }
+ else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+ {
+ CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle;
+ }
+
+ /* Build first word of trigger element */
+ TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \
+ (CycleCode << 8) | \
+ sTriggerConfig->TmEventInt | \
+ sTriggerConfig->TmEventExt | \
+ sTriggerConfig->TriggerType);
+
+ /* Select message number depending on trigger type (transmission or reception) */
+ if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER)
+ {
+ MessageNumber = sTriggerConfig->FilterIndex;
+ }
+ else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) ||
+ (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) ||
+ (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) ||
+ (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED))
+ {
+ MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex);
+ }
+ else
+ {
+ MessageNumber = 0U;
+ }
+
+ /* Build second word of trigger element */
+ TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16));
+
+ /* Calculate trigger address */
+ TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U));
+
+ /* Write trigger element to the message RAM */
+ *TriggerAddress = TriggerElementW1;
+ TriggerAddress++;
+ *TriggerAddress = TriggerElementW2;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Schedule global time adjustment for the next reference message.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimePreset time preset value.
+ * This parameter must be a number between:
+ * - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset
+ * or
+ * - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check that the external clock synchronization is enabled */
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ /* Check that no global time preset is pending */
+ if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+ return HAL_ERROR;
+ }
+
+ /* Configure time preset */
+ MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos));
+
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Schedule time preset to take effect by the next reference message */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Schedule TUR numerator update for the next reference message.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param NewTURNumerator new value of the TUR numerator.
+ * This parameter must be a number between 0x10000 and 0x1FFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check that the external clock synchronization is enabled */
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ /* Check that no external clock synchronization is pending */
+ if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+ return HAL_ERROR;
+ }
+
+ /* Configure new TUR numerator */
+ MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U));
+
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Schedule TUR numerator update by the next reference message */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure stop watch source and polarity.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param Source stop watch source.
+ * This parameter can be a value of @arg FDCAN_TT_stop_watch_source.
+ * @param Polarity stop watch polarity.
+ * This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source));
+ assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Select stop watch source and polarity */
+ MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure register time mark pulse generation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TimeMarkSource time mark source.
+ * This parameter can be a value of @arg FDCAN_TT_time_mark_source.
+ * @param TimeMarkValue time mark value (reference).
+ * This parameter must be a number between 0 and 0xFFFF.
+ * @param RepeatFactor repeat factor of the cycle for which the time mark is valid.
+ * This parameter can be a value of @arg FDCAN_TT_Repeat_Factor.
+ * @param StartCycle index of the first cycle in which the time mark becomes valid.
+ * This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
+ * This parameter must be a number between 0 and RepeatFactor.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan,
+ uint32_t TimeMarkSource, uint32_t TimeMarkValue,
+ uint32_t RepeatFactor, uint32_t StartCycle)
+{
+ uint32_t Counter = 0U;
+ uint32_t CycleCode;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource));
+ assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU));
+ assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor));
+ if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE)
+ {
+ assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U)));
+ }
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Disable the time mark compare function */
+ CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC);
+
+ if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED)
+ {
+ /* Calculate cycle code */
+ if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE)
+ {
+ CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE;
+ }
+ else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */
+ {
+ CycleCode = RepeatFactor + StartCycle;
+ }
+
+ Counter = 0U;
+
+ /* Wait until the LCKM bit into TTTMK register is reset */
+ while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Configure time mark value and cycle code */
+ hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos));
+
+ Counter = 0U;
+
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Update the register time mark compare source */
+ MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable register time mark pulse generation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable Register Time Mark Interrupt output on fdcan1_rtp */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable register time mark pulse generation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Disable Register Time Mark Interrupt output on fdcan1_rtp */
+ CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable trigger time mark pulse generation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable trigger time mark pulse generation.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */
+ CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable gap control by input pin fdcan1_evt.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable gap control by pin fdcan1_evt */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable gap control by input pin fdcan1_evt.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Disable gap control by pin fdcan1_evt */
+ CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable gap control (finish only) by register time mark interrupt.
+ * The next register time mark interrupt (TTIR.RTMI = "1") will finish
+ * the Gap and start the reference message.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable gap control by register time mark interrupt */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable gap control by register time mark interrupt.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Disable gap control by register time mark interrupt */
+ CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Transmit next reference message with Next_is_Gap = "1".
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check that the node is configured for external event-synchronized TT operation */
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Set Next is Gap */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Finish a Gap by requesting start of reference message.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check that the node is configured for external event-synchronized TT operation */
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0)
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Set Finish Gap */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code.
+ Feature not supported for TT Level 0 */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configure target phase used for external synchronization by event
+ * trigger input pin fdcan1_evt.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TargetPhase defines target value of cycle time when a rising edge
+ * of fdcan1_evt is expected.
+ * This parameter must be a number between 0 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Check that no external schedule synchronization is pending */
+ if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING;
+
+ return HAL_ERROR;
+ }
+
+ /* Configure cycle time target phase */
+ MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos));
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Synchronize the phase of the FDCAN schedule to an external schedule
+ * using event trigger input pin fdcan1_evt.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Enable external synchronization */
+ SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable external schedule synchronization.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t Counter = 0U;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Wait until the LCKC bit into TTOCN register is reset */
+ while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U)
+ {
+ /* Check for the Timeout */
+ if (Counter > FDCAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+
+ /* Increment counter */
+ Counter++;
+ }
+
+ /* Disable external synchronization */
+ CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Get TT operation status.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+{
+ uint32_t TTStatusReg;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+
+ /* Read the TT operation status register */
+ TTStatusReg = READ_REG(hfdcan->ttcan->TTOST);
+
+ /* Fill the TT operation status structure */
+ TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL);
+ TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS);
+ TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS);
+ TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos);
+ TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos);
+ TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos);
+ TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos);
+ TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos);
+ TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos);
+ TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos);
+ TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos);
+ TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos);
+ TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos);
+ TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1
+ (+) HAL_FDCAN_TT_ConfigInterruptLines : Assign TT interrupts to either Interrupt line 0 or 1
+ (+) HAL_FDCAN_ActivateNotification : Enable interrupts
+ (+) HAL_FDCAN_DeactivateNotification : Disable interrupts
+ (+) HAL_FDCAN_TT_ActivateNotification : Enable TT interrupts
+ (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts
+ (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Assign interrupts to either Interrupt line 0 or 1.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ITList indicates which interrupts will be assigned to the selected interrupt line.
+ * This parameter can be any combination of @arg FDCAN_Interrupts.
+ * @param InterruptLine Interrupt line.
+ * This parameter can be a value of @arg FDCAN_Interrupt_Line.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT(ITList));
+ assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Assign list of interrupts to the selected line */
+ if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+ {
+ CLEAR_BIT(hfdcan->Instance->ILS, ITList);
+ }
+ else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+ {
+ SET_BIT(hfdcan->Instance->ILS, ITList);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Assign TT interrupts to either Interrupt line 0 or 1.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TTITList indicates which interrupts will be assigned to the selected interrupt line.
+ * This parameter can be any combination of @arg FDCAN_TTInterrupts.
+ * @param InterruptLine Interrupt line.
+ * This parameter can be a value of @arg FDCAN_Interrupt_Line.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_IT(TTITList));
+ assert_param(IS_FDCAN_IT_LINE(InterruptLine));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Assign list of interrupts to the selected line */
+ if (InterruptLine == FDCAN_INTERRUPT_LINE0)
+ {
+ CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList);
+ }
+ else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
+ {
+ SET_BIT(hfdcan->ttcan->TTILS, TTITList);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg FDCAN_Interrupts.
+ * @param BufferIndexes Tx Buffer Indexes.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * This parameter is ignored if ActiveITs does not include one of the following:
+ * - FDCAN_IT_TX_COMPLETE
+ * - FDCAN_IT_TX_ABORT_COMPLETE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT(ActiveITs));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Enable Interrupt lines */
+ if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+ {
+ /* Enable Interrupt line 0 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+ else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+ {
+ /* Enable Interrupt line 1 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+ else
+ {
+ /* Enable Interrupt lines 0 and 1 */
+ hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+ }
+
+ if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+ {
+ /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+ but interrupt will only occure if TC is enabled in IE register */
+ SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+ }
+
+ if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ {
+ /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+ but interrupt will only occure if TCF is enabled in IE register */
+ SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+ }
+
+ /* Enable the selected interrupts */
+ __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg FDCAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
+{
+ uint32_t ITLineSelection;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_IT(InactiveITs));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Disable the selected interrupts */
+ __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
+
+ if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+ {
+ /* Disable Tx Buffer Transmission Interrupts */
+ CLEAR_REG(hfdcan->Instance->TXBTIE);
+ }
+
+ if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ {
+ /* Disable Tx Buffer Cancellation Finished Interrupt */
+ CLEAR_REG(hfdcan->Instance->TXBCIE);
+ }
+
+ ITLineSelection = hfdcan->Instance->ILS;
+
+ if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection)
+ {
+ /* Disable Interrupt line 0 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+
+ if ((hfdcan->Instance->IE & ITLineSelection) == 0U)
+ {
+ /* Disable Interrupt line 1 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Enable TT interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ActiveTTITs indicates which TT interrupts will be enabled.
+ * This parameter can be any combination of @arg FDCAN_TTInterrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs)
+{
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_IT(ActiveTTITs));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Enable Interrupt lines */
+ if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U)
+ {
+ /* Enable Interrupt line 0 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+ else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs)
+ {
+ /* Enable Interrupt line 1 */
+ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+ else
+ {
+ /* Enable Interrupt lines 0 and 1 */
+ hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+ }
+
+ /* Enable the selected TT interrupts */
+ __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable TT interrupts.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param InactiveTTITs indicates which TT interrupts will be disabled.
+ * This parameter can be any combination of @arg FDCAN_TTInterrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs)
+{
+ uint32_t ITLineSelection;
+ HAL_FDCAN_StateTypeDef state = hfdcan->State;
+
+ /* Check function parameters */
+ assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
+ assert_param(IS_FDCAN_TT_IT(InactiveTTITs));
+
+ if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ {
+ /* Disable the selected TT interrupts */
+ __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs);
+
+ ITLineSelection = hfdcan->ttcan->TTILS;
+
+ if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection)
+ {
+ /* Disable Interrupt line 0 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ }
+
+ if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
+ {
+ /* Disable Interrupt line 1 */
+ CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles FDCAN interrupt request.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t ClkCalibrationITs;
+ uint32_t TxEventFifoITs;
+ uint32_t RxFifo0ITs;
+ uint32_t RxFifo1ITs;
+ uint32_t Errors;
+ uint32_t ErrorStatusITs;
+ uint32_t TransmittedBuffers;
+ uint32_t AbortedBuffers;
+ uint32_t TTSchedSyncITs;
+ uint32_t TTTimeMarkITs;
+ uint32_t TTGlobTimeITs;
+ uint32_t TTDistErrors;
+ uint32_t TTFatalErrors;
+ uint32_t SWTime;
+ uint32_t SWCycleCount;
+
+ ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+ ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+ TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+ TxEventFifoITs &= hfdcan->Instance->IE;
+ RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+ RxFifo0ITs &= hfdcan->Instance->IE;
+ RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+ RxFifo1ITs &= hfdcan->Instance->IE;
+ Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+ Errors &= hfdcan->Instance->IE;
+ ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+ ErrorStatusITs &= hfdcan->Instance->IE;
+
+ /* High Priority Message interrupt management *******************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+ {
+ /* Clear the High Priority Message flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+
+ /* High Priority Message Callback */
+ HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+ }
+ }
+
+ /* Transmission Abort interrupt management **********************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+ {
+ /* List of aborted monitored buffers */
+ AbortedBuffers = hfdcan->Instance->TXBCF;
+ AbortedBuffers &= hfdcan->Instance->TXBCIE;
+
+ /* Clear the Transmission Cancellation flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+
+ /* Transmission Cancellation Callback */
+ HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+ }
+ }
+
+ /* Clock calibration unit interrupts management *****************************/
+ if (ClkCalibrationITs != 0U)
+ {
+ /* Clear the Clock Calibration flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+
+ /* Clock Calibration Callback */
+ HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+ }
+
+ /* Tx event FIFO interrupts management **************************************/
+ if (TxEventFifoITs != 0U)
+ {
+ /* Clear the Tx Event FIFO flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+
+ /* Tx Event FIFO Callback */
+ HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+ }
+
+ /* Rx FIFO 0 interrupts management ******************************************/
+ if (RxFifo0ITs != 0U)
+ {
+ /* Clear the Rx FIFO 0 flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+
+ /* Rx FIFO 0 Callback */
+ HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+ }
+
+ /* Rx FIFO 1 interrupts management ******************************************/
+ if (RxFifo1ITs != 0U)
+ {
+ /* Clear the Rx FIFO 1 flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+
+ /* Rx FIFO 1 Callback */
+ HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+ }
+
+ /* Tx FIFO empty interrupt management ***************************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+ {
+ /* Clear the Tx FIFO empty flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+
+ /* Tx FIFO empty Callback */
+ HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+ }
+ }
+
+ /* Transmission Complete interrupt management *******************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+ {
+ /* List of transmitted monitored buffers */
+ TransmittedBuffers = hfdcan->Instance->TXBTO;
+ TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+
+ /* Clear the Transmission Complete flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+
+ /* Transmission Complete Callback */
+ HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+ }
+ }
+
+ /* Rx Buffer New Message interrupt management *******************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
+ {
+ /* Clear the Rx Buffer New Message flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+
+ /* Rx Buffer New Message Callback */
+ HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+ }
+ }
+
+ /* Timestamp Wraparound interrupt management ********************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+ {
+ /* Clear the Timestamp Wraparound flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+
+ /* Timestamp Wraparound Callback */
+ HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+ }
+ }
+
+ /* Timeout Occurred interrupt management ************************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+ {
+ /* Clear the Timeout Occurred flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+
+ /* Timeout Occurred Callback */
+ HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+ }
+ }
+
+ /* Message RAM access failure interrupt management **************************/
+ if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+ {
+ if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+ {
+ /* Clear the Message RAM access failure flag */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+ }
+ }
+
+ /* Error Status interrupts management ***************************************/
+ if (ErrorStatusITs != 0U)
+ {
+ /* Clear the Error flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+
+ /* Error Status Callback */
+ HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+ }
+
+ /* Error interrupts management **********************************************/
+ if (Errors != 0U)
+ {
+ /* Clear the Error flags */
+ __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= Errors;
+ }
+
+ if (hfdcan->Instance == FDCAN1)
+ {
+ if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+ {
+ TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+ TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+ TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+ TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+ TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+ TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+ TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+ TTDistErrors &= hfdcan->ttcan->TTIE;
+ TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+ TTFatalErrors &= hfdcan->ttcan->TTIE;
+
+ /* TT Schedule Synchronization interrupts management **********************/
+ if (TTSchedSyncITs != 0U)
+ {
+ /* Clear the TT Schedule Synchronization flags */
+ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+
+ /* TT Schedule Synchronization Callback */
+ HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+ }
+
+ /* TT Time Mark interrupts management *************************************/
+ if (TTTimeMarkITs != 0U)
+ {
+ /* Clear the TT Time Mark flags */
+ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+
+ /* TT Time Mark Callback */
+ HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+ }
+
+ /* TT Stop Watch interrupt management *************************************/
+ if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
+ {
+ if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
+ {
+ /* Retrieve Stop watch Time and Cycle count */
+ SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+ SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+
+ /* Clear the TT Stop Watch flag */
+ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+
+ /* TT Stop Watch Callback */
+ HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+ }
+ }
+
+ /* TT Global Time interrupts management ***********************************/
+ if (TTGlobTimeITs != 0U)
+ {
+ /* Clear the TT Global Time flags */
+ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+
+ /* TT Global Time Callback */
+ HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+ }
+
+ /* TT Disturbing Error interrupts management ******************************/
+ if (TTDistErrors != 0U)
+ {
+ /* Clear the TT Disturbing Error flags */
+ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= TTDistErrors;
+ }
+
+ /* TT Fatal Error interrupts management ***********************************/
+ if (TTFatalErrors != 0U)
+ {
+ /* Clear the TT Fatal Error flags */
+ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+
+ /* Update error code */
+ hfdcan->ErrorCode |= TTFatalErrors;
+ }
+ }
+ }
+
+ if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+ {
+ /* Error Callback */
+ HAL_FDCAN_ErrorCallback(hfdcan);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
+ * @brief FDCAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_FDCAN_ClockCalibrationCallback
+ (+) HAL_FDCAN_TxEventFifoCallback
+ (+) HAL_FDCAN_RxFifo0Callback
+ (+) HAL_FDCAN_RxFifo1Callback
+ (+) HAL_FDCAN_TxFifoEmptyCallback
+ (+) HAL_FDCAN_TxBufferCompleteCallback
+ (+) HAL_FDCAN_TxBufferAbortCallback
+ (+) HAL_FDCAN_RxBufferNewMessageCallback
+ (+) HAL_FDCAN_HighPriorityMessageCallback
+ (+) HAL_FDCAN_TimestampWraparoundCallback
+ (+) HAL_FDCAN_TimeoutOccurredCallback
+ (+) HAL_FDCAN_ErrorCallback
+ (+) HAL_FDCAN_ErrorStatusCallback
+ (+) HAL_FDCAN_TT_ScheduleSyncCallback
+ (+) HAL_FDCAN_TT_TimeMarkCallback
+ (+) HAL_FDCAN_TT_StopWatchCallback
+ (+) HAL_FDCAN_TT_GlobalTimeCallback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Clock Calibration callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(ClkCalibrationITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Event callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(TxEventFifoITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(RxFifo0ITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(RxFifo1ITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx FIFO Empty callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission Complete callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndexes Indexes of the transmitted buffers.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(BufferIndexes);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission Cancellation callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param BufferIndexes Indexes of the aborted buffers.
+ * This parameter can be any combination of @arg FDCAN_Tx_location.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(BufferIndexes);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Buffer New Message callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timestamp Wraparound callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timeout Occurred callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief High Priority Message callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval None
+ */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error status callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param ErrorStatusITs indicates which Error Status interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(ErrorStatusITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TT Schedule Synchronization callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(TTSchedSyncITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TT Time Mark callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(TTTimeMarkITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TT Stop Watch callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising
+ * edge (as configured via HAL_FDCAN_TTConfigStopWatch).
+ * This parameter is a number between 0 and 0xFFFF.
+ * @param SWCycleCount Cycle count value captured together with SWTime.
+ * This parameter is a number between 0 and 0x3F.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(SWTime);
+ UNUSED(SWCycleCount);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief TT Global Time callback.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+ * This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+ * @retval None
+ */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hfdcan);
+ UNUSED(TTGlobTimeITs);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
+ * @brief FDCAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) HAL_FDCAN_GetState() : Return the FDCAN state.
+ (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Return the FDCAN state
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL state
+ */
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Return FDCAN state */
+ return hfdcan->State;
+}
+
+/**
+ * @brief Return the FDCAN error code
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval FDCAN Error Code
+ */
+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+{
+ /* Return FDCAN error code */
+ return hfdcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FDCAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate each RAM block start address and size
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+ uint32_t RAMcounter;
+ uint32_t StartAddress;
+
+ StartAddress = hfdcan->Init.MessageRAMOffset;
+
+ /* Standard filter list start address */
+ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+
+ /* Standard filter elements number */
+ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+
+ /* Extended filter list start address */
+ StartAddress += hfdcan->Init.StdFiltersNbr;
+ MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+
+ /* Extended filter elements number */
+ MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+
+ /* Rx FIFO 0 start address */
+ StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+
+ /* Rx FIFO 0 elements number */
+ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+
+ /* Rx FIFO 1 start address */
+ StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+
+ /* Rx FIFO 1 elements number */
+ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+
+ /* Rx buffer list start address */
+ StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+ MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+
+ /* Tx event FIFO start address */
+ StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+ MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+
+ /* Tx event FIFO elements number */
+ MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+
+ /* Tx buffer list start address */
+ StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+
+ /* Dedicated Tx buffers number */
+ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+
+ /* Tx FIFO/queue elements number */
+ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+
+ hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+ hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+ hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+ hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+ hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+ hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+ hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+ hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+
+ hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+
+ if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+ {
+ /* Update error code.
+ Message RAM overflow */
+ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+
+ /* Change FDCAN state */
+ hfdcan->State = HAL_FDCAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Flush the allocated Message RAM area */
+ for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+ {
+ *(uint32_t *)(RAMcounter) = 0x00000000;
+ }
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Copy Tx message to the message RAM.
+ * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+ * the configuration information for the specified FDCAN.
+ * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
+ * @param pTxData pointer to a buffer containing the payload of the Tx frame.
+ * @param BufferIndex index of the buffer to be configured.
+ * @retval HAL status
+ */
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+{
+ uint32_t TxElementW1;
+ uint32_t TxElementW2;
+ uint32_t *TxAddress;
+ uint32_t ByteCounter;
+
+ /* Build first word of Tx header element */
+ if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+ {
+ TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ FDCAN_STANDARD_ID |
+ pTxHeader->TxFrameType |
+ (pTxHeader->Identifier << 18));
+ }
+ else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+ {
+ TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ FDCAN_EXTENDED_ID |
+ pTxHeader->TxFrameType |
+ pTxHeader->Identifier);
+ }
+
+ /* Build second word of Tx header element */
+ TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+ pTxHeader->TxEventFifoControl |
+ pTxHeader->FDFormat |
+ pTxHeader->BitRateSwitch |
+ pTxHeader->DataLength);
+
+ /* Calculate Tx element address */
+ TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+
+ /* Write Tx element header to the message RAM */
+ *TxAddress = TxElementW1;
+ TxAddress++;
+ *TxAddress = TxElementW2;
+ TxAddress++;
+
+ /* Write Tx payload to the message RAM */
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+ {
+ *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
+ ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
+ ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+ (uint32_t)pTxData[ByteCounter]);
+ TxAddress++;
+ }
+}
+
+/**
+ * @}
+ */
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FDCAN1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c
new file mode 100644
index 0000000..8d4649b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c
@@ -0,0 +1,565 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_gpio.c
+ * @author MCD Application Team
+ * @brief GPIO HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the General Purpose Input/Output (GPIO) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### GPIO Peripheral features #####
+ ==============================================================================
+ [..]
+ Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+ port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+ in several modes:
+ (+) Input mode
+ (+) Analog mode
+ (+) Output mode
+ (+) Alternate function mode
+ (+) External interrupt/event lines
+
+ [..]
+ During and just after reset, the alternate functions and external interrupt
+ lines are not active and the I/O ports are configured in input floating mode.
+
+ (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+ activated or not.
+
+ [..]
+ In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+ type and the IO speed can be selected depending on the VDD value.
+
+ [..]
+ All ports have external interrupt/event capability. To use external interrupt
+ lines, the port must be configured in input mode. All available GPIO pins are
+ connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+ [..]
+ The external interrupt/event controller consists of up to 23 edge detectors
+ (16 lines are connected to GPIO) for generating event/interrupt requests (each
+ input line can be independently configured to select the type (interrupt or event)
+ and the corresponding trigger event (rising or falling or both). Each line can
+ also be masked independently.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+ (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+ (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+ (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+ structure.
+ (++) In case of Output or alternate function mode selection: the speed is
+ configured through "Speed" member from GPIO_InitTypeDef structure.
+ (++) In alternate mode is selection, the alternate function connected to the IO
+ is configured through "Alternate" member from GPIO_InitTypeDef structure.
+ (++) Analog mode is required when a pin is to be used as ADC channel
+ or DAC output.
+ (++) In case of external interrupt/event selection the "Mode" member from
+ GPIO_InitTypeDef structure select the type (interrupt or event) and
+ the corresponding trigger event (rising or falling or both).
+
+ (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+ HAL_NVIC_EnableIRQ().
+
+ (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+ (#) To set/reset the level of a pin configured in output mode use
+ HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+ (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+
+ (#) During and just after reset, the alternate functions are not
+ active and the GPIO pins are configured in input floating mode (except JTAG
+ pins).
+
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+ (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ priority over the GPIO function.
+
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+ general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+ The HSE has priority over the GPIO function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup GPIO GPIO
+ * @brief GPIO HAL module driver
+ * @{
+ */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+#define GPIO_MODE ((uint32_t)0x00000003)
+#define EXTI_MODE ((uint32_t)0x10000000)
+#define GPIO_MODE_IT ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT ((uint32_t)0x00020000)
+#define RISING_EDGE ((uint32_t)0x00100000)
+#define FALLING_EDGE ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+
+#define GPIO_NUMBER ((uint32_t)16)
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to initialize and de-initialize the GPIOs
+ to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
+ * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ uint32_t position;
+ uint32_t ioposition;
+ uint32_t iocurrent;
+ uint32_t temp;
+ EXTI_Core_TypeDef * EXTI_CurrentCPU;
+
+#if defined(CORE_CM4)
+ EXTI_CurrentCPU = EXTI_C2; /* EXTI for CM4 CPU */
+#else
+ EXTI_CurrentCPU = EXTI_C1; /* EXTI for CA7 CPU */
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+ /* Configure the port pins */
+ for(position = 0; position < GPIO_NUMBER; position++)
+ {
+ /* Get the IO position */
+ ioposition = ((uint32_t)0x01) << position;
+ /* Get the current IO position */
+ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+ if(iocurrent == ioposition)
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Alternate function parameter */
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3];
+ temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ GPIOx->AFR[position >> 3] = temp;
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ GPIOx->MODER = temp;
+
+ /* In case of Output or Alternate function mode selection */
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDR_OSPEEDR0 << (position * 2));
+ temp |= (GPIO_Init->Speed << (position * 2));
+ GPIOx->OSPEEDR = temp;
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ temp &= ~(GPIO_OTYPER_OT0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ GPIOx->OTYPER = temp;
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ temp |= ((GPIO_Init->Pull) << (position * 2));
+ GPIOx->PUPDR = temp;
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ {
+ temp = EXTI->EXTICR[position >> 2U];
+ temp &= ~(0xFFU << (8U * (position & 0x03U)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)));
+ EXTI->EXTICR[position >> 2U] = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI_CurrentCPU->IMR1;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI_CurrentCPU->IMR1 = temp;
+
+ temp = EXTI_CurrentCPU->EMR1;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ {
+ temp |= iocurrent;
+ }
+ EXTI_CurrentCPU->EMR1 = temp;
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR1;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->RTSR1 = temp;
+
+ temp = EXTI->FTSR1;
+ temp &= ~((uint32_t)iocurrent);
+ if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->FTSR1 = temp;
+ }
+ }
+ }
+}
+
+/**
+ * @brief De-initializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..Z) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
+{
+ uint32_t position;
+ uint32_t ioposition;
+ uint32_t iocurrent;
+ uint32_t tmp;
+ EXTI_Core_TypeDef * EXTI_CurrentCPU;
+
+#if defined(CORE_CM4)
+ EXTI_CurrentCPU = EXTI_C2; /* EXTI for CM4 CPU */
+#else
+ EXTI_CurrentCPU = EXTI_C1; /* EXTI for CA7 CPU */
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Configure the port pins */
+ for(position = 0; position < GPIO_NUMBER; position++)
+ {
+ /* Get the IO position */
+ ioposition = ((uint32_t)0x01) << position;
+ /* Get the current IO position */
+ iocurrent = (GPIO_Pin) & ioposition;
+
+ if(iocurrent == ioposition)
+ {
+ /*------------------------- EXTI Mode Configuration --------------------*/
+ tmp = EXTI->EXTICR[position >> 2];
+ tmp &= (((uint32_t)0xFF) << (8 * (position & 0x03)));
+ if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (8 * (position & 0x03))))
+ {
+ /* Clear EXTI line configuration for Current CPU */
+ EXTI_CurrentCPU->IMR1 &= ~((uint32_t)iocurrent);
+ EXTI_CurrentCPU->EMR1 &= ~((uint32_t)iocurrent);
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR1 &= ~((uint32_t)iocurrent);
+ EXTI->FTSR1 &= ~((uint32_t)iocurrent);
+
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = ((uint32_t)0xFF) << (8 * (position & 0x03));
+ EXTI->EXTICR[position >> 2] &= ~tmp;
+ }
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO in Analog Mode */
+ GPIOx->MODER |= (GPIO_MODER_MODER0 << (position * 2));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR0 << (position * 2));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
+ * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_PIN_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ GPIO_PinState bitstatus;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+ {
+ bitstatus = GPIO_PIN_SET;
+ }
+ else
+ {
+ bitstatus = GPIO_PIN_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ *
+ * @note This function uses GPIOx_BSRR register to allow atomic read/modify
+ * accesses. In this way, there is no risk of an IRQ occurring between
+ * the read and the modify access.
+ *
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_PIN_x where x can be (0..15).
+ * @param PinState: specifies the value to be written to the selected bit.
+ * This parameter can be one of the GPIO_PinState enum values:
+ * @arg GPIO_PIN_RESET: to clear the port pin
+ * @arg GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if (PinState != GPIO_PIN_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+ }
+}
+
+/**
+ * @brief Toggles the specified GPIO pins.
+ * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.
+ * @param GPIO_Pin: Specifies the pins to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
+ {
+ GPIOx->BRR = (uint32_t)GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A..K) to select the GPIO peripheral
+ * @param GPIO_Pin: specifies the port bit to be locked.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ /* Apply lock key write sequence */
+ tmp |= GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK register. This read is mandatory to complete key lock sequence */
+ tmp = GPIOx->LCKR;
+
+ /* Read again in order to confirm lock is active */
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ {
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+ /* EXTI line interrupt detected */
+ if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
+ }
+
+ if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != RESET)
+ {
+ __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
+ HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
+ }
+}
+
+/**
+ * @brief EXTI line detection callback.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief EXTI line detection callback.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
+ * @retval None
+ */
+__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(GPIO_Pin);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c
new file mode 100644
index 0000000..f560644
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_hsem.c
@@ -0,0 +1,437 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_hsem.c
+ * @author MCD Application Team
+ * @brief HSEM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the semaphore peripheral:
+ * + Semaphore Take function (2-Step Procedure) , non blocking
+ * + Semaphore FastTake function (1-Step Procedure) , non blocking
+ * + Semaphore Status check
+ * + Semaphore Clear Key Set and Get
+ * + Release and release all functions
+ * + Semaphore notification enabling and disabling and callnack functions
+ * + IRQ handler management
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
+ (++) the semaphore ID from 0 to 31
+ (++) the process ID from 0 to 255
+ (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
+ (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
+ (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
+ (++) the semaphore ID from 0_ID to 31
+ (++) It returns 1 if the given semaphore is taken otherwise (Free) zero
+ (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
+ (++) the semaphore ID from 0 to 31
+ (++) the process ID from 0 to 255:
+ (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
+ may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
+ semaphore remains taken (locked)
+
+ (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
+ This function takes as parameters :
+ (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
+ HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
+ (++) the Master ID:
+ (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
+ to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the
+ Key or the MasterID doesn't match, semaphores remains taken (locked)
+
+ (#)Semaphores Release all key functions:
+ (++) HAL_HSEM_SetClearKey() to set semaphore release all Key
+ (++) HAL_HSEM_GetClearKey() to get release all Key
+ (#)Semaphores notification functions :
+ (++) HAL_HSEM_ActivateNotification to activate a notification callback on
+ a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
+ the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
+ semaphores (bitfield).
+
+ (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
+ (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
+ Used by the notification functions
+ *** HSEM HAL driver macros list ***
+ =============================================
+ [..] Below the list of most used macros in HSEM HAL driver.
+
+ (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
+ [..] Example of use :
+ [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
+ [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.
+ (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
+ (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
+ (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
+ (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
+ (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HSEM HSEM
+ * @brief HSEM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#if defined(DUAL_CORE)
+#ifndef HSEM_R_MASTERID
+#define HSEM_R_MASTERID HSEM_R_COREID
+#endif
+
+#ifndef HSEM_RLR_MASTERID
+#define HSEM_RLR_MASTERID HSEM_RLR_COREID
+#endif
+
+#ifndef HSEM_CR_MASTERID
+#define HSEM_CR_MASTERID HSEM_CR_COREID
+#endif
+#endif /* DUAL_CORE */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
+ * @{
+ */
+
+/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
+ * @brief HSEM Take and Release functions
+ *
+@verbatim
+ ==============================================================================
+ ##### HSEM Take and Release functions #####
+ ==============================================================================
+[..] This section provides functions allowing to:
+ (+) Take a semaphore with 2 Step method
+ (+) Fast Take a semaphore with 1 Step method
+ (+) Check semaphore state Taken or not
+ (+) Release a semaphore
+ (+) Release all semaphore at once
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Take a semaphore in 2 Step mode.
+ * @param SemID: semaphore ID from 0 to 31
+ * @param ProcessID: Process ID from 0 to 255
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
+{
+ /* Check the parameters */
+ assert_param(IS_HSEM_SEMID(SemID));
+ assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+#if USE_MULTI_CORE_SHARED_CODE != 0U
+ /* First step write R register with MasterID, processID and take bit=1*/
+ HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
+
+ /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+ if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
+ {
+ /*take success when MasterID and ProcessID match and take bit set*/
+ return HAL_OK;
+ }
+#else
+ /* First step write R register with MasterID, processID and take bit=1*/
+ HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
+
+ /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
+ if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
+ {
+ /*take success when MasterID and ProcessID match and take bit set*/
+ return HAL_OK;
+ }
+#endif
+
+ /* Semaphore take fails*/
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Fast Take a semaphore with 1 Step mode.
+ * @param SemID: semaphore ID from 0 to 31
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
+{
+ /* Check the parameters */
+ assert_param(IS_HSEM_SEMID(SemID));
+
+#if USE_MULTI_CORE_SHARED_CODE != 0U
+ /* Read the RLR register to take the semaphore */
+ if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
+ {
+ /*take success when MasterID match and take bit set*/
+ return HAL_OK;
+ }
+#else
+ /* Read the RLR register to take the semaphore */
+ if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
+ {
+ /*take success when MasterID match and take bit set*/
+ return HAL_OK;
+ }
+#endif
+
+ /* Semaphore take fails */
+ return HAL_ERROR;
+}
+/**
+ * @brief Check semaphore state Taken or not.
+ * @param SemID: semaphore ID
+ * @retval HAL HSEM state
+ */
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
+{
+ return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
+}
+
+
+/**
+ * @brief Release a semaphore.
+ * @param SemID: semaphore ID from 0 to 31
+ * @param ProcessID: Process ID from 0 to 255
+ * @retval None
+ */
+void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
+{
+ /* Check the parameters */
+ assert_param(IS_HSEM_SEMID(SemID));
+ assert_param(IS_HSEM_PROCESSID(ProcessID));
+
+ /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
+ HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
+
+}
+
+/**
+ * @brief Release All semaphore used by a given Master .
+ * @param Key: Semaphore Key , value from 0 to 0xFFFF
+ * @param CoreID: CoreID of the CPU that is using semaphores to be released
+ * @retval None
+ */
+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
+{
+ assert_param(IS_HSEM_KEY(Key));
+ assert_param(IS_HSEM_COREID(CoreID));
+
+ HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
+ * @brief HSEM Set and Get Key functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### HSEM Set and Get Key functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Set semaphore Key
+ (+) Get semaphore Key
+@endverbatim
+
+ * @{
+ */
+
+/**
+ * @brief Set semaphore Key .
+ * @param Key: Semaphore Key , value from 0 to 0xFFFF
+ * @retval None
+ */
+void HAL_HSEM_SetClearKey(uint32_t Key)
+{
+ assert_param(IS_HSEM_KEY(Key));
+
+ MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
+
+}
+
+/**
+ * @brief Get semaphore Key .
+ * @retval Semaphore Key , value from 0 to 0xFFFF
+ */
+uint32_t HAL_HSEM_GetClearKey(void)
+{
+ return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
+ * @brief HSEM Notification functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### HSEM IRQ handler management and Notification functions #####
+ ==============================================================================
+[..] This section provides HSEM IRQ handler and Notification function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Activate Semaphore release Notification for a given Semaphores Mask .
+ * @param SemMask: Mask of Released semaphores
+ * @retval Semaphore Key
+ */
+void HAL_HSEM_ActivateNotification(uint32_t SemMask)
+{
+#if USE_MULTI_CORE_SHARED_CODE != 0U
+ /*enable the semaphore mask interrupts */
+ if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+ {
+ /*Use interrupt line 0 for CPU1 Master */
+ HSEM->C1IER |= SemMask;
+ }
+ else /* HSEM_CPU2_COREID */
+ {
+ /*Use interrupt line 1 for CPU2 Master*/
+ HSEM->C2IER |= SemMask;
+ }
+#else
+ HSEM_COMMON->IER |= SemMask;
+#endif
+}
+
+/**
+ * @brief Deactivate Semaphore release Notification for a given Semaphores Mask .
+ * @param SemMask: Mask of Released semaphores
+ * @retval Semaphore Key
+ */
+void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
+{
+#if USE_MULTI_CORE_SHARED_CODE != 0U
+ /*enable the semaphore mask interrupts */
+ if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+ {
+ /*Use interrupt line 0 for CPU1 Master */
+ HSEM->C1IER &= ~SemMask;
+ }
+ else /* HSEM_CPU2_COREID */
+ {
+ /*Use interrupt line 1 for CPU2 Master*/
+ HSEM->C2IER &= ~SemMask;
+ }
+#else
+ HSEM_COMMON->IER &= ~SemMask;
+#endif
+}
+
+/**
+ * @brief This function handles HSEM interrupt request
+ * @retval None
+ */
+void HAL_HSEM_IRQHandler(void)
+{
+ uint32_t statusreg;
+#if USE_MULTI_CORE_SHARED_CODE != 0U
+ if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
+ {
+ /* Get the list of masked freed semaphores*/
+ statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
+
+ /*Disable Interrupts*/
+ HSEM->C1IER &= ~((uint32_t)statusreg);
+
+ /*Clear Flags*/
+ HSEM->C1ICR = ((uint32_t)statusreg);
+ }
+ else /* HSEM_CPU2_COREID */
+ {
+ /* Get the list of masked freed semaphores*/
+ statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
+
+ /*Disable Interrupts*/
+ HSEM->C2IER &= ~((uint32_t)statusreg);
+
+ /*Clear Flags*/
+ HSEM->C2ICR = ((uint32_t)statusreg);
+ }
+#else
+ /* Get the list of masked freed semaphores*/
+ statusreg = HSEM_COMMON->MISR;
+
+ /*Disable Interrupts*/
+ HSEM_COMMON->IER &= ~((uint32_t)statusreg);
+
+ /*Clear Flags*/
+ HSEM_COMMON->ICR = ((uint32_t)statusreg);
+
+#endif
+ /* Call FreeCallback */
+ HAL_HSEM_FreeCallback(statusreg);
+}
+
+/**
+ * @brief Semaphore Released Callback.
+ * @param SemMask: Mask of Released semaphores
+ * @retval None
+ */
+__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(SemMask);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_HSEM_FreeCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_HSEM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c
new file mode 100644
index 0000000..0ee318b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ipcc.c
@@ -0,0 +1,780 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_ipcc.c
+ * @author MCD Application Team
+ * @brief IPCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Inter-Processor communication controller
+ * peripherals (IPCC).
+ * + Initialization and de-initialization functions
+ * + Configuration, notification and interrupts handling
+ * + Peripheral State and Error functions
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The IPCC HAL driver can be used as follows:
+
+ (#) Declare a IPCC_HandleTypeDef handle structure, for example: IPCC_HandleTypeDef hipcc;
+ (#) Initialize the IPCC low level resources by implementing the HAL_IPCC_MspInit() API:
+ (##) Enable the IPCC interface clock
+ (##) NVIC configuration if you need to use interrupt process
+ (+++) Configure the IPCC interrupt priority
+ (+++) Enable the NVIC IPCC IRQ
+
+ (#) Initialize the IPCC registers by calling the HAL_IPCC_Init() API which trig
+ HAL_IPCC_MspInit().
+
+ (#) Implement the interrupt callbacks for transmission and reception to use the driver in interrupt mode
+
+ (#) Associate those callback to the corresponding channel and direction using HAL_IPCC_ConfigChannel().
+ This is the interrupt mode.
+ If no callback are configured for a given channel and direction, it is up to the user to poll the
+ status of the communication (polling mode).
+
+ (#) Notify the other MCU when a message is available in a chosen channel
+ or when a message has been retrieved from a chosen channel by calling
+ the HAL_IPCC_NotifyCPU() API.
+
+@endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup IPCC
+ * @{
+ */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IPCC_Private_Constants IPCC Private Constants
+ * @{
+ */
+#define IPCC_ALL_RX_BUF 0x0000003FU /*!< Mask for all RX buffers. */
+#define IPCC_ALL_TX_BUF 0x003F0000U /*!< Mask for all TX buffers. */
+#define CHANNEL_INDEX_Msk 0x0000000FU /*!< Mask the channel index to avoid overflow */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup IPCC_Private_Functions IPCC Private Functions
+ * @{
+ */
+void IPCC_MaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+void IPCC_UnmaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
+void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc);
+void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance);
+/**
+ * @}
+ */
+
+/** @addtogroup IPCC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup IPCC_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ deinitialize the IPCC peripheral:
+
+ (+) User must Implement HAL_IPCC_MspInit() function in which he configures
+ all related peripherals resources (CLOCK and NVIC ).
+
+ (+) Call the function HAL_IPCC_Init() to configure the IPCC register.
+
+ (+) Call the function HAL_PKA_DeInit() to restore the default configuration
+ of the selected IPCC peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the IPCC peripheral.
+ * @param hipcc IPCC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+
+ /* Check the IPCC handle allocation */
+ if (hipcc != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
+
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+#endif
+
+ if (hipcc->State == HAL_IPCC_STATE_RESET)
+ {
+ /* Init the low level hardware : CLOCK, NVIC */
+ HAL_IPCC_MspInit(hipcc);
+ }
+
+ /* Reset all registers of the current cpu to default state */
+ IPCC_Reset_Register(currentInstance);
+
+ /* Activate the interrupts */
+ currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE);
+
+ /* Clear callback pointers */
+ IPCC_SetDefaultCallbacks(hipcc);
+
+ /* Reset all callback notification request */
+ hipcc->callbackRequest = 0;
+
+ hipcc->State = HAL_IPCC_STATE_READY;
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+
+ return err;
+}
+
+/**
+ * @brief DeInitialize the IPCC peripheral.
+ * @param hipcc IPCC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+
+ /* Check the IPCC handle allocation */
+ if (hipcc != NULL)
+ {
+ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+#endif
+
+ /* Set the state to busy */
+ hipcc->State = HAL_IPCC_STATE_BUSY;
+
+ /* Reset all registers of the current cpu to default state */
+ IPCC_Reset_Register(currentInstance);
+
+ /* Clear callback pointers */
+ IPCC_SetDefaultCallbacks(hipcc);
+
+ /* Reset all callback notification request */
+ hipcc->callbackRequest = 0;
+
+ /* DeInit the low level hardware : CLOCK, NVIC */
+ HAL_IPCC_MspDeInit(hipcc);
+
+ hipcc->State = HAL_IPCC_STATE_RESET;
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+
+ return err;
+}
+
+/**
+ * @brief Initialize the IPCC MSP.
+ * @param hipcc IPCC handle
+ * @retval None
+ */
+__weak void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hipcc);
+
+ /* NOTE : This function should not be modified. When the callback is needed
+ the HAL_IPCC_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief IPCC MSP DeInit
+ * @param hipcc IPCC handle
+ * @retval None
+ */
+__weak void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hipcc);
+
+ /* NOTE : This function should not be modified. When the callback is needed
+ the HAL_IPCC_MspDeInit should be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup IPCC_Exported_Functions_Group2
+ * @brief Configuration, notification and Irq handling functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions to allow two MCU to communicate.
+
+ (#) For a given channel (from 0 to IPCC_CHANNEL_NUMBER), for a given direction
+ IPCC_CHANNEL_DIR_TX or IPCC_CHANNEL_DIR_RX, you can choose to communicate
+ in polling mode or in interrupt mode using IPCC.
+ By default, the IPCC HAL driver handle the communication in polling mode.
+ By setting a callback for a channel/direction, this communication use
+ the interrupt mode.
+
+ (#) Polling mode:
+ (++) To transmit information, use HAL_IPCC_NotifyCPU() with
+ IPCC_CHANNEL_DIR_TX. To know when the other processor has handled
+ the notification, poll the communication using HAL_IPCC_NotifyCPU
+ with IPCC_CHANNEL_DIR_TX.
+
+ (++) To receive information, poll the status of the communication with
+ HAL_IPCC_GetChannelStatus with IPCC_CHANNEL_DIR_RX. To notify the other
+ processor that the information has been received, use HAL_IPCC_NotifyCPU
+ with IPCC_CHANNEL_DIR_RX.
+
+ (#) Interrupt mode:
+ (++) Configure a callback for the channel and the direction using HAL_IPCC_ConfigChannel().
+ This callback will be triggered under interrupt.
+
+ (++) To transmit information, use HAL_IPCC_NotifyCPU() with
+ IPCC_CHANNEL_DIR_TX. The callback configured with HAL_IPCC_ConfigChannel() and
+ IPCC_CHANNEL_DIR_TX will be triggered once the communication has been handled by the
+ other processor.
+
+ (++) To receive information, the callback configured with HAL_IPCC_ConfigChannel() and
+ IPCC_CHANNEL_DIR_RX will be triggered on reception of a communication.To notify the other
+ processor that the information has been received, use HAL_IPCC_NotifyCPU
+ with IPCC_CHANNEL_DIR_RX.
+
+ (++) HAL_IPCC_TX_IRQHandler must be added to the IPCC TX IRQHandler
+
+ (++) HAL_IPCC_RX_IRQHandler must be added to the IPCC RX IRQHandler
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Activate the callback notification on receive/transmit interrupt
+ * @param hipcc IPCC handle
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ * @param cb Interrupt callback
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+
+ /* Check the IPCC handle allocation */
+ if (hipcc != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
+
+ /* Check IPCC state */
+ if (hipcc->State == HAL_IPCC_STATE_READY)
+ {
+ /* Set callback and register masking information */
+ if (ChannelDir == IPCC_CHANNEL_DIR_TX)
+ {
+ hipcc->ChannelCallbackTx[ChannelIndex] = cb;
+ hipcc->callbackRequest |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+ else
+ {
+ hipcc->ChannelCallbackRx[ChannelIndex] = cb;
+ hipcc->callbackRequest |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+
+ /* Unmask only the channels in reception (Transmission channel mask/unmask is done in HAL_IPCC_NotifyCPU) */
+ if (ChannelDir == IPCC_CHANNEL_DIR_RX)
+ {
+ IPCC_UnmaskInterrupt(ChannelIndex, ChannelDir);
+ }
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+ return err;
+}
+
+/**
+ * @brief Remove the callback notification on receive/transmit interrupt
+ * @param hipcc IPCC handle
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+
+ /* Check the IPCC handle allocation */
+ if (hipcc != NULL)
+ {
+ /* Check the parameters */
+ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
+
+ /* Check IPCC state */
+ if (hipcc->State == HAL_IPCC_STATE_READY)
+ {
+ /* Set default callback and register masking information */
+ if (ChannelDir == IPCC_CHANNEL_DIR_TX)
+ {
+ hipcc->ChannelCallbackTx[ChannelIndex] = HAL_IPCC_TxCallback;
+ hipcc->callbackRequest &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+ else
+ {
+ hipcc->ChannelCallbackRx[ChannelIndex] = HAL_IPCC_RxCallback;
+ hipcc->callbackRequest &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+
+ /* Mask the interrupt */
+ IPCC_MaskInterrupt(ChannelIndex, ChannelDir);
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+ return err;
+}
+
+/**
+ * @brief Get state of IPCC channel
+ * @param hipcc IPCC handle
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ * @retval Channel status
+ */
+IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+ uint32_t channel_state;
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+ IPCC_CommonTypeDef *otherInstance = IPCC_C1;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+ IPCC_CommonTypeDef *otherInstance = IPCC_C2;
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
+
+ /* Read corresponding channel depending of the MCU and the direction */
+ if (ChannelDir == IPCC_CHANNEL_DIR_TX)
+ {
+ channel_state = (currentInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+ else
+ {
+ channel_state = (otherInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+
+ return (channel_state == 0UL) ? IPCC_CHANNEL_STATUS_FREE : IPCC_CHANNEL_STATUS_OCCUPIED ;
+}
+
+/**
+ * @brief Notify remote processor
+ * @param hipcc IPCC handle
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+ HAL_StatusTypeDef err = HAL_OK;
+ uint32_t mask;
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
+
+ /* Check if IPCC is initiliased */
+ if (hipcc->State == HAL_IPCC_STATE_READY)
+ {
+ /* For IPCC_CHANNEL_DIR_TX, set the status. For IPCC_CHANNEL_DIR_RX, clear the status */
+ currentInstance->SCR |= ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_SCR_CH1S : IPCC_SCR_CH1C) << (ChannelIndex & CHANNEL_INDEX_Msk) ;
+
+ /* Unmask interrupt if the callback is requested */
+ mask = ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_MR_CH1FM_Msk : IPCC_MR_CH1OM_Msk) << (ChannelIndex & CHANNEL_INDEX_Msk) ;
+ if ((hipcc->callbackRequest & mask) == mask)
+ {
+ IPCC_UnmaskInterrupt(ChannelIndex, ChannelDir);
+ }
+ }
+ else
+ {
+ err = HAL_ERROR;
+ }
+
+ return err;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup IPCC_IRQ_Handler_and_Callbacks
+ * @{
+ */
+
+/**
+ * @brief This function handles IPCC Tx Free interrupt request.
+ * @param hipcc IPCC handle
+ * @retval None
+ */
+void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc)
+{
+ uint32_t irqmask;
+ uint32_t bit_pos;
+ uint32_t ch_count = 0U;
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+#endif
+
+ /* check the Tx free channels which are not masked */
+ irqmask = ~(currentInstance->MR) & IPCC_ALL_TX_BUF;
+ irqmask = irqmask & ~(currentInstance->SR << IPCC_MR_CH1FM_Pos);
+
+ while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */
+ {
+ bit_pos = 1UL << (IPCC_MR_CH1FM_Pos + (ch_count & CHANNEL_INDEX_Msk));
+
+ if ((irqmask & bit_pos) != 0U)
+ {
+ /* mask the channel Free interrupt */
+ currentInstance->MR |= bit_pos;
+ if (hipcc->ChannelCallbackTx[ch_count] != NULL)
+ {
+ hipcc->ChannelCallbackTx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_TX);
+ }
+ irqmask = irqmask & ~(bit_pos);
+ }
+ ch_count++;
+ }
+}
+
+/**
+ * @brief This function handles IPCC Rx Occupied interrupt request.
+ * @param hipcc : IPCC handle
+ * @retval None
+ */
+void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc)
+{
+ uint32_t irqmask;
+ uint32_t bit_pos;
+ uint32_t ch_count = 0U;
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+ IPCC_CommonTypeDef *otherInstance = IPCC_C1;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+ IPCC_CommonTypeDef *otherInstance = IPCC_C2;
+#endif
+
+ /* check the Rx occupied channels which are not masked */
+ irqmask = ~(currentInstance->MR) & IPCC_ALL_RX_BUF;
+ irqmask = irqmask & otherInstance->SR;
+
+ while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */
+ {
+ bit_pos = 1UL << (ch_count & CHANNEL_INDEX_Msk);
+
+ if ((irqmask & bit_pos) != 0U)
+ {
+ /* mask the channel occupied interrupt */
+ currentInstance->MR |= bit_pos;
+ if (hipcc->ChannelCallbackRx[ch_count] != NULL)
+ {
+ hipcc->ChannelCallbackRx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_RX);
+ }
+ irqmask = irqmask & ~(bit_pos);
+ }
+ ch_count++;
+ }
+}
+
+/**
+ * @brief Rx occupied callback
+ * @param hipcc IPCC handle
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ */
+__weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hipcc);
+ UNUSED(ChannelIndex);
+ UNUSED(ChannelDir);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IPCC_RxCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx free callback
+ * @param hipcc IPCC handle
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ */
+__weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hipcc);
+ UNUSED(ChannelIndex);
+ UNUSED(ChannelDir);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IPCC_TxCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup IPCC_Exported_Functions_Group3
+ * @brief IPCC Peripheral State and Error functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the IPCC handle state.
+ * @param hipcc IPCC handle
+ * @retval IPCC handle state
+ */
+HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc)
+{
+ return hipcc->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup IPCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Mask IPCC interrupts.
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ */
+void IPCC_MaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+#endif
+ if (ChannelDir == IPCC_CHANNEL_DIR_TX)
+ {
+ /* Mask interrupt */
+ currentInstance->MR |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+ else
+ {
+ /* Mask interrupt */
+ currentInstance->MR |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+}
+/**
+ * @brief Unmask IPCC interrupts.
+ * @param ChannelIndex Channel number
+ * This parameter can be one of the following values:
+ * @arg IPCC_CHANNEL_1: IPCC Channel 1
+ * @arg IPCC_CHANNEL_2: IPCC Channel 2
+ * @arg IPCC_CHANNEL_3: IPCC Channel 3
+ * @arg IPCC_CHANNEL_4: IPCC Channel 4
+ * @arg IPCC_CHANNEL_5: IPCC Channel 5
+ * @arg IPCC_CHANNEL_6: IPCC Channel 6
+ * @param ChannelDir Channel direction
+ */
+void IPCC_UnmaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
+{
+#if defined(CORE_CM4)
+ IPCC_CommonTypeDef *currentInstance = IPCC_C2;
+#else
+ IPCC_CommonTypeDef *currentInstance = IPCC_C1;
+#endif
+ if (ChannelDir == IPCC_CHANNEL_DIR_TX)
+ {
+ /* Unmask interrupt */
+ currentInstance->MR &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+ else
+ {
+ /* Unmask interrupt */
+ currentInstance->MR &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
+ }
+}
+
+/**
+ * @brief Reset all callbacks of the handle to NULL.
+ * @param hipcc IPCC handle
+ */
+void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc)
+{
+ uint32_t i;
+ /* Set all callbacks to default */
+ for (i = 0; i < IPCC_CHANNEL_NUMBER; i++)
+ {
+ hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback;
+ hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback;
+ }
+}
+
+/**
+ * @brief Reset IPCC register to default value for the concerned instance.
+ * @param Instance pointer to register
+ */
+void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance)
+{
+ /* Disable RX and TX interrupts */
+ Instance->CR = 0x00000000U;
+
+ /* Mask RX and TX interrupts */
+ Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF);
+
+ /* Clear RX status */
+ Instance->SCR = IPCC_ALL_RX_BUF;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c
new file mode 100644
index 0000000..4a58d17
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_mdma.c
@@ -0,0 +1,1854 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_mdma.c
+ * @author MCD Application Team
+ * @version V0.3.0
+ * @date 9-December-2016
+ * @brief MDMA HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the Master Direct Memory Access (MDMA) peripheral:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral State and errors functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable and configure the peripheral to be connected to the MDMA Channel
+ (except for internal SRAM/FLASH memories: no initialization is
+ necessary) please refer to Reference manual for connection between peripherals
+ and MDMA requests.
+
+ (#)
+ (+) For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters:
+ HW request (if any), channel priority, data endianness, request, Source increment,
+ destination increment , source data size, destination data size, data alignment, source Burst,
+ destination Burst , buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer
+ or full transfer) source and destination block address offset, mask address and data.
+
+ (+) If using the MDMA in linked list mode then use function HAL_MDMA_CreateLinkedListNode to fill a transfer node.
+ Parameters given to the function HAL_MDMA_Init corresponds always to the node zero.
+ Use function HAL_MDMA_ConnectLinkedListNode connect the created node to the linked list at a given position.
+ User can make a circular linked list by connecting the first node at the end of the list (i.e after the last node)
+ In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init
+ note the initial transfer itself (node 0).
+ Function HAL_MDMA_DisConnectLinkedListNode can be used to remove (disconnect) a node from the transfer linked list.
+ When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops),
+ the linked list remains circular and node 2 becomes the first one.
+ If the linked list is made circular the transfer will loop infinitely (or until aborted by the user).
+
+
+ (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be
+ transfer upon a request :
+ + MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data
+ with BufferTransferLength defined within the HAL_MDMA_Init.
+ + MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block
+ with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT.
+ + MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks
+ with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT.
+ + MDMA_FULL_TRANSFER : each request triggers a full transfer
+ all blocks and all nodes(if a linked list hase been created using HAL_MDMA_CreateLinkedListNode\HAL_MDMA_ConnectLinkedListNode).
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred.
+ (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level
+ In this case a fixed Timeout can be configured by User depending from his application.
+ (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns
+ when the abort ends or timeout (should not be called from an interrupt service routine).
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred. In this
+ case the MDMA interrupt is configured.
+ (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e a member of MDMA handle structure).
+
+ (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API returns immediately
+ then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel hase effectively aborted.
+ (could be called from an interrupt service routine).
+
+ (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks
+ from the following list :
+ (++) XferCpltCallback : transfer complete callback.
+ (++) XferBufferCpltCallback : buffer transfer complete callback.
+ (++) XferBlockCpltCallback : block transfer complete callback.
+ (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback.
+ (++) XferErrorCallback : transfer error callback.
+ (++) XferAbortCallback : transfer abort complete callback.
+
+ [..]
+ (+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to
+ trigger requests manually. function HAL_MDMA_GenerateSWRequest must be used with the following precautions:
+ - this function returns an error if used while the Transfer hase ends or not started.
+ - if used while the current request hase not been served yet (current request transfer on going)
+ this function returns an error and the new request is ignored.
+
+ Generally this function should be used in conjunctions with the MDMA callbacks:
+ example 1:
+ + Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER
+ + Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID)
+ + After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data.
+ + When the buffer transfer complete callback is asserted first buffer hase been transferred and user can ask for a new buffer transfer
+ request using HAL_MDMA_GenerateSWRequest.
+
+ example 2:
+ + Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER
+ + Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID)
+ + After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data.
+ + When the block transfer complete callback is asserted the fisrt block hase been transferred and user can ask
+ for a new block transfer request using HAL_MDMA_GenerateSWRequest.
+
+ [..]
+ (#) Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error
+ detection.
+
+ *** MDMA HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in MDMA HAL driver.
+
+ (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Stream.
+ (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Stream.
+ (+) __HAL_MDMA_GET_FLAG: Get the MDMA Stream pending flags.
+ (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Stream pending flags.
+ (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Stream interrupts.
+ (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Stream interrupts.
+ (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Stream interrupt hase occurred or not.
+
+ [..]
+ (@) You can refer to the MDMA HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup MDMA MDMA
+ * @brief MDMA HAL module driver
+ * @{
+ */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup MDMA_Private_Constants
+ * @{
+ */
+#define HAL_TIMEOUT_MDMA_ABORT ((uint32_t)5U) /* 5 ms */
+#define HAL_MDMA_CHANNEL_SIZE ((uint32_t)0x40U) /* an MDMA instance channel size is 64 byte */
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup MDMA_Private_Functions_Prototypes
+ * @{
+ */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma);
+
+/**
+ * @}
+ */
+
+/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions
+ * @{
+ */
+
+/** @addtogroup MDMA_Exported_Functions_Group1
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to :
+ Initialize and de-initialize the MDMA channel.
+ Define and Add an MDMA linked list node.
+ Register and Unregister MDMA callbacks
+ [..]
+ The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in
+ reference manual.
+ The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel.
+ HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows
+ respectevely to register/unregister an MDMA callback function.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the MDMA according to the specified
+ * parameters in the MDMA_InitTypeDef and create the associated handle.
+ * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance));
+ assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority));
+ assert_param(IS_MDMA_SECURE_MODE(hmdma->Init.SecureMode));
+ assert_param(IS_MDMA_ENDIANESS_MODE(hmdma->Init.Endianess));
+ assert_param(IS_MDMA_REQUEST(hmdma->Init.Request));
+ assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc));
+ assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc));
+ assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize));
+ assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize));
+ assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment));
+ assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst));
+ assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst));
+ assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength));
+ assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode));
+ assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset));
+ assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset));
+
+
+ /* Allocate lock resource */
+ __HAL_UNLOCK(hmdma);
+
+ if(hmdma->State == HAL_MDMA_STATE_RESET)
+ {
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_MDMA_MspInit(hmdma);
+ }
+
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_BUSY;
+
+ /* Disable the MDMA channel */
+ __HAL_MDMA_DISABLE(hmdma);
+
+ /* Check if the MDMA channel is effectively disabled */
+ while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+ {
+ /* Update error code */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT;
+
+ /* Change the MDMA state */
+ hmdma->State = HAL_MDMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Init MDMA channel registers */
+ MDMA_Init(hmdma);
+
+ /* Reset the MDMA first/last linkedlist node addresses and node counter */
+ hmdma->FirstLinkedListNodeAddress = 0;
+ hmdma->LastLinkedListNodeAddress = 0;
+ hmdma->LinkedListNodeCounter = 0;
+
+ /* Initialise the error code */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+ /* Initialize the MDMA state */
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the MDMA peripheral
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma)
+{
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the MDMA peripheral state */
+ if(hmdma->State == HAL_MDMA_STATE_BUSY)
+ {
+ hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+
+ /* Disable the selected MDMA Channelx */
+ __HAL_MDMA_DISABLE(hmdma);
+
+ /* Reset MDMA Channel control register */
+ hmdma->Instance->CCR = 0;
+ hmdma->Instance->CTCR = 0;
+ hmdma->Instance->CBNDTR = 0;
+ hmdma->Instance->CSAR = 0;
+ hmdma->Instance->CDAR = 0;
+ hmdma->Instance->CBRUR = 0;
+ hmdma->Instance->CLAR = 0;
+ hmdma->Instance->CTBR = 0;
+ hmdma->Instance->CMAR = 0;
+ hmdma->Instance->CMDR = 0;
+
+ /* Clear all flags */
+ __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC));
+
+ /* DeInit the low level hardware */
+ HAL_MDMA_MspDeInit(hmdma);
+
+ /* Reset the MDMA first/last linkedlist node addresses and node counter */
+ hmdma->FirstLinkedListNodeAddress = 0;
+ hmdma->LastLinkedListNodeAddress = 0;
+ hmdma->LinkedListNodeCounter = 0;
+
+ /* Initialise the error code */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+ /* Initialize the MDMA state */
+ hmdma->State = HAL_MDMA_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmdma);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Config the Post request Mask address and Mask data
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @param MaskAddress: specifies the address to be updated (written) with MaskData after a request is served.
+ * @param MaskData: specifies the value to be written to MaskAddress after a request is served.
+ * MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ /* if HW request set Post Request MaskAddress and MaskData, */
+ if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0)
+ {
+ /* Set the HW request clear Mask and Data */
+ hmdma->Instance->CMAR = MaskAddress;
+ hmdma->Instance->CMDR = MaskData;
+
+ /*
+ -If the request is done by SW : BWM could be set to 1 or 0.
+ -If the request is done by a peripheral :
+ If mask address not set (0) => BWM must be set to 0
+ If mask address set (different than 0) => BWM could be set to 1 or 0
+ */
+ if(MaskAddress == 0)
+ {
+ hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+ /* Release Lock */
+ __HAL_UNLOCK(hmdma);
+
+ return status;
+}
+
+/**
+ * @brief Register callbacks
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @param CallbackID: User Callback identifier
+ * @param pCallback: pointer to callbacsk function.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDMA_XFER_CPLT_CB_ID:
+ hmdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+ hmdma->XferBufferCpltCallback = pCallback;
+ break;
+
+ case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+ hmdma->XferBlockCpltCallback = pCallback;
+ break;
+
+ case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+ hmdma->XferRepeatBlockCpltCallback = pCallback;
+ break;
+
+ case HAL_MDMA_XFER_ERROR_CB_ID:
+ hmdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_MDMA_XFER_ABORT_CB_ID:
+ hmdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @param CallbackID: User Callback identifier
+ * a HAL_MDMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_MDMA_XFER_CPLT_CB_ID:
+ hmdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_MDMA_XFER_BUFFERCPLT_CB_ID:
+ hmdma->XferBufferCpltCallback = NULL;
+ break;
+
+ case HAL_MDMA_XFER_BLOCKCPLT_CB_ID:
+ hmdma->XferBlockCpltCallback = NULL;
+ break;
+
+ case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID:
+ hmdma->XferRepeatBlockCpltCallback = NULL;
+ break;
+
+ case HAL_MDMA_XFER_ERROR_CB_ID:
+ hmdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_MDMA_XFER_ABORT_CB_ID:
+ hmdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_MDMA_XFER_ALL_CB_ID:
+ hmdma->XferCpltCallback = NULL;
+ hmdma->XferBufferCpltCallback = NULL;
+ hmdma->XferBlockCpltCallback = NULL;
+ hmdma->XferRepeatBlockCpltCallback = NULL;
+ hmdma->XferErrorCallback = NULL;
+ hmdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hmdma);
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup MDMA_Exported_Functions_Group2
+ *
+@verbatim
+ ===============================================================================
+ ##### Linked list operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Create a linked list node
+ (+) Add a node to the MDMA linked list
+ (+) Remove a node from the MDMA linked list
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes an MDMA Link Node according to the specified
+ * parameters in the pMDMA_LinkedListNodeConfig .
+ * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+ * registers configurations.
+ * @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains
+ * the configuration information for the specified MDMA Linked List Node.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig)
+{
+ uint32_t addressMask = 0;
+
+ /* Check the MDMA peripheral state */
+ if((pNode == NULL) || (pNodeConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority));
+ assert_param(IS_MDMA_SECURE_MODE(pNodeConfig->Init.SecureMode));
+ assert_param(IS_MDMA_ENDIANESS_MODE(pNodeConfig->Init.Endianess));
+ assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request));
+ assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc));
+ assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc));
+ assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize));
+ assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize));
+ assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment));
+ assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst));
+ assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst));
+ assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength));
+ assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode));
+ assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset));
+ assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset));
+
+ assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength));
+ assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount));
+
+
+ /*configure next Link node Address Register to zero */
+ pNode->CLAR = 0;
+
+ /*Configure the Link Node registers*/
+ pNode->CTBR = 0;
+ pNode->CMAR = 0;
+ pNode->CMDR = 0;
+
+ /* write new CTCR Register value */
+ pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \
+ pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \
+ pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \
+ pNodeConfig->Init.DestBurst | \
+ ((pNodeConfig->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
+ pNodeConfig->Init.TransferTriggerMode;
+
+ /* If SW request set the CTCR register to SW Request Mode*/
+ if(pNodeConfig->Init.Request == MDMA_REQUEST_SW)
+ {
+ pNode->CTCR |= MDMA_CTCR_SWRM;
+ }
+
+ /*
+ -If the request is done by SW : BWM could be set to 1 or 0.
+ -If the request is done by a peripheral :
+ If mask address not set (0) => BWM must be set to 0
+ If mask address set (different than 0) => BWM could be set to 1 or 0
+ */
+ if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0))
+ {
+ pNode->CTCR |= MDMA_CTCR_BWM;
+ }
+
+ /* Set the new CBNDTR Register value */
+ pNode->CBNDTR = ((pNodeConfig->BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC;
+
+ /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+ if(pNodeConfig->Init.SourceBlockAddressOffset < 0)
+ {
+ pNode->CBNDTR |= MDMA_CBNDTR_BRSUM;
+ /*write new CBRUR Register value : source repeat block offset */
+ pNode->CBRUR = (((uint32_t)(-1 * pNodeConfig->Init.SourceBlockAddressOffset)) & 0x0000FFFFU);
+ }
+ else
+ {
+ /*write new CBRUR Register value : source repeat block offset */
+ pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+ }
+
+ /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+ if(pNodeConfig->Init.DestBlockAddressOffset < 0)
+ {
+ pNode->CBNDTR |= MDMA_CBNDTR_BRDUM;
+ /*write new CBRUR Register value : destination repeat block offset */
+ pNode->CBRUR |= (((uint32_t)(-1 * pNodeConfig->Init.DestBlockAddressOffset)) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
+ }
+ else
+ {
+ /*write new CBRUR Register value : destination repeat block offset */
+ pNode->CBRUR |= (((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
+ }
+
+ /* Configure MDMA Link Node data length */
+ pNode->CBNDTR |= pNodeConfig->BlockDataLength;
+
+ /* Configure MDMA Link Node destination address */
+ pNode->CDAR = pNodeConfig->DstAddress;
+
+ /* Configure MDMA Link Node Source address */
+ pNode->CSAR = pNodeConfig->SrcAddress;
+
+ /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+ if(pNodeConfig->Init.Request != MDMA_REQUEST_SW)
+ {
+ /* Set the HW request in CTBR register */
+ pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL;
+ /* Set the HW request clear Mask and Data */
+ pNode->CMAR = pNodeConfig->PostRequestMaskAddress;
+ pNode->CMDR = pNodeConfig->PostRequestMaskData;
+ }
+
+ addressMask = pNodeConfig->SrcAddress & 0xFF000000U;
+ if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+ {
+ /*The AHBSbus is used as source (read operation) on channel x */
+ pNode->CTBR |= MDMA_CTBR_SBUS;
+ }
+
+ addressMask = pNodeConfig->DstAddress & 0xFF000000U;
+ if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+ {
+ /*The AHB bus is used as destination (write operation) on channel x */
+ pNode->CTBR |= MDMA_CTBR_DBUS;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Connect a node to the linked list
+ * parameters in the MDMA_InitTypeDef .
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+ * to be add to the list.
+ * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node
+ * at the end of the list
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
+{
+ MDMA_LinkNodeTypeDef *pNode = 0;
+ uint32_t counter = 0, nodeConter = 0, nodeInserted = 0;
+ HAL_StatusTypeDef hal_status = HAL_OK;
+
+ /* Check the MDMA peripheral handle */
+ if((hmdma == NULL) || (pNewNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_BUSY;
+
+ /* Check if this is the first node (after the Inititlization node) */
+ if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0)
+ {
+ if(pPrevNode == NULL)
+ {
+ /* if this is the first node after the initialization
+ connect this node to the node 0 by updating
+ the MDMA channel CLAR register to this node address */
+ hmdma->Instance->CLAR = (uint32_t)pNewNode;
+ /* Set the MDMA handle First linked List node*/
+ hmdma->FirstLinkedListNodeAddress = pNewNode;
+
+ /*reset New node link */
+ pNewNode->CLAR = 0;
+
+ /* Update the Handle last node address */
+ hmdma->LastLinkedListNodeAddress = pNewNode;
+
+ hmdma->LinkedListNodeCounter = 1;
+ }
+ else
+ {
+ hal_status = HAL_ERROR;
+ }
+ }
+ else if(((uint32_t)hmdma->LastLinkedListNodeAddress != 0) && (hmdma->LinkedListNodeCounter != 0))
+ {
+ /* if new node is equal to first node then linked list is circular */
+ if(hmdma->FirstLinkedListNodeAddress == pNewNode)
+ {
+ pNode = hmdma->FirstLinkedListNodeAddress;
+ if(pPrevNode == 0)
+ {
+ pPrevNode = hmdma->LastLinkedListNodeAddress;
+ }
+ while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0))
+ {
+ if(pNode == pPrevNode)
+ {
+ pNode->CLAR = (uint32_t)pNewNode;
+ hmdma->LastLinkedListNodeAddress = pNode;
+ nodeInserted = 1;
+ }
+
+ pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+ nodeConter++;
+ counter ++;
+ }
+ if(nodeInserted == 0)
+ {
+ hal_status = HAL_ERROR;
+ }
+ else
+ {
+ /* update linked lis counter */
+ hmdma->LinkedListNodeCounter = nodeConter;
+ }
+ }
+ else
+ {
+ /* Check if the node to insert already exists*/
+ pNode = hmdma->FirstLinkedListNodeAddress;
+ while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK))
+ {
+ if(pNode->CLAR == (uint32_t)pNewNode)
+ {
+ hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */
+ }
+ pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+ counter++;
+ }
+
+ if(hal_status == HAL_OK)
+ {
+ /* Check if the previous node is the last one in the current list or zero */
+ if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == 0))
+ {
+ /* insert the new node at the end of the list. */
+ pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR;
+ hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode;
+ /* Update the Handle last node address */
+ hmdma->LastLinkedListNodeAddress = pNewNode;
+ /* Increment the linked list node counter */
+ hmdma->LinkedListNodeCounter++;
+ }
+ else
+ {
+ /*insert the new node after the pPreviousNode node */
+ pNode = hmdma->FirstLinkedListNodeAddress;
+ counter = 0;
+ while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0))
+ {
+ counter++;
+ if(pNode == pPrevNode)
+ {
+ /*Insert the new node after the previous one */
+ pNewNode->CLAR = pNode->CLAR;
+ pNode->CLAR = (uint32_t)pNewNode;
+ /* Increment the linked list node counter */
+ hmdma->LinkedListNodeCounter++;
+ nodeInserted = 1;
+ }
+ else
+ {
+ pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR;
+ }
+ }
+
+ if(nodeInserted == 0)
+ {
+ hal_status = HAL_ERROR;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ hal_status = HAL_ERROR;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ return hal_status;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Return error status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disconnect/Remove a node from the transfer linked list
+ * parameters in the MDMA_InitTypeDef .
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node
+ * to be removed from the list.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode)
+{
+ MDMA_LinkNodeTypeDef *ptmpNode = 0;
+ uint32_t counter = 0, nodeDeleted = 0;
+ HAL_StatusTypeDef hal_status = HAL_OK;
+
+ /* Check the MDMA peripheral handle */
+ if((hmdma == NULL) || (pNode == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_BUSY;
+
+ /* If first and last node are null (no nodes in the list) : return error*/
+ if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0) || (hmdma->LinkedListNodeCounter == 0))
+ {
+ hal_status = HAL_ERROR;
+ }
+ else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */
+ {
+ /* Delete 1st node */
+ if(hmdma->LastLinkedListNodeAddress == pNode)
+ {
+ /*if the last node is at the same time the first one (1 single node after the init node 0)
+ then update the last node too */
+
+ hmdma->FirstLinkedListNodeAddress = 0;
+ hmdma->LastLinkedListNodeAddress = 0;
+ hmdma->LinkedListNodeCounter = 0;
+
+ hmdma->Instance->CLAR = 0;
+ }
+ else
+ {
+ if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR)
+ {
+ /* if last node is looping to first (circular list) one update the last node connection */
+ hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR;
+ }
+
+ /* if deleting the first node after the initialization
+ connect the next node to the node 0 by updating
+ the MDMA channel CLAR register to this node address */
+ hmdma->Instance->CLAR = pNode->CLAR;
+ hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR;
+ /* Update the Handle node counter */
+ hmdma->LinkedListNodeCounter--;
+ }
+ }
+ else /* Deleting any other node */
+ {
+ /*Deleted node is not the first one : find it */
+ ptmpNode = hmdma->FirstLinkedListNodeAddress;
+ while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0))
+ {
+ counter++;
+ if(ptmpNode->CLAR == ((uint32_t)pNode))
+ {
+ /* if deleting the last node */
+ if(pNode == hmdma->LastLinkedListNodeAddress)
+ {
+ /*Update the linked list last node address in the handle*/
+ hmdma->LastLinkedListNodeAddress = ptmpNode;
+ }
+ /* update the next node link after deleting pMDMA_LinkedListNode */
+ ptmpNode->CLAR = pNode->CLAR;
+ nodeDeleted = 1;
+ /* Update the Handle node counter */
+ hmdma->LinkedListNodeCounter--;
+ }
+ else
+ {
+ ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR;
+ }
+ }
+
+ if(nodeDeleted == 0)
+ {
+ /* last node reashed without finding the node to delete : return error */
+ hal_status = HAL_ERROR;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ return hal_status;
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Return error status */
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup MDMA_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the source, destination address and data length and Start MDMA transfer
+ (+) Configure the source, destination address and data length and
+ Start MDMA transfer with interrupt
+ (+) Abort MDMA transfer
+ (+) Poll for transfer complete
+ (+) Handle MDMA interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the MDMA Transfer.
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @param SrcAddress : The source memory Buffer address
+ * @param DstAddress : The destination memory Buffer address
+ * @param BlockDataLength : The length of a block transfer in bytes
+ * @param BlockCount : The number of a blocks to be transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+ /* Check the parameters */
+ assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+ assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_MDMA_DISABLE(hmdma);
+
+ /* Configure the source, destination address and the data length */
+ MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+
+ /* Enable the Peripheral */
+ __HAL_MDMA_ENABLE(hmdma);
+
+
+ if(hmdma->Init.Request == MDMA_REQUEST_SW)
+ {
+ /* activate If SW request mode*/
+ hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Return error status */
+ return HAL_BUSY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the MDMA Transfer with interrupts enabled.
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @param SrcAddress : The source memory Buffer address
+ * @param DstAddress : The destination memory Buffer address
+ * @param BlockDataLength : The length of a block transfer in bytes
+ * @param BlockCount : The number of a blocks to be transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+ /* Check the parameters */
+ assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength));
+ assert_param(IS_MDMA_BLOCK_COUNT(BlockCount));
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hmdma);
+
+ if(HAL_MDMA_STATE_READY == hmdma->State)
+ {
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_BUSY;
+
+ /* Initialize the error code */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_MDMA_DISABLE(hmdma);
+
+ /* Configure the source, destination address and the data length */
+ MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount);
+
+ /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/
+ __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC));
+
+ if(hmdma->XferBlockCpltCallback != NULL)
+ {
+ /* if Block transfer complete Callback is set enable the corresponding IT*/
+ __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT);
+ }
+
+ if(hmdma->XferRepeatBlockCpltCallback != NULL)
+ {
+ /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/
+ __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT);
+ }
+
+ if(hmdma->XferBufferCpltCallback != NULL)
+ {
+ /* if buffer transfer complete Callback is set enable the corresponding IT*/
+ __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_MDMA_ENABLE(hmdma);
+
+ if(hmdma->Init.Request == MDMA_REQUEST_SW)
+ {
+ /* activate If SW request mode*/
+ hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
+ }
+ }
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Return error status */
+ return HAL_BUSY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the MDMA Transfer.
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ *
+ * @note After disabling a MDMA Stream, a check for wait until the MDMA Channel is
+ * effectively disabled is added. If a Stream is disabled
+ * while a data transfer is ongoing, the current data will be transferred
+ * and the Stream will be effectively disabled only after the transfer of
+ * this single data is finished.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma)
+{
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(HAL_MDMA_STATE_BUSY != hmdma->State)
+ {
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable all the transfer interrupts */
+ __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+ /* Disable the channel */
+ __HAL_MDMA_DISABLE(hmdma);
+
+ /* Check if the MDMA Channel is effectively disabled */
+ while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0)
+ {
+ /* Check for the Timeout */
+ if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT)
+ {
+ /* Update error code */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Change the MDMA state */
+ hmdma->State = HAL_MDMA_STATE_TIMEOUT;
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear all interrupt flags */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Change the MDMA state*/
+ hmdma->State = HAL_MDMA_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Aborts the MDMA Transfer in Interrupt mode.
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
+{
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(HAL_MDMA_STATE_BUSY != hmdma->State)
+ {
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set Abort State */
+ hmdma->State = HAL_MDMA_STATE_ABORT;
+
+ /* Disable the stream */
+ __HAL_MDMA_DISABLE(hmdma);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Polling for transfer complete.
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Channel.
+ * @param CompleteLevel: Specifies the MDMA level complete.
+ * @param Timeout: Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+ uint32_t levelFlag = 0, errorFlag = 0;
+ uint32_t tickstart = 0;
+
+ /* Check the parameters */
+ assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel));
+
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if(HAL_MDMA_STATE_BUSY != hmdma->State)
+ {
+ /* No transfer ongoing */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+
+ return HAL_ERROR;
+ }
+
+ /* Get the level transfer complete flag */
+ levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC :\
+ (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC :\
+ (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT :\
+ MDMA_FLAG_BRT);
+
+
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
+ while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == RESET)
+ {
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
+ {
+ /* Get the transfer error source flag */
+ errorFlag = hmdma->Instance->CESR;
+
+ if((errorFlag & MDMA_CESR_TED) == 0)
+ {
+ /* Update error code : Read Transfer error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+ }
+ else
+ {
+ /* Update error code : Write Transfer error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+ }
+
+ if((errorFlag & MDMA_CESR_TEMD) != 0)
+ {
+ /* Update error code : Error Mask Data */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+ }
+
+ if((errorFlag & MDMA_CESR_TELD) != 0)
+ {
+ /* Update error code : Error Linked list */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+ }
+
+ if((errorFlag & MDMA_CESR_ASE) != 0)
+ {
+ /* Update error code : Address/Size alignment error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+ }
+
+ if((errorFlag & MDMA_CESR_BSE) != 0)
+ {
+ /* Update error code : Block Size error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+ }
+
+ HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */
+
+ /* Clear the transfer error flags */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Change the MDMA state */
+ hmdma->State= HAL_MDMA_STATE_READY;
+
+ return HAL_ERROR;
+
+ }
+
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ /* Update error code */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Change the MDMA state */
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the transfer level flag */
+ if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)
+ {
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+ }
+ else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER)
+ {
+ __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT));
+
+ }
+ else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER)
+ {
+ __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT));
+ }
+ else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER)
+ {
+ __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC));
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ hmdma->State = HAL_MDMA_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Generate an MDMA SW request trigger to activate the request on the given Channel.
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma)
+{
+ /* Check the MDMA peripheral handle */
+ if(hmdma == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if((hmdma->Instance->CCR & MDMA_CCR_EN) == RESET)
+ {
+ /* if no Transfer on going (MDMA enable bit not set) retrun error */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+ return HAL_ERROR;
+ }
+ else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != RESET) || ((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == RESET))
+ {
+ /* if an MDMA ongoing request hase not yet ends or if request mode is not SW request retrun error */
+ hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Set the SW request bit to activate the request on the Channel */
+ hmdma->Instance->CCR |= MDMA_CCR_SWRQ;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @brief Handles MDMA interrupt request.
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @retval None
+ */
+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
+{
+ __IO uint32_t count = 0;
+ uint32_t timeout = SystemCoreClock / 9600;
+
+ uint32_t generalIntFlag, errorFlag;
+
+ /* General Interrupt Flag management ****************************************/
+ if((hmdma->Instance->CCR & MDMA_CCR_SM) != MDMA_CCR_SM)
+ {
+ /*Check non secure mode general flag */
+ generalIntFlag = 1 << (((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE);
+ if((MDMA->GISR0 & generalIntFlag) == RESET)
+ {
+ return; /* the General interrupt flag for the current channel is down , nothing to do */
+ }
+ }
+ else
+ {
+ /*Check secure mode general flag */
+ generalIntFlag = 1 << (((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE);
+ if((MDMA->SGISR0 & generalIntFlag) == RESET)
+ {
+ return; /* the General interrupt flag for the current channel is down , nothing to do */
+ }
+ }
+ /* Transfer Error Interrupt management ***************************************/
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != RESET))
+ {
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != RESET)
+ {
+ /* Disable the transfer error interrupt */
+ __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE);
+
+ /* Get the transfer error source flag */
+ errorFlag = hmdma->Instance->CESR;
+
+ if((errorFlag & MDMA_CESR_TED) == 0)
+ {
+ /* Update error code : Read Transfer error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER;
+ }
+ else
+ {
+ /* Update error code : Write Transfer error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER;
+ }
+
+ if((errorFlag & MDMA_CESR_TEMD) != 0)
+ {
+ /* Update error code : Error Mask Data */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA;
+ }
+
+ if((errorFlag & MDMA_CESR_TELD) != 0)
+ {
+ /* Update error code : Error Linked list */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST;
+ }
+
+ if((errorFlag & MDMA_CESR_ASE) != 0)
+ {
+ /* Update error code : Address/Size alignment error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT;
+ }
+
+ if((errorFlag & MDMA_CESR_BSE) != 0)
+ {
+ /* Update error code : Block Size error error */
+ hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE;
+ }
+
+ /* Clear the transfer error flags */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE);
+ }
+ }
+
+ /* Buffer Transfer Complete Interrupt management ******************************/
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != RESET))
+ {
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != RESET)
+ {
+ /* Clear the buffer transfer complete flag */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC);
+
+ if(hmdma->XferBufferCpltCallback != NULL)
+ {
+ /* Buffer transfer callback */
+ hmdma->XferBufferCpltCallback(hmdma);
+ }
+ }
+ }
+
+ /* Block Transfer Complete Interrupt management ******************************/
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != RESET))
+ {
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != RESET)
+ {
+ /* Clear the block transfer complete flag */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT);
+
+ if(hmdma->XferBlockCpltCallback != NULL)
+ {
+ /* Block transfer callback */
+ hmdma->XferBlockCpltCallback(hmdma);
+ }
+ }
+ }
+
+ /* Repeated Block Transfer Complete Interrupt management ******************************/
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != RESET))
+ {
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != RESET)
+ {
+ /* Clear the repeat block transfer complete flag */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT);
+
+ if(hmdma->XferRepeatBlockCpltCallback != NULL)
+ {
+ /* Repeated Block transfer callback */
+ hmdma->XferRepeatBlockCpltCallback(hmdma);
+ }
+ }
+ }
+
+ /* Channel Transfer Complete Interrupt management ***********************************/
+ if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != RESET))
+ {
+ if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != RESET)
+ {
+ /* Disable all the transfer interrupts */
+ __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC));
+
+ if(HAL_MDMA_STATE_ABORT == hmdma->State)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Change the DMA state */
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ if(hmdma->XferAbortCallback != NULL)
+ {
+ hmdma->XferAbortCallback(hmdma);
+ }
+ return;
+
+ }
+ /* Clear the Channel Transfer Complete flag */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Change MDMA peripheral state */
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ if(hmdma->XferCpltCallback != NULL)
+ {
+ /* Channel Transfer Complete callback */
+ hmdma->XferCpltCallback(hmdma);
+ }
+ }
+ }
+
+ /* manage error case */
+ if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE)
+ {
+ hmdma->State = HAL_MDMA_STATE_ABORT;
+
+ /* Disable the channel */
+ __HAL_MDMA_DISABLE(hmdma);
+
+ do
+ {
+ if (++count > timeout)
+ {
+ break;
+ }
+ }
+ while((hmdma->Instance->CCR & MDMA_CCR_EN) != RESET);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hmdma);
+
+ /* Change the MDMA state */
+ hmdma->State = HAL_MDMA_STATE_READY;
+
+ if (hmdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hmdma->XferErrorCallback(hmdma);
+ }
+ }
+
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup MDMA_Exported_Functions_Group4
+ *
+@verbatim
+ ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Check the MDMA state
+ (+) Get error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the MDMA state.
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @retval HAL state
+ */
+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
+{
+ return hmdma->State;
+}
+
+/**
+ * @brief Return the MDMA error code
+ * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @retval MDMA Error Code
+ */
+uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
+{
+ return hmdma->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup JPEG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the MDMA Transfer parameter.
+ * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains
+ * the configuration information for the specified MDMA Stream.
+ * @param SrcAddress: The source memory Buffer address
+ * @param DstAddress: The destination memory Buffer address
+ * @param BlockDataLength : The length of a block transfer in bytes
+ * @param BlockCount: The number of a blocks to be transfer
+ * @retval HAL status
+ */
+static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount)
+{
+ uint32_t addressMask;
+ /* Configure MDMA Channel data length */
+ MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT));
+
+ /*Configure the MDMA block repeat count*/
+ MODIFY_REG( hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1) << POSITION_VAL(MDMA_CBNDTR_BRC)) & MDMA_CBNDTR_BRC);
+
+ /* Clear all interrupt flags */
+ __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF);
+
+ /* Configure MDMA Channel destination address */
+ hmdma->Instance->CDAR = DstAddress;
+
+ /* Configure MDMA Channel Source address */
+ hmdma->Instance->CSAR = SrcAddress;
+
+ addressMask = SrcAddress & 0xFF000000U;
+ if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+ {
+ /*The AHBSbus is used as source (read operation) on channel x */
+ hmdma->Instance->CTBR |= MDMA_CTBR_SBUS;
+ }
+ else
+ {
+ /*The AXI bus is used as source (read operation) on channel x */
+ hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS);
+ }
+
+ addressMask = DstAddress & 0xFF000000U;
+ if((addressMask == 0x20000000U) || (addressMask == 0x00000000U))
+ {
+ /*The AHB bus is used as destination (write operation) on channel x */
+ hmdma->Instance->CTBR |= MDMA_CTBR_DBUS;
+ }
+ else
+ {
+ /*The AXI bus is used as destination (write operation) on channel x */
+ hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS);
+ }
+
+ /* Set the linked list rgeitser to the first node of the list */
+ hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress;
+}
+
+static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
+{
+ /* Prepare the MDMA Channel configuration */
+ hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.SecureMode | hmdma->Init.Endianess;
+
+ /* write new CTCR Register value */
+ hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \
+ hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \
+ hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \
+ hmdma->Init.DestBurst | \
+ ((hmdma->Init.BufferTransferLength - 1) << POSITION_VAL(MDMA_CTCR_TLEN)) | \
+ hmdma->Init.TransferTriggerMode;
+
+ /* If SW request set the CTCR register to SW Request Mode*/
+ if(hmdma->Init.Request == MDMA_REQUEST_SW)
+ {
+ hmdma->Instance->CTCR |= MDMA_CTCR_SWRM;
+ }
+
+ /* Reset CBNDTR Register */
+ hmdma->Instance->CBNDTR = 0;
+
+ /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */
+ if(hmdma->Init.SourceBlockAddressOffset < 0)
+ {
+ hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM;
+ /*write new CBRUR Register value : source repeat block offset */
+ hmdma->Instance->CBRUR = (((uint32_t)(-1 * hmdma->Init.SourceBlockAddressOffset)) & 0x0000FFFFU);
+ }
+ else
+ {
+ /*write new CBRUR Register value : source repeat block offset */
+ hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU);
+ }
+
+ /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */
+ if(hmdma->Init.DestBlockAddressOffset < 0)
+ {
+ hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM;
+ /*write new CBRUR Register value : destination repeat block offset */
+ hmdma->Instance->CBRUR |= (((uint32_t)(-1 * hmdma->Init.DestBlockAddressOffset)) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
+ }
+ else
+ {
+ /*write new CBRUR Register value : destination repeat block offset */
+ hmdma->Instance->CBRUR |= (((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << POSITION_VAL(MDMA_CBRUR_DUV);
+ }
+
+ /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */
+ if(hmdma->Init.Request != MDMA_REQUEST_SW)
+ {
+ /* Set the HW request in CTRB register */
+ hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL;
+ }
+ else /* SW request : reset the CTBR register */
+ {
+ hmdma->Instance->CTBR = 0;
+ }
+
+ /*Write Link Address Register*/
+ hmdma->Instance->CLAR = 0;
+}
+
+
+/**
+ * @brief MDMA MSP Init
+ * @param hmdma: MDMA handle
+ * @retval None
+ */
+ __weak void HAL_MDMA_MspInit(MDMA_HandleTypeDef *hmdma)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MDMA_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief MDMA MSP DeInit
+ * @param hmdma: MDMA handle
+ * @retval None
+ */
+ __weak void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MDMA_MspDeInit can be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_MDMA_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c
new file mode 100644
index 0000000..0ee0379
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c
@@ -0,0 +1,781 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_pwr.c
+ * @author MCD Application Team
+ * @brief PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Power Controller (PWR) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWR PWR
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWR_Private_Constants PWR Private Constants
+ * @{
+ */
+
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+ * @{
+ */
+#define PVD_MODE_IT ((uint32_t)0x00010000U)
+#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
+#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
+#define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions PWR Private Functions
+ * @{
+ */
+
+/** @defgroup PWR_Group1 Initialization and de-initialization functions
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ After reset, the backup domain (RTC registers, RTC backup data
+ registers and backup SRAM) is protected against possible unwanted
+ write accesses.
+ To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess()
+ function.
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @brief Enables access to the backup domain
+ * In reset state, the RCC_BDCR, PWR_CR2, RTC, and backup registers are
+ * protected against parasitic write access. DBP bit must be set to
+ * enable write access to these.
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+ /* Enable access to RTC and backup registers */
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+ * @brief Disables access to the backup domain (RTC registers, RTC
+ * backup data registers and backup SRAM).
+ * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
+ * Backup Domain Access should be kept enabled.
+ * @retval None
+ */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+ /* Disable access to RTC and backup registers */
+ CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Group2 Peripheral Control functions
+ * @brief Low Power modes configuration functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+
+ *** PVD configuration ***
+ =========================
+ [..]
+ (+) The PVD is used to monitor the VDD power supply by comparing it to a
+ threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR1).
+ (+) The PVD can also be used to monitor a voltage level on the PVD_IN pin.
+ In this case, the voltage level on PVD_IN is compared to the internal
+ VREFINT level.
+ (+) A PVDO flag is available, in the PWR control status register 1
+ (PWR_CSR1), to indicate whether VDD or voltage level on PVD_IN is
+ higher or lower than the PVD threshold. This event is internally
+ connected to the EXTI line16 and can generate an interrupt if enabled.
+ This is done through __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT() macro.
+ (+) The PVD is stopped in Standby mode.
+
+ *** WakeUp pins configuration ***
+ ================================
+ [..]
+ (+) WakeUp pins are used to wake up the system from Standby mode. WKUP
+ pins, if enabled, the WKUP pin pulls can be configured by WKUPPUPD
+ register bits in PWR wakeup control register (PWR_WKUPCR).
+
+ *** Low Power modes configuration ***
+ =====================================
+ [..]
+ Several Low-power modes are available to save power when the MPU and/or
+ MCU do not need to execute code (i.e. when waiting for an external event).
+ Please refer to Reference Manual for more information.
+ MPU and MCU sub-system modes:
+ (+) CSleep mode: MPU/MCU clocks stopped and the MPU/MCU sub-system allocated
+ peripheral(s) clocks operate according to RCC PERxLPEN
+ (+) CStop mode: MPU/MCU and MPU/MCU sub-system peripheral(s) clock stopped
+ (+) CStandby mode: MPU and MPU sub-system peripheral(s) clock stopped and
+ wakeup via reset
+ System modes:
+ (+) Stop mode: bus matrix clocks stalled, the oscillators can be stopped.
+ VDDCORE is supplied.
+ To enter into this mode:
+ - Both MPU and MCU sub-systems are in CStop or CStandby.
+ - At least one PDDS bit (PWR_MPUCR/PWR_MCUCR) selects Stop.
+ (+) LP-Stop mode: bus matrix clocks stalled, the oscillators can be stopped.
+ VDDCORE is supplied.
+ To enter into this mode:
+ - Both MPU and MCU sub-systems are in CStop or CStandby.
+ - The LPDS bit (PWR_CR1) selects LP-Stop.
+ - The LVDS bit (PWR_CR1) selects normal voltage.
+ - At least one PDDS bit (PWR_MPUCR/PWR_MCUCR) selects Stop.
+ (+) LPLV-Stop mode: bus matrix clocks stalled, the oscillators can be stopped.
+ VDDCORE may be supplied at a lower level.
+ To enter into this mode:
+ - Both MPU and MCU sub-systems are in CStop or CStandby.
+ - The LPDS and LVDS bits (PWR_CR1) select LPLV-Stop.
+ - At least one PDDS bit (PWR_MPUCR/PWR_MCUCR) selects Stop.
+ (+) Standby mode: System powered down.
+ To enter into this mode:
+ - MPU sub-system is in CStandby or CStop with CSTBYDIS = 1
+ and MCU subsystem is in CStop.
+ - All PDDS bits (PWR_MPUCR/PWR_MCUCR) select Standby.
+
+ *** CSleep mode ***
+ ==================
+ [..]
+ (+) Entry:
+ The CSleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry)
+ functions with:
+ (++) STOPEntry:
+ (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+ (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+
+ -@@- The Regulator parameter is not used for the STM32MP1 family
+ and is kept as parameter just to maintain compatibility with the
+ lower power families (STM32L). Use i.e. PWR_MAINREGULATOR_ON
+ (+) Exit:
+ MCU: Any peripheral interrupt acknowledged by the nested vectored interrupt
+ controller (NVIC) if entered by WFI or any event if entered by WFE
+ MPU: Any Interrupt enabled in GIC if entered by WFI or any event if
+ entered by WFE
+
+
+ *** CStop mode ***
+ =================
+ [..]
+ (+) Entry:
+ The CStop mode is entered using the HAL_PWR_EnterSTOP(ModeRegulator, STOPEntry)
+ function with:
+ (++) Regulator:
+ (+++) PWR_MAINREGULATOR_ON: Main regulator ON.
+ (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
+ (++) STOPEntry:
+ (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction
+ (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
+ (+) Exit:
+ MCU: Any EXTI Line (Internal or External) configured in Interrupt/Event mode
+ depending of entry mode.
+ MPU: Any EXTI Line (Internal or External) configured in Interrupt mode
+
+ *** MPU CStandby mode / MCU CStop allowing Standby mode ***
+ ====================
+ [..]
+ (+)
+ The Standby mode allows to achieve the lowest power consumption. On Standby
+ mode the voltage regulator is disabled. The PLLs, the HSI oscillator and
+ the HSE oscillator are also switched off. SRAM and register contents are
+ lost except for the RTC registers, RTC backup registers, backup SRAM and
+ Standby circuitry.
+
+ (++) Entry:
+ (+++) The MPU CStandby mode / MCU CStop allowing Standby mode is entered
+ using the HAL_PWR_EnterSTANDBYMode() function.
+ (++) Exit:
+ Any EXTI Line (Internal or External) configured in Interrupt mode
+ if system is not in Standby mode
+ (+++) If system is in Standby mode wake up is generated by reset through:
+ WKUP pins, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper
+ event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * information for the PVD.
+ * @note Refer to the electrical characteristics of your device datasheet for
+ * more details about the voltage threshold corresponding to each
+ * detection level.
+ * @retval None
+ */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+ assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+ /* Set PLS[7:5] bits according to PVDLevel value */
+ MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
+
+ /* Clear any previous config. Keep it clear if no IT mode is selected */
+ __HAL_PWR_PVD_AVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_FALLING_EDGE();
+
+ /* Configure interrupt mode */
+ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+ {
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure the edge */
+ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+ {
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+ {
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+}
+
+/**
+ * @brief Enables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_EnablePVD(void)
+{
+ /* Enable the power voltage detector */
+ SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+ * @brief Disables the Power Voltage Detector(PVD).
+ * @retval None
+ */
+void HAL_PWR_DisablePVD(void)
+{
+ /* Disable the power voltage detector */
+ CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
+}
+
+/**
+ * @brief Enable the WakeUp PINx functionality.
+ * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
+ * This parameter can be one of the following legacy values, which sets the default polarity:
+ * detection on high level (rising edge):
+ * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
+ * or one of the following value where the user can explicitly states the enabled pin and
+ * the chosen polarity
+ * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW or
+ * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
+ * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
+ * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+ * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
+ * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
+ * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
+ *
+ * @note GPIOs are set as next when WKUP pin is enabled (Additional function)
+ * WKUP1 : PA0
+ * WKUP2 : PA2
+ * WKUP3 : PC13
+ * WKUP4 : PI8
+ * WKUP5 : PI11
+ * WKUP6 : PC1
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+ uint32_t clear_mask = 0;
+
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
+
+ if ((WakeUpPinPolarity & PWR_WAKEUP_PIN1) == PWR_WAKEUP_PIN1)
+ {
+ clear_mask |= (PWR_WKUPCR_WKUPP_1 | PWR_WKUPCR_WKUPPUPD1);
+ }
+ if ((WakeUpPinPolarity & PWR_WAKEUP_PIN2) == PWR_WAKEUP_PIN2)
+ {
+ clear_mask |= (PWR_WKUPCR_WKUPP_2 | PWR_WKUPCR_WKUPPUPD2);
+ }
+ if ((WakeUpPinPolarity & PWR_WAKEUP_PIN3) == PWR_WAKEUP_PIN3)
+ {
+ clear_mask |= (PWR_WKUPCR_WKUPP_3 | PWR_WKUPCR_WKUPPUPD3);
+ }
+ if ((WakeUpPinPolarity & PWR_WAKEUP_PIN4) == PWR_WAKEUP_PIN4)
+ {
+ clear_mask |= (PWR_WKUPCR_WKUPP_4 | PWR_WKUPCR_WKUPPUPD4);
+ }
+ if ((WakeUpPinPolarity & PWR_WAKEUP_PIN5) == PWR_WAKEUP_PIN5)
+ {
+ clear_mask |= (PWR_WKUPCR_WKUPP_5 | PWR_WKUPCR_WKUPPUPD5);
+ }
+ if ((WakeUpPinPolarity & PWR_WAKEUP_PIN6) == PWR_WAKEUP_PIN6)
+ {
+ clear_mask |= (PWR_WKUPCR_WKUPP_6 | PWR_WKUPCR_WKUPPUPD6);
+ }
+
+ /* Enables and Specifies the Wake-Up pin polarity and the pull configuration
+ for the event detection (rising or falling edge) */
+#ifdef CORE_CA7
+ CLEAR_BIT(PWR->MPUWKUPENR, (WakeUpPinPolarity & PWR_WAKEUP_PIN_MASK)); /* Disable WKUP pin */
+ MODIFY_REG(PWR->WKUPCR, clear_mask,
+ (WakeUpPinPolarity & (PWR_WKUPCR_WKUPP | PWR_WKUPCR_WKUPPUPD))); /* Modify polarity and pull configuration */
+ SET_BIT(PWR->WKUPCR, (WakeUpPinPolarity & PWR_WKUPCR_WKUPC)); /* Clear wake up flag */
+ SET_BIT(PWR->MPUWKUPENR, (WakeUpPinPolarity & PWR_WAKEUP_PIN_MASK)); /* Enable the Wake up pin for CPU1 */
+#endif
+#ifdef CORE_CM4
+ CLEAR_BIT(PWR->MCUWKUPENR, (WakeUpPinPolarity & PWR_WAKEUP_PIN_MASK)); /* Disable WKUP pin */
+ MODIFY_REG(PWR->WKUPCR, clear_mask,
+ (WakeUpPinPolarity & (PWR_WKUPCR_WKUPP | PWR_WKUPCR_WKUPPUPD))); /* Modify polarity and pull configuration */
+ SET_BIT(PWR->WKUPCR, (WakeUpPinPolarity & PWR_WKUPCR_WKUPC)); /* Clear wake up flag */
+ SET_BIT(PWR->MCUWKUPENR, (WakeUpPinPolarity & PWR_WAKEUP_PIN_MASK)); /* Enable the Wake up pin for CPU2 */
+#endif
+}
+
+
+/**
+ * @brief Disables the WakeUp PINx functionality.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2
+ * @arg PWR_WAKEUP_PIN3
+ * @arg PWR_WAKEUP_PIN4
+ * @arg PWR_WAKEUP_PIN5
+ * @arg PWR_WAKEUP_PIN6
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+#ifdef CORE_CA7
+ CLEAR_BIT(PWR->MPUWKUPENR, (WakeUpPinx & PWR_WAKEUP_PIN_MASK));
+#endif
+#ifdef CORE_CM4
+ CLEAR_BIT(PWR->MCUWKUPENR, (WakeUpPinx & PWR_WAKEUP_PIN_MASK));
+#endif
+}
+
+
+/**
+ * @brief Enable WakeUp PINx Interrupt on AIEC and NVIC.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2
+ * @arg PWR_WAKEUP_PIN3
+ * @arg PWR_WAKEUP_PIN4
+ * @arg PWR_WAKEUP_PIN5
+ * @arg PWR_WAKEUP_PIN6
+ * @retval None
+ */
+void HAL_PWR_EnableWakeUpPinIT(uint32_t WakeUpPinx)
+{
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ switch ((WakeUpPinx & PWR_WAKEUP_PIN_MASK))
+ {
+ case PWR_WAKEUP_PIN1:
+ __HAL_WKUP_EXTI_ENABLE_IT(EXTI_IMR2_IM55);
+ break;
+
+ case PWR_WAKEUP_PIN2:
+ __HAL_WKUP_EXTI_ENABLE_IT(EXTI_IMR2_IM56);
+ break;
+
+ case PWR_WAKEUP_PIN3:
+ __HAL_WKUP_EXTI_ENABLE_IT(EXTI_IMR2_IM57);
+ break;
+
+ case PWR_WAKEUP_PIN4:
+ __HAL_WKUP_EXTI_ENABLE_IT(EXTI_IMR2_IM58);
+ break;
+
+ case PWR_WAKEUP_PIN5:
+ __HAL_WKUP_EXTI_ENABLE_IT(EXTI_IMR2_IM59);
+ break;
+
+ case PWR_WAKEUP_PIN6:
+ __HAL_WKUP_EXTI_ENABLE_IT(EXTI_IMR2_IM60);
+ break;
+ }
+}
+
+
+/**
+ * @brief Disable WakeUp PINx Interrupt on AIEC and NVIC.
+ * @param WakeUpPinx: Specifies the Power Wake-Up pin
+ * This parameter can be one of the following values:
+ * @arg PWR_WAKEUP_PIN1
+ * @arg PWR_WAKEUP_PIN2
+ * @arg PWR_WAKEUP_PIN3
+ * @arg PWR_WAKEUP_PIN4
+ * @arg PWR_WAKEUP_PIN5
+ * @arg PWR_WAKEUP_PIN6
+ * @retval None
+ */
+void HAL_PWR_DisableWakeUpPinIT(uint32_t WakeUpPinx)
+{
+ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+ switch ((WakeUpPinx & PWR_WAKEUP_PIN_MASK))
+ {
+ case PWR_WAKEUP_PIN1:
+ __HAL_WKUP_EXTI_DISABLE_IT(EXTI_IMR2_IM55);
+ break;
+
+ case PWR_WAKEUP_PIN2:
+ __HAL_WKUP_EXTI_DISABLE_IT(EXTI_IMR2_IM56);
+ break;
+
+ case PWR_WAKEUP_PIN3:
+ __HAL_WKUP_EXTI_DISABLE_IT(EXTI_IMR2_IM57);
+ break;
+
+ case PWR_WAKEUP_PIN4:
+ __HAL_WKUP_EXTI_DISABLE_IT(EXTI_IMR2_IM58);
+ break;
+
+ case PWR_WAKEUP_PIN5:
+ __HAL_WKUP_EXTI_DISABLE_IT(EXTI_IMR2_IM59);
+ break;
+
+ case PWR_WAKEUP_PIN6:
+ __HAL_WKUP_EXTI_DISABLE_IT(EXTI_IMR2_IM60);
+ break;
+ }
+}
+
+/**
+ * @brief Enters CSleep mode.
+ *
+ * @note In CSleep mode, all I/O pins keep the same state as in Run mode.
+ *
+ * @note In CSleep mode, the systick is stopped to avoid exit from this mode with
+ * systick interrupt when used as time base for Timeout
+ *
+ * @param Regulator: Specifies the regulator state in CSLEEP mode.
+ * This parameter is not used for the STM32MP1 family and is kept as
+ * parameter just to maintain compatibility with the lower power families
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: CSLEEP mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: CSLEEP mode with low power regulator ON
+ * @param SLEEPEntry: Specifies if CSLEEP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_SLEEPENTRY_WFI: enter CSLEEP mode with WFI instruction
+ * @arg PWR_SLEEPENTRY_WFE: enter CSLEEP mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+#ifdef CORE_CM4
+ /* Ensure CM4 do not enter to CSTOP mode */
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+#endif
+
+ /* Select SLEEP mode entry -------------------------------------------------*/
+ if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+
+/**
+ * @brief Enters CSTOP
+ * This function puts core domain into CSTOP allowing system STOP mode
+ * if both MPU and MCU cores are on CSTOP mode
+ * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+ * @note When exiting Stop mode by issuing an interrupt or a wake up event,
+ * the HSI oscillator is selected as CM4 system clock.
+ * @note RCC_WAKEUP_IRQn IT must be programmed to have the highest priority and
+ * to be the only one IT having this value before calling HAL_PWR_EnterSTOPMode.
+ * Make sure RCC_WAKEUP_IRQn is the only one IT allowed to wake up core
+ * before calling HAL_PWR_EnterSTOPMode (BASEPRI)
+ * Reestablish priority level once system is completely waken up (clock
+ * restore and IO compensation)
+ * @note When the voltage regulator operates in low power mode, an additional
+ * startup delay is incurred when waking up from Stop mode.
+ * By keeping the internal regulator ON during Stop mode, the consumption
+ * is higher although the startup time is reduced.
+ * @param Regulator: Specifies the regulator state in Stop mode.
+ * This parameter is unused on MCU but any value must be provided.
+ * This parameter can be one of the following values:
+ * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+ * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+ * @param STOPEntry: Specifies if CStop mode is entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPENTRY_WFI: Enter CStop mode with WFI instruction
+ * @arg PWR_STOPENTRY_WFE: Enter CStop mode with WFE instruction
+ * @retval None
+ */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+
+#ifdef CORE_CM4
+ /*Forbid going to STANDBY mode (select STOP mode) */
+ CLEAR_BIT(PWR->MCUCR, PWR_MCUCR_PDDS);
+
+ /*Allow CORE_CM4 to enter CSTOP mode
+ Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
+#endif/* CORE_CM4 */
+
+#ifdef CORE_CA7
+ if (Regulator == PWR_MAINREGULATOR_ON)
+ {
+ /* Select STOP mode */
+ CLEAR_BIT(PWR->CR1, PWR_CR1_LPDS);
+ }
+ else
+ {
+ /* Select LP-STOP mode */
+ SET_BIT(PWR->CR1, PWR_CR1_LPDS);
+ }
+
+ /* Clear MPU STANDBY, STOP and HOLD flags.(Always read as 0) */
+ SET_BIT(PWR->MPUCR, PWR_MPUCR_CSSF);
+
+ /* MPU STAY in STOP MODE */
+ CLEAR_BIT(PWR->MPUCR, PWR_MPUCR_PDDS);
+ /* MPU CSTANDBY mode disabled */
+ SET_BIT(PWR->MPUCR, PWR_MPUCR_CSTBYDIS);
+
+ /* RCC Stop Request Set Register */
+ RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+
+#else
+ /* Prevent unused argument compilation warning */
+ UNUSED(Regulator);
+#endif /*CORE_CA7*/
+
+ /* Select Stop mode entry --------------------------------------------------*/
+ if ((STOPEntry == PWR_STOPENTRY_WFI))
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else if (STOPEntry == PWR_STOPENTRY_WFE)
+ {
+ /* Request Wait For Event */
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+#ifdef CORE_CM4
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+#endif/* CORE_CM4 */
+
+#ifdef CORE_CA7
+ /* RCC Clear Request Set Register */
+ RCC->MP_SREQCLRR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#endif
+}
+
+/**
+ * @brief Enters MPU CStandby / MCU CSTOP allowing system Standby mode.
+ * @note In Standby mode, all I/O pins are high impedance except for:
+ * - Reset pad (still available)
+ * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
+ * Alarm out, or RTC clock calibration out.
+ * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
+ * - WKUP pins if enabled.
+ * @retval None
+ */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+
+#ifdef CORE_CM4
+ /*Allow to go to STANDBY mode */
+ SET_BIT(PWR->MCUCR, PWR_MCUCR_PDDS);
+
+ /*Allow CORE_CM4 to enter CSTOP mode
+ Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+#endif /* CORE_CM4 */
+
+#ifdef CORE_CA7
+
+ /* Clear MPU STANDBY, STOP and HOLD flags.(Always read as 0) */
+ SET_BIT(PWR->MPUCR, PWR_MPUCR_CSSF);
+ /* system Power Down Deepsleep selection */
+ /* MPU go in STANDBY MODE */
+ SET_BIT(PWR->MPUCR, PWR_MPUCR_PDDS);
+ /* MPU CSTANDBY mode enabled */
+ CLEAR_BIT(PWR->MPUCR, PWR_MPUCR_CSTBYDIS);
+
+ /* RCC Stop Request Set Register */
+ RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#endif
+
+ /* Clear Reset Status */
+ __HAL_RCC_CLEAR_RESET_FLAGS();
+
+
+ /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+
+/**
+ * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+ * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters CSleep mode when an interruption handling is over.
+ * Setting this bit is useful when the processor is expected to run only on
+ * interruptions handling.
+ * @retval None
+ */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+#ifdef CORE_CM4
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+#endif
+}
+
+
+/**
+ * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+ * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+ * re-enters CSLEEP mode when an interruption handling is over.
+ * @retval None
+ */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+#ifdef CORE_CM4
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+#endif
+}
+
+/**
+ * @brief Enables CORTEX SEVONPEND bit.
+ * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+#ifdef CORE_CM4
+ /* Set SEVONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+#endif
+}
+
+/**
+ * @brief Disables CORTEX SEVONPEND bit.
+ * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+ * WFE to wake up when an interrupt moves from inactive to pended.
+ * @retval None
+ */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+#ifdef CORE_CM4
+ /* Clear SEVONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+#endif
+}
+
+/**
+ * @brief PWR PVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWR_PVDCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWR_PVDCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c
new file mode 100644
index 0000000..89dc7e3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr_ex.c
@@ -0,0 +1,798 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_pwr_ex.c
+ * @author MCD Application Team
+ * @brief Extended PWR HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of PWR extension peripheral:
+ * + Peripheral Extended features functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup PWREx PWREx
+ * @brief PWR HAL module driver
+ * @{
+ */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Constants PWREx Private Constants
+ * @{
+ */
+
+/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
+ * @{
+ */
+#define AVD_MODE_IT ((uint32_t)0x00010000U)
+#define AVD_MODE_EVT ((uint32_t)0x00020000U)
+#define AVD_RISING_EDGE ((uint32_t)0x00000001U)
+#define AVD_FALLING_EDGE ((uint32_t)0x00000002U)
+#define AVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
+/**
+ * @}
+ */
+
+/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
+ * @{
+ */
+#define PWR_FLAG_SETTING_DELAY_US ((uint32_t)1000U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWREx_Private_Functions PWREx Private Functions
+ * @{
+ */
+
+/** @defgroup PWREx_Group1 Peripheral Extended features functions
+ * @brief Peripheral Extended features functions
+ *
+@verbatim
+
+ ===============================================================================
+ ##### Peripheral extended features functions #####
+ ===============================================================================
+
+ *** Main and Backup Regulators configuration ***
+ ================================================
+ [..]
+ (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
+ the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
+ retained even in Standby or VBAT mode when the low power backup regulator
+ is enabled. It can be considered as an internal EEPROM when VBAT is
+ always present. You can use the HAL_PWR_EnableBkUpReg() function to
+ enable the low power backup regulator.
+
+ (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
+ the backup SRAM is powered from VDD which replaces the VBAT power supply to
+ save battery life.
+
+ (+) The backup SRAM is not mass erased by a tamper event. It is read
+ protected to prevent confidential data, such as cryptographic private
+ key, from being accessed.
+
+ Refer to the product datasheets for more details.
+
+
+ *** VBAT battery charging ***
+ =============================
+ [..]
+ (+) When VDD is present, the external battery connected to VBAT can be charged through an
+ internal resistance. VBAT charging can be performed either through a 5 KOhm resistor
+ or through a 1.5 KOhm resistor.
+ (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging(ResistorValue) function
+ with:
+ (++) ResistorValue:
+ (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
+ (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
+ (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() function.
+
+ *** VBAT and Temperature supervision ***
+ ========================================
+ [..]
+ (+) The VBAT battery voltage supply can be monitored by comparing it with two threshold
+ levels: VBAThigh and VBATlow. VBATH flag and VBATL flag in the PWR control register 2
+ (PWR_CR2), indicate if VBAT is higher or lower than the threshold.
+ (+) The temperature can be monitored by comparing it with two threshold levels, TEMPhigh
+ and TEMPlow. TEMPH and TEMPL flags, in the PWR control register 2 (PWR_CR2),
+ indicate whether the device temperature is higher or lower than the threshold.
+ (+) The VBAT and the temperature monitoring is enabled by HAL_PWREx_EnableMonitoring()
+ function and disabled by HAL_PWREx_DisableMonitoring() function.
+ (+) The HAL_PWREx_GetVBATLevel() function return the VBAT level which can be:
+ PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
+ PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
+ (+) The HAL_PWREx_GetTemperatureLevel() function return the Temperature level which
+ can be: PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
+ PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
+
+ *** AVD configuration ***
+ =========================
+ [..]
+ (+) The AVD is used to monitor the VDDA power supply by comparing it to a
+ threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CSR1 register).
+ (+) A AVDO flag is available to indicate if VDDA is higher or lower
+ than the AVD threshold. This event is internally connected to the EXTI
+ line 16 to generate an interrupt if enabled.
+ It is configurable through __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT() macro.
+ (+) The AVD is stopped in System Standby mode.
+
+
+ *** USB Regulator supervision ***
+ ===================================
+ [..]
+ (+) When the USB regulator is enabled, the VDD33USB supply level detector shall
+ be enabled through HAL_PWREx_EnableUSBVoltageDetector() function and disabled by
+ HAL_PWREx_DisableUSBVoltageDetector() function.
+
+@endverbatim
+ * @{
+ */
+
+
+
+/**
+ * @brief Enables the Backup Regulator.
+ * @note After reset PWR_CR2 register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * Use HAL_PWR_EnableBkUpAccess() to do this.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Enable Backup regulator */
+ SET_BIT(PWR->CR2, PWR_CR2_BREN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till Backup regulator ready flag is set */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the Backup Regulator.
+ * @note After reset PWR_CR2 register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * Use HAL_PWR_EnableBkUpAccess() to do this.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable Backup regulator */
+ CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till Backup regulator ready flag is reset */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the Retention Regulator.
+ * @note After reset PWR_CR2 register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * Use HAL_PWR_EnableBkUpAccess() to do this.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableRetReg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Enable Backup regulator */
+ SET_BIT(PWR->CR2, PWR_CR2_RREN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till Retention regulator ready flag is set */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_RRR) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disables the Retention Regulator.
+ * @note After reset PWR_CR2 register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * Use HAL_PWR_EnableBkUpAccess() to do this.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableRetReg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable Backup regulator */
+ CLEAR_BIT(PWR->CR2, PWR_CR2_RREN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till Backup regulator ready flag is set */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_RRR) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Enables the 1V1 Regulator.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_Enable1V1Reg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Enable 1V1 regulator */
+ SET_BIT(PWR->CR3, PWR_CR3_REG11EN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till 1V1 regulator ready flag is set */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_11R) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables the 1V1 Regulator.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_Disable1V1Reg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable 1V1 regulator */
+ CLEAR_BIT(PWR->CR3, PWR_CR3_REG11EN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till 1V1 regulator ready flag is reset */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_11R) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables the 1V8 Regulator.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_Enable1V8Reg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Enable 1V8 regulator */
+ SET_BIT(PWR->CR3, PWR_CR3_REG18EN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till 1V8 regulator ready flag is set */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_18R) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Disables the 1V8 Regulator.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_Disable1V8Reg(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable 1V8 regulator */
+ CLEAR_BIT(PWR->CR3, PWR_CR3_REG18EN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till 1V8 regulator ready flag is reset */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_18R) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Enable the USB voltage level detector.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_EnableUSBVoltageDetector(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Enable the USB voltage detector */
+ SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until USB33 regulator ready flag is set */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_USB) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the USB voltage level detector.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PWREx_DisableUSBVoltageDetector(void)
+{
+ uint32_t tickstart = 0;
+
+ /* Disable the USB voltage detector */
+ CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until USB33 regulator ready flag is reset */
+ while (__HAL_PWR_GET_FLAG(PWR_FLAG_USB) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY_US)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Enable the Battery charging.
+ * When VDD is present, charge the external battery through an internal resistor.
+ * @param ResistorValue: Specifies the charging resistor.
+ * This parameter can be one of the following values:
+ * @arg PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
+ * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
+ * @retval None
+ */
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
+{
+ assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
+
+ /* Specify the charging resistor */
+ MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, ResistorValue);
+
+ /* Enable the Battery charging */
+ SET_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+
+/**
+ * @brief Disable the Battery charging.
+ * @retval None
+ */
+void HAL_PWREx_DisableBatteryCharging(void)
+{
+ /* Disable the Battery charging */
+ CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
+}
+
+
+/**
+ * @brief Enable the VBAT and temperature monitoring.
+ * @note After reset PWR_CR2 register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * Use HAL_PWR_EnableBkUpAccess() to do this.
+ * @retval HAL status
+ */
+void HAL_PWREx_EnableMonitoring(void)
+{
+ /* Enable the VBAT and Temperature monitoring */
+ SET_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+ * @brief Disable the VBAT and temperature monitoring.
+ * @note After reset PWR_CR2 register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * Use HAL_PWR_EnableBkUpAccess() to do this.
+ * @retval HAL status
+ */
+void HAL_PWREx_DisableMonitoring(void)
+{
+ /* Disable the VBAT and Temperature monitoring */
+ CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
+}
+
+/**
+ * @brief Indicate whether the junction temperature is between, above or below the threshold.
+ * @retval Temperature level.
+ */
+uint32_t HAL_PWREx_GetTemperatureLevel(void)
+{
+ uint32_t tempLevel;
+ uint32_t regValue;
+
+ /* Read the temperature flags */
+ regValue = PWR->CR2 & (PWR_CR2_TEMPH | PWR_CR2_TEMPL);
+
+ /* Compare the read value to the temperature threshold */
+ if (regValue == PWR_CR2_TEMPL)
+ {
+ tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
+ }
+ else if (regValue == PWR_CR2_TEMPH)
+ {
+ tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
+ }
+ else
+ {
+ tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
+ }
+
+ return tempLevel;
+}
+
+
+/**
+ * @brief Indicate whether the Battery voltage level is between, above or below the threshold.
+ * @retval VBAT level.
+ */
+uint32_t HAL_PWREx_GetVBATLevel(void)
+{
+ uint32_t VBATLevel;
+ uint32_t regValue;
+
+ /* Read the VBAT flags */
+ regValue = PWR->CR2 & (PWR_CR2_VBATH | PWR_CR2_VBATL);
+
+ /* Compare the read value to the VBAT threshold */
+ if (regValue == PWR_CR2_VBATL)
+ {
+ VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
+ }
+ else if (regValue == PWR_CR2_VBATH)
+ {
+ VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
+ }
+ else
+ {
+ VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
+ }
+
+ return VBATLevel;
+}
+
+
+/**
+ * @brief Configure the analog voltage threshold detected by the Analog Voltage Detector(AVD).
+ * @param sConfigAVD: pointer to an PWR_AVDTypeDef structure that contains the configuration
+ * information for the AVD.
+ * @note Refer to the electrical characteristics of your device datasheet for more details
+ * about the voltage threshold corresponding to each detection level.
+ * @retval None
+ */
+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel));
+ assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode));
+
+ /* Set the ALS[18:17] bits according to AVDLevel value */
+ MODIFY_REG(PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
+
+ /* Clear any previous config. Keep it clear if no IT mode is selected */
+ __HAL_PWR_PVD_AVD_EXTI_DISABLE_IT();
+ __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_EDGE();
+ __HAL_PWR_PVD_AVD_EXTI_DISABLE_FALLING_EDGE();
+
+ /* Configure the interrupt mode */
+ if (AVD_MODE_IT == (sConfigAVD->Mode & AVD_MODE_IT))
+ {
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT();
+ }
+
+ /* Configure the edge */
+ if (AVD_RISING_EDGE == (sConfigAVD->Mode & AVD_RISING_EDGE))
+ {
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_EDGE();
+ }
+
+ if (AVD_FALLING_EDGE == (sConfigAVD->Mode & AVD_FALLING_EDGE))
+ {
+ __HAL_PWR_PVD_AVD_EXTI_ENABLE_FALLING_EDGE();
+ }
+}
+
+
+/**
+ * @brief Enable the Analog Voltage Detector(AVD).
+ * @retval None
+ */
+void HAL_PWREx_EnableAVD(void)
+{
+ /* Enable the Analog Voltage Detector */
+ SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+/**
+ * @brief Disable the Analog Voltage Detector(AVD).
+ * @retval None
+ */
+void HAL_PWREx_DisableAVD(void)
+{
+ /* Disable the Analog Voltage Detector */
+ CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
+}
+
+
+/**
+ * @brief This function handles the PWR PVD/AVD interrupt request.
+ * @note This API should be called under the PVD_AVD_IRQHandler().
+ * @retval None
+ */
+void HAL_PWREx_PVD_AVD_IRQHandler(void)
+{
+ /* PVD EXTI line interrupt detected */
+ if (READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != RESET)
+ {
+ /* PWR PVD interrupt user callback */
+ HAL_PWR_PVDCallback();
+ }
+
+ /* AVD EXTI line interrupt detected */
+ if (READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != RESET)
+ {
+ /* PWR AVD interrupt user callback */
+ HAL_PWREx_AVDCallback();
+ }
+
+ /* Clear PWR PVD AVD EXTI pending bit */
+ __HAL_PWR_PVD_AVD_EXTI_CLEAR_FLAG();
+}
+
+/**
+ * @brief PWR AVD interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_AVDCallback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWREx_AVDCallback could be implemented in the user file
+ */
+}
+
+
+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void)
+{
+
+ /* Wakeup pin EXTI line interrupt detected */
+ if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != RESET)
+ {
+ /* Clear PWR WKUPF1 flag */
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
+
+ /* PWR WKUP1 interrupt user callback */
+ HAL_PWREx_WKUP1_Callback();
+ }
+
+ if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != RESET)
+ {
+ /* Clear PWR WKUPF2 flag */
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
+
+ /* PWR WKUP2 interrupt user callback */
+ HAL_PWREx_WKUP2_Callback();
+ }
+
+ if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != RESET)
+ {
+ /* Clear PWR WKUPF3 flag */
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
+
+ /* PWR WKUP3 interrupt user callback */
+ HAL_PWREx_WKUP3_Callback();
+ }
+
+ if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != RESET)
+ {
+ /* Clear PWR WKUPF4 flag */
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
+
+ /* PWR WKUP4 interrupt user callback */
+ HAL_PWREx_WKUP4_Callback();
+ }
+
+ if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != RESET)
+ {
+ /* Clear PWR WKUPF5 flag */
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
+
+ /* PWR WKUP5 interrupt user callback */
+ HAL_PWREx_WKUP5_Callback();
+ }
+
+ if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) != RESET)
+ {
+ /* Clear PWR WKUPF6 flag */
+ SET_BIT(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
+
+ /* PWR WKUP6 interrupt user callback */
+ HAL_PWREx_WKUP6_Callback();
+ }
+
+}
+
+/**
+ * @brief PWR WKUP1 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_WKUP1_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWREx_WKUP1Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR WKUP2 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_WKUP2_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWREx_WKUP2Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR WKUP3 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_WKUP3_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWREx_WKUP3Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR WKUP4 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_WKUP4_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWREx_WKUP4Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR WKUP5 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_WKUP5_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWREx_WKUP5Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWR WKUP6 interrupt callback
+ * @retval None
+ */
+__weak void HAL_PWREx_WKUP6_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_PWREx_WKUP6Callback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c
new file mode 100644
index 0000000..4d50fa3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c
@@ -0,0 +1,2701 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_rcc.c
+ * @author MCD Application Team
+ * @brief RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Reset and Clock Control (RCC) peripheral:
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### RCC specific features #####
+ ==============================================================================
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 64MHz) and all peripherals are off except
+ internal SRAM1, SRAM2, SRAM3 and PWR
+ (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
+ all peripherals mapped on these buses are running at HSI speed.
+ (+) The clock for all peripherals is switched off, except the SRAM
+
+ [..]
+ Once the device started from reset, the user application has to:
+ (+) Configure the clock source to be used to drive the MPU, AXI and MCU
+ (if the application needs higher frequency/performance)
+ (+) Configure the AHB and APB buses pre-scalers
+ (+) Enable the clock for the peripheral(s) to be used
+ (+) Configure the clock kernel source(s) for peripherals which clocks are not
+ derived from Bus clocks
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCC RCC
+ * @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define LSE_MASK (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP)
+#define HSE_MASK (RCC_OCENSETR_HSEON | RCC_OCENSETR_HSEBYP | RCC_OCENSETR_DIGBYP)
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_Private_Function_Prototypes RCC Private Functions Prototypes
+ * @{
+ */
+HAL_StatusTypeDef RCC_MPUConfig(RCC_MPUInitTypeDef *RCC_MPUInitStruct);
+HAL_StatusTypeDef RCC_AXISSConfig(RCC_AXISSInitTypeDef *RCC_AXISSInitStruct);
+HAL_StatusTypeDef RCC_MCUConfig(RCC_MCUInitTypeDef *MCUInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the internal/external oscillators
+ (HSE, HSI, LSE,CSI, LSI) PLL, HSECSS, LSECSS and MCO and the System busses clocks (
+ MPUSS,AXISS, MCUSS, AHB[1:4], AHB[5:6], APB1, APB2, APB3, APB4 and APB5).
+
+ [..] Internal/external clock and PLL configuration
+ (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
+ the PLL as System clock source.
+
+ (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
+ clock, or PLL input.But even with frequency calibration, is less accurate than an
+ external crystal oscillator or ceramic resonator.
+
+ (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+ clock source.
+
+ (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
+ through the PLL as System clock source. Can be used also as RTC clock source.
+
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+ (#) PLL , The RCC features four independent PLLs (clocked by HSI , HSE or CSI),
+ featuring three different output clocks and able to work either in integer, Fractional or
+ Spread Sprectum mode.
+ (++) PLL1, which is used to provide clock to the A7 sub-system
+ (++) PLL2, which is used to provide clock to the AXI sub-system, DDR and GPU
+ (++) PLL3, which is used to provide clock to the MCU sub-system and to generate the kernel
+ clock for peripherals.
+ (++) PLL4, which is used to generate the kernel clock for peripherals.
+
+
+ (#) HSECSS (HSE Clock security system), once enabled and if a HSE clock failure occurs
+ HSECSS will generate a system reset, and protect sensitive data of the BKPSRAM
+
+ (#) LSECSS (LSE Clock security system), once enabled and if a LSE clock failure occurs
+ (++) The clock provided to the RTC is disabled immediately by the hardware
+ (++) A failure event is generated (rcc_lsecss_fail). This event is connected to the TAMP
+ block, allowing to wake up from Standby, and allowing the protection of backup
+ registers and BKPSRAM
+ (++) An interrupt flag (LSECSSF) is activated in order to generate an interrupt to the
+ MCU or MPU if needed.
+
+ (#) MCO1 (micro controller clock output), used to output HSI, HSE, CSI,LSI or LSE clock
+ (through a configurable pre-scaler).
+
+ (#) MCO2 (micro controller clock output), used to output MPUSS, AXISS, MCUSS, PLL4(PLL4_P),
+ HSE, or HSI clock (through a configurable pre-scaler).
+
+
+ [..] Sub-system clock configuration
+
+ (#) The MPUDIV divider located into RCC MPU Clock Divider Register (RCC_MPCKDIVR) can be used
+ to adjust dynamically the clock for the MPU.
+
+ (#) The AXIDIV divider located into RCC AXI Clock Divider Register (RCC_AXIDIVR) can be used
+ to adjust dynamically the clock for the AXI matrix. The value of this divider also impacts
+ the clock frequency of AHB5, AHB6, APB4 and APB5.
+
+ (#) The APB4DIV divider located into RCC APB4 Clock Divider Register (RCC_APB4DIVR) can be used
+ to adjust dynamically the clock for the APB4 bridge.
+
+ (#) In the same way, the APB5DIV divider located into RCC APB5 Clock Divider Register
+ (RCC_APB5DIVR), can be used to adjust dynamically the clock for the APB5 bridge.
+
+ (#) In the MCU clock tree, the MCUDIV divider located into RCC MCU Clock Divider Register
+ (RCC_MCUDIVR), can be used to adjust dynamically the clock for the MCU. The value of
+ this divider also impacts the clock frequency of AHB bridges, APB1, APB2 and APB3.
+
+ (#) The APB1DIV divider located into RCC APB1 Clock Divider Register (RCC_APB1DIVR), can be used
+ to adjust dynamically the clock for the APB1 bridge. Similar implementation is available for
+ APB2 and APB3.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE, PLL1, PLL2 and PLL3 and PLL4 OFF
+ * - AHB, APB Bus pre-scaler set to 1.
+ * - MCO1 and MCO2 OFF
+ * - All interrupts disabled (except Wake-up from CSTOP Interrupt Enable)
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clock
+ * - HSECSS and LSECSS
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+ uint32_t tickstart;
+
+ /* Set HSION bit to enable HSI oscillator */
+ SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSION);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while ((RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset MCO1 Configuration Register */
+ CLEAR_REG(RCC->MCO1CFGR);
+
+ /* Reset MCO2 Configuration Register */
+ CLEAR_REG(RCC->MCO2CFGR);
+
+ /* Reset MPU Clock Selection Register */
+ MODIFY_REG(RCC->MPCKSELR, (RCC_MPCKSELR_MPUSRC), RCC_MPCKSELR_MPUSRC_0);
+
+ /* Reset AXI Sub-System Clock Selection Register */
+ MODIFY_REG(RCC->ASSCKSELR, (RCC_ASSCKSELR_AXISSRC), RCC_ASSCKSELR_AXISSRC_0);
+
+ /* Reset MCU Sub-System Clock Selection Register */
+ MODIFY_REG(RCC->MSSCKSELR, (RCC_MSSCKSELR_MCUSSRC), RCC_MSSCKSELR_MCUSSRC_0);
+
+ /* Reset RCC MPU Clock Divider Register */
+ MODIFY_REG(RCC->MPCKDIVR, (RCC_MPCKDIVR_MPUDIV), RCC_MPCKDIVR_MPUDIV_1);
+
+ /* Reset RCC AXI Clock Divider Register */
+ MODIFY_REG(RCC->AXIDIVR, (RCC_AXIDIVR_AXIDIV), RCC_AXIDIVR_AXIDIV_0);
+
+ /* Reset RCC APB4 Clock Divider Register */
+ MODIFY_REG(RCC->APB4DIVR, (RCC_APB4DIVR_APB4DIV), RCC_APB4DIVR_APB4DIV_0);
+
+ /* Reset RCC APB5 Clock Divider Register */
+ MODIFY_REG(RCC->APB5DIVR, (RCC_APB5DIVR_APB5DIV), RCC_APB5DIVR_APB5DIV_0);
+
+ /* Reset RCC MCU Clock Divider Register */
+ MODIFY_REG(RCC->MCUDIVR, (RCC_MCUDIVR_MCUDIV), RCC_MCUDIVR_MCUDIV_0);
+
+ /* Reset RCC APB1 Clock Divider Register */
+ MODIFY_REG(RCC->APB1DIVR, (RCC_APB1DIVR_APB1DIV), RCC_APB1DIVR_APB1DIV_0);
+
+ /* Reset RCC APB2 Clock Divider Register */
+ MODIFY_REG(RCC->APB2DIVR, (RCC_APB2DIVR_APB2DIV), RCC_APB2DIVR_APB2DIV_0);
+
+ /* Reset RCC APB3 Clock Divider Register */
+ MODIFY_REG(RCC->APB3DIVR, (RCC_APB3DIVR_APB3DIV), RCC_APB3DIVR_APB3DIV_0);
+
+ /* Disable PLL1 outputs */
+ CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN | RCC_PLL1CR_DIVQEN |
+ RCC_PLL1CR_DIVREN);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Disable PLL1 */
+ CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while ((RCC->PLL1CR & RCC_PLL1CR_PLL1RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear remaining SSCG_CTRL bit */
+ CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL);
+
+ /* Disable PLL2 outputs */
+ CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVPEN | RCC_PLL2CR_DIVQEN |
+ RCC_PLL2CR_DIVREN);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Disable PLL2 */
+ CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while ((RCC->PLL2CR & RCC_PLL2CR_PLL2RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear remaining SSCG_CTRL bit */
+ CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL);
+
+ /* Disable PLL3 outputs */
+ CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVPEN | RCC_PLL3CR_DIVQEN |
+ RCC_PLL3CR_DIVREN);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Disable PLL3 */
+ CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while ((RCC->PLL3CR & RCC_PLL3CR_PLL3RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear remaining SSCG_CTRL bit */
+ CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL);
+
+ /* Disable PLL4 outputs */
+ CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVPEN | RCC_PLL4CR_DIVQEN |
+ RCC_PLL4CR_DIVREN);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Disable PLL4 */
+ CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while ((RCC->PLL4CR & RCC_PLL4CR_PLL4RDY) != 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear remaining SSCG_CTRL bit */
+ CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL);
+
+ /* Reset PLL 1 and 2 Ref. Clock Selection Register */
+ MODIFY_REG(RCC->RCK12SELR, (RCC_RCK12SELR_PLL12SRC), RCC_RCK12SELR_PLL12SRC_0);
+
+ /* Reset RCC PLL 3 Ref. Clock Selection Register */
+ MODIFY_REG(RCC->RCK3SELR, (RCC_RCK3SELR_PLL3SRC), RCC_RCK3SELR_PLL3SRC_0);
+
+ /* Reset PLL4 Ref. Clock Selection Register */
+ MODIFY_REG(RCC->RCK4SELR, (RCC_RCK4SELR_PLL4SRC), RCC_RCK4SELR_PLL4SRC_0);
+
+ /* Reset RCC PLL1 Configuration Register 1 */
+ WRITE_REG(RCC->PLL1CFGR1, 0x00010031U);
+
+ /* Reset RCC PLL1 Configuration Register 2 */
+ WRITE_REG(RCC->PLL1CFGR2, 0x00010100U);
+
+ /* Reset RCC PLL1 Fractional Register */
+ CLEAR_REG(RCC->PLL1FRACR);
+
+ /* Reset RCC PLL1 Clock Spreading Generator Register */
+ CLEAR_REG(RCC->PLL1CSGR);
+
+ /* Reset RCC PLL2 Configuration Register 1 */
+ WRITE_REG(RCC->PLL2CFGR1, 0x00010063U);
+
+ /* Reset RCC PLL2 Configuration Register 2 */
+ WRITE_REG(RCC->PLL2CFGR2, 0x00010101U);
+
+ /* Reset RCC PLL2 Fractional Register */
+ CLEAR_REG(RCC->PLL2FRACR);
+
+ /* Reset RCC PLL2 Clock Spreading Generator Register */
+ CLEAR_REG(RCC->PLL2CSGR);
+
+ /* Reset RCC PLL3 Configuration Register 1 */
+ WRITE_REG(RCC->PLL3CFGR1, 0x00010031U);
+
+ /* Reset RCC PLL3 Configuration Register 2 */
+ WRITE_REG(RCC->PLL3CFGR2, 0x00010101U);
+
+ /* Reset RCC PLL3 Fractional Register */
+ CLEAR_REG(RCC->PLL3FRACR);
+
+ /* Reset RCC PLL3 Clock Spreading Generator Register */
+ CLEAR_REG(RCC->PLL3CSGR);
+
+ /* Reset RCC PLL4 Configuration Register 1 */
+ WRITE_REG(RCC->PLL4CFGR1, 0x00010031U);
+
+ /* Reset RCC PLL4 Configuration Register 2 */
+ WRITE_REG(RCC->PLL4CFGR2, 0x00000000U);
+
+ /* Reset RCC PLL4 Fractional Register */
+ CLEAR_REG(RCC->PLL4FRACR);
+
+ /* Reset RCC PLL4 Clock Spreading Generator Register */
+ CLEAR_REG(RCC->PLL4CSGR);
+
+ /* Reset HSIDIV once PLLs are off */
+ CLEAR_BIT(RCC->HSICFGR, RCC_HSICFGR_HSIDIV);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSIDIV is ready */
+ while ((RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reset HSITRIM value */
+ CLEAR_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM);
+
+ /* Reset the Oscillator Enable Control registers */
+ WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON | RCC_OCENCLRR_CSION |
+ RCC_OCENCLRR_CSIKERON | RCC_OCENCLRR_DIGBYP | RCC_OCENCLRR_HSEON |
+ RCC_OCENCLRR_HSEKERON | RCC_OCENCLRR_HSEBYP);
+
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION);
+
+ /* Reset CSITRIM value */
+ CLEAR_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM);
+
+#ifdef CORE_CA7
+ /* Reset RCC Clock Source Interrupt Enable Register */
+ CLEAR_BIT(RCC->MP_CIER, (RCC_MP_CIER_LSIRDYIE | RCC_MP_CIER_LSERDYIE |
+ RCC_MP_CIER_HSIRDYIE | RCC_MP_CIER_HSERDYIE | RCC_MP_CIER_CSIRDYIE |
+ RCC_MP_CIER_PLL1DYIE | RCC_MP_CIER_PLL2DYIE | RCC_MP_CIER_PLL3DYIE |
+ RCC_MP_CIER_PLL4DYIE | RCC_MP_CIER_LSECSSIE | RCC_MP_CIER_WKUPIE));
+
+ /* Clear all RCC MPU interrupt flags */
+ SET_BIT(RCC->MP_CIFR, (RCC_MP_CIFR_LSIRDYF | RCC_MP_CIFR_LSERDYF |
+ RCC_MP_CIFR_HSIRDYF | RCC_MP_CIFR_HSERDYF | RCC_MP_CIFR_CSIRDYF |
+ RCC_MP_CIFR_PLL1DYF | RCC_MP_CIFR_PLL2DYF | RCC_MP_CIFR_PLL3DYF |
+ RCC_MP_CIFR_PLL4DYF | RCC_MP_CIFR_LSECSSF | RCC_MP_CIFR_WKUPF));
+
+ /* Clear all RCC MPU Reset Flags */
+ SET_BIT(RCC->MP_RSTSCLRR, (RCC_MP_RSTSCLRR_MPUP1RSTF |
+ RCC_MP_RSTSCLRR_MPUP0RSTF | RCC_MP_RSTSCLRR_CSTDBYRSTF |
+ RCC_MP_RSTSCLRR_STDBYRSTF | RCC_MP_RSTSCLRR_IWDG2RSTF |
+ RCC_MP_RSTSCLRR_IWDG1RSTF | RCC_MP_RSTSCLRR_MCSYSRSTF |
+ RCC_MP_RSTSCLRR_MPSYSRSTF | RCC_MP_RSTSCLRR_VCORERSTF |
+ RCC_MP_RSTSCLRR_HCSSRSTF | RCC_MP_RSTSCLRR_PADRSTF |
+ RCC_MP_RSTSCLRR_BORRSTF | RCC_MP_RSTSCLRR_PORRSTF));
+#endif
+
+#ifdef CORE_CM4
+ /* Reset RCC Clock Source Interrupt Enable Register */
+ CLEAR_BIT(RCC->MC_CIER, (RCC_MC_CIER_LSIRDYIE | RCC_MC_CIER_LSERDYIE |
+ RCC_MC_CIER_HSIRDYIE | RCC_MC_CIER_HSERDYIE | RCC_MC_CIER_CSIRDYIE |
+ RCC_MC_CIER_PLL1DYIE | RCC_MC_CIER_PLL2DYIE | RCC_MC_CIER_PLL3DYIE |
+ RCC_MC_CIER_PLL4DYIE | RCC_MC_CIER_LSECSSIE | RCC_MC_CIER_WKUPIE));
+
+ /* Clear all RCC MCU interrupt flags */
+ SET_BIT(RCC->MC_CIFR, (RCC_MC_CIFR_LSIRDYF | RCC_MC_CIFR_LSERDYF |
+ RCC_MC_CIFR_HSIRDYF | RCC_MC_CIFR_HSERDYF | RCC_MC_CIFR_CSIRDYF |
+ RCC_MC_CIFR_PLL1DYF | RCC_MC_CIFR_PLL2DYF | RCC_MC_CIFR_PLL3DYF |
+ RCC_MC_CIFR_PLL4DYF | RCC_MC_CIFR_LSECSSF | RCC_MC_CIFR_WKUPF));
+
+ /* Clear all RCC MCU Reset Flags */
+ SET_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_WWDG1RSTF |
+ RCC_MC_RSTSCLRR_IWDG2RSTF | RCC_MC_RSTSCLRR_IWDG1RSTF |
+ RCC_MC_RSTSCLRR_MCSYSRSTF | RCC_MC_RSTSCLRR_MPSYSRSTF |
+ RCC_MC_RSTSCLRR_MCURSTF | RCC_MC_RSTSCLRR_VCORERSTF |
+ RCC_MC_RSTSCLRR_HCSSRSTF | RCC_MC_RSTSCLRR_PADRSTF |
+ RCC_MC_RSTSCLRR_BORRSTF | RCC_MC_RSTSCLRR_PORRSTF);
+#endif
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RCC Oscillators according to the specified parameters in the
+ * RCC_OscInitTypeDef.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC Oscillators.
+ * @note The PLL is not disabled when used as system clock.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef result = HAL_OK;
+
+ /* Check Null pointer */
+ if (RCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+ /*------------------------------- HSE Configuration ------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+ /* When the HSE is used somewhere in the system it will not be disabled */
+ if (IS_HSE_IN_USE())
+ {
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Configure HSE oscillator */
+ result = HAL_RCC_HSEConfig(RCC_OscInitStruct->HSEState);
+ if (result != HAL_OK)
+ {
+ return result;
+ }
+ }
+ }
+ /*----------------------------- HSI Configuration --------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+ assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+ assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDivValue));
+
+ /* When the HSI is used as system clock it will not disabled */
+ if (IS_HSI_IN_USE())
+ {
+ /* When HSI is used as system clock it will not disabled */
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+
+ /* It is not allowed to change HSIDIV if HSI is currently used as
+ * reference clock for a PLL
+ */
+ if (((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) ||
+ ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY)) &&
+ ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY))))) &&
+ ((__HAL_RCC_GET_PLL3_SOURCE() != RCC_PLL3SOURCE_HSI) ||
+ (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY))) &&
+ ((__HAL_RCC_GET_PLL4_SOURCE() != RCC_PLL4SOURCE_HSI) ||
+ (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY))))
+ {
+ /* Update HSIDIV value */
+ __HAL_RCC_HSI_DIV(RCC_OscInitStruct->HSIDivValue);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSIDIV is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
+
+ /* Adapt Systick interrupt period */
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Check the HSI State */
+ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Update HSIDIV value */
+ __HAL_RCC_HSI_DIV(RCC_OscInitStruct->HSIDivValue);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSIDIV is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (HSI). */
+ __HAL_RCC_HSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*----------------------------- CSI Configuration --------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
+ assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
+
+ /* When the CSI is used as system clock it will not disabled */
+ if (IS_CSI_IN_USE())
+ {
+ /* When CSI is used as system clock it will not disabled */
+ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+ {
+ return HAL_ERROR;
+ }
+ /* Otherwise, just the calibration is allowed */
+ else
+ {
+ /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ }
+ }
+ else
+ {
+ /* Check the CSI State */
+ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
+ {
+ /* Enable the Internal High Speed oscillator (CSI). */
+ __HAL_RCC_CSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till CSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ }
+ else
+ {
+ /* Disable the Internal High Speed oscillator (CSI). */
+ __HAL_RCC_CSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till CSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ }
+ /*------------------------------ LSI Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+ /* Check the LSI State */
+ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
+ {
+ /* Enable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable the Internal Low Speed oscillator (LSI). */
+ __HAL_RCC_LSI_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSI is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+
+ /*------------------------------ LSE Configuration -------------------------*/
+ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while ((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ result = HAL_RCC_LSEConfig(RCC_OscInitStruct->LSEState);
+ if (result != HAL_OK)
+ {
+ return result;
+ }
+
+ } /* Close LSE Configuration */
+
+ /*-------------------------------- PLL Configuration -----------------------*/
+
+ /* Configure PLL1 */
+ result = RCC_PLL1_Config(&(RCC_OscInitStruct->PLL));
+ if (result != HAL_OK)
+ {
+ return result;
+ }
+
+ /* Configure PLL2 */
+ result = RCCEx_PLL2_Config(&(RCC_OscInitStruct->PLL2));
+ if (result != HAL_OK)
+ {
+ return result;
+ }
+
+ /* Configure PLL3 */
+ result = RCCEx_PLL3_Config(&(RCC_OscInitStruct->PLL3));
+ if (result != HAL_OK)
+ {
+ return result;
+ }
+
+ /* Configure PLL4 */
+ result = RCCEx_PLL4_Config(&(RCC_OscInitStruct->PLL4));
+ if (result != HAL_OK)
+ {
+ return result;
+ }
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the RCC HSE Oscillator according to the specified
+ * parameter State
+ * @note Beware HSE oscillator is not used as clock before using this function.
+ * If this is the case, you have to select another source clock for item
+ * using HSE then change the HSE state (Eg.: disable it).
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note This function reset the CSSON bit, so if the clock security system(CSS)
+ * was previously enabled you have to enable it again after calling this
+ * function.
+ * @param State contains the configuration for the RCC HSE Oscillator.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: turn OFF the HSE oscillator
+ * @arg RCC_HSE_ON: turn ON the HSE oscillator using an external
+ * crystal/ceramic resonator
+ * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external
+ * clock using a low-swing analog signal provided to OSC_IN
+ * @arg RCC_HSE_BYPASS_DIG: HSE oscillator bypassed with external
+ * clock using a full-swing digital signal provided to OSC_IN
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_HSEConfig(uint32_t State)
+{
+ uint32_t tickstart;
+
+ /* Check parameter */
+ assert_param(IS_RCC_HSE(State));
+
+ /* Disable HSEON before configuring the HSE --------------*/
+ WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEON);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is disabled */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear remaining bits */
+ WRITE_REG(RCC->OCENCLRR, (RCC_OCENCLRR_DIGBYP | RCC_OCENSETR_HSEBYP));
+
+ /* Enable HSE if needed ---------------------------------------*/
+ if (State != RCC_HSE_OFF)
+ {
+ if (State == RCC_HSE_BYPASS)
+ {
+ SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEBYP);
+ }
+ else if (State == RCC_HSE_BYPASS_DIG)
+ {
+ SET_BIT(RCC->OCENSETR, RCC_OCENCLRR_DIGBYP);
+ SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEBYP);
+ }
+
+ /* Enable oscillator */
+ SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEON);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till HSE is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RCC External Low Speed oscillator (LSE) according
+ * to the specified parameter State
+ * @note Beware LSE oscillator is not used as clock before using this function.
+ * If this is the case, you have to select another source clock for item
+ * using LSE then change the LSE state (Eg.: disable it).
+ * @note As the LSE is in the Backup domain and write access is denied to
+ * this domain after reset, you have to enable write access using
+ * HAL_PWR_EnableBkUpAccess() function (set PWR_CR1_DBP bit) before
+ * to configure the LSE (to be done once after reset).
+ * @param State contains the configuration for the RCC LSE Oscillator
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: turn OFF the LSE oscillator
+ * @arg RCC_LSE_ON: turn ON the LSE oscillator using an external
+ * crystal/ceramic resonator
+ * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
+ * using a low-swing analog signal provided to OSC32_IN
+ * @arg RCC_LSE_BYPASS_DIG: LSE oscillator bypassed with external
+ * clock using a full-swing digital signal provided to OSC32_IN
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCC_LSEConfig(uint32_t State)
+{
+ uint32_t tickstart;
+
+ /* Check parameter */
+ assert_param(IS_RCC_LSE(State));
+
+ /* Turning LSE off is needed before configuring */
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is disabled */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear remaining bits */
+ CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP));
+
+ /* Enable LSE if needed */
+ if (State != RCC_LSE_OFF)
+ {
+ if (State == RCC_LSE_BYPASS)
+ {
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+ }
+ else if (State == RCC_LSE_BYPASS_DIG)
+ {
+ SET_BIT(RCC->BDCR, RCC_BDCR_DIGBYP);
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+ }
+
+ /* Enable oscillator */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till LSE is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ } /* Enable LSE if needed */
+
+ return HAL_OK;
+}
+
+HAL_StatusTypeDef RCC_PLL1_Config(RCC_PLLInitTypeDef *pll1)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(pll1->PLLState));
+ if ((pll1->PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
+ if (!__IS_PLL1_IN_USE()) /* If not used then */
+ {
+ if ((pll1->PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLMODE(pll1->PLLMODE));
+ assert_param(IS_RCC_PLL12SOURCE(pll1->PLLSource));
+ assert_param(IS_RCC_PLLM1_VALUE(pll1->PLLM));
+ if (pll1->PLLMODE == RCC_PLL_FRACTIONAL)
+ {
+ assert_param(IS_RCC_PLLN1_FRAC_VALUE(pll1->PLLN));
+ }
+ else
+ {
+ assert_param(IS_RCC_PLLN1_INT_VALUE(pll1->PLLN));
+ }
+ assert_param(IS_RCC_PLLP1_VALUE(pll1->PLLP));
+ assert_param(IS_RCC_PLLQ1_VALUE(pll1->PLLQ));
+ assert_param(IS_RCC_PLLR1_VALUE(pll1->PLLR));
+
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL1CLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL1_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+
+ /*The PLL configuration below must be done before enabling the PLL:
+ -Selection of PLL clock entry (HSI or HSE)
+ -Frequency input range (PLLxRGE)
+ -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
+ Once the PLL is enabled, these parameters can not be changed.
+ If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
+ PLLxRDY flag to be at 0.
+ The PLL configuration below can be done at any time:
+ -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
+ -Fractional Division Enable (PLLxFRACNEN)
+ -Fractional Division factor (FRACNx)*/
+
+ /* Do not change pll src if already in use */
+ if (__IS_PLL2_IN_USE())
+ {
+ if (pll1->PLLSource != __HAL_RCC_GET_PLL12_SOURCE())
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Configure PLL1 and PLL2 clock source */
+ __HAL_RCC_PLL12_SOURCE(pll1->PLLSource);
+ }
+
+ /* Wait till PLL SOURCE is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL12SRCRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the PLL1 multiplication and division factors. */
+ __HAL_RCC_PLL1_CONFIG(
+ pll1->PLLM,
+ pll1->PLLN,
+ pll1->PLLP,
+ pll1->PLLQ,
+ pll1->PLLR);
+
+
+ /* Configure the Fractional Divider */
+ __HAL_RCC_PLL1FRACV_DISABLE(); /*Set FRACLE to '0' */
+ /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
+ if ((pll1->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll1->PLLMODE == RCC_PLL_INTEGER))
+ {
+ /* Do not use the fractional divider */
+ __HAL_RCC_PLL1FRACV_CONFIG(0U); /* Set FRACV to '0' */
+ }
+ else
+ {
+ /* Configure PLL PLL1FRACV in fractional mode*/
+ __HAL_RCC_PLL1FRACV_CONFIG(pll1->PLLFRACV);
+ }
+ __HAL_RCC_PLL1FRACV_ENABLE(); /* Set FRACLE to 1 */
+
+
+ /* Configure the Spread Control */
+ if (pll1->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
+ {
+ assert_param(IS_RCC_INC_STEP(pll1->INC_STEP));
+ assert_param(IS_RCC_SSCG_MODE(pll1->SSCG_MODE));
+ assert_param(IS_RCC_RPDFN_DIS(pll1->RPDFN_DIS));
+ assert_param(IS_RCC_TPDFN_DIS(pll1->TPDFN_DIS));
+ assert_param(IS_RCC_MOD_PER(pll1->MOD_PER));
+
+ __HAL_RCC_PLL1CSGCONFIG(pll1->MOD_PER, pll1->TPDFN_DIS, pll1->RPDFN_DIS,
+ pll1->SSCG_MODE, pll1->INC_STEP);
+
+ __HAL_RCC_PLL1_SSMODE_ENABLE();
+ }
+ else
+ {
+ __HAL_RCC_PLL1_SSMODE_DISABLE();
+ }
+
+ /* Enable the PLL1. */
+ __HAL_RCC_PLL1_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Enable post-dividers */
+ __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
+ }
+ else
+ {
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL1CLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
+ /* Disable the PLL1. */
+ __HAL_RCC_PLL1_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+
+}
+
+
+
+/**
+ * @brief Initializes the MPU,AXI, AHB and APB busses clocks according to the specified
+ * parameters in the RCC_ClkInitStruct.
+ * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * contains the configuration information for the RCC peripheral.
+ *
+ * @note The SystemCoreClock CCSIS variable is used to store System Clock Frequency
+ * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ *
+ * @note The HSI is used (enabled by hardware) as system clock source after
+ * startup from Reset, wake-up from STOP and STANDBY mode, or in case
+ * of failure of the HSE used directly or indirectly as system clock
+ * (if the Clock Security System CSS is enabled).
+ *
+ * @note A switch from one clock source to another occurs only if the target
+ * clock source is ready (clock stable after startup delay or PLL locked).
+ * If a clock source which is not yet ready is selected, the switch will
+ * occur when the clock source will be ready.
+ *
+ * @note Depending on the device voltage range, the software has to set correctly
+ * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+ * (for more details refer to section above "Initialization/de-initialization functions")
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct)
+{
+
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if (RCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ assert_param(IS_RCC_CLOCKTYPETYPE(RCC_ClkInitStruct->ClockType));
+
+ /* Configure MPU block if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_MPU) == RCC_CLOCKTYPE_MPU)
+ {
+ status = RCC_MPUConfig(&(RCC_ClkInitStruct->MPUInit));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ }
+
+ /* Configure AXISS block if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_ACLK) == RCC_CLOCKTYPE_ACLK)
+ {
+ status = RCC_AXISSConfig(&(RCC_ClkInitStruct->AXISSInit));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ }
+
+ /* Configure MCU block if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ {
+ status = RCC_MCUConfig(&(RCC_ClkInitStruct->MCUInit));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ }
+
+ /* Configure APB4 divisor if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4)
+ {
+ assert_param(IS_RCC_APB4DIV(RCC_ClkInitStruct->APB4_Div));
+ /* Set APB4 division factor */
+ __HAL_RCC_APB4_DIV(RCC_ClkInitStruct->APB4_Div);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till APB4 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB4DIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure APB5 divisor if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5)
+ {
+ assert_param(IS_RCC_APB5DIV(RCC_ClkInitStruct->APB5_Div));
+ /* Set APB5 division factor */
+ __HAL_RCC_APB5_DIV(RCC_ClkInitStruct->APB5_Div);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till APB5 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB5DIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure APB1 divisor if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ assert_param(IS_RCC_APB1DIV(RCC_ClkInitStruct->APB1_Div));
+ /* Set APB1 division factor */
+ __HAL_RCC_APB1_DIV(RCC_ClkInitStruct->APB1_Div);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till APB1 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB1DIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure APB2 divisor if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ assert_param(IS_RCC_APB2DIV(RCC_ClkInitStruct->APB2_Div));
+ /* Set APB2 division factor */
+ __HAL_RCC_APB2_DIV(RCC_ClkInitStruct->APB2_Div);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till APB2 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB2DIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Configure APB3 divisor if needed */
+ if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
+ {
+ assert_param(IS_RCC_APB3DIV(RCC_ClkInitStruct->APB3_Div));
+ /* Set APB3 division factor */
+ __HAL_RCC_APB3_DIV(RCC_ClkInitStruct->APB3_Div);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till APB3 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB3DIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+HAL_StatusTypeDef RCC_MPUConfig(RCC_MPUInitTypeDef *RCC_MPUInitStruct)
+{
+ uint32_t tickstart;
+
+ assert_param(IS_RCC_MPUSOURCE(RCC_MPUInitStruct->MPU_Clock));
+
+ /* Ensure clock source is ready*/
+ switch (RCC_MPUInitStruct->MPU_Clock)
+ {
+ case (RCC_MPUSOURCE_HSI):
+ {
+ /* Check the HSI ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_MPUSOURCE_HSE):
+ {
+ /* Check the HSE ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_MPUSOURCE_PLL1):
+ {
+ /* Check the PLL1 ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_MPUSOURCE_MPUDIV):
+ {
+ assert_param(IS_RCC_MPUDIV(RCC_MPUInitStruct->MPU_Div));
+
+ /* Check the PLL1 ready flag (as PLL1_P is the MPUDIV source */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set MPU division factor */
+ __HAL_RCC_MPU_DIV(RCC_MPUInitStruct->MPU_Div);
+
+ break;
+ }
+
+ default:
+ /* This case is impossible */
+ return HAL_ERROR;
+
+ }
+
+ /* Set MPU clock source */
+ __HAL_RCC_MPU_SOURCE(RCC_MPUInitStruct->MPU_Clock);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till MPU is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+#ifdef CORE_CA7
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick(uwTickPrio);
+#endif
+
+ return HAL_OK;
+}
+
+
+HAL_StatusTypeDef RCC_AXISSConfig(RCC_AXISSInitTypeDef *RCC_AXISSInitStruct)
+{
+ uint32_t tickstart;
+
+ assert_param(IS_RCC_AXISSOURCE(RCC_AXISSInitStruct->AXI_Clock));
+ assert_param(IS_RCC_AXIDIV(RCC_AXISSInitStruct->AXI_Div));
+
+ /* Ensure clock source is ready*/
+ switch (RCC_AXISSInitStruct->AXI_Clock)
+ {
+ case (RCC_AXISSOURCE_HSI):
+ {
+ /* Check the HSI ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_AXISSOURCE_HSE):
+ {
+ /* Check the HSI ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_AXISSOURCE_PLL2):
+ {
+ /* Check the HSI ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ default:
+ break;
+
+ }
+
+ /* Set AXISS clock source */
+ __HAL_RCC_AXISS_SOURCE(RCC_AXISSInitStruct->AXI_Clock);
+
+ if (RCC_AXISSInitStruct->AXI_Clock != RCC_AXISSOURCE_OFF)
+ {
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till AXISS is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ // RCC_AXISSOURCE_OFF case
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till AXISS is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set AXISS division factor */
+ __HAL_RCC_AXI_DIV(RCC_AXISSInitStruct->AXI_Div);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till AXISS is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXIDIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+HAL_StatusTypeDef RCC_MCUConfig(RCC_MCUInitTypeDef *MCUInitStruct)
+{
+ uint32_t tickstart;
+
+ assert_param(IS_RCC_MCUSSOURCE(MCUInitStruct->MCU_Clock));
+ assert_param(IS_RCC_MCUDIV(MCUInitStruct->MCU_Div));
+
+ /* Ensure clock source is ready*/
+ switch (MCUInitStruct->MCU_Clock)
+ {
+ case (RCC_MCUSSOURCE_HSI):
+ {
+ /* Check the HSI ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_MCUSSOURCE_HSE):
+ {
+ /* Check the HSE ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_MCUSSOURCE_CSI):
+ {
+ /* Check the HSI ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ case (RCC_MCUSSOURCE_PLL3):
+ {
+ /* Check the HSI ready flag */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+
+ default:
+ break;
+
+ }
+
+ /* Set MCU clock source */
+ __HAL_RCC_MCU_SOURCE(MCUInitStruct->MCU_Clock);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till MCU is ready */
+
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+#ifdef CORE_CM4
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick(uwTickPrio);
+#endif
+
+ /* Set MCU division factor */
+ __HAL_RCC_MCU_DIV(MCUInitStruct->MCU_Div);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till MCU is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUDIVRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+#ifdef CORE_CM4
+ /* Update the SystemCoreClock global variable */
+ SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
+
+ /* Configure the source of time base considering new system clocks settings*/
+ HAL_InitTick(uwTickPrio);
+#endif
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ @endverbatim
+ * @{
+ */
+
+/**
+ * @brief Selects the clock source to output on MCO1 pin or on MCO2 pin
+ * @note BSP_MCO_Init shall be called before to configure output pins depending on the board
+ * @param RCC_MCOx: specifies the output direction for the clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1: Clock source to output on MCO1
+ * @arg RCC_MCO2: Clock source to output on MCO2
+ * @param RCC_MCOSource: specifies the clock source to output.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 clock entry
+ * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 clock entry
+ * @arg RCC_MCO1SOURCE_CSI: CSI clock selected as MCO1 clock entry
+ * @arg RCC_MCO1SOURCE_LSI: LSI clock selected as MCO1 clock entry
+ * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 clock entry
+ * @arg RCC_MCO2SOURCE_MPU: MPU clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_AXI: AXI clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_MCU: MCU clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_PLL4: PLL4 clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 clock entry
+ * @arg RCC_MCO2SOURCE_HSI: HSI clock selected as MCO2 clock entry
+ *
+ * @param RCC_MCODiv: specifies the MCOx prescaler.
+ * This parameter can be one of the following values:
+ * @arg RCC_MCODIV_1 up to RCC_MCODIV_16 : divider applied to MCOx clock
+ * @retval None
+ */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCOx));
+ assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+ /* RCC_MCO1 */
+ if (RCC_MCOx == RCC_MCO1)
+ {
+ assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+ /* Configure MCO1 */
+ __HAL_RCC_MCO1_CONFIGURE(RCC_MCOSource, RCC_MCODiv);
+
+ /* Enable MCO1 output */
+ __HAL_RCC_MCO1_ENABLE();
+ }
+ else
+ {
+ assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+ /* Configure MCO2 */
+ __HAL_RCC_MCO2_CONFIGURE(RCC_MCOSource, RCC_MCODiv);
+
+ /* Enable MCO2 output */
+ __HAL_RCC_MCO2_ENABLE();
+ }
+}
+
+
+/**
+ * @brief Enables the HSE Clock Security System.
+ * @note If a failure is detected on the HSE:
+ * - The RCC generates a system reset (nreset). The flag HCSSRSTF is set in order to
+ * allow the application to identify the reset root cause.
+ * - A failure event is generated (rcc_hsecss_fail). This event is connected to the TAMP
+ * block, allowing the protection of backup registers and BKPSRAM.
+ *
+ * @note HSECSSON can be activated even when the HSEON is set to ‘0’. The CSS on HSE will be
+ * enabled by the hardware when the HSE is enabled and ready, and HSECSSON is set to ‘1’.
+ *
+ * @note The HSECSS is disabled when the HSE is disabled (i.e. when the system is STOP or
+ * STANDBY).
+ *
+ * @note It is not possible to clear the bit HSECSSON by software.
+ *
+ * @note The bit HSECSSON will be cleared by the hardware when a system reset occurs or when
+ the system enters in STANDBY mode
+ * @retval None
+ */
+void HAL_RCC_EnableHSECSS(void)
+{
+ SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSECSSON);
+}
+
+/**
+ * @brief Configures the RCC_OscInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * will be configured.
+ * @retval None
+ */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+{
+
+ /* Set all possible values for the Oscillator type parameter ---------------*/
+ RCC_OscInitStruct->OscillatorType =
+ RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI |
+ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+ /* Get the HSE configuration -----------------------------------------------*/
+ if ((RCC->OCENSETR & RCC_OCENSETR_HSEBYP) == RCC_OCENSETR_HSEBYP)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+ }
+ else if ((RCC->OCENSETR & RCC_OCENSETR_HSEON) == RCC_OCENSETR_HSEON)
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+ }
+
+ /* Get the CSI configuration -----------------------------------------------*/
+ if ((RCC->OCENSETR & RCC_OCENSETR_CSION) == RCC_OCENSETR_CSION)
+ {
+ RCC_OscInitStruct->CSIState = RCC_CSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
+ }
+
+ RCC_OscInitStruct->CSICalibrationValue =
+ (uint32_t)((RCC->CSICFGR & RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+
+
+ /* Get the HSI configuration -----------------------------------------------*/
+ if ((RCC->OCENSETR & RCC_OCENSETR_HSION) == RCC_OCENSETR_HSION)
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+ }
+
+ RCC_OscInitStruct->HSICalibrationValue =
+ (uint32_t)((RCC->HSICFGR & RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+ }
+ else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+ }
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ if ((RCC->RDLSICR & RCC_RDLSICR_LSION) == RCC_RDLSICR_LSION)
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+ }
+
+
+ /* Get the PLL1 configuration -----------------------------------------------*/
+ if ((RCC->PLL1CR & RCC_PLL1CR_PLLON) == RCC_PLL1CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+ }
+
+ RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC);
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVM1) >> RCC_PLL1CFGR1_DIVM1_Pos) + 1;
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVN) >> RCC_PLL1CFGR1_DIVN_Pos) + 1;
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVR) >> RCC_PLL1CFGR2_DIVR_Pos) + 1;
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVP) >> RCC_PLL1CFGR2_DIVP_Pos) + 1;
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVQ) >> RCC_PLL1CFGR2_DIVQ_Pos) + 1;
+ RCC_OscInitStruct->PLL.PLLFRACV = (uint32_t)((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACV) >> RCC_PLL1FRACR_FRACV_Pos);
+
+ if ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACV) == 0)
+ {
+ if ((RCC->PLL1CR & RCC_PLL1CR_SSCG_CTRL) == RCC_PLL1CR_SSCG_CTRL)
+ {
+ //SSMODE enabled
+ RCC_OscInitStruct->PLL.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLMODE = RCC_PLL_INTEGER;
+ }
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL.PLLMODE = RCC_PLL_FRACTIONAL;
+ }
+
+ RCC_OscInitStruct->PLL.MOD_PER = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_MOD_PER);
+ RCC_OscInitStruct->PLL.TPDFN_DIS = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_TPDFN_DIS);
+ RCC_OscInitStruct->PLL.RPDFN_DIS = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_RPDFN_DIS);
+ RCC_OscInitStruct->PLL.SSCG_MODE = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_SSCG_MODE);
+ RCC_OscInitStruct->PLL.INC_STEP = (uint32_t)((RCC->PLL1CSGR & RCC_PLL1CSGR_INC_STEP) >> RCC_PLL1CSGR_INC_STEP_Pos);
+
+
+ /* Get the PLL2 configuration -----------------------------------------------*/
+ if ((RCC->PLL2CR & RCC_PLL2CR_PLLON) == RCC_PLL2CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL2.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL2.PLLState = RCC_PLL_OFF;
+ }
+
+ RCC_OscInitStruct->PLL2.PLLSource = (uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC);
+ RCC_OscInitStruct->PLL2.PLLM = (uint32_t)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_DIVM2_Pos) + 1;
+ RCC_OscInitStruct->PLL2.PLLN = (uint32_t)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) >> RCC_PLL2CFGR1_DIVN_Pos) + 1;
+ RCC_OscInitStruct->PLL2.PLLR = (uint32_t)((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVR) >> RCC_PLL2CFGR2_DIVR_Pos) + 1;
+ RCC_OscInitStruct->PLL2.PLLP = (uint32_t)((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVP) >> RCC_PLL2CFGR2_DIVP_Pos) + 1;
+ RCC_OscInitStruct->PLL2.PLLQ = (uint32_t)((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVQ) >> RCC_PLL2CFGR2_DIVQ_Pos) + 1;
+ RCC_OscInitStruct->PLL2.PLLFRACV = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACV) >> RCC_PLL2FRACR_FRACV_Pos);
+
+ if ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACV) == 0)
+ {
+ if ((RCC->PLL2CR & RCC_PLL2CR_SSCG_CTRL) == RCC_PLL2CR_SSCG_CTRL)
+ {
+ //SSMODE enabled
+ RCC_OscInitStruct->PLL2.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL2.PLLMODE = RCC_PLL_INTEGER;
+ }
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
+ }
+
+ RCC_OscInitStruct->PLL2.MOD_PER = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_MOD_PER);
+ RCC_OscInitStruct->PLL2.TPDFN_DIS = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_TPDFN_DIS);
+ RCC_OscInitStruct->PLL2.RPDFN_DIS = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_RPDFN_DIS);
+ RCC_OscInitStruct->PLL2.SSCG_MODE = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_SSCG_MODE);
+ RCC_OscInitStruct->PLL2.INC_STEP = (uint32_t)((RCC->PLL2CSGR & RCC_PLL2CSGR_INC_STEP) >> RCC_PLL2CSGR_INC_STEP_Pos);
+
+
+ /* Get the PLL3 configuration -----------------------------------------------*/
+ if ((RCC->PLL3CR & RCC_PLL3CR_PLLON) == RCC_PLL3CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL3.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL3.PLLState = RCC_PLL_OFF;
+ }
+
+ RCC_OscInitStruct->PLL3.PLLSource = (uint32_t)(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
+ RCC_OscInitStruct->PLL3.PLLM = (uint32_t)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1;
+ RCC_OscInitStruct->PLL3.PLLN = (uint32_t)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) >> RCC_PLL3CFGR1_DIVN_Pos) + 1;
+ RCC_OscInitStruct->PLL3.PLLR = (uint32_t)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVR) >> RCC_PLL3CFGR2_DIVR_Pos) + 1;
+ RCC_OscInitStruct->PLL3.PLLP = (uint32_t)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) >> RCC_PLL3CFGR2_DIVP_Pos) + 1;
+ RCC_OscInitStruct->PLL3.PLLQ = (uint32_t)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVQ) >> RCC_PLL3CFGR2_DIVQ_Pos) + 1;
+ RCC_OscInitStruct->PLL3.PLLRGE = (uint32_t)(RCC->PLL3CFGR1 & RCC_PLL3CFGR1_IFRGE);
+ RCC_OscInitStruct->PLL3.PLLFRACV = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> RCC_PLL3FRACR_FRACV_Pos);
+
+ if ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) == 0)
+ {
+ if ((RCC->PLL3CR & RCC_PLL3CR_SSCG_CTRL) == RCC_PLL3CR_SSCG_CTRL)
+ {
+ //SSMODE enabled
+ RCC_OscInitStruct->PLL3.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL3.PLLMODE = RCC_PLL_INTEGER;
+ }
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
+ }
+
+ RCC_OscInitStruct->PLL3.MOD_PER = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_MOD_PER);
+ RCC_OscInitStruct->PLL3.TPDFN_DIS = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_TPDFN_DIS);
+ RCC_OscInitStruct->PLL3.RPDFN_DIS = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_RPDFN_DIS);
+ RCC_OscInitStruct->PLL3.SSCG_MODE = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_SSCG_MODE);
+ RCC_OscInitStruct->PLL3.INC_STEP = (uint32_t)((RCC->PLL3CSGR & RCC_PLL3CSGR_INC_STEP) >> RCC_PLL3CSGR_INC_STEP_Pos);
+
+ /* Get the PLL4 configuration -----------------------------------------------*/
+ if ((RCC->PLL4CR & RCC_PLL4CR_PLLON) == RCC_PLL4CR_PLLON)
+ {
+ RCC_OscInitStruct->PLL4.PLLState = RCC_PLL_ON;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL4.PLLState = RCC_PLL_OFF;
+ }
+
+ RCC_OscInitStruct->PLL4.PLLSource = (uint32_t)(RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRC);
+ RCC_OscInitStruct->PLL4.PLLM = (uint32_t)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_DIVM4_Pos) + 1;
+ RCC_OscInitStruct->PLL4.PLLN = (uint32_t)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) >> RCC_PLL4CFGR1_DIVN_Pos) + 1;
+ RCC_OscInitStruct->PLL4.PLLR = (uint32_t)((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVR) >> RCC_PLL4CFGR2_DIVR_Pos) + 1;
+ RCC_OscInitStruct->PLL4.PLLP = (uint32_t)((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVP) >> RCC_PLL4CFGR2_DIVP_Pos) + 1;
+ RCC_OscInitStruct->PLL4.PLLQ = (uint32_t)((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVQ) >> RCC_PLL4CFGR2_DIVQ_Pos) + 1;
+ RCC_OscInitStruct->PLL4.PLLRGE = (uint32_t)(RCC->PLL4CFGR1 & RCC_PLL4CFGR1_IFRGE);
+ RCC_OscInitStruct->PLL4.PLLFRACV = (uint32_t)((RCC->PLL4FRACR & RCC_PLL4FRACR_FRACV) >> RCC_PLL4FRACR_FRACV_Pos);
+
+ if ((RCC->PLL4FRACR & RCC_PLL4FRACR_FRACV) == 0)
+ {
+ if ((RCC->PLL4CR & RCC_PLL4CR_SSCG_CTRL) == RCC_PLL4CR_SSCG_CTRL)
+ {
+ //SSMODE enabled
+ RCC_OscInitStruct->PLL4.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL4.PLLMODE = RCC_PLL_INTEGER;
+ }
+ }
+ else
+ {
+ RCC_OscInitStruct->PLL4.PLLMODE = RCC_PLL_FRACTIONAL;
+ }
+
+ RCC_OscInitStruct->PLL4.MOD_PER = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_MOD_PER);
+ RCC_OscInitStruct->PLL4.TPDFN_DIS = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_TPDFN_DIS);
+ RCC_OscInitStruct->PLL4.RPDFN_DIS = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_RPDFN_DIS);
+ RCC_OscInitStruct->PLL4.SSCG_MODE = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_SSCG_MODE);
+ RCC_OscInitStruct->PLL4.INC_STEP = (uint32_t)((RCC->PLL4CSGR & RCC_PLL4CSGR_INC_STEP) >> RCC_PLL4CSGR_INC_STEP_Pos);
+
+}
+
+/**
+ * @brief Configures the RCC_ClkInitStruct according to the internal
+ * RCC configuration registers.
+ * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * will be configured.
+ * @param pFLatency: Pointer on the Flash Latency.
+ * @retval None
+ */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+ /* Prevent unused argument compilation warning */
+ UNUSED(pFLatency);
+
+ /* Set all possible values for the Clock type parameter --------------------*/
+ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_MPU | RCC_CLOCKTYPE_ACLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK4 |
+ RCC_CLOCKTYPE_PCLK5 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+
+ RCC_ClkInitStruct->MPUInit.MPU_Clock = __HAL_RCC_GET_MPU_SOURCE();
+ RCC_ClkInitStruct->MPUInit.MPU_Div = __HAL_RCC_GET_MPU_DIV();
+
+ RCC_ClkInitStruct->AXISSInit.AXI_Clock = __HAL_RCC_GET_AXIS_SOURCE();
+ RCC_ClkInitStruct->AXISSInit.AXI_Div = __HAL_RCC_GET_AXI_DIV();
+
+ RCC_ClkInitStruct->MCUInit.MCU_Clock = __HAL_RCC_GET_MCU_SOURCE();
+ RCC_ClkInitStruct->MCUInit.MCU_Div = __HAL_RCC_GET_MCU_DIV();
+
+ RCC_ClkInitStruct->APB1_Div = __HAL_RCC_GET_APB1_DIV();
+ RCC_ClkInitStruct->APB2_Div = __HAL_RCC_GET_APB2_DIV();
+ RCC_ClkInitStruct->APB3_Div = __HAL_RCC_GET_APB3_DIV();
+ RCC_ClkInitStruct->APB4_Div = __HAL_RCC_GET_APB4_DIV();
+ RCC_ClkInitStruct->APB5_Div = __HAL_RCC_GET_APB5_DIV();
+}
+
+
+/**
+* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
+ * @note The PLL1 clock frequencies computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note The function returns values based on HSE_VALUE or HSI_VALUE Value multiplied/divided by the PLL factors.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time PLL1CLK changes, this function must be called to update the
+ * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @param PLL1_Clocks structure.
+ * @retval None
+ */
+__weak void HAL_RCC_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
+{
+ uint32_t pllsource = 0U, pll1m = 1U, pll1fracen = 0U, hsivalue = 0U;
+ float fracn1, pll1vco = 0;
+
+ pllsource = __HAL_RCC_GET_PLL12_SOURCE();
+ pll1m = ((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVM1) >> RCC_PLL1CFGR1_DIVM1_Pos) + 1U;
+ pll1fracen = (RCC->PLL1FRACR & RCC_PLL1FRACR_FRACLE) >> RCC_PLL1FRACR_FRACLE_Pos;
+ fracn1 = (float)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACV) >> RCC_PLL1FRACR_FRACV_Pos));
+ pll1vco = (float)((float)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVN) + 1U) + (fracn1 / (float)0x1FFF)); //Intermediary value
+ switch (pllsource)
+ {
+ case RCC_PLL12SOURCE_HSI: /* HSI used as PLL clock source */
+
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
+ {
+ hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ pll1vco *= (float)(hsivalue / pll1m);
+ }
+ else
+ {
+ pll1vco *= (float)(HSI_VALUE / pll1m);
+ }
+ break;
+
+ case RCC_PLL12SOURCE_HSE: /* HSE used as PLL clock source */
+ pll1vco *= (float)(HSE_VALUE / pll1m);
+ break;
+
+ case RCC_PLL12SOURCE_OFF: /* No clock source for PLL */
+ pll1vco = 0;
+ break;
+
+ default:
+ pll1vco = 0;
+ break;
+ }
+
+ PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(pll1vco / ((float)(((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVP) >> RCC_PLL1CFGR2_DIVP_Pos) + 1U)));
+ PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(pll1vco / ((float)(((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVQ) >> RCC_PLL1CFGR2_DIVQ_Pos) + 1U)));
+ PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(pll1vco / ((float)(((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVR) >> RCC_PLL1CFGR2_DIVR_Pos) + 1U)));
+}
+
+
+/**
+* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
+ * @note The PLL2 clock frequencies computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note The function returns values based on HSE_VALUE or HSI_VALUE Value multiplied/divided by the PLL factors.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time PLL2CLK changes, this function must be called to update the
+ * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @param PLL2_Clocks structure.
+ * @retval None
+ */
+__weak void HAL_RCC_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
+{
+ uint32_t pllsource = 0U, pll2m = 1U, pll2fracen = 0U, hsivalue = 0U;
+ float fracn1, pll2vco = 0;
+
+ pllsource = __HAL_RCC_GET_PLL12_SOURCE();
+ pll2m = ((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_DIVM2_Pos) + 1U;
+ pll2fracen = (RCC->PLL2FRACR & RCC_PLL2FRACR_FRACLE) >> RCC_PLL2FRACR_FRACLE_Pos;
+ fracn1 = (float)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACV) >> RCC_PLL2FRACR_FRACV_Pos));
+ pll2vco = (float)((float)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) + 1U) + (fracn1 / (float)0x1FFF)); //Intermediary value
+ switch (pllsource)
+ {
+ case RCC_PLL12SOURCE_HSI: /* HSI used as PLL clock source */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
+ {
+ hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ pll2vco *= (float)(hsivalue / pll2m);
+ }
+ else
+ {
+ pll2vco *= (float)(HSI_VALUE / pll2m);
+ }
+ break;
+
+ case RCC_PLL12SOURCE_HSE: /* HSE used as PLL clock source */
+ pll2vco *= (float)(HSE_VALUE / pll2m);
+ break;
+
+ case RCC_PLL12SOURCE_OFF: /* No clock source for PLL */
+ pll2vco = 0;
+ break;
+
+ default:
+ pll2vco = 0;
+ break;
+ }
+
+ PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(pll2vco / ((float)(((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVP) >> RCC_PLL2CFGR2_DIVP_Pos) + 1U)));
+ PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(pll2vco / ((float)(((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVQ) >> RCC_PLL2CFGR2_DIVQ_Pos) + 1U)));
+ PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(pll2vco / ((float)(((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVR) >> RCC_PLL2CFGR2_DIVR_Pos) + 1U)));
+}
+
+
+/**
+* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
+ * @note The PLL3 clock frequencies computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time PLL3CLK changes, this function must be called to update the
+ * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @param PLL3_Clocks structure.
+ * @retval None
+ */
+__weak void HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
+{
+ uint32_t pllsource = 0, pll3m = 1, pll3fracen = 0, hsivalue = 0;
+ float fracn1, pll3vco = 0;
+
+ pllsource = __HAL_RCC_GET_PLL3_SOURCE();
+ pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
+ pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> RCC_PLL3FRACR_FRACLE_Pos;
+ fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> RCC_PLL3FRACR_FRACV_Pos));
+ pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF)); //Intermediary value
+ switch (pllsource)
+ {
+ case RCC_PLL3SOURCE_HSI: /* HSI used as PLL clock source */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
+ {
+ hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ pll3vco *= (float)(hsivalue / pll3m);
+ }
+ else
+ {
+ pll3vco *= (float)(HSI_VALUE / pll3m);
+ }
+ break;
+
+ case RCC_PLL3SOURCE_HSE: /* HSE used as PLL clock source */
+ pll3vco *= (float)(HSE_VALUE / pll3m);
+ break;
+
+
+
+ case RCC_PLL3SOURCE_CSI: /* CSI used as PLL clock source */
+ pll3vco *= (float)(CSI_VALUE / pll3m);
+ break;
+
+ case RCC_PLL3SOURCE_OFF: /* No clock source for PLL */
+ pll3vco = 0;
+ break;
+ }
+
+ PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) >> RCC_PLL3CFGR2_DIVP_Pos) + 1U)));
+ PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVQ) >> RCC_PLL3CFGR2_DIVQ_Pos) + 1U)));
+ PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVR) >> RCC_PLL3CFGR2_DIVR_Pos) + 1U)));
+}
+
+
+/**
+* @brief Returns the PLL4 clock frequencies :PLL4_P_Frequency,PLL4_R_Frequency and PLL4_Q_Frequency
+ * @note The PLL4 clock frequencies computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ *
+ * @note Each time PLL4CLK changes, this function must be called to update the
+ * right PLL4CLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @param PLL4_Clocks structure.
+ * @retval None
+ */
+__weak void HAL_RCC_GetPLL4ClockFreq(PLL4_ClocksTypeDef *PLL4_Clocks)
+{
+ uint32_t pllsource = 0U, pll4m = 1U, pll4fracen = 0U, hsivalue = 0U;
+ float fracn1, pll4vco = 0;
+
+ pllsource = __HAL_RCC_GET_PLL4_SOURCE();
+ pll4m = ((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_DIVM4_Pos) + 1U;
+ pll4fracen = (RCC->PLL4FRACR & RCC_PLL4FRACR_FRACLE) >> RCC_PLL4FRACR_FRACLE_Pos;
+ fracn1 = (float)(pll4fracen * ((RCC->PLL4FRACR & RCC_PLL4FRACR_FRACV) >> RCC_PLL4FRACR_FRACV_Pos));
+ pll4vco = (float)((float)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF)); //Intermediary value
+ switch (pllsource)
+ {
+ case RCC_PLL4SOURCE_HSI: /* HSI used as PLL clock source */
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
+ {
+ hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ pll4vco *= (float)(hsivalue / pll4m);
+ }
+ else
+ {
+ pll4vco *= (float)(HSI_VALUE / pll4m);
+ }
+ break;
+
+ case RCC_PLL4SOURCE_HSE: /* HSE used as PLL clock source */
+ pll4vco *= (float)(HSE_VALUE / pll4m);
+ break;
+
+ case RCC_PLL4SOURCE_CSI: /* CSI used as PLL clock source */
+ pll4vco *= (float)(CSI_VALUE / pll4m);
+ break;
+
+ case RCC_PLL4SOURCE_I2S_CKIN: /* Signal I2S_CKIN used as reference clock */
+ pll4vco *= (float)(EXTERNAL_CLOCK_VALUE / pll4m);
+ break;
+ }
+
+ PLL4_Clocks->PLL4_P_Frequency = (uint32_t)(pll4vco / ((float)(((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVP) >> RCC_PLL4CFGR2_DIVP_Pos) + 1U)));
+ PLL4_Clocks->PLL4_Q_Frequency = (uint32_t)(pll4vco / ((float)(((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVQ) >> RCC_PLL4CFGR2_DIVQ_Pos) + 1U)));
+ PLL4_Clocks->PLL4_R_Frequency = (uint32_t)(pll4vco / ((float)(((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVR) >> RCC_PLL4CFGR2_DIVR_Pos) + 1U)));
+}
+
+/**
+ * @brief Returns the PCLK1 frequency
+ * @note Each time PCLK1 changes, this function must be called to update the
+ * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK1 frequency
+ */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ uint32_t apb1div = 0;
+
+ /* Compute PCLK1 frequency ---------------------------*/
+ apb1div = __HAL_RCC_GET_APB1_DIV();
+ if (apb1div > RCC_APB1_DIV16)
+ {
+ apb1div = RCC_APB1_DIV16;
+ }
+
+ return (HAL_RCC_GetMCUFreq() >> apb1div);
+}
+
+
+/**
+ * @brief Returns the PCLK2 frequency
+ * @note Each time PCLK2 changes, this function must be called to update the
+ * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK2 frequency
+ */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ uint32_t apb2div = 0;
+
+ /* Compute PCLK2 frequency ---------------------------*/
+ apb2div = __HAL_RCC_GET_APB2_DIV();
+ if (apb2div > RCC_APB2_DIV16)
+ {
+ apb2div = RCC_APB2_DIV16;
+ }
+
+ return (HAL_RCC_GetMCUFreq() >> apb2div);
+}
+
+/**
+ * @brief Returns the PCLK3 frequency
+ * @note Each time PCLK3 changes, this function must be called to update the
+ * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK3 frequency
+ */
+uint32_t HAL_RCC_GetPCLK3Freq(void)
+{
+ uint32_t apb3div = 0;
+
+ /* Compute PCLK3 frequency ---------------------------*/
+ apb3div = __HAL_RCC_GET_APB3_DIV();
+ if (apb3div > RCC_APB3_DIV16)
+ {
+ apb3div = RCC_APB3_DIV16;
+ }
+
+ return (HAL_RCC_GetMCUFreq() >> apb3div);
+}
+
+/**
+ * @brief Returns the PCLK4 frequency
+ * @note Each time PCLK4 changes, this function must be called to update the
+ * right PCLK4 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK4 frequency
+ */
+uint32_t HAL_RCC_GetPCLK4Freq(void)
+{
+ uint32_t apb4div = 0;
+
+ /* Compute PCLK4 frequency ---------------------------*/
+ apb4div = __HAL_RCC_GET_APB4_DIV();
+ if (apb4div > RCC_APB4_DIV16)
+ {
+ apb4div = RCC_APB4_DIV16;
+ }
+
+ return (HAL_RCC_GetACLKFreq() >> apb4div);
+}
+
+/**
+ * @brief Returns the PCLK5 frequency
+ * @note Each time PCLK5 changes, this function must be called to update the
+ * right PCLK5 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval PCLK5 frequency
+ */
+uint32_t HAL_RCC_GetPCLK5Freq(void)
+{
+ uint32_t apb5div = 0;
+
+ /* Compute PCLK5 frequency ---------------------------*/
+ apb5div = __HAL_RCC_GET_APB5_DIV();
+ if (apb5div > RCC_APB5_DIV16)
+ {
+ apb5div = RCC_APB5_DIV16;
+ }
+
+ return (HAL_RCC_GetACLKFreq() >> apb5div);
+}
+
+/**
+ * @brief Returns the ACLK frequency
+ * @note Each time ACLK changes, this function must be called to update the
+ * right ACLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval ACLK frequency
+ */
+uint32_t HAL_RCC_GetACLKFreq(void)
+{
+ uint32_t axidiv = 0;
+
+ /* Compute ACLK frequency ---------------------------*/
+ axidiv = __HAL_RCC_GET_AXI_DIV();
+ if (axidiv > RCC_AXI_DIV4)
+ {
+ axidiv = RCC_AXI_DIV4;
+ }
+ axidiv += 1;
+
+ return HAL_RCC_GetAXISSFreq() / axidiv;
+}
+
+/**
+ * @brief Returns the HCLK5 frequency
+ * @note Each time HCLK5 changes, this function must be called to update the
+ * right HCLK5 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval HCLK5 frequency
+ */
+uint32_t HAL_RCC_GetHCLK5Freq(void)
+{
+ return HAL_RCC_GetACLKFreq();
+}
+
+/**
+ * @brief Returns the HCLK6 frequency
+ * @note Each time HCLK6 changes, this function must be called to update the
+ * right HCLK6 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval HCLK6 frequency
+ */
+uint32_t HAL_RCC_GetHCLK6Freq(void)
+{
+ return HAL_RCC_GetACLKFreq();
+}
+
+/**
+ * @brief Returns the HCLK1 frequency
+ * @note Each time HCLK1 changes, this function must be called to update the
+ * right HCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval HCLK1 frequency
+ */
+uint32_t HAL_RCC_GetHCLK1Freq(void)
+{
+ return HAL_RCC_GetMCUFreq();
+}
+
+/**
+ * @brief Returns the HCLK2 frequency
+ * @note Each time HCLK1 changes, this function must be called to update the
+ * right HCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval HCLK2 frequency
+ */
+uint32_t HAL_RCC_GetHCLK2Freq(void)
+{
+ return HAL_RCC_GetMCUFreq();
+}
+
+/**
+ * @brief Returns the HCLK3 frequency
+ * @note Each time HCLK3 changes, this function must be called to update the
+ * right HCLK3 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval HCLK3 frequency
+ */
+uint32_t HAL_RCC_GetHCLK3Freq(void)
+{
+ return HAL_RCC_GetMCUFreq();
+}
+
+/**
+ * @brief Returns the HCLK4 frequency
+ * @note Each time HCLK4 changes, this function must be called to update the
+ * right HCLK4 value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval HCLK4 frequency
+ */
+uint32_t HAL_RCC_GetHCLK4Freq(void)
+{
+ return HAL_RCC_GetMCUFreq();
+}
+
+/**
+ * @brief Returns the MLHCLK frequency
+ * @note Each time MLHCLK changes, this function must be called to update the
+ * right MLHCLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval HCLK4 frequency
+ */
+uint32_t HAL_RCC_GetMLHCLKFreq(void)
+{
+ return HAL_RCC_GetMCUFreq();
+}
+
+
+/**
+ * @brief Returns the MCU frequency
+ * @note Each time MCU changes, this function must be called to update the
+ * right MCU value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval MCU frequency
+ */
+uint32_t HAL_RCC_GetMCUFreq(void)
+{
+ uint32_t mcudiv = 0;
+
+ /* Compute MCU frequency ---------------------------*/
+ mcudiv = __HAL_RCC_GET_MCU_DIV();
+ if (mcudiv > RCC_MCU_DIV512)
+ {
+ mcudiv = RCC_MCU_DIV512;
+ }
+
+ return HAL_RCC_GetMCUSSFreq() >> mcudiv;
+}
+
+
+/**
+ * @brief Returns the FCLK frequency
+ * @note Each time FCLK changes, this function must be called to update the
+ * right FCLK value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval FCLK frequency
+ */
+uint32_t HAL_RCC_GetFCLKFreq(void)
+{
+ return HAL_RCC_GetMCUFreq();
+}
+
+/**
+ * @brief Returns the CKPER frequency
+ * @note Each time CKPER changes, this function must be called to update the
+ * right CKPER value. Otherwise, any configuration based on this function will be incorrect.
+ * @retval CKPER frequency
+ */
+uint32_t RCC_GetCKPERFreq(void)
+{
+ uint32_t ckperclocksource = 0, frequency = 0;
+
+ ckperclocksource = __HAL_RCC_GET_CKPER_SOURCE();
+
+ if (ckperclocksource == RCC_CKPERCLKSOURCE_HSI)
+ {
+ /* In Case the main PLL Source is HSI */
+ frequency = HSI_VALUE;
+ }
+
+ else if (ckperclocksource == RCC_CKPERCLKSOURCE_CSI)
+ {
+ /* In Case the main PLL Source is CSI */
+ frequency = CSI_VALUE;
+ }
+
+ else if (ckperclocksource == RCC_CKPERCLKSOURCE_HSE)
+ {
+ /* In Case the main PLL Source is HSE */
+ frequency = HSE_VALUE;
+ }
+ else
+ {
+ frequency = 0;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Returns the System Core frequency
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constants and the selected clock source
+ * @retval System Core frequency
+ */
+uint32_t HAL_RCC_GetSystemCoreClockFreq(void)
+{
+#ifdef CORE_CA7
+ return HAL_RCC_GetMPUSSFreq();
+#else /* CORE_CM4 */
+ return HAL_RCC_GetMCUFreq();
+#endif
+}
+
+uint32_t HAL_RCC_GetMPUSSFreq()
+{
+ uint32_t mpussfreq = 0, mpudiv = 0;
+ PLL1_ClocksTypeDef pll1_clocks;
+
+ switch (__HAL_RCC_GET_MPU_SOURCE())
+ {
+ case RCC_MPUSOURCE_PLL1:
+ HAL_RCC_GetPLL1ClockFreq(&pll1_clocks);
+ mpussfreq = pll1_clocks.PLL1_P_Frequency;
+ break;
+
+ case RCC_MPUSOURCE_MPUDIV:
+ mpudiv = __HAL_RCC_GET_MPU_DIV();
+ if (mpudiv == RCC_MPU_DIV_OFF)
+ {
+ mpussfreq = 0;
+ }
+ else if (mpudiv <= RCC_MPU_DIV16)
+ {
+ HAL_RCC_GetPLL1ClockFreq(&pll1_clocks);
+ mpussfreq = (pll1_clocks.PLL1_P_Frequency >> mpudiv);
+ }
+ else
+ {
+ HAL_RCC_GetPLL1ClockFreq(&pll1_clocks);
+ mpussfreq = (pll1_clocks.PLL1_P_Frequency >> 16); /* divided by 16 */
+ }
+ break;
+
+ case RCC_MPUSOURCE_HSI:
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
+ {
+ mpussfreq = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ }
+ else
+ {
+ mpussfreq = HSI_VALUE;
+ }
+ break;
+
+ case RCC_MPUSOURCE_HSE:
+ mpussfreq = HSE_VALUE;
+ break;
+ }
+
+ return mpussfreq;
+}
+
+
+uint32_t HAL_RCC_GetAXISSFreq()
+{
+ uint32_t axissfreq = 0;
+ PLL2_ClocksTypeDef pll2_clocks;
+
+ switch (__HAL_RCC_GET_AXIS_SOURCE())
+ {
+ case RCC_AXISSOURCE_PLL2:
+ HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
+ axissfreq = pll2_clocks.PLL2_P_Frequency;
+ break;
+
+ case RCC_AXISSOURCE_HSI:
+ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
+ {
+ axissfreq = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ }
+ else
+ {
+ axissfreq = HSI_VALUE;
+ }
+ break;
+
+ case RCC_AXISSOURCE_HSE:
+ axissfreq = HSE_VALUE;
+ break;
+
+ case RCC_AXISSOURCE_OFF:
+ default:
+ axissfreq = 0; /* ck_axiss is gated */
+ break;
+ }
+
+ return axissfreq;
+}
+
+uint32_t HAL_RCC_GetMCUSSFreq()
+{
+ uint32_t mcussfreq = 0;
+ PLL3_ClocksTypeDef pll3_clocks;
+
+ switch (__HAL_RCC_GET_MCU_SOURCE())
+ {
+ case RCC_MCUSSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ mcussfreq = pll3_clocks.PLL3_P_Frequency;
+ break;
+
+ case RCC_MCUSSOURCE_HSI:
+ mcussfreq = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+
+ break;
+
+ case RCC_MCUSSOURCE_HSE:
+ mcussfreq = HSE_VALUE;
+ break;
+
+ case RCC_MCUSSOURCE_CSI:
+ mcussfreq = CSI_VALUE;
+ break;
+ }
+
+ return mcussfreq;
+}
+
+
+
+/**
+ * @brief This function handles the RCC global interrupt (rcc_mcu_irq/rcc_mpu_irq)
+ * @note This API should be called under the RCC_Handler().
+ * @retval None
+ */
+void HAL_RCC_IRQHandler(void)
+{
+#if defined(CORE_CM4)
+ uint32_t flags = (READ_REG(RCC->MC_CIFR) & RCC_IT_ALL);
+#endif /* CORE_CM4 */
+#if defined(CORE_CA7)
+ uint32_t flags = (READ_REG(RCC->MP_CIFR) & RCC_IT_ALL);
+#endif
+ /* Clear the RCC interrupt bits */
+ __HAL_RCC_CLEAR_IT(flags);
+
+ if ((flags & RCC_IT_LSECSS) != RESET)
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+ /* Clear LSECSSON bit */
+ HAL_RCCEx_DisableLSECSS();
+ /* Clear LSEON bit */
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+ }
+
+ /* RCC interrupt user callback */
+ HAL_RCC_Callback(flags);
+}
+
+
+/**
+ * @brief RCC global interrupt callback
+ * @param Flags: It contains the flags which were set during the RCC_IRQHandler
+ * before cleaning them
+ * @retval None
+ */
+__weak void HAL_RCC_Callback(uint32_t Flags)
+{
+ /* Prevent unused argument compilation warning */
+ UNUSED(Flags);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_Callback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief This function handles the RCC Wake up interrupt (rcc_mcu_wkup_irq/rcc_mpu_wkup_irq)
+ * @note This API should be called under the RCC_WAKEUP_Handler().
+ * @retval None
+ */
+void HAL_RCC_WAKEUP_IRQHandler(void)
+{
+ /* Check RCC WKUP flag is set */
+ if (__HAL_RCC_GET_IT(RCC_IT_WKUP) != RESET)
+ {
+ /* Clear the RCC WKUP flag bit */
+ __HAL_RCC_CLEAR_IT(RCC_IT_WKUP);
+
+ /* RCC WKUP interrupt user callback */
+ HAL_RCC_WAKEUP_Callback();
+ }
+}
+
+
+/**
+ * @brief RCC WAKEUP interrupt callback
+ * @retval None
+ */
+__weak void HAL_RCC_WAKEUP_Callback(void)
+{
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_RCC_WAKEUP_Callback could be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c
new file mode 100644
index 0000000..38a0ce6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c
@@ -0,0 +1,3408 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_rcc_ex.c
+ * @author MCD Application Team
+ * @brief Extended RCC HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities RCC extension peripheral:
+ * + Extended Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup RCCEx RCCEx
+ * @brief RCC HAL module driver
+ * @{
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+#define LSE_MASK (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP)
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCCEx_Private_Function_Prototypes RCCEx Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+ * @{
+ */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the RCC Clocks
+ frequencies.
+ [..]
+ (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
+ the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Configures PLL2
+ * @param pll2: pointer to an RCC_PLLInitTypeDef structure
+ *
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLLInitTypeDef *pll2)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(pll2->PLLState));
+ if ((pll2->PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
+ if (!__IS_PLL2_IN_USE()) /* If not used then */
+ {
+ if ((pll2->PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLMODE(pll2->PLLMODE));
+ assert_param(IS_RCC_PLL12SOURCE(pll2->PLLSource));
+ assert_param(IS_RCC_PLLM2_VALUE(pll2->PLLM));
+ if (pll2->PLLMODE == RCC_PLL_FRACTIONAL)
+ {
+ assert_param(IS_RCC_PLLN2_FRAC_VALUE(pll2->PLLN));
+ }
+ else
+ {
+ assert_param(IS_RCC_PLLN2_INT_VALUE(pll2->PLLN));
+ }
+ assert_param(IS_RCC_PLLP2_VALUE(pll2->PLLP));
+ assert_param(IS_RCC_PLLQ2_VALUE(pll2->PLLQ));
+ assert_param(IS_RCC_PLLR2_VALUE(pll2->PLLR));
+
+ /* Check that PLL2 OSC clock source is already set */
+ if ((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) &&
+ (__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSE))
+ {
+ return HAL_ERROR;
+ }
+
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /*The PLL configuration below must be done before enabling the PLL:
+ -Selection of PLL clock entry (HSI or HSE)
+ -Frequency input range (PLLxRGE)
+ -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
+ Once the PLL is enabled, these parameters can not be changed.
+ If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
+ PLLxRDY flag to be at 0.
+ The PLL configuration below can be done at any time:
+ -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
+ -Fractional Division Enable (PLLxFRACNEN)
+ -Fractional Division factor (FRACNx)*/
+
+ /* Do not change pll src if already in use */
+ if (__IS_PLL1_IN_USE())
+ {
+ if (pll2->PLLSource != __HAL_RCC_GET_PLL12_SOURCE())
+ {
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Configure PLL1 and PLL2 clock source */
+ __HAL_RCC_PLL12_SOURCE(pll2->PLLSource);
+ }
+
+ /* Configure the PLL2 multiplication and division factors. */
+ __HAL_RCC_PLL2_CONFIG(
+ pll2->PLLM,
+ pll2->PLLN,
+ pll2->PLLP,
+ pll2->PLLQ,
+ pll2->PLLR);
+
+
+ /* Configure the Fractional Divider */
+ __HAL_RCC_PLL2FRACV_DISABLE(); //Set FRACLE to ‘0’
+ /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
+ if ((pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll2->PLLMODE == RCC_PLL_INTEGER))
+ {
+ /* Do not use the fractional divider */
+ __HAL_RCC_PLL2FRACV_CONFIG(0); //Set FRACV to '0'
+ }
+ else
+ {
+ /* Configure PLL PLL2FRACV in fractional mode*/
+ __HAL_RCC_PLL2FRACV_CONFIG(pll2->PLLFRACV);
+ }
+ __HAL_RCC_PLL2FRACV_ENABLE(); //Set FRACLE to ‘1’
+
+
+ /* Configure the Spread Control */
+ if (pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
+ {
+ assert_param(IS_RCC_INC_STEP(pll2->INC_STEP));
+ assert_param(IS_RCC_SSCG_MODE(pll2->SSCG_MODE));
+ assert_param(IS_RCC_RPDFN_DIS(pll2->RPDFN_DIS));
+ assert_param(IS_RCC_TPDFN_DIS(pll2->TPDFN_DIS));
+ assert_param(IS_RCC_MOD_PER(pll2->MOD_PER));
+
+ __HAL_RCC_PLL2CSGCONFIG(pll2->MOD_PER, pll2->TPDFN_DIS, pll2->RPDFN_DIS,
+ pll2->SSCG_MODE, pll2->INC_STEP);
+ __HAL_RCC_PLL2_SSMODE_ENABLE();
+ }
+ else
+ {
+ __HAL_RCC_PLL2_SSMODE_DISABLE();
+ }
+
+
+ /* Enable the PLL2. */
+ __HAL_RCC_PLL2_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /*Enable the post-dividers*/
+ __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
+ }
+ else
+ {
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
+ /* Disable the PLL2. */
+ __HAL_RCC_PLL2_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+
+}
+
+
+
+/**
+ * @brief Configures PLL3
+ * @param pll3: pointer to a RCC_PLLInitTypeDef structure
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLLInitTypeDef *pll3)
+{
+
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(pll3->PLLState));
+ if ((pll3->PLLState) != RCC_PLL_NONE)
+ {
+ /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
+ if (!__IS_PLL3_IN_USE()) /* If not used then*/
+ {
+ if ((pll3->PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLMODE(pll3->PLLMODE));
+ assert_param(IS_RCC_PLL3SOURCE(pll3->PLLSource));
+ assert_param(IS_RCC_PLLM1_VALUE(pll3->PLLM));
+ if (pll3->PLLMODE == RCC_PLL_FRACTIONAL)
+ {
+ assert_param(IS_RCC_PLLN3_FRAC_VALUE(pll3->PLLN));
+ }
+ else
+ {
+ assert_param(IS_RCC_PLLN3_INT_VALUE(pll3->PLLN));
+ }
+ assert_param(IS_RCC_PLLP3_VALUE(pll3->PLLP));
+ assert_param(IS_RCC_PLLQ3_VALUE(pll3->PLLQ));
+ assert_param(IS_RCC_PLLR3_VALUE(pll3->PLLR));
+
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL3_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+
+ /*The PLL configuration below must be done before enabling the PLL:
+ -Selection of PLL clock entry (HSI or CSI or HSE)
+ -Frequency input range (PLLxRGE)
+ -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
+ Once the PLL is enabled, these parameters can not be changed.
+ If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
+ PLLxRDY flag to be at 0.
+ The PLL configuration below can be done at any time:
+ -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
+ -Fractional Division Enable (PLLxFRACNEN)
+ -Fractional Division factor (FRACNx)*/
+
+ /* Configure PLL3 clock source */
+ __HAL_RCC_PLL3_SOURCE(pll3->PLLSource);
+
+ /* Wait till PLL SOURCE is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3SRCRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Select PLL3 input reference frequency range */
+ __HAL_RCC_PLL3_IFRANGE(pll3->PLLRGE) ;
+
+ /* Configure the PLL3 multiplication and division factors. */
+ __HAL_RCC_PLL3_CONFIG(
+ pll3->PLLM,
+ pll3->PLLN,
+ pll3->PLLP,
+ pll3->PLLQ,
+ pll3->PLLR);
+
+ /* Configure the Fractional Divider */
+ __HAL_RCC_PLL3FRACV_DISABLE(); //Set FRACLE to ‘0’
+ /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
+ if ((pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll3->PLLMODE == RCC_PLL_INTEGER))
+ {
+ /* Do not use the fractional divider */
+ __HAL_RCC_PLL3FRACV_CONFIG(0); //Set FRACV to '0'
+ }
+ else
+ {
+ /* Configure PLL PLL3FRACV in fractional mode*/
+ __HAL_RCC_PLL3FRACV_CONFIG(pll3->PLLFRACV);
+ }
+ __HAL_RCC_PLL3FRACV_ENABLE(); //Set FRACLE to ‘1’
+
+
+ /* Configure the Spread Control */
+ if (pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
+ {
+ assert_param(IS_RCC_INC_STEP(pll3->INC_STEP));
+ assert_param(IS_RCC_SSCG_MODE(pll3->SSCG_MODE));
+ assert_param(IS_RCC_RPDFN_DIS(pll3->RPDFN_DIS));
+ assert_param(IS_RCC_TPDFN_DIS(pll3->TPDFN_DIS));
+ assert_param(IS_RCC_MOD_PER(pll3->MOD_PER));
+
+ __HAL_RCC_PLL3CSGCONFIG(pll3->MOD_PER, pll3->TPDFN_DIS, pll3->RPDFN_DIS,
+ pll3->SSCG_MODE, pll3->INC_STEP);
+ __HAL_RCC_PLL3_SSMODE_ENABLE();
+ }
+ else
+ {
+ __HAL_RCC_PLL3_SSMODE_DISABLE();
+ }
+
+
+ /* Enable the PLL3. */
+ __HAL_RCC_PLL3_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Enable the post-dividers */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
+ }
+ else
+ {
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
+ /* Disable the PLL3. */
+ __HAL_RCC_PLL3_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Configures PLL4
+ * @param pll4: pointer to a RCC_PLLInitTypeDef structure
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RCCEx_PLL4_Config(RCC_PLLInitTypeDef *pll4)
+{
+
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL(pll4->PLLState));
+ if ((pll4->PLLState) != RCC_PLL_NONE)
+ {
+
+ if ((pll4->PLLState) == RCC_PLL_ON)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLMODE(pll4->PLLMODE));
+ assert_param(IS_RCC_PLL4SOURCE(pll4->PLLSource));
+ assert_param(IS_RCC_PLLM4_VALUE(pll4->PLLM));
+ if (pll4->PLLMODE == RCC_PLL_FRACTIONAL)
+ {
+ assert_param(IS_RCC_PLLN4_FRAC_VALUE(pll4->PLLN));
+ }
+ else
+ {
+ assert_param(IS_RCC_PLLN4_INT_VALUE(pll4->PLLN));
+ }
+ assert_param(IS_RCC_PLLP4_VALUE(pll4->PLLP));
+ assert_param(IS_RCC_PLLQ4_VALUE(pll4->PLLQ));
+ assert_param(IS_RCC_PLLR4_VALUE(pll4->PLLR));
+
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
+ /* Disable the main PLL. */
+ __HAL_RCC_PLL4_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+
+ /*The PLL configuration below must be done before enabling the PLL:
+ -Selection of PLL clock entry (HSI or CSI or HSE)
+ -Frequency input range (PLLxRGE)
+ -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
+ Once the PLL is enabled, these parameters can not be changed.
+ If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
+ PLLxRDY flag to be at 0.
+ The PLL configuration below can be done at any time:
+ -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
+ -Fractional Division Enable (PLLxFRACNEN)
+ -Fractional Division factor (FRACNx)*/
+
+ /* Configure PLL4 and PLL4 clock source */
+ __HAL_RCC_PLL4_SOURCE(pll4->PLLSource);
+
+ /* Wait till PLL SOURCE is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4SRCRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Select PLL4 input reference frequency range */
+ __HAL_RCC_PLL4_IFRANGE(pll4->PLLRGE) ;
+
+ /* Configure the PLL4 multiplication and division factors. */
+ __HAL_RCC_PLL4_CONFIG(
+ pll4->PLLM,
+ pll4->PLLN,
+ pll4->PLLP,
+ pll4->PLLQ,
+ pll4->PLLR);
+
+ /* Configure the Fractional Divider */
+ __HAL_RCC_PLL4FRACV_DISABLE(); //Set FRACLE to ‘0’
+ /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
+ if ((pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll4->PLLMODE == RCC_PLL_INTEGER))
+ {
+ /* Do not use the fractional divider */
+ __HAL_RCC_PLL4FRACV_CONFIG(0); //Set FRACV to '0'
+ }
+ else
+ {
+ /* Configure PLL PLL4FRACV in fractional mode*/
+ __HAL_RCC_PLL4FRACV_CONFIG(pll4->PLLFRACV);
+ }
+ __HAL_RCC_PLL4FRACV_ENABLE(); //Set FRACLE to ‘1’
+
+ /* Configure the Spread Control */
+ if (pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
+ {
+ assert_param(IS_RCC_INC_STEP(pll4->INC_STEP));
+ assert_param(IS_RCC_SSCG_MODE(pll4->SSCG_MODE));
+ assert_param(IS_RCC_RPDFN_DIS(pll4->RPDFN_DIS));
+ assert_param(IS_RCC_TPDFN_DIS(pll4->TPDFN_DIS));
+ assert_param(IS_RCC_MOD_PER(pll4->MOD_PER));
+
+ __HAL_RCC_PLL4CSGCONFIG(pll4->MOD_PER, pll4->TPDFN_DIS, pll4->RPDFN_DIS,
+ pll4->SSCG_MODE, pll4->INC_STEP);
+ __HAL_RCC_PLL4_SSMODE_ENABLE();
+ }
+ else
+ {
+ __HAL_RCC_PLL4_SSMODE_DISABLE();
+ }
+
+ /* Enable the PLL4. */
+ __HAL_RCC_PLL4_ENABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Enable PLL4P Clock output. */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
+ }
+ else
+ {
+ /*Disable the post-dividers*/
+ __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
+ /* Disable the PLL4. */
+ __HAL_RCC_PLL4_DISABLE();
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLL is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the RCC extended peripherals clocks according to the
+ * specified parameters in the RCC_PeriphCLKInitTypeDef.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * contains a field PeriphClockSelection which can be a combination of
+ * the following values:
+ * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART24 USART2 and UART4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART35 USART3 and UART5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C12 I2C1 and I2C2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C35 I2C3 and I2C5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_UART78 UART7 and UART8 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_I2C46 I2C4 and I2C6 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM23 LPTIM2 and LPTIM3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_LPTIM45 LPTIM4 and LPTIM5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI3 SAI3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_FMC FMC peripheral clock
+ * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock
+ * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock
+ * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPDIFRX SPDIFRX peripheral clock
+ * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI1 SPI/I2S1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI23 SPI/I2S2 and SPI/I2S3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI45 SPI4 and SPI5 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SAI4 SAI4 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDMMC12 SDMMC1 and SDMMC2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_SDMMC3 SDMMC3 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_ETH ETH peripheral clock
+ * @arg @ref RCC_PERIPHCLK_RNG1 RNG1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_RNG2 RNG2 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_USBO USBO peripheral clock
+ * @arg @ref RCC_PERIPHCLK_STGEN STGEN peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIMG1 TIMG1 peripheral clock
+ * @arg @ref RCC_PERIPHCLK_TIMG2 TIMG2 peripheral clock
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+ * select the RTC clock source; in this case the Backup domain will be
+ * reset in order to modify the RTC Clock source, as consequence RTC
+ * registers (including the backup registers) are set to their reset
+ * values.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef
+ *PeriphClkInit)
+{
+ uint32_t tmpreg = 0, RESERVED_BDCR_MASK = 0;
+ uint32_t tickstart;
+ HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
+ HAL_StatusTypeDef status = HAL_OK; /* Final status */
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+ /*---------------------------- CKPER configuration -------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) ==
+ RCC_PERIPHCLK_CKPER)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection));
+
+ __HAL_RCC_CKPER_CONFIG(PeriphClkInit->CkperClockSelection);
+ }
+
+ /*------------------------------ I2C12 Configuration -----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C12) ==
+ RCC_PERIPHCLK_I2C12)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C12CLKSOURCE(PeriphClkInit->I2c12ClockSelection));
+
+ if ((PeriphClkInit->I2c12ClockSelection) == RCC_I2C12CLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+ }
+
+ __HAL_RCC_I2C12_CONFIG(PeriphClkInit->I2c12ClockSelection);
+ }
+
+ /*------------------------------ I2C35 Configuration -----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C35) ==
+ RCC_PERIPHCLK_I2C35)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C35CLKSOURCE(PeriphClkInit->I2c35ClockSelection));
+
+ if ((PeriphClkInit->I2c35ClockSelection) == RCC_I2C35CLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+ }
+
+ __HAL_RCC_I2C35_CONFIG(PeriphClkInit->I2c35ClockSelection);
+ }
+
+ /*------------------------------ I2C46 Configuration -----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C46) ==
+ RCC_PERIPHCLK_I2C46)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_I2C46CLKSOURCE(PeriphClkInit->I2c46ClockSelection));
+
+ if ((PeriphClkInit->I2c46ClockSelection) == RCC_I2C46CLKSOURCE_PLL3)
+ {
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+ }
+
+ __HAL_RCC_I2C46_CONFIG(PeriphClkInit->I2c46ClockSelection);
+ }
+
+ /*---------------------------- SAI1 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) ==
+ RCC_PERIPHCLK_SAI1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+ switch (PeriphClkInit->Sai1ClockSelection)
+ {
+ case RCC_SAI1CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI1*/
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI1*/
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3 */
+
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI1*/
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3 */
+
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+ }
+
+ /* Set the source of SAI1 clock*/
+ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ }
+
+ /*---------------------------- SAI2 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) ==
+ RCC_PERIPHCLK_SAI2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+ switch (PeriphClkInit->Sai2ClockSelection)
+ {
+ case RCC_SAI2CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI2*/
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI2 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI2 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+ }
+
+ /* Set the source of SAI2 clock*/
+ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+ }
+
+ /*---------------------------- SAI3 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI3) ==
+ RCC_PERIPHCLK_SAI3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI3CLKSOURCE(PeriphClkInit->Sai3ClockSelection));
+
+ switch (PeriphClkInit->Sai3ClockSelection)
+ {
+ case RCC_SAI3CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI3*/
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+
+ break;
+
+ case RCC_SAI3CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI3 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_SAI3CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI3 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+ }
+
+ /* Set the source of SAI3 clock*/
+ __HAL_RCC_SAI3_CONFIG(PeriphClkInit->Sai3ClockSelection);
+ }
+
+ /*---------------------------- SAI4 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4) ==
+ RCC_PERIPHCLK_SAI4)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SAI4CLKSOURCE(PeriphClkInit->Sai4ClockSelection));
+
+ switch (PeriphClkInit->Sai4ClockSelection)
+ {
+ case RCC_SAI4CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI4 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+
+ break;
+
+
+ case RCC_SAI4CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI4 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3_Q */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_SAI4CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI4 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SAI Clock output generated on PLL3_R */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+ }
+
+ /* Set the source of SAI4 clock*/
+ __HAL_RCC_SAI4_CONFIG(PeriphClkInit->Sai4ClockSelection);
+ }
+
+ /*---------------------------- SPI1 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) ==
+ RCC_PERIPHCLK_SPI1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
+
+ switch (PeriphClkInit->Spi1ClockSelection)
+ {
+ case RCC_SPI1CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI1 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+
+ case RCC_SPI1CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SPI1*/
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_SPI1CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SPI1 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+
+ }
+
+ /* Set the source of SPI1 clock*/
+ __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
+ }
+
+ /*---------------------------- SPI23 configuration -------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI23) ==
+ RCC_PERIPHCLK_SPI23)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPI23CLKSOURCE(PeriphClkInit->Spi23ClockSelection));
+
+ switch (PeriphClkInit->Spi23ClockSelection)
+ {
+ case RCC_SPI23CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI23 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+
+ case RCC_SPI23CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SPI23 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_SPI23CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SPI23 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+ }
+
+ /* Set the source of SPI2 clock*/
+ __HAL_RCC_SPI23_CONFIG(PeriphClkInit->Spi23ClockSelection);
+ }
+
+ /*---------------------------- SPI45 configuration -------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) ==
+ RCC_PERIPHCLK_SPI45)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPI45CLKSOURCE(PeriphClkInit->Spi45ClockSelection));
+
+ if (PeriphClkInit->Spi45ClockSelection == RCC_SPI45CLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+ }
+
+ /* Set the source of SPI45 clock*/
+ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
+ }
+
+ /*---------------------------- SPI6 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) ==
+ RCC_PERIPHCLK_SPI6)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection));
+
+ switch (PeriphClkInit->Spi6ClockSelection)
+ {
+ case RCC_SPI6CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI6 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+
+ break;
+
+ case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPI Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+ }
+
+ /* Set the source of SPI6 clock*/
+ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+ }
+
+ /*---------------------------- USART6 configuration ------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) ==
+ RCC_PERIPHCLK_USART6)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
+
+ if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_PLL4)
+ {
+ /* PLL4 is used as clock source for USART6 */
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable USART Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+ }
+
+ /* Set the source of USART6 clock*/
+ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
+ }
+
+ /*---------------------------- UART24 configuration ------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART24) ==
+ RCC_PERIPHCLK_UART24)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART24CLKSOURCE(PeriphClkInit->Uart24ClockSelection));
+
+ if (PeriphClkInit->Uart24ClockSelection == RCC_UART24CLKSOURCE_PLL4)
+ {
+ /* PLL4 is used as clock source for UART24 */
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable UART Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+ }
+
+ /* Set the source of UART24 clock*/
+ __HAL_RCC_UART24_CONFIG(PeriphClkInit->Uart24ClockSelection);
+ }
+
+ /*---------------------------- UART35 configuration ------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART35) ==
+ RCC_PERIPHCLK_UART35)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART35CLKSOURCE(PeriphClkInit->Uart35ClockSelection));
+
+ if (PeriphClkInit->Uart35ClockSelection == RCC_UART35CLKSOURCE_PLL4)
+ {
+ /* PLL4 is used as clock source for UART35 */
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable UART Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+ }
+
+ /* Set the source of UART35 clock*/
+ __HAL_RCC_UART35_CONFIG(PeriphClkInit->Uart35ClockSelection);
+ }
+
+ /*---------------------------- UAUART78 configuration ----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART78) ==
+ RCC_PERIPHCLK_UART78)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_UART78CLKSOURCE(PeriphClkInit->Uart78ClockSelection));
+
+ if (PeriphClkInit->Uart78ClockSelection == RCC_UART78CLKSOURCE_PLL4)
+ {
+ /* PLL4 is used as clock source for UART78 */
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable UART Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+ }
+
+ /* Set the source of UART78 clock*/
+ __HAL_RCC_UART78_CONFIG(PeriphClkInit->Uart78ClockSelection);
+ }
+
+ /*---------------------------- USART1 configuration ------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) ==
+ RCC_PERIPHCLK_USART1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
+
+ switch (PeriphClkInit->Usart1ClockSelection)
+ {
+ case RCC_USART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable UART Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_USART1CLKSOURCE_PLL4: /* PLL4 is used as clock source for USART1 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable USART Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+
+ break;
+ }
+
+ /* Set the source of USART1 clock*/
+ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
+ }
+
+ /*---------------------------- SDMMC12 configuration -----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC12) ==
+ RCC_PERIPHCLK_SDMMC12)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDMMC12CLKSOURCE(PeriphClkInit->Sdmmc12ClockSelection));
+
+ switch (PeriphClkInit->Sdmmc12ClockSelection)
+ {
+ case RCC_SDMMC12CLKSOURCE_PLL3: /* PLL3 is used as clock source for SDMMC12 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SDMMC12 Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+
+ case RCC_SDMMC12CLKSOURCE_PLL4: /* PLL4 is used as clock source for SDMMC12 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SDMMC12 Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+ }
+
+ /* Set the source of SDMMC12 clock*/
+ __HAL_RCC_SDMMC12_CONFIG(PeriphClkInit->Sdmmc12ClockSelection);
+ }
+
+ /*---------------------------- SDMMC3 configuration ------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC3) ==
+ RCC_PERIPHCLK_SDMMC3)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SDMMC3CLKSOURCE(PeriphClkInit->Sdmmc3ClockSelection));
+
+ switch (PeriphClkInit->Sdmmc3ClockSelection)
+ {
+ case RCC_SDMMC3CLKSOURCE_PLL3: /* PLL3 is used as clock source for SDMMC3 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SDMMC3 Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+
+ case RCC_SDMMC3CLKSOURCE_PLL4: /* PLL4 is used as clock source for SDMMC3 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SDMMC3 Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+ }
+
+ /* Set the source of SDMMC3 clock*/
+ __HAL_RCC_SDMMC3_CONFIG(PeriphClkInit->Sdmmc3ClockSelection);
+ }
+
+ /*---------------------------- ETH configuration ---------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ETH) ==
+ RCC_PERIPHCLK_ETH)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ETHCLKSOURCE(PeriphClkInit->EthClockSelection));
+
+ switch (PeriphClkInit->EthClockSelection)
+ {
+ case RCC_ETHCLKSOURCE_PLL4: /* PLL4 is used as clock source for ETH */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable ETH Clock output generated on PLL2 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+
+ case RCC_ETHCLKSOURCE_PLL3: /* PLL3 is used as clock source for ETH */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable ETH Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+ }
+
+ /* Set the source of ETH clock*/
+ __HAL_RCC_ETH_CONFIG(PeriphClkInit->EthClockSelection);
+ }
+
+ /*---------------------------- QSPI configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) ==
+ RCC_PERIPHCLK_QSPI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
+
+ switch (PeriphClkInit->QspiClockSelection)
+ {
+ case RCC_QSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for QSPI */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable QSPI Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+
+ case RCC_QSPICLKSOURCE_PLL4: /* PLL4 is used as clock source for QSPI */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable QSPI Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+ }
+
+ /* Set the source of QSPI clock*/
+ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+ }
+
+ /*---------------------------- FMC configuration ---------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) ==
+ RCC_PERIPHCLK_FMC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection));
+
+ switch (PeriphClkInit->FmcClockSelection)
+ {
+ case RCC_FMCCLKSOURCE_PLL3: /* PLL3 is used as clock source for FMC */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable FMC Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+
+ break;
+
+ case RCC_FMCCLKSOURCE_PLL4: /* PLL4 is used as clock source for FMC */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable FMC Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+ }
+
+ /* Set the source of FMC clock*/
+ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+ }
+
+#if defined(FDCAN1)
+ /*---------------------------- FDCAN configuration -------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) ==
+ RCC_PERIPHCLK_FDCAN)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
+
+ switch (PeriphClkInit->FdcanClockSelection)
+ {
+ case RCC_FDCANCLKSOURCE_PLL3: /* PLL3 is used as clock source for FDCAN */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable FDCAN Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_FDCANCLKSOURCE_PLL4_Q: /* PLL4_Q is used as clock source for FDCAN */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable FDCAN Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+
+ break;
+
+ case RCC_FDCANCLKSOURCE_PLL4_R: /* PLL4_R is used as clock source for FDCAN */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable FDCAN Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+
+ break;
+ }
+
+ /* Set the source of FDCAN clock*/
+ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+ }
+#endif /*FDCAN1*/
+
+ /*---------------------------- SPDIFRX configuration -----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) ==
+ RCC_PERIPHCLK_SPDIFRX)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifrxClockSelection));
+
+ switch (PeriphClkInit->SpdifrxClockSelection)
+ {
+ case RCC_SPDIFRXCLKSOURCE_PLL4: /* PLL4 is used as clock source for SPDIF */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPDIF Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+
+ case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIF */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable SPDIF Clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+ }
+
+ /* Set the source of SPDIF clock*/
+ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
+ }
+
+ /*---------------------------- CEC configuration ---------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) ==
+ RCC_PERIPHCLK_CEC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ }
+
+ /*---------------------------- USBPHY configuration ------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) ==
+ RCC_PERIPHCLK_USBPHY)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USBPHYCLKSOURCE(PeriphClkInit->UsbphyClockSelection));
+
+ if (PeriphClkInit->UsbphyClockSelection == RCC_USBPHYCLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable USB PHY Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+ }
+
+ __HAL_RCC_USBPHY_CONFIG(PeriphClkInit->UsbphyClockSelection);
+ }
+
+ /*---------------------------- USBO configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBO) ==
+ RCC_PERIPHCLK_USBO)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_USBOCLKSOURCE(PeriphClkInit->UsboClockSelection));
+
+ if (PeriphClkInit->UsboClockSelection == RCC_USBOCLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable USB OTG Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+ }
+
+ __HAL_RCC_USBO_CONFIG(PeriphClkInit->UsboClockSelection);
+ }
+
+ /*---------------------------- RNG1 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG1) ==
+ RCC_PERIPHCLK_RNG1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_RNG1CLKSOURCE(PeriphClkInit->Rng1ClockSelection));
+
+ if (PeriphClkInit->Rng1ClockSelection == RCC_RNG1CLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable RNG1 Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+ }
+
+ /* Set the source of RNG1 clock*/
+ __HAL_RCC_RNG1_CONFIG(PeriphClkInit->Rng1ClockSelection);
+ }
+
+ /*---------------------------- RNG2 configuration --------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG2) ==
+ RCC_PERIPHCLK_RNG2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_RNG2CLKSOURCE(PeriphClkInit->Rng2ClockSelection));
+
+ if (PeriphClkInit->Rng2ClockSelection == RCC_RNG2CLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable RNG2 Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+ }
+
+ /* Set the source of RNG2 clock*/
+ __HAL_RCC_RNG2_CONFIG(PeriphClkInit->Rng2ClockSelection);
+ }
+
+ /*---------------------------- STGEN configuration -------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_STGEN) ==
+ RCC_PERIPHCLK_STGEN)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_STGENCLKSOURCE(PeriphClkInit->StgenClockSelection));
+
+ __HAL_RCC_STGEN_CONFIG(PeriphClkInit->StgenClockSelection);
+ }
+
+#if defined(DSI)
+ /*---------------------------- DSI configuration ---------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) ==
+ RCC_PERIPHCLK_DSI)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));
+
+ if (PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable DSI Clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+ }
+
+ __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
+ }
+#endif /*DSI*/
+
+ /*---------------------------- ADC configuration ---------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) ==
+ RCC_PERIPHCLK_ADC)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
+
+ switch (PeriphClkInit->AdcClockSelection)
+ {
+ case RCC_ADCCLKSOURCE_PLL4: /* PLL4 is used as clock source for ADC */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable ADC Clock output generated on PLL4 */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
+ break;
+
+ case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable ADC Clock output generated on PLL3 */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+ }
+
+ /* Set the source of ADC clock*/
+ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+ }
+
+ /*---------------------------- LPTIM45 configuration -----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM45) ==
+ RCC_PERIPHCLK_LPTIM45)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM45CLKSOURCE(PeriphClkInit->Lptim45ClockSelection));
+
+ switch (PeriphClkInit->Lptim45ClockSelection)
+ {
+ case RCC_LPTIM45CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM45 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_LPTIM45CLKSOURCE_PLL4: /* PLL4 is used as clock source for LPTIM45 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+ }
+
+ /* Set the source of LPTIM45 clock*/
+ __HAL_RCC_LPTIM45_CONFIG(PeriphClkInit->Lptim45ClockSelection);
+ }
+
+ /*---------------------------- LPTIM23 configuration -----------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM23) ==
+ RCC_PERIPHCLK_LPTIM23)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM23CLKSOURCE(PeriphClkInit->Lptim23ClockSelection));
+
+ if (PeriphClkInit->Lptim23ClockSelection == RCC_LPTIM23CLKSOURCE_PLL4)
+ {
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
+ }
+
+ /* Set the source of LPTIM23 clock*/
+ __HAL_RCC_LPTIM23_CONFIG(PeriphClkInit->Lptim23ClockSelection);
+ }
+
+ /*---------------------------- LPTIM1 configuration ------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) ==
+ RCC_PERIPHCLK_LPTIM1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+ switch (PeriphClkInit->Lptim1ClockSelection)
+ {
+ case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1 */
+
+ status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable clock output generated on PLL3 . */
+ __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+
+ break;
+
+ case RCC_LPTIM1CLKSOURCE_PLL4: /* PLL4 is used as clock source for LPTIM1 */
+
+ status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
+ if (status != HAL_OK)
+ {
+ return status;
+ }
+ /* Enable clock output generated on PLL4 . */
+ __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
+
+ break;
+ }
+
+ /* Set the source of LPTIM1 clock*/
+ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ }
+
+ /*---------------------------- RTC configuration ---------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) ==
+ RCC_PERIPHCLK_RTC)
+ {
+ /* check for RTC Parameters used to output RTCCLK */
+ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR1, PWR_CR1_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while ((PWR->CR1 & PWR_CR1_DBP) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
+ {
+ ret = HAL_TIMEOUT;
+ }
+ }
+
+ if (ret == HAL_OK)
+ {
+ /* Reset the Backup domain only if the RTC Clock source selection is modified */
+ if ((RCC->BDCR & RCC_BDCR_RTCSRC) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSRC))
+ {
+ /* Store the content of BDCR register before the reset of Backup Domain */
+ tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSRC));
+ /* RTC Clock selection can be changed only if the Backup Domain is reset */
+ __HAL_RCC_BACKUPRESET_FORCE();
+ __HAL_RCC_BACKUPRESET_RELEASE();
+
+ /* Set the LSEDrive value */
+ __HAL_RCC_LSEDRIVE_CONFIG(tmpreg & RCC_BDCR_LSEDRV);
+
+ /* RCC_BDCR_LSEON can be enabled for RTC or another IP, re-enable it */
+ RCC_OscInitTypeDef RCC_OscInitStructure;
+ /* Configure LSE Oscillator*/
+ RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStructure.LSEState = (tmpreg & LSE_MASK);
+
+ RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStructure.PLL2.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStructure.PLL3.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStructure.PLL4.PLLState = RCC_PLL_NONE;
+ ret = HAL_RCC_OscConfig(&RCC_OscInitStructure);
+ if (ret != HAL_OK)
+ {
+ return ret;
+ }
+
+ /* Write the RTCSRC */
+ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+
+ /* Fill up Reserved register mask for BDCR
+ * All already filled up or what shouldn't be modified must be put on the mask */
+ RESERVED_BDCR_MASK = ~(RCC_BDCR_VSWRST | RCC_BDCR_RTCCKEN | RCC_BDCR_RTCSRC |
+ RCC_BDCR_LSECSSD | RCC_BDCR_LSEDRV | RCC_BDCR_DIGBYP |
+ RCC_BDCR_LSERDY | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
+
+ /* Restore the BDCR context: RESERVED registers plus RCC_BDCR_LSECSSON */
+ WRITE_REG(RCC->BDCR, (READ_REG(RCC->BDCR) | (tmpreg & RESERVED_BDCR_MASK)));
+
+ }/* End RTCSRC changed */
+
+ /*Enable RTC clock */
+ __HAL_RCC_RTC_ENABLE();
+ }
+ else
+ {
+ // Enable write access to Backup domain failed
+ /* return the error */
+ return ret;
+ }
+ }
+
+ /*---------------------------- TIMG1 configuration -------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMG1) ==
+ RCC_PERIPHCLK_TIMG1)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIMG1PRES(PeriphClkInit->TIMG1PresSelection));
+
+ /* Set TIMG1 division factor */
+ __HAL_RCC_TIMG1PRES(PeriphClkInit->TIMG1PresSelection);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till TIMG1 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_TIMG1PRERDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /*---------------------------- TIMG2 configuration -------------------------*/
+ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMG2) ==
+ RCC_PERIPHCLK_TIMG2)
+ {
+ /* Check the parameters */
+ assert_param(IS_RCC_TIMG2PRES(PeriphClkInit->TIMG2PresSelection));
+
+ /* Set TIMG1 division factor */
+ __HAL_RCC_TIMG2PRES(PeriphClkInit->TIMG2PresSelection);
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
+ /* Wait till TIMG1 is ready */
+ while (__HAL_RCC_GET_FLAG(RCC_FLAG_TIMG2PRERDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief Get the RCC_ClkInitStruct according to the internal RCC
+ * configuration registers.
+ * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * returns the configuration information for the Extended Peripherals
+ * clocks : CKPER, I2C12, I2C35, I2C46, I2C5, SAI1, SAI2, SAI3, SAI4,
+ * SPI1, SPI2, SPI3, SPI45, SPI6, USART1, UART24, USART3, UART24, UART35,
+ * USART6, UART78, SDMMC12, SDMMC3, ETH, QSPI,FMC, FDCAN,
+ * SPDIFRX, CEC, USBPHY, USBO, RNG1, RNG2, STGEN, DSI, ADC, RTC,
+ * LPTIM1, LPTIM23, LPTIM45
+ * @retval None
+ */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
+{
+ /* Set all possible values for the extended clock type parameter------------*/
+ PeriphClkInit->PeriphClockSelection =
+ RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_I2C12 | RCC_PERIPHCLK_I2C35 |
+ RCC_PERIPHCLK_I2C46 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |
+ RCC_PERIPHCLK_SAI3 | RCC_PERIPHCLK_SAI4 | RCC_PERIPHCLK_SPI1 |
+ RCC_PERIPHCLK_SPI23 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 |
+ RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_UART24 | RCC_PERIPHCLK_UART35 |
+ RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART78 | RCC_PERIPHCLK_SDMMC12 |
+ RCC_PERIPHCLK_SDMMC3 | RCC_PERIPHCLK_ETH | RCC_PERIPHCLK_QSPI |
+ RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SPDIFRX |
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_USBO |
+ RCC_PERIPHCLK_RNG1 | RCC_PERIPHCLK_RNG2 | RCC_PERIPHCLK_STGEN |
+ RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC |
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM23 | RCC_PERIPHCLK_LPTIM45;
+
+ /* Get the CKPER clock source ----------------------------------------------*/
+ PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CKPER_SOURCE();
+
+ /* Get the I2C12 clock source ----------------------------------------------*/
+ PeriphClkInit->I2c12ClockSelection = __HAL_RCC_GET_I2C12_SOURCE();
+ /* Get the I2C35 clock source ----------------------------------------------*/
+ PeriphClkInit->I2c35ClockSelection = __HAL_RCC_GET_I2C35_SOURCE();
+ /* Get the I2C46 clock source -----------------------------------------------*/
+ PeriphClkInit->I2c46ClockSelection = __HAL_RCC_GET_I2C46_SOURCE();
+
+ /* Get the SAI1 clock source -----------------------------------------------*/
+ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+ /* Get the SAI2 clock source -----------------------------------------------*/
+ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+ /* Get the SAI3 clock source -----------------------------------------------*/
+ PeriphClkInit->Sai3ClockSelection = __HAL_RCC_GET_SAI3_SOURCE();
+ /* Get the SAI4 clock source -----------------------------------------------*/
+ PeriphClkInit->Sai4ClockSelection = __HAL_RCC_GET_SAI4_SOURCE();
+
+ /* Get the SPI1 clock source -----------------------------------------------*/
+ PeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
+ /* Get the SPI23 clock source ----------------------------------------------*/
+ PeriphClkInit->Spi23ClockSelection = __HAL_RCC_GET_SPI23_SOURCE();
+ /* Get the SPI45 clock source ----------------------------------------------*/
+ PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
+ /* Get the SPI6 clock source -----------------------------------------------*/
+ PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
+
+ /* Get the USART1 configuration --------------------------------------------*/
+ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
+ /* Get the UART24 clock source ----------------------------------------------*/
+ PeriphClkInit->Uart24ClockSelection = __HAL_RCC_GET_UART24_SOURCE();
+ /* Get the UART35 clock source ---------------------------------------------*/
+ PeriphClkInit->Uart35ClockSelection = __HAL_RCC_GET_UART35_SOURCE();
+ /* Get the USART6 clock source ---------------------------------------------*/
+ PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
+ /* Get the UART78 clock source ---------------------------------------------*/
+ PeriphClkInit->Uart78ClockSelection = __HAL_RCC_GET_UART78_SOURCE();
+
+ /* Get the SDMMC12 clock source --------------------------------------------*/
+ PeriphClkInit->Sdmmc12ClockSelection = __HAL_RCC_GET_SDMMC12_SOURCE();
+ /* Get the SDMMC3 clock source ---------------------------------------------*/
+ PeriphClkInit->Sdmmc3ClockSelection = __HAL_RCC_GET_SDMMC3_SOURCE();
+ /* Get the SDMMC3 clock source ---------------------------------------------*/
+ PeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE();
+
+ /* Get the QSPI clock source -----------------------------------------------*/
+ PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
+ /* Get the FMC clock source ------------------------------------------------*/
+ PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
+#if defined(FDCAN1)
+ /* Get the FDCAN clock source ----------------------------------------------*/
+ PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
+#endif /*FDCAN1*/
+ /* Get the SPDIFRX clock source --------------------------------------------*/
+ PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
+ /* Get the CEC clock source ------------------------------------------------*/
+ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+ /* Get the USBPHY clock source ---------------------------------------------*/
+ PeriphClkInit-> UsbphyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE();
+ /* Get the USBO clock source -----------------------------------------------*/
+ PeriphClkInit-> UsboClockSelection = __HAL_RCC_GET_USBO_SOURCE();
+ /* Get the RNG1 clock source -----------------------------------------------*/
+ PeriphClkInit->Rng1ClockSelection = __HAL_RCC_GET_RNG1_SOURCE();
+ /* Get the RNG2 clock source -----------------------------------------------*/
+ PeriphClkInit->Rng2ClockSelection = __HAL_RCC_GET_RNG2_SOURCE();
+ /* Get the STGEN clock source ----------------------------------------------*/
+ PeriphClkInit->StgenClockSelection = __HAL_RCC_GET_STGEN_SOURCE();
+#if defined(DSI)
+ /* Get the DSI clock source ------------------------------------------------*/
+ PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
+#endif /*DSI*/
+ /* Get the ADC clock source ------------------------------------------------*/
+ PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
+ /* Get the RTC clock source ------------------------------------------------*/
+ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
+
+ /* Get the LPTIM1 clock source ---------------------------------------------*/
+ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+ /* Get the LPTIM23 clock source ---------------------------------------------*/
+ PeriphClkInit->Lptim23ClockSelection = __HAL_RCC_GET_LPTIM23_SOURCE();
+ /* Get the LPTIM45 clock source ---------------------------------------------*/
+ PeriphClkInit->Lptim45ClockSelection = __HAL_RCC_GET_LPTIM45_SOURCE();
+
+ /* Get the TIM1 Prescaler configuration ------------------------------------*/
+ PeriphClkInit->TIMG1PresSelection = __HAL_RCC_GET_TIMG1PRES();
+ /* Get the TIM2 Prescaler configuration ------------------------------------*/
+ PeriphClkInit->TIMG2PresSelection = __HAL_RCC_GET_TIMG2PRES();
+}
+
+/**
+ * @brief Enables the LSE Clock Security System.
+ * @note After reset BDCR register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
+ * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
+ * clock with HAL_RCCEx_PeriphCLKConfig().
+ * @retval None
+ */
+void HAL_RCCEx_EnableLSECSS(void)
+{
+ /* Set LSECSSON bit */
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+/**
+ * @brief Disables the LSE Clock Security System.
+ * @note LSE Clock Security System can only be disabled after a LSE failure detection.
+ * @note After reset BDCR register is write-protected and the DBP bit in the
+ * PWR control register 1 (PWR_CR1) has to be set before it can be written.
+ * @retval None
+ */
+void HAL_RCCEx_DisableLSECSS(void)
+{
+ /* Unset LSECSSON bit */
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
+}
+
+
+/**
+ * @brief Returns the peripheral clock frequency
+ * @note Returns 0 if peripheral clock is unknown
+ * @param PeriphClk: Peripheral clock identifier
+ * This parameter can be a value of :
+ * @ref RCCEx_Periph_Clock_Selection
+ * @ref RCCEx_Periph_One_Clock
+ * @retval Frequency in Hz
+ */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
+{
+ uint32_t frequency = 0, clksource = 0;
+
+ PLL2_ClocksTypeDef pll2_clocks;
+ PLL3_ClocksTypeDef pll3_clocks;
+ PLL4_ClocksTypeDef pll4_clocks;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk) || IS_RCC_PERIPHONECLOCK(PeriphClk));
+
+ switch (PeriphClk)
+ {
+
+ case RCC_PERIPHCLK_DAC:
+ {
+ frequency = LSI_VALUE;
+ }
+ break; /*RCC_PERIPHCLK_DAC*/
+
+
+ case RCC_PERIPHCLK_WWDG:
+ {
+ frequency = HAL_RCC_GetPCLK1Freq();
+ }
+ break; /* RCC_PERIPHCLK_WWDG */
+
+
+ case RCC_PERIPHCLK_CEC:
+ {
+ clksource = __HAL_RCC_GET_CEC_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_CECCLKSOURCE_LSE:
+ frequency = LSE_VALUE;
+ break;
+
+ case RCC_CECCLKSOURCE_LSI:
+ frequency = LSI_VALUE;
+ break;
+
+ case RCC_CECCLKSOURCE_CSI122:
+ frequency = (CSI_VALUE / 122);
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_CEC */
+
+
+ case RCC_PERIPHCLK_I2C12:
+ {
+ clksource = __HAL_RCC_GET_I2C12_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_I2C12CLKSOURCE_PCLK1:
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_I2C12CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ case RCC_I2C12CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_I2C12CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_I2C12 */
+
+
+ case RCC_PERIPHCLK_I2C35:
+ {
+ clksource = __HAL_RCC_GET_I2C35_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_I2C35CLKSOURCE_PCLK1:
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_I2C35CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ case RCC_I2C35CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_I2C35CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_I2C35 */
+
+
+ case RCC_PERIPHCLK_LPTIM1:
+ {
+ clksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_LPTIM1CLKSOURCE_PCLK1:
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_LPTIM1CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_LPTIM1CLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_LPTIM1CLKSOURCE_LSE:
+ frequency = LSE_VALUE;
+ break;
+
+ case RCC_LPTIM1CLKSOURCE_LSI:
+ frequency = LSI_VALUE;
+ break;
+
+ case RCC_LPTIM1CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_LPTIM1 */
+
+
+ case RCC_PERIPHCLK_SPDIFRX:
+ {
+ clksource = __HAL_RCC_GET_SPDIFRX_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SPDIFRXCLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_SPDIFRXCLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_SPDIFRXCLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_SPDIFRX */
+
+ case RCC_PERIPHCLK_SPI23:
+ {
+ clksource = __HAL_RCC_GET_SPI23_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SPI23CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_SPI23CLKSOURCE_PLL3_Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_SPI23CLKSOURCE_PLL3_R:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SPI23CLKSOURCE_I2SCKIN:
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case RCC_SPI23CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_SPI23 */
+
+
+ case RCC_PERIPHCLK_UART24:
+ {
+ clksource = __HAL_RCC_GET_UART24_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_UART24CLKSOURCE_PCLK1:
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_UART24CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_UART24CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_UART24CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_UART24CLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_UART24 */
+
+
+ case RCC_PERIPHCLK_UART35:
+ {
+ clksource = __HAL_RCC_GET_UART35_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_UART35CLKSOURCE_PCLK1:
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_UART35CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_UART35CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_UART35CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_UART35CLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_USART35 */
+
+
+ case RCC_PERIPHCLK_UART78:
+ {
+ clksource = __HAL_RCC_GET_UART78_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_UART78CLKSOURCE_PCLK1:
+ frequency = HAL_RCC_GetPCLK1Freq();
+ break;
+
+ case RCC_UART78CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_UART78CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_UART78CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_UART78CLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /*RCC_PERIPHCLK_UART78 */
+
+
+ case RCC_PERIPHCLK_DFSDM1:
+ {
+ frequency = HAL_RCC_GetMLHCLKFreq();
+ }
+ break;//RCC_PERIPHCLK_DFSDM1
+
+#if defined(FDCAN1)
+ case RCC_PERIPHCLK_FDCAN:
+ {
+ clksource = __HAL_RCC_GET_FDCAN_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_FDCANCLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ case RCC_FDCANCLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_FDCANCLKSOURCE_PLL4_Q:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_FDCANCLKSOURCE_PLL4_R:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_FDCAN
+#endif /*FDCAN1*/
+
+ case RCC_PERIPHCLK_SAI1:
+ {
+ clksource = __HAL_RCC_GET_SAI1_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SAI1CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL3_Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_SAI1CLKSOURCE_PLL3_R:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SAI1CLKSOURCE_I2SCKIN:
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI1CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_SAI1
+
+
+ case RCC_PERIPHCLK_SAI2:
+ {
+ clksource = __HAL_RCC_GET_SAI2_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SAI2CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL3_Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PLL3_R:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SAI2CLKSOURCE_I2SCKIN:
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ case RCC_SAI2CLKSOURCE_SPDIF:
+ frequency = 0; //SAI2 manage this SPDIF_CKSYMB_VALUE
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_SAI2
+
+
+ case RCC_PERIPHCLK_SAI3:
+ {
+ clksource = __HAL_RCC_GET_SAI3_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SAI3CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_SAI3CLKSOURCE_PLL3_Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_SAI3CLKSOURCE_PLL3_R:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SAI3CLKSOURCE_I2SCKIN:
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI2CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_SAI3
+
+
+ case RCC_PERIPHCLK_SPI1:
+ {
+ clksource = __HAL_RCC_GET_SPI1_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SPI1CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_SPI1CLKSOURCE_PLL3_Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_SPI1CLKSOURCE_PLL3_R:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SPI1CLKSOURCE_I2SCKIN:
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case RCC_SPI1CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_SPI1
+
+
+ case RCC_PERIPHCLK_SPI45:
+ {
+ clksource = __HAL_RCC_GET_SPI45_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SPI45CLKSOURCE_PCLK2:
+ frequency = HAL_RCC_GetPCLK2Freq();
+ break;
+
+ case RCC_SPI45CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_SPI45CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_SPI45CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_SPI45CLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_SPI45 */
+
+
+ case RCC_PERIPHCLK_USART6:
+ {
+ clksource = __HAL_RCC_GET_USART6_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_USART6CLKSOURCE_PCLK2:
+ frequency = HAL_RCC_GetPCLK2Freq();
+ break;
+
+ case RCC_USART6CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_USART6CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_USART6CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_USART6CLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_USART6
+
+ case RCC_PERIPHCLK_LPTIM23:
+ {
+ clksource = __HAL_RCC_GET_LPTIM23_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_LPTIM23CLKSOURCE_PCLK3:
+ frequency = HAL_RCC_GetPCLK3Freq();
+ break;
+
+ case RCC_LPTIM23CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_LPTIM23CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ case RCC_LPTIM23CLKSOURCE_LSE:
+ frequency = LSE_VALUE;
+ break;
+
+ case RCC_LPTIM23CLKSOURCE_LSI:
+ frequency = LSI_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_LPTIM23 */
+
+ case RCC_PERIPHCLK_LPTIM45:
+ {
+ clksource = __HAL_RCC_GET_LPTIM45_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_LPTIM45CLKSOURCE_PCLK3:
+ frequency = HAL_RCC_GetPCLK3Freq();
+ break;
+
+ case RCC_LPTIM45CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_LPTIM45CLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_LPTIM45CLKSOURCE_LSE:
+ frequency = LSE_VALUE;
+ break;
+
+ case RCC_LPTIM45CLKSOURCE_LSI:
+ frequency = LSI_VALUE;
+ break;
+
+ case RCC_LPTIM45CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_LPTIM45 */
+
+
+ case RCC_PERIPHCLK_SAI4:
+ {
+ clksource = __HAL_RCC_GET_SAI4_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SAI4CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_SAI4CLKSOURCE_PLL3_Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_SAI4CLKSOURCE_PLL3_R:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SAI4CLKSOURCE_I2SCKIN:
+ frequency = EXTERNAL_CLOCK_VALUE;
+ break;
+
+ case RCC_SAI4CLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_SAI4
+
+
+ case RCC_PERIPHCLK_TEMP:
+ {
+ frequency = LSE_VALUE;
+ }
+ break;//RCC_PERIPHCLK_TEMP
+
+
+#if defined(DSI)
+ case RCC_PERIPHCLK_DSI:
+ {
+ clksource = __HAL_RCC_GET_DSI_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_DSICLKSOURCE_PHY:
+ /* It has no sense to ask for DSIPHY freq. because it is generated
+ * by DSI itself, so send back 0 as kernel frequency
+ */
+ frequency = 0;
+ break;
+
+ case RCC_DSICLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_DSI
+#endif /*DSI*/
+
+ case RCC_PERIPHCLK_LTDC:
+ {
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ }
+ break;//RCC_PERIPHCLK_LTDC
+
+
+ case RCC_PERIPHCLK_USBPHY:
+ {
+ clksource = __HAL_RCC_GET_USBPHY_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_USBPHYCLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ case RCC_USBPHYCLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ case RCC_USBPHYCLKSOURCE_HSE2:
+ frequency = (HSE_VALUE / 2);
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_USBPHY
+
+
+ case RCC_PERIPHCLK_IWDG2:
+ {
+ frequency = LSI_VALUE;
+ }
+ break;//RCC_PERIPHCLK_IWDG2
+
+
+ case RCC_PERIPHCLK_DDRPHYC:
+ {
+ HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_R_Frequency;
+ }
+ break;//RCC_PERIPHCLK_DDRPHYC
+
+
+ case RCC_PERIPHCLK_RTC:
+ {
+ clksource = __HAL_RCC_GET_RTC_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_RTCCLKSOURCE_OFF:
+ frequency = 0;
+ break;
+
+ case RCC_RTCCLKSOURCE_LSE:
+ frequency = LSE_VALUE;
+ break;
+
+ case RCC_RTCCLKSOURCE_LSI:
+ frequency = LSI_VALUE;
+ break;
+
+ case RCC_RTCCLKSOURCE_HSE_DIV:
+ frequency = (HSE_VALUE / __HAL_RCC_GET_RTC_HSEDIV());
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_RTC
+
+
+ case RCC_PERIPHCLK_IWDG1:
+ {
+ frequency = LSI_VALUE;
+ }
+ break;//RCC_PERIPHCLK_IWDG1
+
+
+ case RCC_PERIPHCLK_I2C46:
+ {
+ clksource = __HAL_RCC_GET_I2C46_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_I2C46CLKSOURCE_PCLK5:
+ frequency = HAL_RCC_GetPCLK5Freq();
+ break;
+
+ case RCC_I2C46CLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_I2C46CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_I2C46CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_I2C46 */
+
+
+ case RCC_PERIPHCLK_SPI6:
+ {
+ clksource = __HAL_RCC_GET_SPI6_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SPI6CLKSOURCE_PCLK5:
+ frequency = HAL_RCC_GetPCLK5Freq();
+ break;
+
+ case RCC_SPI6CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_SPI6CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_SPI6CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_SPI6CLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ case RCC_SPI6CLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_SPI6
+
+ case RCC_PERIPHCLK_USART1:
+ {
+ clksource = __HAL_RCC_GET_USART1_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_USART1CLKSOURCE_PCLK5:
+ frequency = HAL_RCC_GetPCLK5Freq();
+ break;
+
+ case RCC_USART1CLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ case RCC_USART1CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_USART1CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_USART1CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_Q_Frequency;
+ break;
+
+ case RCC_USART1CLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_USART1
+
+
+ case RCC_PERIPHCLK_STGEN:
+ {
+ clksource = __HAL_RCC_GET_STGEN_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_STGENCLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ case RCC_STGENCLKSOURCE_HSE:
+ frequency = HSE_VALUE;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_STGEN
+
+
+ case RCC_PERIPHCLK_QSPI:
+ {
+ clksource = __HAL_RCC_GET_QSPI_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_QSPICLKSOURCE_ACLK:
+ frequency = HAL_RCC_GetACLKFreq();
+ break;
+
+ case RCC_QSPICLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_QSPICLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_QSPICLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_QSPI
+
+
+ case RCC_PERIPHCLK_ETH:
+ {
+ clksource = __HAL_RCC_GET_ETH_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_ETHCLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_ETHCLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_ETH
+
+
+ case RCC_PERIPHCLK_FMC:
+ {
+ clksource = __HAL_RCC_GET_FMC_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_FMCCLKSOURCE_ACLK:
+ frequency = HAL_RCC_GetACLKFreq();
+ break;
+
+ case RCC_FMCCLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_FMCCLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_FMCCLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ }
+ }
+ break;//RCC_PERIPHCLK_FMC
+
+
+ case RCC_PERIPHCLK_GPU:
+ {
+ HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
+ frequency = pll2_clocks.PLL2_Q_Frequency;
+ }
+ break;//RCC_PERIPHCLK_GPU
+
+
+ case RCC_PERIPHCLK_USBO:
+ {
+ clksource = __HAL_RCC_GET_USBO_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_USBOCLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ case RCC_USBOCLKSOURCE_PHY:
+ frequency = USB_PHY_VALUE;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_USBO
+
+
+ case RCC_PERIPHCLK_SDMMC3:
+ {
+ clksource = __HAL_RCC_GET_SDMMC3_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SDMMC3CLKSOURCE_HCLK2:
+ frequency = HAL_RCC_GetHCLK2Freq();
+ break;
+
+ case RCC_SDMMC3CLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SDMMC3CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_SDMMC3CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_SDMMC3
+
+
+ case RCC_PERIPHCLK_ADC:
+ {
+ clksource = __HAL_RCC_GET_ADC_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_ADCCLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ case RCC_ADCCLKSOURCE_PER:
+ frequency = RCC_GetCKPERFreq();
+ break;
+
+ case RCC_ADCCLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_Q_Frequency;
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_ADC */
+
+
+ case RCC_PERIPHCLK_RNG2:
+ {
+ clksource = __HAL_RCC_GET_RNG2_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_RNG2CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_RNG2CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ case RCC_RNG2CLKSOURCE_LSE:
+ frequency = LSE_VALUE;
+ break;
+
+ case RCC_RNG2CLKSOURCE_LSI:
+ frequency = LSI_VALUE;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_RNG2
+
+
+ case RCC_PERIPHCLK_RNG1:
+ {
+ clksource = __HAL_RCC_GET_RNG1_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_RNG1CLKSOURCE_CSI:
+ frequency = CSI_VALUE;
+ break;
+
+ case RCC_RNG1CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_R_Frequency;
+ break;
+
+ case RCC_RNG1CLKSOURCE_LSE:
+ frequency = LSE_VALUE;
+ break;
+
+ case RCC_RNG1CLKSOURCE_LSI:
+ frequency = LSI_VALUE;
+ break;
+ }
+ }
+ break;//RCC_PERIPHCLK_RNG1
+
+ case RCC_PERIPHCLK_SDMMC12:
+ {
+ clksource = __HAL_RCC_GET_SDMMC12_SOURCE();
+
+ switch (clksource)
+ {
+ case RCC_SDMMC12CLKSOURCE_HCLK6:
+ frequency = HAL_RCC_GetHCLK6Freq();
+ break;
+
+ case RCC_SDMMC12CLKSOURCE_PLL3:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ frequency = pll3_clocks.PLL3_R_Frequency;
+ break;
+
+ case RCC_SDMMC12CLKSOURCE_PLL4:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ frequency = pll4_clocks.PLL4_P_Frequency;
+ break;
+
+ case RCC_SDMMC12CLKSOURCE_HSI:
+ frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
+ break;
+
+ default:
+ frequency = 0;
+ break;
+ }
+ }
+ break; /* RCC_PERIPHCLK_SDMMC12 */
+
+ case RCC_PERIPHCLK_TIMG1:
+ {
+ frequency = HAL_RCC_GetMCUFreq();
+ if (__HAL_RCC_GET_TIMG1PRES() == RCC_TIMG1PRES_ACTIVATED)
+ {
+ switch (__HAL_RCC_GET_APB1_DIV())
+ {
+ case RCC_APB1_DIV1:
+ case RCC_APB1_DIV2:
+ case RCC_APB1_DIV4:
+ break;
+ case RCC_APB1_DIV8:
+ frequency /= 2;
+ break;
+ case RCC_APB1_DIV16:
+ frequency /= 4;
+ break;
+ }
+ }
+ else
+ {
+ switch (__HAL_RCC_GET_APB1_DIV())
+ {
+ case RCC_APB1_DIV1:
+ case RCC_APB1_DIV2:
+ break;
+ case RCC_APB1_DIV4:
+ frequency /= 2;
+ break;
+ case RCC_APB1_DIV8:
+ frequency /= 4;
+ break;
+ case RCC_APB1_DIV16:
+ frequency /= 8;
+ break;
+ }
+ }
+ }
+ break;
+
+
+ case RCC_PERIPHCLK_TIMG2:
+ {
+ frequency = HAL_RCC_GetMCUFreq();
+ if (__HAL_RCC_GET_TIMG2PRES() == RCC_TIMG2PRES_ACTIVATED)
+ {
+ switch (__HAL_RCC_GET_APB2_DIV())
+ {
+ case RCC_APB2_DIV1:
+ case RCC_APB2_DIV2:
+ case RCC_APB2_DIV4:
+ break;
+ case RCC_APB2_DIV8:
+ frequency /= 2;
+ break;
+ case RCC_APB2_DIV16:
+ frequency /= 4;
+ break;
+ }
+ }
+ else
+ {
+ switch (__HAL_RCC_GET_APB2_DIV())
+ {
+ case RCC_APB2_DIV1:
+ case RCC_APB2_DIV2:
+ break;
+ case RCC_APB2_DIV4:
+ frequency /= 2;
+ break;
+ case RCC_APB2_DIV8:
+ frequency /= 4;
+ break;
+ case RCC_APB2_DIV16:
+ frequency /= 8;
+ break;
+ }
+ }
+ }
+ break;
+
+ }
+
+ return (frequency);
+}
+
+#ifdef CORE_CA7
+/**
+ * @brief Control the enable boot function when the system exits from STANDBY
+ * @param RCC_BootCx: Boot Core to be enabled (set to 1)
+ * This parameter can be one (or both) of the following values:
+ * @arg RCC_BOOT_C1: CA7 core selection
+ * @arg RCC_BOOT_C2: CM4 core selection
+ *
+ * @note Next combinations are possible:
+ * RCC_BOOT_C1 RCC_BOOT_C2 Expected result
+ * 0 0 MPU boots, MCU does not boot
+ * 0 1 Only MCU boots
+ * 1 0 Only MPU boots
+ * 1 1 MPU and MCU boot
+ *
+ * @note This function is reset when a system reset occurs, but not when the
+ * circuit exits from STANDBY (rst_app reset)
+ * @note This function can only be called by the CA7
+ * @retval None
+ */
+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
+{
+ assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
+ SET_BIT(RCC->MP_BOOTCR, RCC_BootCx);
+}
+
+/**
+ * @brief Control the disable boot function when the system exits from STANDBY
+ * @param RCC_BootCx: Boot Core to be disabled (set to 0)
+ * This parameter can be one (or both) of the following values:
+ * @arg RCC_BOOT_C1: CA7 core selection
+ * @arg RCC_BOOT_C2: CM4 core selection
+ *
+ * @note Next combinations are possible:
+ * RCC_BOOT_C1 RCC_BOOT_C2 Expected result
+ * 0 0 MPU boots, MCU does not boot
+ * 0 1 Only MCU boots
+ * 1 0 Only MPU boots
+ * 1 1 MPU and MCU boot
+ *
+ * @note This function is reset when a system reset occurs, but not when the
+ * circuit exits from STANDBY (rst_app reset)
+ * @note This function can only be called by the CA7
+ * @retval None
+ */
+void HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx)
+{
+ assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
+ CLEAR_BIT(RCC->MP_BOOTCR, RCC_BootCx);
+}
+
+
+/**
+ * @brief The MCU will be set in HOLD_BOOT when the next MCU core reset occurs
+ * @retval None
+ */
+void HAL_RCCEx_HoldBootMCU(void)
+{
+ CLEAR_BIT(RCC->MP_GCR, RCC_MP_GCR_BOOT_MCU);
+}
+
+/**
+ * @brief The MCU will not be in HOLD_BOOT mode when the next MCU core reset occurs.
+ * @note If the MCU was in HOLD_BOOT it will cause the MCU to boot.
+ * @retval None
+ */
+void HAL_RCCEx_BootMCU(void)
+{
+ SET_BIT(RCC->MP_GCR, RCC_MP_GCR_BOOT_MCU);
+}
+
+#endif /*CORE_CA7*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
new file mode 100644
index 0000000..bd68e95
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
@@ -0,0 +1,3796 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_spi.c
+ * @author MCD Application Team
+ * @brief SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Serial Peripheral Interface (SPI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The SPI HAL driver can be used as follows:
+
+ (#) Declare a SPI_HandleTypeDef handle structure, for example:
+ SPI_HandleTypeDef hspi;
+
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
+ (##) SPI pins configuration
+ (+++) Enable the clock for the SPI GPIOs
+ (+++) Configure these SPI pins as alternate function push-pull
+ (##) NVIC configuration if you need to use interrupt process or DMA process
+ (+++) Configure the SPIx interrupt priority
+ (+++) Enable the NVIC SPI IRQ handle
+ (##) DMA Configuration if you need to use DMA process
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
+ (+++) Enable the DMAx clock
+ (+++) Configure the DMA handle parameters
+ (+++) Configure the DMA Tx or Rx Stream/Channel
+ (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
+ management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
+
+ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SPI_MspInit() API.
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : SPI Tx Completed callback
+ (+) RxCpltCallback : SPI Rx Completed callback
+ (+) TxRxCpltCallback : SPI TxRx Completed callback
+ (+) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (+) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (+) ErrorCallback : SPI Error callback
+ (+) AbortCpltCallback : SPI Abort callback
+ (+) MspInitCallback : SPI Msp Init callback
+ (+) MspDeInitCallback : SPI Msp DeInit callback
+
+ By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+ or HAL_SPI_Init() function.
+
+ When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ [..]
+ Circular mode restriction:
+ (+) The DMA circular mode cannot be used when the SPI is configured in these modes:
+ (++) Master 2Lines RxOnly
+ (++) Master 1Line Rx
+ (+) The CRC feature is not managed when the DMA circular mode is enabled
+ (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always
+ HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED.
+ Those functions are maintained for backward compatibility reasons.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPI SPI
+ * @brief SPI HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_DEFAULT_TIMEOUT 100UL
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
+ * @{
+ */
+#if defined(HAL_DMA_MODULE_ENABLED)
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SPI_DMAError(DMA_HandleTypeDef *hdma);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+#endif
+
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
+ uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
+static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and de-initialization functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
+
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
+ all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
+
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
+ the selected configuration:
+ (++) Mode
+ (++) Direction
+ (++) Data Size
+ (++) Clock Polarity and Phase
+ (++) NSS Management
+ (++) BaudRate Prescaler
+ (++) FirstBit
+ (++) TIMode
+ (++) CRC Calculation
+ (++) CRC Polynomial if CRC enabled
+ (++) CRC Length, used only with Data8 and Data16
+ (++) FIFO reception threshold
+ (++) FIFO transmission threshold
+
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+ uint32_t crc_length = 0UL;
+ uint32_t packet_length;
+
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+ assert_param(IS_SPI_MODE(hspi->Init.Mode));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
+ assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
+ assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold));
+ assert_param(IS_SPI_NSS(hspi->Init.NSS));
+ assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
+ assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ }
+#if (USE_SPI_CRC != 0UL)
+ assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
+ assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ /* Verify that the SPI instance supports Data Size higher than 16bits */
+ if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Verify that the SPI instance supports requested data packing */
+ packet_length = SPI_GetPacketSize(hspi);
+ if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) ||
+ ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)))
+ {
+ return HAL_ERROR;
+ }
+
+#if (USE_SPI_CRC != 0UL)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Verify that the SPI instance supports CRC Length higher than 16bits */
+ if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Align the CRC Length on the data size */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos;
+ }
+ else
+ {
+ crc_length = hspi->Init.CRCLength;
+ }
+
+ /* Verify that the CRC Length is higher than DataSize */
+ if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->State == HAL_SPI_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hspi->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ /* Init the SPI Callback settings */
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hspi->MspInitCallback == NULL)
+ {
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hspi->MspInitCallback(hspi);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the selected SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
+ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
+ Communication speed, First bit, CRC calculation state, CRC Length */
+
+ if ((hspi->Init.NSS == SPI_NSS_SOFT) && (hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
+ }
+
+ /* SPIx CFG1 Configuration */
+ WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
+ hspi->Init.FifoThreshold | hspi->Init.DataSize));
+
+ /* SPIx CFG2 Configuration */
+ WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | hspi->Init.NSSPolarity |
+ hspi->Init.NSS | hspi->Init.CLKPolarity | hspi->Init.CLKPhase |
+ hspi->Init.FirstBit | hspi->Init.Mode | hspi->Init.MasterInterDataIdleness |
+ hspi->Init.Direction | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
+
+#if (USE_SPI_CRC != 0UL)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
+ /* Configure : CRC Polynomial */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Initialize TXCRC Pattern Initial Value */
+ if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
+ }
+ else
+ {
+ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI);
+ }
+
+ /* Initialize RXCRC Pattern Initial Value */
+ if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
+ }
+ else
+ {
+ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI);
+ }
+
+ /* Enable 33/17 bits CRC computation */
+ if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
+ ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT)))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+ }
+ else
+ {
+ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+ }
+
+ /* Write CRC polynomial in SPI Register */
+ WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Insure that Underrun configuration is managed only by Salve */
+ if (hspi->Init.Mode == SPI_MODE_SLAVE)
+ {
+ /* Set Default Underrun configuration */
+#if (USE_SPI_CRC != 0UL)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE)
+#endif
+ {
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
+ }
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1);
+ }
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
+ /* Insure that AFCNTR is managed only by Master */
+ if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
+ {
+ /* Alternate function GPIOs control */
+ MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
+ }
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initialize the SPI peripheral.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Check the SPI handle allocation */
+ if (hspi == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check SPI Instance parameter */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
+ hspi->State = HAL_SPI_STATE_BUSY;
+
+ /* Disable the SPI Peripheral Clock */
+ __HAL_SPI_DISABLE(hspi);
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ if (hspi->MspDeInitCallback == NULL)
+ {
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hspi->MspDeInitCallback(hspi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->State = HAL_SPI_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
+}
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+/**
+ * @brief Register a User SPI Callback
+ * To be used instead of the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+
+/**
+ * @brief Unregister an SPI Callback
+ * SPI callback is redirected to the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SPI
+ data transfers.
+
+ [..] The SPI supports master and slave mode :
+
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (##) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
+ exist for 1Line (simplex) and 2Lines (full duplex) modes.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Transmit an amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pRxBuffPtr = NULL;
+ hspi->RxXferSize = (uint16_t) 0UL;
+ hspi->RxXferCount = (uint16_t) 0UL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Transmit data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ /* Transmit data in 32 Bit mode */
+ while (hspi->TxXferCount > 0UL)
+ {
+ /* Wait until TXP flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ /* Transmit data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Transmit data in 16 Bit mode */
+ while (hspi->TxXferCount > 0UL)
+ {
+ /* Wait until TXP flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+ {
+ if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ /* Transmit data in 8 Bit mode */
+ else
+ {
+ while (hspi->TxXferCount > 0UL)
+ {
+ /* Wait until TXP flag is set to send data */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
+ {
+ if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)4UL;
+ }
+ else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+ /* Wait for Tx (and CRC) data to be sent */
+ if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData : pointer to data buffer
+ * @param Size : amount of data to be received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint32_t tickstart;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pTxBuffPtr = NULL;
+ hspi->TxXferSize = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Receive data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0UL)
+ {
+ /* Check the RXWNE/EOT flag */
+ if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ /* Receive data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0UL)
+ {
+ /* Check the RXWNE/FRLVL flag */
+ if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ /* Transfer loop */
+ while (hspi->RxXferCount > 0UL)
+ {
+ /* Check the RXWNE/FRLVL flag */
+ if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)4UL;
+ }
+ else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ }
+ else
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ }
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+ }
+
+#if (USE_SPI_CRC != 0UL)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait for crc data to be received */
+ if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size : amount of data to be sent and received
+ * @param Timeout: Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
+{
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ uint32_t tickstart;
+ uint32_t tmp_mode;
+ uint16_t initial_TxXferCount;
+ uint16_t initial_RxXferCount;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ initial_TxXferCount = Size;
+ initial_RxXferCount = Size;
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ __HAL_SPI_ENABLE(hspi);
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Transmit and Receive data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+ {
+ /* Check TXP flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount --;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+
+ /* Check RXWNE/EOT flag */
+ if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL))
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount --;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ }
+
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ /* Transmit and Receive data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+ {
+ /* Check TXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL))
+ {
+ if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ }
+
+ /* Check RXWNE/FRLVL flag */
+ if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ }
+
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
+ {
+ /* check TXP flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+ {
+ if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
+ {
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount -= (uint16_t)4UL;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
+ {
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount -= (uint16_t)2UL;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ initial_TxXferCount = hspi->TxXferCount;
+ }
+ }
+
+ /* Wait until RXWNE/FRLVL flag is reset */
+ if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+ {
+ if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount -= (uint16_t)4UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ }
+
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Wait for Tx/Rx (and CRC) data to be sent/received */
+ if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return errorcode;
+}
+
+/**
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = NULL;
+ hspi->RxXferSize = (uint16_t) 0UL;
+ hspi->RxXferCount = (uint16_t) 0UL;
+ hspi->RxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ hspi->TxISR = SPI_TxISR_32BIT;
+ }
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ /* Enable EOT, TXP, FRE, MODF, UDR and TSERF interrupts */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = NULL;
+ hspi->TxXferSize = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+ hspi->TxISR = NULL;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ hspi->RxISR = SPI_RxISR_32BIT;
+ }
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->RxISR = SPI_RxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_RxISR_8BIT;
+ }
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ /* Enable EOT, RXP, OVR, FRE, MODF and TSERF interrupts */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size : amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ uint32_t tmp_mode;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ hspi->TxISR = SPI_TxISR_32BIT;
+ hspi->RxISR = SPI_RxISR_32BIT;
+ }
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->RxISR = SPI_RxISR_16BIT;
+ hspi->TxISR = SPI_TxISR_16BIT;
+ }
+ else
+ {
+ hspi->RxISR = SPI_RxISR_8BIT;
+ hspi->TxISR = SPI_TxISR_8BIT;
+ }
+
+ /* Set the number of data at current transfer */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ /* Enable EOT, RXP, TXP, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+/**
+ * @brief Transmit an additional amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ HAL_SPI_StateTypeDef tmp_state;
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if (hspi->State == HAL_SPI_STATE_BUSY_TX)
+ {
+ /* check if there is already a request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Insert the new number of data to be sent just after the current one */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
+
+ /* Set the transaction information */
+ hspi->Reload.Requested = 1UL;
+ hspi->Reload.pTxBuffPtr = (uint8_t *)pData;
+ hspi->Reload.TxXferSize = Size;
+
+ tmp_state = hspi->State;
+
+ /* Check if the current transmit is already completed */
+ if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
+ {
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
+ hspi->Reload.Requested = 0UL;
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+ }
+ else
+ {
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+/**
+ * @brief Receive an additional amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ HAL_SPI_StateTypeDef tmp_state;
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* check if there is already a request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Insert the new number of data that will be received just after the current one */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
+
+ /* Set the transaction information */
+ hspi->Reload.Requested = 1UL;
+ hspi->Reload.pRxBuffPtr = (uint8_t *)pData;
+ hspi->Reload.RxXferSize = Size;
+
+ tmp_state = hspi->State;
+
+ /* Check if the current reception is already completed */
+ if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
+ {
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
+ hspi->Reload.Requested = 0UL;
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+ }
+ else
+ {
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+/**
+ * @brief Transmit and receive an additional amount of data in blocking mode.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size : amount of data to be sent and received
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ HAL_SPI_StateTypeDef tmp_state;
+
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if (hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ /* check if there is already a request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Insert the new number of data that will be sent and received just after the current one */
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
+
+ /* Set the transaction information */
+ hspi->Reload.Requested = 1UL;
+ hspi->Reload.pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->Reload.TxXferSize = Size;
+ hspi->Reload.pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->Reload.RxXferSize = Size;
+
+ tmp_state = hspi->State;
+
+ /* Check if the current transmit is already completed */
+ if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
+ {
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
+ hspi->Reload.Requested = 0UL;
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+ }
+ else
+ {
+ errorcode = HAL_ERROR;
+ return errorcode;
+ }
+
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = NULL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = (uint16_t)0UL;
+ hspi->RxXferCount = (uint16_t)0UL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Packing mode management is enabled by the DMA settings */
+ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
+ ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
+ (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Adjust XferCount according to DMA alignment / Data size */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ }
+ else
+ {
+ /* Adjustment done */
+ }
+
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+
+ /* Clear TXDMAEN bit*/
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ hspi->State = HAL_SPI_STATE_READY;
+ return errorcode;
+ }
+
+ /* Set the number of data at current transfer */
+ if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+ }
+ else
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+ #endif
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+
+/**
+ * @brief Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pData: pointer to data buffer
+ * @param Size : amount of data to be sent
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+
+ /* Configure communication direction : 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Packing mode management is enabled by the DMA settings */
+ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
+ ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
+ (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Clear RXDMAEN bit */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+ /* Adjust XferCount according to DMA alignment / Data size */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ }
+ else
+ {
+ /* Adjustment done */
+ }
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ hspi->State = HAL_SPI_STATE_READY;
+ return errorcode;
+ }
+
+ /* Set the number of data at current transfer */
+ if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+ }
+ else
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+ }
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
+ * @param hspi : pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param pTxData: pointer to transmission data buffer
+ * @param pRxData: pointer to reception data buffer
+ * @param Size : amount of data to be sent
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
+{
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ uint32_t tmp_mode;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!(((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)) || (tmp_state == HAL_SPI_STATE_READY)))
+ {
+ errorcode = HAL_BUSY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ {
+ errorcode = HAL_ERROR;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+ /* Reset the Tx/Rx DMA bits */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Packing mode management is enabled by the DMA settings */
+ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
+ ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
+ (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Adjust XferCount according to DMA alignment / Data size */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ {
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL;
+ }
+ }
+ else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT)
+ {
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD)
+ {
+ hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL;
+ }
+ }
+ else
+ {
+ /* Adjustment done */
+ }
+
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ }
+ else
+ {
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ }
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ hspi->State = HAL_SPI_STATE_READY;
+ return errorcode;
+ }
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ hspi->State = HAL_SPI_STATE_READY;
+ return errorcode;
+ }
+
+ if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL);
+ }
+ else
+ {
+ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
+ }
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ /* Master transfer start */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+#endif
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * @note This procedure performs following operations :
+ * + Disable SPI Interrupts (depending of transfer direction)
+ * + Disable the DMA transfer in the peripheral register (if enabled)
+ * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * + Set handle State to READY.
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+
+ __IO uint32_t count;
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ /* Set hspi->state to aborting to avoid any interaction */
+ hspi->State = HAL_SPI_STATE_ABORT;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
+
+ /* If master communication on going, make sure current frame is done before closing the connection */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ }
+ #if defined(HAL_DMA_MODULE_ENABLED)
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
+ {
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
+ {
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ }
+ }
+ #endif
+
+ /* Proceed with abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * @note This procedure performs following operations :
+ * + Disable SPI Interrupts (depending of transfer direction)
+ * + Disable the DMA transfer in the peripheral register (if enabled)
+ * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * + Set handle State to READY
+ * + At abort completion, call user abort complete callback.
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ __IO uint32_t count;
+ uint32_t dma_tx_abort_done = 1UL, dma_rx_abort_done = 1UL;
+
+ /* Set hspi->state to aborting to avoid any interaction */
+ hspi->State = HAL_SPI_STATE_ABORT;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL);
+
+ /* If master communication on going, make sure current frame is done before closing the connection */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
+ do
+ {
+ count--;
+ if (count == 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ }
+ #if defined(HAL_DMA_MODULE_ENABLED)
+ /* Reset Callbacks */
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
+ before any call to DMA Abort functions */
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN) && (hspi->hdmatx != NULL))
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled */
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+
+ if ((HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) && (hspi->hdmarx != NULL))
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled */
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ }
+
+ /* Disable the SPI DMA Tx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) && (hspi->hdmatx != NULL))
+ {
+ dma_tx_abort_done = 0UL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
+ {
+ dma_tx_abort_done = 1UL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN) && (hspi->hdmarx != NULL))
+ {
+ dma_rx_abort_done = 0UL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
+ {
+ dma_rx_abort_done = 1UL;
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+ }
+ #endif
+
+ /* If no running DMA transfer, finish cleanup and call callbacks */
+ if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
+ {
+ /* Proceed with abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+
+ return errorcode;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Pause the DMA Transfer.
+ * This API is not supported, it is maintained for backward compatibility.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL_ERROR
+ */
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
+{
+ /* Set error code to not supported */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * This API is not supported, it is maintained for backward compatibility.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL_ERROR
+ */
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
+{
+ /* Set error code to not supported */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * This API is not supported, it is maintained for backward compatibility.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL_ERROR
+ */
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
+{
+ /* Set error code to not supported */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED);
+
+ return HAL_ERROR;
+}
+#endif
+
+/**
+ * @brief Handle SPI interrupt request.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval None
+ */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itsource = hspi->Instance->IER;
+ uint32_t itflag = hspi->Instance->SR;
+ uint32_t trigger = itsource & itflag;
+ uint32_t cfg1 = hspi->Instance->CFG1;
+ uint32_t handled = 0UL;
+
+ HAL_SPI_StateTypeDef State = hspi->State;
+
+
+ /* SPI in mode Transmitter and Receiver ------------------------------------*/
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
+ {
+ hspi->TxISR(hspi);
+ hspi->RxISR(hspi);
+ handled = 1UL;
+ }
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+ {
+ hspi->RxISR(hspi);
+ handled = 1UL;
+ }
+
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+ {
+ hspi->TxISR(hspi);
+ handled = 1UL;
+ }
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ /* SPI Reload -------------------------------------------------*/
+ if (HAL_IS_BIT_SET(trigger, SPI_FLAG_TSERF))
+ {
+ hspi->Reload.Requested = 0UL;
+ __HAL_SPI_CLEAR_TSERFFLAG(hspi);
+ }
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+ if (handled != 0UL)
+ {
+ return;
+ }
+
+ /* SPI End Of Transfer: DMA or IT based transfer */
+ if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT))
+ {
+ /* Clear EOT/TXTF/SUSP flag */
+ __HAL_SPI_CLEAR_EOTFLAG(hspi);
+ __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+ __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+ /* Disable EOT interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
+
+ /* DMA Normal Mode */
+ #if defined(HAL_DMA_MODULE_ENABLED)
+ if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || // IT based transfer is done
+ ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode
+ ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) // DMA is used in normal mode
+ #else
+ if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ #endif
+ {
+ /* For the IT based receive extra polling maybe required for last packet */
+ if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ {
+ /* Pooling remaining data */
+ while (hspi->RxXferCount != 0UL)
+ {
+ /* Receive data in 32 Bit mode */
+ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ }
+ /* Receive data in 16 Bit mode */
+ else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ }
+ /* Receive data in 8 Bit mode */
+ else
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ }
+
+ hspi->RxXferCount--;
+ }
+ }
+
+ /* Call SPI Standard close procedure */
+ SPI_CloseTransfer(hspi);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ return;
+ }
+ }
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ /* Call appropriate user callback */
+ if (State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ hspi->TxRxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->RxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_TX)
+ {
+ hspi->TxCpltCallback(hspi);
+ }
+#else
+ /* Call appropriate user callback */
+ if (State == HAL_SPI_STATE_BUSY_TX_RX)
+ {
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_RX)
+ {
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else if (State == HAL_SPI_STATE_BUSY_TX)
+ {
+ HAL_SPI_TxCpltCallback(hspi);
+ }
+ else
+ {
+ /* end of the appropriate call */
+ }
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+
+ return;
+ }
+
+ if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
+ {
+ /* Abort on going, clear SUSP flag to avoid infinite looping */
+ __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+ return;
+ }
+
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL)
+ {
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if ((trigger & SPI_FLAG_OVR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((trigger & SPI_FLAG_MODF) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((trigger & SPI_FLAG_FRE) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ /* SPI Underrun error interrupt occurred ------------------------------------*/
+ if ((trigger & SPI_FLAG_UDR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
+ __HAL_SPI_CLEAR_UDRFLAG(hspi);
+ }
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR);
+
+ /* Disable the SPI DMA requests if enabled */
+ if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ {
+ /* Disable the SPI DMA requests */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ #if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the SPI DMA Rx channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+
+ /* Abort the SPI DMA Tx channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
+ }
+ #endif
+
+ }
+ else
+ {
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ }
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Half Transfer callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
+}
+
+/**
+ * @brief SPI error callback.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SPI.
+ (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
+ (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the SPI handle state.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI state
+ */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI handle state */
+ return hspi->State;
+}
+
+/**
+ * @brief Return the SPI error code.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
+ */
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+{
+ /* Return SPI ErrorCode */
+ return hspi->ErrorCode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Private_Functions
+ * @brief Private functions
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hspi->State != HAL_SPI_STATE_ABORT)
+ {
+ if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxCpltCallback(hspi);
+#else
+ HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Enable EOT interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+ }
+ }
+}
+
+/**
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hspi->State != HAL_SPI_STATE_ABORT)
+ {
+ if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR)
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->RxCpltCallback(hspi);
+#else
+ HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Enable EOT interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+ }
+ }
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ if (hspi->State != HAL_SPI_STATE_ABORT)
+ {
+ if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
+ {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxRxCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Enable EOT interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT);
+ }
+ }
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->RxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->TxRxHalfCpltCallback(hspi);
+#else
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* if DMA error is FIFO error ignore it */
+ if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
+ {
+ /* Call SPI standard close procedure */
+ SPI_CloseTransfer(hspi);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ hspi->RxXferCount = (uint16_t) 0UL;
+ hspi->TxXferCount = (uint16_t) 0UL;
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->ErrorCallback(hspi);
+#else
+ HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL)
+ {
+ if (hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* Call the Abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL)
+ {
+ if (hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* Call the Abort procedure */
+ SPI_AbortTransfer(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+ hspi->AbortCpltCallback(hspi);
+#else
+ HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+}
+
+#endif
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 8 Bit mode */
+ *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->RxXferCount == 0UL)
+ {
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ /* Check if there is any request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ hspi->RxXferSize = hspi->Reload.RxXferSize;
+ hspi->RxXferCount = hspi->Reload.RxXferSize;
+ hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
+ }
+ else
+ {
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+ }
+#else
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+ }
+}
+
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->RxXferCount == 0UL)
+ {
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ /* Check if there is any request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ hspi->RxXferSize = hspi->Reload.RxXferSize;
+ hspi->RxXferCount = hspi->Reload.RxXferSize;
+ hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
+ }
+ else
+ {
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+ }
+#else
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+ }
+}
+
+
+/**
+ * @brief Manage the 32-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 32 Bit mode */
+ *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->RxXferCount == 0UL)
+ {
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ /* Check if there is any request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ hspi->RxXferSize = hspi->Reload.RxXferSize;
+ hspi->RxXferCount = hspi->Reload.RxXferSize;
+ hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
+ }
+ else
+ {
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+ }
+#else
+ /* Disable RXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+ }
+}
+
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 8 Bit mode */
+ *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint8_t);
+ hspi->TxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->TxXferCount == 0UL)
+ {
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ /* Check if there is any request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ hspi->TxXferSize = hspi->Reload.TxXferSize;
+ hspi->TxXferCount = hspi->Reload.TxXferSize;
+ hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
+ }
+ else
+ {
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+ }
+#else
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->TxXferCount == 0UL)
+ {
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ /* Check if there is any request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ hspi->TxXferSize = hspi->Reload.TxXferSize;
+ hspi->TxXferCount = hspi->Reload.TxXferSize;
+ hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
+ }
+ else
+ {
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+ }
+#else
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+ }
+}
+
+/**
+ * @brief Handle the data 32-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 32 Bit mode */
+ *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint32_t);
+ hspi->TxXferCount--;
+
+ /* Disable IT if no more data excepted */
+ if (hspi->TxXferCount == 0UL)
+ {
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ /* Check if there is any request to reload */
+ if (hspi->Reload.Requested == 1UL)
+ {
+ hspi->TxXferSize = hspi->Reload.TxXferSize;
+ hspi->TxXferCount = hspi->Reload.TxXferSize;
+ hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
+ }
+ else
+ {
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+ }
+#else
+ /* Disable TXP interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
+#endif /* USE_HSPI_RELOAD_TRANSFER */
+ }
+}
+
+/**
+ * @brief Abort Transfer and clear flags.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
+{
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable ITs */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Clear the Status flags in the SR register */
+ __HAL_SPI_CLEAR_EOTFLAG(hspi);
+ __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_UDRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+#if (USE_SPI_CRC != 0U)
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+#endif /* USE_SPI_CRC */
+
+ hspi->TxXferCount = (uint16_t)0UL;
+ hspi->RxXferCount = (uint16_t)0UL;
+}
+
+
+/**
+ * @brief Close Transfer and clear flags.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval HAL_ERROR: if any error detected
+* HAL_OK: if nothing detected
+ */
+static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
+{
+ uint32_t itflag = hspi->Instance->SR;
+
+ __HAL_SPI_CLEAR_EOTFLAG(hspi);
+ __HAL_SPI_CLEAR_TXTFFLAG(hspi);
+
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable ITs */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+
+ /* Report UnderRun error for non RX Only communication */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ if ((itflag & SPI_FLAG_UDR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR);
+ __HAL_SPI_CLEAR_UDRFLAG(hspi);
+ }
+ }
+
+ /* Report OverRun error for non TX Only communication */
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
+ {
+ if ((itflag & SPI_FLAG_OVR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+#if (USE_SPI_CRC != 0UL)
+ /* Check if CRC error occurred */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ if ((itflag & SPI_FLAG_CRCERR) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+#endif /* USE_SPI_CRC */
+ }
+
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((itflag & SPI_FLAG_MODF) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
+ }
+
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((itflag & SPI_FLAG_FRE) != 0UL)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+ }
+
+ hspi->TxXferCount = (uint16_t)0UL;
+ hspi->RxXferCount = (uint16_t)0UL;
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param Status: flag state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Compute configured packet size from fifo perspective.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval Packet size occupied in the fifo
+ */
+static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
+{
+ uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
+ uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL;
+
+ /* Convert data size to Byte */
+ data_size = (data_size + 7UL) / 8UL;
+
+ return data_size * fifo_threashold;
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c
new file mode 100644
index 0000000..bea245b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi_ex.c
@@ -0,0 +1,229 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_spi_ex.c
+ * @author MCD Application Team
+ * @brief Extended SPI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * SPI peripheral extended functionalities :
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup SPIEx SPIEx
+ * @brief SPI Extended HAL module driver
+ * @{
+ */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+ * @{
+ */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of extended functions to manage the SPI
+ data transfers.
+
+ (#) SPIEx function:
+ (++) HAL_SPIEx_FlushRxFifo()
+ (++) HAL_SPIEx_FlushRxFifo()
+ (++) HAL_SPIEx_EnableLockConfiguration()
+ (++) HAL_SPIEx_ConfigureUnderrun()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Flush the RX fifo.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+ uint8_t count = 0;
+ uint32_t itflag = hspi->Instance->SR;
+ __IO uint32_t tmpreg;
+
+ while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL))
+ {
+ count += (uint8_t)4UL;
+ tmpreg = hspi->Instance->RXDR;
+ UNUSED(tmpreg); /* To avoid GCC warning */
+
+ if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
+ {
+ if (count > SPI_HIGHEND_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ else
+ {
+ if (count > SPI_LOWEND_FIFO_SIZE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Enable the Lock for the AF configuration of associated IOs
+ * and write protect the Content of Configuration register 2
+ * when SPI is enabled
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Check if the SPI is disabled to edit IOLOCK bit */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
+ }
+ else
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @brief Configure the UNDERRUN condition and behavior of slave transmitter.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param UnderrunDetection : Detection of underrun condition at slave transmitter
+ * This parameter can be a value of @ref SPI_Underrun_Detection.
+ * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition
+ * This parameter can be a value of @ref SPI_Underrun_Behaviour.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
+{
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Check State and Insure that Underrun configuration is managed only by Salve */
+ if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
+ {
+ errorcode = HAL_BUSY;
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
+ assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
+
+ /* Check if the SPI is disabled to edit CFG1 register */
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Configure Underrun fields */
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
+ }
+ else
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Configure Underrun fields */
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
+ MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
+
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
new file mode 100644
index 0000000..b4f3ac6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
@@ -0,0 +1,6917 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_tim.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer (TIM) peripheral:
+ * + TIM Time Base Initialization
+ * + TIM Time Base Start
+ * + TIM Time Base Start Interruption
+ * + TIM Time Base Start DMA
+ * + TIM Output Compare/PWM Initialization
+ * + TIM Output Compare/PWM Channel Configuration
+ * + TIM Output Compare/PWM Start
+ * + TIM Output Compare/PWM Start Interruption
+ * + TIM Output Compare/PWM Start DMA
+ * + TIM Input Capture Initialization
+ * + TIM Input Capture Channel Configuration
+ * + TIM Input Capture Start
+ * + TIM Input Capture Start Interruption
+ * + TIM Input Capture Start DMA
+ * + TIM One Pulse Initialization
+ * + TIM One Pulse Channel Configuration
+ * + TIM One Pulse Start
+ * + TIM Encoder Interface Initialization
+ * + TIM Encoder Interface Start
+ * + TIM Encoder Interface Start Interruption
+ * + TIM Encoder Interface Start DMA
+ * + Commutation Event configuration with Interruption and DMA
+ * + TIM OCRef clear configuration
+ * + TIM External Clock configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Generic features #####
+ ==============================================================================
+ [..] The Timer features include:
+ (#) 16-bit up, down, up/down auto-reload counter.
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ counter clock frequency either by any factor between 1 and 65536.
+ (#) Up to 4 independent channels for:
+ (++) Input Capture
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to interconnect
+ several timers together.
+ (#) Supports incremental encoder for positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
+ (++) Time Base : HAL_TIM_Base_MspInit()
+ (++) Input Capture : HAL_TIM_IC_MspInit()
+ (++) Output Compare : HAL_TIM_OC_MspInit()
+ (++) PWM generation : HAL_TIM_PWM_MspInit()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
+ (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ Initialization function of this driver:
+ (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ Output Compare signal.
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ PWM signal.
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ external signal.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
+ (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
+
+ (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
+ (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
+ (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
+ (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
+ (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
+ (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
+ (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
+
+ (#) The DMA Burst is managed with the two following functions:
+ HAL_TIM_DMABurst_WriteStart()
+ HAL_TIM_DMABurst_ReadStart()
+
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+ @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ [..]
+ These functions allow to register/unregister following callbacks:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
+ (+) BreakCallback : TIM Break Callback.
+ (+) Break2Callback : TIM Break2 Callback.
+
+ [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+ examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+ [..]
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init / DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+ [..]
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ Exception done MspInit / MspDeInit that can be registered / unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+ [..]
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIM TIM
+ * @brief TIM HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup TIM_Private_Functions
+ * @{
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+#ifdef HAL_DMA_MODULE_ENABLED
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Time Base functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM base.
+ (+) De-initialize the TIM base.
+ (+) Start the Time Base.
+ (+) Stop the Time Base.
+ (+) Start the Time Base and enable interrupt.
+ (+) Stop the Time Base and disable interrupt.
+ (+) Start the Time Base and enable DMA transfer.
+ (+) Stop the Time Base and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Time base Unit according to the specified
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Base_MspInitCallback == NULL)
+ {
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the Time Base configuration */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Base peripheral
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Base_MspDeInitCallback == NULL)
+ {
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Base_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Base MSP.
+ * @param htim TIM Base handle
+ * @retval None
+ */
+__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Base_MspDeInit could be implemented in the user file
+ */
+}
+
+
+/**
+ * @brief Starts the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Change the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in interrupt mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ /* Disable the TIM Update interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Update DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Base generation in DMA mode.
+ * @param htim TIM Base handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
+
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Output Compare.
+ (+) De-initialize the TIM Output Compare.
+ (+) Start the TIM Output Compare.
+ (+) Stop the TIM Output Compare.
+ (+) Start the TIM Output Compare and enable interrupt.
+ (+) Stop the TIM Output Compare and disable interrupt.
+ (+) Start the TIM Output Compare and enable DMA transfer.
+ (+) Stop the TIM Output Compare and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Output Compare according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OC_MspInitCallback == NULL)
+ {
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the Output Compare */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Output Compare handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OC_MspDeInitCallback == NULL)
+ {
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Output Compare MSP.
+ * @param htim TIM Output Compare handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Output compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM PWM.
+ (+) De-initialize the TIM PWM.
+ (+) Start the TIM PWM.
+ (+) Stop the TIM PWM.
+ (+) Start the TIM PWM and enable interrupt.
+ (+) Stop the TIM PWM and disable interrupt.
+ (+) Start the TIM PWM and enable DMA transfer.
+ (+) Stop the TIM PWM and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM PWM Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->PWM_MspInitCallback == NULL)
+ {
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->PWM_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the PWM */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM PWM handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->PWM_MspDeInitCallback == NULL)
+ {
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->PWM_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM PWM MSP.
+ * @param htim TIM PWM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the PWM signal generation.
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Capture/Compare 3 request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode.
+ * @param htim TIM PWM handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Input Capture functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Input Capture.
+ (+) De-initialize the TIM Input Capture.
+ (+) Start the TIM Input Capture.
+ (+) Stop the TIM Input Capture.
+ (+) Start the TIM Input Capture and enable interrupt.
+ (+) Stop the TIM Input Capture and disable interrupt.
+ (+) Start the TIM Input Capture and enable DMA transfer.
+ (+) Stop the TIM Input Capture and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Input Capture Time base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->IC_MspInitCallback == NULL)
+ {
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->IC_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Init the base time for the input capture */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM Input Capture handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->IC_MspDeInitCallback == NULL)
+ {
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->IC_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture MSP.
+ * @param htim TIM Input Capture handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Input Capture MSP.
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Enable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in interrupt mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((pData == NULL) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Input Capture measurement in DMA mode.
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Disable the TIM Capture/Compare 4 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM One Pulse.
+ (+) De-initialize the TIM One Pulse.
+ (+) Start the TIM One Pulse.
+ (+) Stop the TIM One Pulse.
+ (+) Start the TIM One Pulse and enable interrupt.
+ (+) Stop the TIM One Pulse and disable interrupt.
+ (+) Start the TIM One Pulse and enable DMA transfer.
+ (+) Stop the TIM One Pulse and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM One Pulse Time Base according to the specified
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @param htim TIM One Pulse handle
+ * @param OnePulseMode Select the One pulse mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
+{
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OnePulse_MspInitCallback == NULL)
+ {
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OnePulse_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the One Pulse Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Reset the OPM Bit */
+ htim->Instance->CR1 &= ~TIM_CR1_OPM;
+
+ /* Configure the OPM Mode */
+ htim->Instance->CR1 |= OnePulseMode;
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM One Pulse
+ * @param htim TIM One Pulse handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OnePulse_MspDeInitCallback == NULL)
+ {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM One Pulse MSP.
+ * @param htim TIM One Pulse handle
+ * @retval None
+ */
+__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be disable
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Enable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+
+ No need to enable the counter, it's enabled automatically by hardware
+ (the counter starts in response to a stimulus and generate a pulse */
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Enable the main output */
+ __HAL_TIM_MOE_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the Capture compare and the Input Capture channels
+ (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
+ if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ {
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Encoder functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure the TIM Encoder.
+ (+) De-initialize the TIM Encoder.
+ (+) Start the TIM Encoder.
+ (+) Stop the TIM Encoder.
+ (+) Start the TIM Encoder and enable interrupt.
+ (+) Stop the TIM Encoder and disable interrupt.
+ (+) Start the TIM Encoder and enable DMA transfer.
+ (+) Stop the TIM Encoder and disable DMA transfer.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Encoder Interface configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+{
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Encoder_MspInitCallback == NULL)
+ {
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = htim->Instance->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr |= sConfig->EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
+ tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
+ tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ htim->Instance->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ htim->Instance->CCER = tmpccer;
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Encoder_MspDeInitCallback == NULL)
+ {
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Encoder_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Encoder Interface MSP.
+ * @param htim TIM Encoder Interface handle
+ * @retval None
+ */
+__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
+ }
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Enable the encoder interface channels */
+ /* Enable the capture compare Interrupts 1 and/or 2 */
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ default :
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+ }
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in interrupt mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts 1 and 2 */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @param pData1 The destination Buffer address for IC1.
+ * @param pData2 The destination Buffer address for IC2.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
+ }
+
+ case TIM_CHANNEL_ALL:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the Peripheral */
+ __HAL_TIM_ENABLE(htim);
+
+ /* Enable the Capture compare channel */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ /* Enable the TIM Input Capture DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ default:
+ break;
+ }
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Encoder Interface in DMA mode.
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1 and 2
+ (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
+ if (Channel == TIM_CHANNEL_1)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+ else
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare DMA Request 1 and 2 */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ }
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief TIM IRQ handler management
+ *
+@verbatim
+ ==============================================================================
+ ##### IRQ handler management #####
+ ==============================================================================
+ [..]
+ This section provides Timer IRQ handler function.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief This function handles TIM interrupts requests.
+ * @param htim TIM handle
+ * @retval None
+ */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ /* Capture compare 1 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+ {
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ }
+ /* Capture compare 2 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ /* Input capture event */
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 3 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* Capture compare 4 event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ /* Input capture event */
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ /* Output compare event */
+ else
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_OC_DelayElapsedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ }
+ }
+ /* TIM Update event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
+ HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Break2 input event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->Break2Callback(htim);
+#else
+ HAL_TIMEx_Break2Callback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM Trigger detection event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+ /* TIM commutation event */
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ {
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+ {
+ __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief TIM Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
+ (+) Configure External Clock source.
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master and the Slave synchronization.
+ (+) Configure the DMA Burst Mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the TIM Output Compare Channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 1 in Output Compare */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 2 in Output Compare */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 3 in Output Compare */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 5 in Output Compare */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the TIM Channel 6 in Output Compare */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Input Capture Channels according to the specified
+ * parameters in the TIM_IC_InitTypeDef.
+ * @param htim TIM IC handle
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (Channel == TIM_CHANNEL_1)
+ {
+ /* TI1 Configuration */
+ TIM_TI1_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->ICPrescaler;
+ }
+ else if (Channel == TIM_CHANNEL_2)
+ {
+ /* TI2 Configuration */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Set the IC2PSC value */
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
+ }
+ else if (Channel == TIM_CHANNEL_3)
+ {
+ /* TI3 Configuration */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ TIM_TI3_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC3PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
+
+ /* Set the IC3PSC value */
+ htim->Instance->CCMR2 |= sConfig->ICPrescaler;
+ }
+ else
+ {
+ /* TI4 Configuration */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ TIM_TI4_SetConfig(htim->Instance,
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
+
+ /* Reset the IC4PSC Bits */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
+
+ /* Set the IC4PSC value */
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM PWM channels according to the specified
+ * parameters in the TIM_OC_InitTypeDef.
+ * @param htim TIM PWM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be configured
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNELS(Channel));
+ assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
+ assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
+ assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 1 in PWM mode */
+ TIM_OC1_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel1 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 2 in PWM mode */
+ TIM_OC2_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel2 */
+ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 3 in PWM mode */
+ TIM_OC3_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel3 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 4 in PWM mode */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel4 */
+ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ case TIM_CHANNEL_5:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 5 in PWM mode */
+ TIM_OC5_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel5*/
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ break;
+ }
+
+ case TIM_CHANNEL_6:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
+
+ /* Configure the Channel 6 in PWM mode */
+ TIM_OC6_SetConfig(htim->Instance, sConfig);
+
+ /* Set the Preload enable bit for channel6 */
+ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM One Pulse Channels according to the specified
+ * parameters in the TIM_OnePulse_InitTypeDef.
+ * @param htim TIM One Pulse handle
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM output channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @param InputChannel TIM input Channel to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel)
+{
+ TIM_OC_InitTypeDef temp1;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
+ assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
+
+ if (OutputChannel != InputChannel)
+ {
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Extract the Output compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
+
+ switch (OutputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+ default:
+ break;
+ }
+
+ switch (InputChannel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
+
+ /* Reset the IC2PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+ /* Select the Trigger source */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+ /* Select the Slave Mode */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_TISEL
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM DMA Burst mode
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ break;
+ }
+
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+#endif
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_AF1
+ * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_TISEL
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+ assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ /* Set the DMA Period elapsed callbacks */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ /* Set the DMA capture/compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ /* Set the DMA commutation callbacks */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ /* Set the DMA trigger callbacks */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ /* configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA burst reading
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
+
+ /* Abort the DMA transfer (at least disable the DMA channel) */
+ switch (BurstRequestSrc)
+ {
+ case TIM_DMA_UPDATE:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
+ }
+ case TIM_DMA_CC1:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+ case TIM_DMA_CC2:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+ case TIM_DMA_CC3:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+ case TIM_DMA_CC4:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
+ }
+ case TIM_DMA_COM:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
+ }
+ case TIM_DMA_TRIGGER:
+ {
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
+ }
+ default:
+ break;
+ }
+
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
+
+ /* Return function status */
+ return status;
+}
+#endif
+
+/**
+ * @brief Generate a software event
+ * @param htim TIM handle
+ * @param EventSource specifies the event source.
+ * This parameter can be one of the following values:
+ * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
+ * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
+ * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
+ * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
+ * @note Basic timers can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+ * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
+ * only for timer instances supporting break input(s).
+ * @retval HAL status
+ */
+
+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_EVENT_SOURCE(EventSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Set the event sources */
+ htim->Instance->EGR = EventSource;
+
+ /* Change the TIM state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the OCRef clear feature
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
+ * contains the OCREF clear feature and parameters for the TIM peripheral.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5
+ * @arg TIM_CHANNEL_6: TIM Channel 6
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ switch (sClearInputConfig->ClearInputSource)
+ {
+ case TIM_CLEARINPUTSOURCE_NONE:
+ {
+ /* Clear the OCREF clear selection bit and the the ETR Bits */
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+ break;
+ }
+
+ case TIM_CLEARINPUTSOURCE_ETR:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ TIM_ETR_SetConfig(htim->Instance,
+ sClearInputConfig->ClearInputPrescaler,
+ sClearInputConfig->ClearInputPolarity,
+ sClearInputConfig->ClearInputFilter);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_3:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_4:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_5:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 5 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 5 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+ }
+ break;
+ }
+ case TIM_CHANNEL_6:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+ {
+ /* Enable the OCREF clear feature for Channel 6 */
+ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 6 */
+ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the clock source to be used
+ * @param htim TIM handle
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+ * contains the clock source information for the TIM peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ uint32_t tmpsmcr;
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+ /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ htim->Instance->SMCR = tmpsmcr;
+
+ switch (sClockSourceConfig->ClockSource)
+ {
+ case TIM_CLOCKSOURCE_INTERNAL:
+ {
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE1:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+
+ /* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr = htim->Instance->SMCR;
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ETRMODE2:
+ {
+ /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
+
+ /* Check ETR input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ /* Configure the ETR Clock source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sClockSourceConfig->ClockPrescaler,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ /* Enable the External clock mode2 */
+ htim->Instance->SMCR |= TIM_SMCR_ECE;
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI2:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI2 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_TI1ED:
+ {
+ /* Check whether or not the timer instance supports external clock mode 1 */
+ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
+
+ /* Check TI1 input conditioning related parameters */
+ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+ assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sClockSourceConfig->ClockPolarity,
+ sClockSourceConfig->ClockFilter);
+ TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ break;
+ }
+
+ case TIM_CLOCKSOURCE_ITR0:
+ case TIM_CLOCKSOURCE_ITR1:
+ case TIM_CLOCKSOURCE_ITR2:
+ case TIM_CLOCKSOURCE_ITR3:
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
+
+ default:
+ break;
+ }
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Selects the signal connected to the TI1 input: direct from CH1_input
+ * or a XOR combination between CH1_input, CH2_input & CH3_input
+ * @param htim TIM handle.
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the
+ * output of a XOR gate.
+ * This parameter can be one of the following values:
+ * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
+ * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
+ * pins are connected to the TI1 input (XOR combination)
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
+{
+ uint32_t tmpcr2;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Reset the TI1 selection */
+ tmpcr2 &= ~TIM_CR2_TI1S;
+
+ /* Set the TI1 selection */
+ tmpcr2 |= TI1_Selection;
+
+ /* Write to TIMxCR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Disable Trigger Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIM in Slave mode in interrupt mode
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
+ * contains the selected trigger (internal trigger input, filtered
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
+ assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
+ /* Enable Trigger Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
+
+ /* Disable Trigger DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read the captured value from Capture Compare unit
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval Captured value
+ */
+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpreg = 0U;
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
+ /* Return the capture 1 value */
+ tmpreg = htim->Instance->CCR1;
+
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+ /* Return the capture 2 value */
+ tmpreg = htim->Instance->CCR2;
+
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
+ /* Return the capture 3 value */
+ tmpreg = htim->Instance->CCR3;
+
+ break;
+ }
+
+ case TIM_CHANNEL_4:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
+ /* Return the capture 4 value */
+ tmpreg = htim->Instance->CCR4;
+
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### TIM Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides TIM callback functions:
+ (+) TIM Period elapsed callback
+ (+) TIM Output Compare callback
+ (+) TIM Input capture callback
+ (+) TIM Trigger callback
+ (+) TIM Error callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Period elapsed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Period elapsed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output Compare callback in non-blocking mode
+ * @param htim TIM OC handle
+ * @retval None
+ */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_ErrorCallback could be implemented in the user file
+ */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ htim->Break2Callback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a TIM callback
+ * TIM callback is redirected to the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ break;
+
+ case HAL_TIM_BREAK2_CB_ID :
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief TIM Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Base handle state.
+ * @param htim TIM Base handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM OC handle state.
+ * @param htim TIM Output Compare handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM PWM handle state.
+ * @param htim TIM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Input Capture handle state.
+ * @param htim TIM IC handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM One Pulse Mode handle state.
+ * @param htim TIM OPM handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM Encoder Interface handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief TIM DMA error callback
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
+ HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Delay Pulse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Delay Pulse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureHalfCpltCallback(htim);
+#else
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Period Elapse complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Period Elapse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
+ HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerHalfCpltCallback(htim);
+#else
+ HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+#endif
+
+/**
+ * @brief Time Base configuration
+ * @param TIMx TIM peripheral
+ * @param Structure TIM Base configuration structure
+ * @retval None
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = Structure->Prescaler;
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = Structure->RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+/**
+ * @brief Timer Output Compare 1 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC1M;
+ tmpccmrx &= ~TIM_CCMR1_CC1S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC1P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= OC_Config->OCPolarity;
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC1NP;
+ /* Set the Output N Polarity */
+ tmpccer |= OC_Config->OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC1NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS1;
+ tmpcr2 &= ~TIM_CR2_OIS1N;
+ /* Set the Output Idle state */
+ tmpcr2 |= OC_Config->OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= OC_Config->OCNIdleState;
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR1_OC2M;
+ tmpccmrx &= ~TIM_CCMR1_CC2S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC2P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 4U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC2NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC2NE;
+
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS2;
+ tmpcr2 &= ~TIM_CR2_OIS2N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 3: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC3M;
+ tmpccmrx &= ~TIM_CCMR2_CC3S;
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC3P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 8U);
+
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ {
+ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= ~TIM_CCER_CC3NP;
+ /* Set the Output N Polarity */
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
+ /* Reset the Output N State */
+ tmpccer &= ~TIM_CCER_CC3NE;
+ }
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS3;
+ tmpcr2 &= ~TIM_CR2_OIS3N;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= ~TIM_CCMR2_OC4M;
+ tmpccmrx &= ~TIM_CCMR2_CC4S;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC4P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Check parameters */
+ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS4;
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 5 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC5E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= OC_Config->OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= ~TIM_CCER_CC5P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS5;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR5 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Timer Output Compare 6 configuration
+ * @param TIMx to select the TIM peripheral
+ * @param OC_Config The ouput configuration structure
+ * @retval None
+ */
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
+ TIM_OC_InitTypeDef *OC_Config)
+{
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
+
+ /* Disable the output: Reset the CCxE Bit */
+ TIMx->CCER &= ~TIM_CCER_CC6E;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR3;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (OC_Config->OCMode << 8U);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint32_t)~TIM_CCER_CC6P;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (OC_Config->OCPolarity << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= ~TIM_CR2_OIS6;
+ /* Set the Output Idle state */
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR3 */
+ TIMx->CCMR3 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR6 = OC_Config->Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Slave Timer configuration function
+ * @param htim TIM handle
+ * @param sSlaveConfig Slave timer configuration
+ * @retval None
+ */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* Reset the Trigger Selection Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source */
+ tmpsmcr |= sSlaveConfig->InputTrigger;
+
+ /* Reset the slave mode Bits */
+ tmpsmcr &= ~TIM_SMCR_SMS;
+ /* Set the slave mode */
+ tmpsmcr |= sSlaveConfig->SlaveMode;
+
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Configure the trigger prescaler, filter, and polarity */
+ switch (sSlaveConfig->InputTrigger)
+ {
+ case TIM_TS_ETRF:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ /* Configure the ETR Trigger source */
+ TIM_ETR_SetConfig(htim->Instance,
+ sSlaveConfig->TriggerPrescaler,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI1F_ED:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = htim->Instance->CCER;
+ htim->Instance->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = htim->Instance->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ htim->Instance->CCMR1 = tmpccmr1;
+ htim->Instance->CCER = tmpccer;
+ break;
+ }
+
+ case TIM_TS_TI1FP1:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI1 Filter and Polarity */
+ TIM_TI1_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_TI2FP2:
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
+ assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+
+ /* Configure TI2 Filter and Polarity */
+ TIM_TI2_ConfigInputStage(htim->Instance,
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
+ }
+
+ case TIM_TS_ITR0:
+ case TIM_TS_ITR1:
+ case TIM_TS_ITR2:
+ case TIM_TS_ITR3:
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
+
+ default:
+ break;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ {
+ tmpccmr1 &= ~TIM_CCMR1_CC1S;
+ tmpccmr1 |= TIM_ICSelection;
+ }
+ else
+ {
+ tmpccmr1 |= TIM_CCMR1_CC1S_0;
+ }
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI1.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ tmpccmr1 |= (TIM_ICFilter << 4U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ tmpccer |= TIM_ICPolarity;
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr1 &= ~TIM_CCMR1_CC2S;
+ tmpccmr1 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the Polarity and Filter for TI2.
+ * @param TIMx to select the TIM peripheral.
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC2E;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+
+ /* Set the filter */
+ tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ tmpccmr1 |= (TIM_ICFilter << 12U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (TIM_ICPolarity << 4U);
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ */
+static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC3E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC3S;
+ tmpccmr2 |= TIM_ICSelection;
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC3F;
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
+
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ICPolarity The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPOLARITY_RISING
+ * @arg TIM_ICPOLARITY_FALLING
+ * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @param TIM_ICSelection specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * protected against un-initialized filter and polarity values.
+ * @retval None
+ */
+static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
+ uint32_t TIM_ICFilter)
+{
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= ~TIM_CCER_CC4E;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+
+ /* Select the Input */
+ tmpccmr2 &= ~TIM_CCMR2_CC4S;
+ tmpccmr2 |= (TIM_ICSelection << 8U);
+
+ /* Set the filter */
+ tmpccmr2 &= ~TIM_CCMR2_IC4F;
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx to select the TIM peripheral
+ * @param InputTriggerSource The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ uint32_t tmpsmcr;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx to select the TIM peripheral
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
+ * @param ExtTRGFilter External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+ uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ uint32_t tmpsmcr;
+
+ tmpsmcr = TIMx->SMCR;
+
+ /* Reset the ETR Bits */
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
+ * @retval None
+ */
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_TIM_CHANNELS(Channel));
+
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+ /* Reset the TIM callback to the legacy weak callbacks */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
+ htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
new file mode 100644
index 0000000..357c0ed
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
@@ -0,0 +1,2381 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_tim_ex.c
+ * @author MCD Application Team
+ * @brief TIM HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Timer Extended peripheral:
+ * + Time Hall Sensor Interface Initialization
+ * + Time Hall Sensor Interface Start
+ * + Time Complementary signal break and dead time configuration
+ * + Time Master and Slave synchronization configuration
+ * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
+ * + Timer remapping capabilities configuration
+ @verbatim
+ ==============================================================================
+ ##### TIMER Extended features #####
+ ==============================================================================
+ [..]
+ The Timer Extended features include:
+ (#) Complementary outputs with programmable dead-time for :
+ (++) Output Compare
+ (++) PWM generation (Edge and Center-aligned Mode)
+ (++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to
+ interconnect several timers together.
+ (#) Break input to put the timer output signals in reset state or in a known state.
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ positioning purposes
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
+
+ (#) Initialize the TIM low level resources :
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
+ (##) TIM pins configuration
+ (+++) Enable the clock for the TIM GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
+
+ (#) The external Clock can be configured, if needed (the default clock is the
+ internal clock from the APBx), using the following function:
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ any start function.
+
+ (#) Configure the TIM in the desired functioning mode using one of the
+ initialization function of this driver:
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
+
+ (#) Activate the TIM peripheral using one of the start functions:
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
+ (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+ (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup TIMEx TIMEx
+ * @brief TIM Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+ * @{
+ */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Hall Sensor functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Initialize and configure TIM HAL Sensor.
+ (+) De-initialize TIM HAL Sensor.
+ (+) Start the Hall Sensor Interface.
+ (+) Stop the Hall Sensor Interface.
+ (+) Start the Hall Sensor Interface and enable interrupts.
+ (+) Stop the Hall Sensor Interface and disable interrupts.
+ (+) Start the Hall Sensor Interface and enable DMA transfers.
+ (+) Stop the Hall Sensor Interface and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param sConfig TIM Hall Sensor configuration structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+{
+ TIM_OC_InitTypeDef OC_Config;
+
+ /* Check the TIM handle allocation */
+ if (htim == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
+ assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+
+ if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->HallSensor_MspInitCallback == NULL)
+ {
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->HallSensor_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
+ /* Set the TIM state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Configure the Time base in the Encoder Mode */
+ TIM_Base_SetConfig(htim->Instance, &htim->Init);
+
+ /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
+ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
+
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Set the IC1PSC value */
+ htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
+
+ /* Enable the Hall sensor interface (XOR function of the three inputs) */
+ htim->Instance->CR2 |= TIM_CR2_TI1S;
+
+ /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= TIM_TS_TI1F_ED;
+
+ /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
+ htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
+
+ /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
+ OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
+ OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
+ OC_Config.OCMode = TIM_OCMODE_PWM2;
+ OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
+ OC_Config.Pulse = sConfig->Commutation_Delay;
+
+ TIM_OC2_SetConfig(htim->Instance, &OC_Config);
+
+ /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
+ register to 101 */
+ htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+
+ /* Initialize the TIM state*/
+ htim->State = HAL_TIM_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Disable the TIM Peripheral Clock */
+ __HAL_TIM_DISABLE(htim);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->HallSensor_MspDeInitCallback == NULL)
+ {
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->HallSensor_MspDeInitCallback(htim);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ /* Change TIM state */
+ htim->State = HAL_TIM_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes TIM Hall Sensor MSP.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall sensor Interface.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channels 1, 2 and 3
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Enable the capture compare Interrupts 1 event */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+ /* Disable the capture compare Interrupts event */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if (((uint32_t)pData == 0U) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ /* Enable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
+ /* Set the DMA Input Capture 1 Callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel for Capture 1*/
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the capture compare 1 Interrupt */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Hall Sensor Interface in DMA mode.
+ * @param htim TIM Hall Sensor Interface handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ /* Disable the Input Capture channel 1
+ (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+
+
+ /* Disable the capture compare Interrupts 1 event */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary Output Compare functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary Output Compare/PWM.
+ (+) Stop the Complementary Output Compare/PWM.
+ (+) Start the Complementary Output Compare/PWM and enable interrupts.
+ (+) Stop the Complementary Output Compare/PWM and disable interrupts.
+ (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
+ (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation on the complementary
+ * output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Output Compare interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer;
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if (((uint32_t)pData == 0U) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Output Compare DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * on the complementary output.
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Output Compare DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary PWM functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary PWM.
+ (+) Stop the Complementary PWM.
+ (+) Start the Complementary PWM and enable interrupts.
+ (+) Stop the Complementary PWM and disable interrupts.
+ (+) Start the Complementary PWM and enable DMA transfers.
+ (+) Stop the Complementary PWM and disable DMA transfers.
+ (+) Start the Complementary Input Capture measurement.
+ (+) Stop the Complementary Input Capture.
+ (+) Start the Complementary Input Capture and enable interrupts.
+ (+) Stop the Complementary Input Capture and disable interrupts.
+ (+) Start the Complementary Input Capture and enable DMA transfers.
+ (+) Stop the Complementary Input Capture and disable DMA transfers.
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation on the complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Enable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the TIM Break interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the PWM signal generation in interrupt mode on the
+ * complementary output.
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ uint32_t tmpccer;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the TIM Break interrupt (only if no more channel is active) */
+ tmpccer = htim->Instance->CCER;
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ {
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+ }
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * complementary output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+{
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ else if (htim->State == HAL_TIM_STATE_READY)
+ {
+ if (((uint32_t)pData == 0U) && (Length > 0U))
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ htim->State = HAL_TIM_STATE_BUSY;
+ }
+ }
+ else
+ {
+ /* nothing to do */
+ }
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
+
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Enable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
+ * output
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ {
+ /* Disable the TIM Capture/Compare 1 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
+ }
+
+ case TIM_CHANNEL_2:
+ {
+ /* Disable the TIM Capture/Compare 2 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
+ }
+
+ case TIM_CHANNEL_3:
+ {
+ /* Disable the TIM Capture/Compare 3 DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ /* Disable the complementary PWM output */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Timer Complementary One Pulse functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Start the Complementary One Pulse generation.
+ (+) Stop the Complementary One Pulse.
+ (+) Start the Complementary One Pulse and enable interrupts.
+ (+) Stop the Complementary One Pulse and disable interrupts.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation on the complementary
+ * output.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Enable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+
+ /* Enable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+
+ /* Enable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
+
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
+ * complementary channel.
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
+
+ /* Disable the TIM Capture/Compare 1 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+
+ /* Disable the TIM Capture/Compare 2 interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+
+ /* Disable the complementary One Pulse output */
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
+
+ /* Disable the Peripheral */
+ __HAL_TIM_DISABLE(htim);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to:
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
+ (+) Configure Complementary channels, break features and dead time.
+ (+) Configure Master synchronization.
+ (+) Configure timer remapping capabilities.
+ (+) Select timer input source.
+ (+) Enable or disable channel grouping.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configure the TIM commutation event sequence.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configure the TIM commutation event sequence with interrupt.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ /* Enable the Commutation Interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Configure the TIM commutation event sequence with DMA.
+ * @note This function is mandatory to use the commutation event in order to
+ * update the configuration at each commutation detection on the TRGI input of the Timer,
+ * the typical use of this feature is with the use of another Timer(interface Timer)
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
+ * the TI1 of the Interface Timer detect a commutation at its input TI1.
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal trigger 0 selected
+ * @arg TIM_TS_ITR1: Internal trigger 1 selected
+ * @arg TIM_TS_ITR2: Internal trigger 2 selected
+ * @arg TIM_TS_ITR3: Internal trigger 3 selected
+ * @arg TIM_TS_NONE: No trigger is needed
+ * @param CommutationSource the Commutation Event source
+ * This parameter can be one of the following values:
+ * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
+ * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
+
+ __HAL_LOCK(htim);
+
+ if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
+ (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
+ {
+ /* Select the Input trigger */
+ htim->Instance->SMCR &= ~TIM_SMCR_TS;
+ htim->Instance->SMCR |= InputTrigger;
+ }
+
+ /* Select the Capture Compare preload feature */
+ htim->Instance->CR2 |= TIM_CR2_CCPC;
+ /* Select the Commutation event source */
+ htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+ htim->Instance->CR2 |= CommutationSource;
+
+ /* Enable the Commutation DMA Request */
+ /* Set the DMA Commutation Callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
+ /* Set the DMA error callback */
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Enable the Commutation DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @brief Configures the TIM in master mode.
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
+ * contains the selected trigger output (TRGO) and the Master/Slave
+ * mode.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+ assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Change the handler state */
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+ if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+ /* Clear the MMS2 bits */
+ tmpcr2 &= ~TIM_CR2_MMS2;
+ /* Select the TRGO2 source*/
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ }
+
+ /* Reset the MMS Bits */
+ tmpcr2 &= ~TIM_CR2_MMS;
+ /* Select the TRGO source */
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
+
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+{
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ uint32_t tmpbdtr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
+ assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
+ assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
+ assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
+ assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
+ assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+
+ /* Set BREAK AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+ }
+
+ if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
+ assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
+ assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+
+ /* Set the BREAK2 input related BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+
+ if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
+ {
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+
+ /* Set BREAK2 AF mode */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+ }
+ }
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the break input source.
+ * @param htim TIM handle.
+ * @param BreakInput Break input to configure
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @param sBreakInputConfig Break input source configuration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
+ uint32_t BreakInput,
+ TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+
+{
+ uint32_t tmporx;
+ uint32_t bkin_enable_mask;
+ uint32_t bkin_polarity_mask;
+ uint32_t bkin_enable_bitpos;
+ uint32_t bkin_polarity_bitpos;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+ assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
+ assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+ {
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+ }
+
+ /* Check input state */
+ __HAL_LOCK(htim);
+
+ switch (sBreakInputConfig->Source)
+ {
+ case TIM_BREAKINPUTSOURCE_BKIN:
+ {
+ bkin_enable_mask = TIM1_AF1_BKINE;
+ bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+ bkin_polarity_mask = TIM1_AF1_BKINP;
+ bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+ break;
+ }
+
+ default:
+ {
+ bkin_enable_mask = 0U;
+ bkin_polarity_mask = 0U;
+ bkin_enable_bitpos = 0U;
+ bkin_polarity_bitpos = 0U;
+ break;
+ }
+ }
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Get the TIMx_AF1 register value */
+ tmporx = htim->Instance->AF1;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
+
+ /* Set TIMx_AF1 */
+ htim->Instance->AF1 = tmporx;
+ break;
+ }
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Get the TIMx_AF2 register value */
+ tmporx = htim->Instance->AF2;
+
+ /* Enable the break input */
+ tmporx &= ~bkin_enable_mask;
+ tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+
+ /* Set the break input polarity */
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
+
+ /* Set TIMx_AF2 */
+ htim->Instance->AF2 = tmporx;
+ break;
+ }
+ default:
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Configures the TIMx Remapping input capabilities.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
+ *
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
+{
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Select the timer input source
+ * @param htim TIM handle.
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TI1 input channel
+ * @arg TIM_CHANNEL_2: TI2 input channel
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
+ * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
+ * For TIM1, the parameter is one of the following values:
+ * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO
+ * @arg TIM_TIM1_TI2_GPIO: TIM1 TI2 is connected to GPIO
+ * @arg TIM_TIM1_TI3_GPIO: TIM1 TI3 is connected to GPIO
+ * @arg TIM_TIM1_TI4_GPIO: TIM1 TI4 is connected to GPIO
+ *
+ * For TIM2, the parameter is one of the following values:
+ * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
+ * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO
+ * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO
+ * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO
+ *
+ * For TIM3, the parameter is one of the following values:
+ * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
+ * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO
+ * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO
+ * @arg TIM_TIM3_TI4_GPIO: TIM3 TI4 is connected to GPIO
+ *
+ * For TIM4, the parameter is one of the following values:
+ * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO
+ * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO
+ * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO
+ * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO
+ *
+ * For TIM5, the parameter is one of the following values:
+ * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO
+ * @arg TIM_TIM5_TI1_FDCAN_TMP: TIM5 TI1 is connected to FDCAN TMP
+ * @arg TIM_TIM5_TI1_FDCAN_RTP: TIM5 TI1 is connected to FDCAN RTP
+ * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO
+ * @arg TIM_TIM5_TI3_GPIO: TIM5 TI3 is connected to GPIO
+ * @arg TIM_TIM5_TI4_GPIO: TIM5 TI4 is connected to GPIO
+ *
+ * For TIM8, the parameter is one of the following values:
+ * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
+ * @arg TIM_TIM8_TI2_GPIO: TIM8 TI2 is connected to GPIO
+ * @arg TIM_TIM8_TI3_GPIO: TIM8 TI3 is connected to GPIO
+ * @arg TIM_TIM8_TI4_GPIO: TIM8 TI4 is connected to GPIO
+ *
+ * For TIM12, the parameter can have the following values:
+ * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
+ * @arg TIM_TIM12_TI2_GPIO: TIM12 TI2 is connected to GPIO
+ *
+ * For TIM13, the parameter can have the following values:
+ * @arg TIM_TIM13_TI1_GPIO: TIM13 TI1 is connected to GPIO
+ *
+ * For TIM14, the parameter can have the following values:
+ * @arg TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO
+ *
+ * For TIM15, the parameter is one of the following values:
+ * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
+ * @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1
+ * @arg TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1
+ * @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1
+ * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
+ * @arg TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI
+ * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
+ * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
+ * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
+ * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
+ * @arg TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2
+ *
+ * For TIM16, the parameter can have the following values:
+ * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
+ * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
+ * @arg TIM_TIM16_TI1_WKUP_IT: TIM16 TI1 is connected to RTC wakeup interrupt
+ *
+ * For TIM17, the parameter can have the following values:
+ * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
+ * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (**)
+ * @arg TIM_TIM17_TI1_HSE_RTC: TIM17 TI1 is connected to HSE_RTC
+ * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check parameters */
+ assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_TISEL(TISelection));
+
+ __HAL_LOCK(htim);
+
+ switch (Channel)
+ {
+ case TIM_CHANNEL_1:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
+ break;
+ case TIM_CHANNEL_2:
+ MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Group channel 5 and channel 1, 2 or 3
+ * @param htim TIM handle.
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.
+ * This parameter can be any combination of the following values:
+ * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
+ * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
+ * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
+ * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
+{
+ /* Check parameters */
+ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_GROUPCH5(Channels));
+
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
+ htim->State = HAL_TIM_STATE_BUSY;
+
+ /* Clear GC5Cx bit fields */
+ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
+
+ /* Set GC5Cx bit fields */
+ htim->Instance->CCR5 |= Channels;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disarm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to disarm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note The break input can be disarmed only when it is configured in
+ * bidirectional mode and when when MOE is reset.
+ * @note Purpose is to be able to have the input voltage back to high-state,
+ * whatever the time constant on the output .
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ uint32_t tmpbdtr;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ tmpbdtr = READ_REG(htim->Instance->BDTR);
+ if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+ (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+ {
+ /* Break input BRK is disarmed */
+ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Arm the designated break input (when it operates in bidirectional mode).
+ * @param htim TIM handle.
+ * @param BreakInput Break input to arm
+ * This parameter can be one of the following values:
+ * @arg TIM_BREAKINPUT_BRK: Timer break input
+ * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+ * @note Arming is possible at anytime, even if fault is present.
+ * @note Break input is automatically armed as soon as MOE bit is set.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+ uint32_t tickstart;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+ switch (BreakInput)
+ {
+ case TIM_BREAKINPUT_BRK:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+ {
+ /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ do
+ {
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM)
+ {
+ return HAL_OK;
+ }
+ } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
+
+ return HAL_TIMEOUT;
+ }
+ break;
+ }
+
+ case TIM_BREAKINPUT_BRK2:
+ {
+ /* Check initial conditions */
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+ {
+ /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+ do
+ {
+ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM)
+ {
+ return HAL_OK;
+ }
+ } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
+
+ return HAL_TIMEOUT;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Callbacks functions #####
+ ==============================================================================
+ [..]
+ This section provides Extended TIM callback functions:
+ (+) Timer Commutation callback
+ (+) Timer Break callback
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Hall commutation changed callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break detection callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_BreakCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Extended Peripheral State functions #####
+ ==============================================================================
+ [..]
+ This subsection permits to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the TIM Hall Sensor interface handle state.
+ * @param htim TIM Hall Sensor handle
+ * @retval HAL state
+ */
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+{
+ return htim->State;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Commutation half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationHalfCpltCallback(htim);
+#else
+ HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+#endif
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx to select the TIM peripheral
+ * @param Channel specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
+ * @retval None
+ */
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
+{
+ uint32_t tmp;
+
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_TIM_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
new file mode 100644
index 0000000..2e5cd35
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
@@ -0,0 +1,4579 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_uart.c
+ * @author MCD Application Team
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The UART HAL driver can be used as follows:
+
+ (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+ (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+ (++) Enable the USARTx interface clock.
+ (++) UART pins configuration:
+ (+++) Enable the clock for the UART GPIOs.
+ (+++) Configure these UART pins as alternate function pull-up.
+ (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+ and HAL_UART_Receive_IT() APIs):
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
+ (++) UART interrupts handling:
+ -@@- The specific UART interrupts (Transmission complete interrupt,
+ RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+ are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+ inside the transmit and receive processes.
+ (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+ and HAL_UART_Receive_DMA() APIs):
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+ flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+ (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+ in the huart handle AdvancedInit structure.
+
+ (#) For the UART asynchronous mode, initialize the UART registers by calling
+ the HAL_UART_Init() API.
+
+ (#) For the UART Half duplex mode, initialize the UART registers by calling
+ the HAL_HalfDuplex_Init() API.
+
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+ by calling the HAL_LIN_Init() API.
+
+ (#) For the UART Multiprocessor mode, initialize the UART registers
+ by calling the HAL_MultiProcessor_Init() API.
+
+ (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ [..]
+ (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+ also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ calling the customized HAL_UART_MspInit() API.
+
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+ Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+ and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+ or @ref HAL_UART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UART UART
+ * @brief HAL UART module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \
+ USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \
+ USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+
+#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
+#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+#ifdef HAL_DMA_MODULE_ENABLED
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+#endif
+#ifdef HAL_MDMA_MODULE_ENABLED
+static void UART_MDMATransmitCplt(MDMA_HandleTypeDef *hmdma);
+static void UART_MDMAReceiveCplt(MDMA_HandleTypeDef *hmdma);
+static void UART_MDMAError(MDMA_HandleTypeDef *hmdma);
+static void UART_MDMAAbortOnError(MDMA_HandleTypeDef *hmdma);
+static void UART_MDMATxAbortCallback(MDMA_HandleTypeDef *hmdma);
+static void UART_MDMARxAbortCallback(MDMA_HandleTypeDef *hmdma);
+static void UART_MDMATxOnlyAbortCallback(MDMA_HandleTypeDef *hmdma);
+static void UART_MDMARxOnlyAbortCallback(MDMA_HandleTypeDef *hmdma);
+#endif /* HAL_MDMA_MODULE_ENABLED */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+ * @{
+ */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+ follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+ and UART multiprocessor mode configuration procedures (details for the procedures
+ are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+ }
+ else
+ {
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In asynchronous mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Initialize the half-duplex mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check UART instance */
+ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In half-duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param BreakDetectLength Specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief Initialize the multiprocessor mode according to the specified
+ * parameters in the UART_InitTypeDef and initialize the associated handle.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod Specifies the UART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+ * @note If the user resorts to idle line detection wake up, the Address parameter
+ * is useless and ignored by the initialization function.
+ * @note If the user resorts to address mark wake up, the address length detection
+ * is configured by default to 4 bits only. For the UART to be able to
+ * manage 6-, 7- or 8-bit long addresses detection, the API
+ * HAL_MultiProcessorEx_AddressLength_Set() must be called after
+ * HAL_MultiProcessor_Init().
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the wake up method parameter */
+ assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In multiprocessor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN, HDSEL and IREN bits in the USART_CR3 register. */
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+ if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+ {
+ /* If address mark wake up method is chosen, set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+ }
+
+ /* Set the wake up method by setting the WAKE bit in the CR1 register */
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+
+/**
+ * @brief DeInitialize the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(huart->Instance));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ huart->Instance->CR1 = 0x0U;
+ huart->Instance->CR2 = 0x0U;
+ huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ if (huart->MspDeInitCallback == NULL)
+ {
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ huart->MspDeInitCallback(huart);
+#else
+ /* DeInit the low level hardware */
+ HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspInit can be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitialize the UART MSP.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_MspDeInit can be implemented in the user file
+ */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User UART Callback
+ * To be used instead of the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID :
+ huart->RxFifoFullCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ huart->TxFifoEmptyCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(huart);
+
+ if (HAL_UART_STATE_READY == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ break;
+
+ case HAL_UART_RX_FIFO_FULL_CB_ID :
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ break;
+
+ case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ break;
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_UART_STATE_RESET == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+ * @brief UART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of functions allowing to manage the UART asynchronous
+ and Half duplex data transfers.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (+) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
+
+ (#) Non-Blocking mode API's with DMA are :
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_UART_Abort()
+ (+) HAL_UART_AbortTransmit()
+ (+) HAL_UART_AbortReceive()
+ (+) HAL_UART_Abort_IT()
+ (+) HAL_UART_AbortTransmit_IT()
+ (+) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_UART_AbortCpltCallback()
+ (+) HAL_UART_AbortTransmitCpltCallback()
+ (+) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+ -@- In the Half duplex communication, it is forbidden to run the transmit
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+ * data to the TXFIFO. Write operations to the TDR register are performed
+ * when TXFNF flag is set. From hardware perspective, TXFNF flag and
+ * TXE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
+
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ while (huart->TxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
+ }
+ huart->TxXferCount--;
+ }
+
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ huart->RxXferCount--;
+ }
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+ huart->TxISR = NULL;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Configure Tx interrupt processing */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the TX FIFO threshold interrupt */
+ SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+ }
+ else
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the Transmit Data Register Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+ huart->RxISR = NULL;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing*/
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
+ huart->TxXferCount = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the UART transmit DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+#ifdef HAL_MDMA_MODULE_ENABLED
+ if (huart->hmdmatx != NULL)
+ {
+ /* Set the UART MDMA transfer complete callback */
+ huart->hmdmatx->XferCpltCallback = UART_MDMATransmitCplt;
+
+ /* Set the MDMA error callback */
+ huart->hmdmatx->XferErrorCallback = UART_MDMAError;
+
+ /* Set the MDMA abort callback */
+ huart->hmdmatx->XferAbortCallback = NULL;
+
+ /* Enable the UART transmit MDMA channel */
+ if (HAL_MDMA_Start_IT(huart->hmdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size, 1) != HAL_OK)
+ {
+ /* Set error code to MDMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ /* Clear the TC flag in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+#ifdef HAL_MDMA_MODULE_ENABLED
+ if (huart->hmdmarx != NULL)
+ {
+ /* Set the UART MDMA transfer complete callback */
+ huart->hmdmarx->XferCpltCallback = UART_MDMAReceiveCplt;
+
+ /* Set the MDMA error callback */
+ huart->hmdmarx->XferErrorCallback = UART_MDMAError;
+
+ /* Set the MDMA abort callback */
+ huart->hmdmarx->XferAbortCallback = NULL;
+
+ /* Enable the MDMA channel */
+ if (HAL_MDMA_Start_IT(huart->hmdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size, 1) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ __HAL_LOCK(huart);
+
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ /* Disable the UART DMA Tx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ /* Enable the UART DMA Tx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART DMA Rx request */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the DMA Transfer.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if (huart->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Tx channel */
+ if (huart->hmdmatx != NULL)
+ {
+ if (HAL_MDMA_Abort(huart->hmdmatx) != HAL_OK)
+ {
+ if (HAL_MDMA_GetError(huart->hmdmatx) == HAL_MDMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if (huart->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Rx channel */
+ if (huart->hmdmarx != NULL)
+ {
+ if (HAL_MDMA_Abort(huart->hmdmarx) != HAL_OK)
+ {
+ if (HAL_MDMA_GetError(huart->hmdmarx) == HAL_MDMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+#endif
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+ /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hmdmatx != NULL)
+ {
+ /* Set the UART MDMA Abort callback to Null.
+ No call back execution at end of MDMA abort procedure */
+ huart->hmdmatx->XferAbortCallback = NULL;
+
+ if (HAL_MDMA_Abort(huart->hmdmatx) != HAL_OK)
+ {
+ if (HAL_MDMA_GetError(huart->hmdmatx) == HAL_MDMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hmdmarx != NULL)
+ {
+ /* Set the UART MDMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hmdmarx->XferAbortCallback = NULL;
+
+ if (HAL_MDMA_Abort(huart->hmdmarx) != HAL_OK)
+ {
+ if (HAL_MDMA_GetError(huart->hmdmarx) == HAL_MDMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TCIE, TXEIE and TXFTIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Tx channel : use blocking MDMA Abort API (no callback) */
+ if (huart->hmdmatx != NULL)
+ {
+ /* Set the UART MDMA Abort callback to Null.
+ No call back execution at end of MDMA abort procedure */
+ huart->hmdmatx->XferAbortCallback = NULL;
+
+ if (HAL_MDMA_Abort(huart->hmdmatx) != HAL_OK)
+ {
+ if (HAL_MDMA_GetError(huart->hmdmatx) == HAL_MDMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+ /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Rx channel : use blocking MDMA Abort API (no callback) */
+ if (huart->hmdmarx != NULL)
+ {
+ /* Set the UART MDMA Abort callback to Null.
+ No call back execution at end of MDMA abort procedure */
+ huart->hmdmarx->XferAbortCallback = NULL;
+
+ if (HAL_MDMA_Abort(huart->hmdmarx) != HAL_OK)
+ {
+ if (HAL_MDMA_GetError(huart->hmdmarx) == HAL_MDMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+#if defined(HAL_DMA_MODULE_ENABLED)
+ if (huart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+#endif
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* MDMA Tx Handle is valid */
+ if (huart->hmdmatx != NULL)
+ {
+ /* Set MDMA Abort Complete callback if UART MDMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hmdmatx->XferAbortCallback = UART_MDMATxAbortCallback;
+ }
+ else
+ {
+ huart->hmdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* MDMA Rx Handle is valid */
+ if (huart->hmdmarx != NULL)
+ {
+ /* Set MDMA Abort Complete callback if UART MDMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hmdmarx->XferAbortCallback = UART_MDMARxAbortCallback;
+ }
+ else
+ {
+ huart->hmdmarx->XferAbortCallback = NULL;
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+#endif
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Tx channel : use non blocking MDMA Abort API (callback) */
+ if (huart->hmdmatx != NULL)
+ {
+ /* UART Tx MDMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of MDMA abort procedure */
+
+ /* Abort MDMA TX */
+ if (HAL_MDMA_Abort_IT(huart->hmdmatx) != HAL_OK)
+ {
+ huart->hmdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+#endif
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Rx channel : use non blocking MDMA Abort API (callback) */
+ if (huart->hmdmarx != NULL)
+ {
+ /* UART Rx MDMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of MDMA abort procedure */
+
+ /* Abort MDMA RX */
+ if (HAL_MDMA_Abort_IT(huart->hmdmarx) != HAL_OK)
+ {
+ huart->hmdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+#endif
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Tx channel : use non blocking MDMA Abort API (callback) */
+ else if (huart->hmdmatx != NULL)
+ {
+ /* Set the UART MDMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of MDMA abort procedure */
+ huart->hmdmatx->XferAbortCallback = UART_MDMATxOnlyAbortCallback;
+
+ /* Abort MDMA TX */
+ if (HAL_MDMA_Abort_IT(huart->hmdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hmdmatx->XferAbortCallback function in case of error */
+ huart->hmdmatx->XferAbortCallback(huart->hmdmatx);
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ if (1 == 2) {
+ // dummy
+ }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+#endif
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Rx channel : use non blocking MDMA Abort API (callback) */
+ else if (huart->hmdmarx != NULL)
+ {
+ /* Set the UART MDMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of MDMA abort procedure */
+ huart->hmdmarx->XferAbortCallback = UART_MDMARxOnlyAbortCallback;
+
+ /* Abort MDMA RX */
+ if (HAL_MDMA_Abort_IT(huart->hmdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hmdmarx->XferAbortCallback function in case of error */
+ huart->hmdmarx->XferAbortCallback(huart->hmdmarx);
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART interrupt request.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
+ uint32_t errorflags;
+ uint32_t errorcode;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if ((errorflags != 0U)
+ && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver --------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ {
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
+ }
+
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = huart->ErrorCode;
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
+ /* Abort the UART DMA Rx channel */
+ else if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+#endif
+#ifdef HAL_MDMA_MODULE_ENABLED
+ /* Abort the UART MDMA Rx channel */
+ else if (huart->hmdmarx != NULL)
+ {
+ /* Set the UART MDMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of MDMA abort procedure */
+ huart->hmdmarx->XferAbortCallback = UART_MDMAAbortOnError;
+
+ /* Abort MDMA RX */
+ if (HAL_MDMA_Abort_IT(huart->hmdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hmdmarx->XferAbortCallback function in case of error */
+ huart->hmdmarx->XferAbortCallback(huart->hmdmarx);
+ }
+ }
+#endif /* HAL_MDMA_MODULE_ENABLED */
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+ /* UART Rx state is not reset as a reception process might be ongoing.
+ If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Wakeup Callback */
+ huart->WakeupCallback(huart);
+#else
+ /* Call legacy weak Wakeup Callback */
+ HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* UART in mode Transmitter ------------------------------------------------*/
+ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ {
+ if (huart->TxISR != NULL)
+ {
+ huart->TxISR(huart);
+ }
+ return;
+ }
+
+ /* UART in mode Transmitter (transmission end) -----------------------------*/
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ {
+ UART_EndTransmit_IT(huart);
+ return;
+ }
+
+ /* UART TX Fifo Empty occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Fifo Empty Callback */
+ huart->TxFifoEmptyCallback(huart);
+#else
+ /* Call legacy weak Tx Fifo Empty Callback */
+ HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+
+ /* UART RX Fifo Full occurred ----------------------------------------------*/
+ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Fifo Full Callback */
+ huart->RxFifoFullCallback(huart);
+#else
+ /* Call legacy weak Rx Fifo Full Callback */
+ HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ return;
+ }
+}
+
+/**
+ * @brief Tx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Tx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief Rx Half Transfer completed callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART error callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+ * @brief UART control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+ (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+ (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+ (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+ (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) UART_SetConfig() API configures the UART peripheral
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+ (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+ (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+ assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+ MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+}
+
+/**
+ * @brief Enable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Enable USART mute mode by setting the MME bit in the CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Disable UART mute mode (does not mean the UART actually exits mute mode
+ * as it may not have been in mute mode at this very moment).
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Enter UART mute mode (means UART actually enters mute mode).
+ * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+ * @param huart UART handle.
+ * @retval None
+ */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+ __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+ * @brief Enable the UART transmitter and disable the UART receiver.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the UART receiver and disable the UART transmitter.
+ * @param huart UART handle.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+ __HAL_LOCK(huart);
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear TE and RE bits */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+ /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Transmit break characters.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief UART Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Return the UART handle state.
+ (+) Return the UART handle error code
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Return the UART handle state.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval HAL state
+ */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+ * @brief Return the UART handle error code.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART.
+ * @retval UART Error Code
+ */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+ return huart->ErrorCode;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param huart UART handle.
+ * @retval none
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+ /* Init the UART Callback settings */
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the UART peripheral.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpreg;
+ uint16_t brrtemp;
+ UART_ClockSourceTypeDef clocksource;
+ uint32_t usartdiv = 0x00000000U;
+ HAL_StatusTypeDef ret = HAL_OK;
+ PLL3_ClocksTypeDef pll3_clocks;
+ PLL4_ClocksTypeDef pll4_clocks;
+ uint32_t pclk;
+
+ /* Check the parameters */
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+ assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+
+ assert_param(IS_UART_PARITY(huart->Init.Parity));
+ assert_param(IS_UART_MODE(huart->Init.Mode));
+ assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+ assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+ assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
+ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ tmpreg |= (uint32_t)huart->FifoMode;
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+ * to huart->Init.StopBits value */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+ tmpreg |= huart->Init.OneBitSampling;
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART PRESC Configuration -----------------------*/
+ /* Configure
+ * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ UART_GETCLOCKSOURCE(huart, clocksource);
+
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PCLK5:
+ pclk = HAL_RCC_GetPCLK5Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PLL3Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PLL4Q:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pll4_clocks.PLL4_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_CSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_HSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+ else
+ {
+ switch (clocksource)
+ {
+ case UART_CLOCKSOURCE_PCLK1:
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PCLK2:
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PCLK5:
+ pclk = HAL_RCC_GetPCLK5Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PLL3Q:
+ HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_PLL4Q:
+ HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pll4_clocks.PLL4_Q_Frequency, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_HSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_CSI:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(CSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ case UART_CLOCKSOURCE_HSE:
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ break;
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ huart->Instance->BRR = usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+ }
+
+ /* Initialize the number of data to process during RX/TX ISR execution */
+ huart->NbTxDataToProcess = 1;
+ huart->NbRxDataToProcess = 1;
+
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ return ret;
+}
+
+/**
+ * @brief Configure the UART peripheral advanced features.
+ * @param huart UART handle.
+ * @retval None
+ */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure auto Baud rate detection scheme */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ {
+ assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ /* set auto Baudrate detection parameters if detection is enabled */
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ {
+ assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ }
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ }
+}
+
+/**
+ * @brief Check the UART Idle State.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ uint32_t tickstart;
+
+ /* Initialize the UART ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check if the Receiver is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle UART Communication Timeout.
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+
+ if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ {
+ /* Clear Receiver Timeout flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE, TCIE, TXFT interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Reset RxIsr function pointer */
+ huart->RxISR = NULL;
+}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
+/**
+ * @brief DMA UART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (hdma->Init.Mode != DMA_CIRCULAR)
+ {
+ huart->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief DMA UART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx Half complete callback*/
+ huart->TxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Tx Half complete callback*/
+ HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if (hdma->Init.Mode != DMA_CIRCULAR)
+ {
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART communication error callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmarx != NULL)
+ {
+ if (huart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hdmatx != NULL)
+ {
+ if (huart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Flush the whole TX FIFO (if needed) */
+ if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+ {
+ __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+ }
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+#endif
+
+#if defined(HAL_MDMA_MODULE_ENABLED)
+
+/**
+ * @brief MDMA UART transmit process complete callback.
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMATransmitCplt(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hmdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Disable the MDMA transfer for transmit request by resetting the DMAT bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief MDMA UART receive process complete callback.
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMAReceiveCplt(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hmdma->Parent);
+
+
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the MDMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief MDMA UART communication error callback.
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMAError(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hmdma->Parent);
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX)
+ && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART MDMA Rx request if ongoing */
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX)
+ && (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
+ huart->ErrorCode |= HAL_UART_ERROR_DMA;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief MDMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of MDMA Abort procedure following error occurrence).
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMAAbortOnError(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hmdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief MDMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of MDMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx MDMA Handle.
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMATxAbortCallback(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hmdma->Parent);
+
+ huart->hmdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hmdmarx != NULL)
+ {
+ if (huart->hmdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All MDMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief MDMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of MDMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx MDMA Handle.
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMARxAbortCallback(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hmdma->Parent);
+
+ huart->hmdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if (huart->hmdmatx != NULL)
+ {
+ if (huart->hmdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All MDMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief MDMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of MDMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMATxOnlyAbortCallback(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hmdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief MDMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of MDMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hmdma MDMA handle.
+ * @retval None
+ */
+static void UART_MDMARxOnlyAbortCallback(MDMA_HandleTypeDef *hmdma)
+{
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent;
+
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+/**
+ * @brief TX interrrupt handler for 7 or 8 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrrupt handler for 9 bits data word length.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ tmp = (uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+/**
+ * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ }
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
+ huart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t nb_tx_data;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the TX FIFO threshold interrupt */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ break; /* force exit loop */
+ }
+ else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+ {
+ tmp = (uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval None
+ */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable the UART Transmit Complete Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Cleat TxISR function pointer */
+ huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief RX interrrupt handler for 7 or 8 bits data word length .
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrrupt handler for 9 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_8BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+ uint16_t nb_rx_data;
+ uint16_t rxdatacount;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* When remaining number of bytes to receive is less than the RX FIFO
+ threshold, next incoming frames are processed as if FIFO mode was
+ disabled (i.e. one interrupt per received frame).
+ */
+ rxdatacount = huart->RxXferCount;
+ if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ {
+ /* Disable the UART RXFT interrupt*/
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+ /* Update the RxISR function pointer */
+ huart->RxISR = UART_RxISR_16BIT;
+
+ /* Enable the UART Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c
new file mode 100644
index 0000000..5770d1d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart_ex.c
@@ -0,0 +1,729 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_hal_uart_ex.c
+ * @author MCD Application Team
+ * @brief Extended UART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### UART peripheral extended features #####
+ ==============================================================================
+
+ (#) Declare a UART_HandleTypeDef handle structure.
+
+ (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+ by calling the HAL_RS485Ex_Init() API.
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup UARTEx UARTEx
+ * @brief UART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+ * @{
+ */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+ * @{
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Extended Initialization and Configuration Functions
+ *
+@verbatim
+===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in asynchronous mode.
+ (+) For the asynchronous mode the parameters below can be configured:
+ (++) Baud Rate
+ (++) Word Length
+ (++) Stop Bit
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ (++) Hardware flow control
+ (++) Receiver/transmitter modes
+ (++) Over Sampling Method
+ (++) One-Bit Sampling Method
+ (+) For the asynchronous mode, the following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) auto Baud rate detection
+ [..]
+ The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+ procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
+ * @{
+ */
+
+/**
+ * @brief Initialize the RS485 Driver enable feature according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param Polarity Select the driver enable polarity.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
+ * @param AssertionTime Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime)
+{
+ uint32_t temp;
+
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Check the Driver Enable UART instance */
+ assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+ /* Check the Driver Enable polarity */
+ assert_param(IS_UART_DE_POLARITY(Polarity));
+
+ /* Check the Driver Enable assertion time */
+ assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+ /* Check the Driver Enable deassertion time */
+ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+ * @brief Extended functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+ (#) Wakeup from Stop mode Callback:
+ (+) HAL_UARTEx_WakeupCallback()
+
+ (#) TX/RX Fifos Callbacks:
+ (+) HAL_UARTEx_RxFifoFullCallback()
+ (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief UART wakeup from Stop mode callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART RX Fifo full callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART TX Fifo empty callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+ detection length to more than 4 bits for multiprocessor address mark wake up.
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+ trigger: address match, Start Bit detection or RXNE bit status.
+ (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+ (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+ (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart UART handle.
+ * @param AddressLength This parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+/**
+ * @brief Set Wakeup from Stop mode interrupt flag selection.
+ * @note It is the application responsibility to enable the interrupt used as
+ * usart_wkup interrupt source before entering low-power mode.
+ * @param huart UART handle.
+ * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_STARTBIT
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* check the wake-up from stop mode UART instance */
+ assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+ /* check the wake-up selection parameter */
+ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the wake-up selection scheme */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+ {
+ UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+ }
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ status = HAL_TIMEOUT;
+ }
+ else
+ {
+ /* Initialize the UART State */
+ huart->gState = HAL_UART_STATE_READY;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Enable UART Stop Mode.
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Set UESM bit */
+ SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable UART Stop Mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ /* Clear UESM bit */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Enable FIFO mode */
+ SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the FIFO mode.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Enable FIFO mode */
+ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the TXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold TX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_TXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_TXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_TXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update TX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Set the RXFIFO threshold.
+ * @param huart UART handle.
+ * @param Threshold RX FIFO threshold value
+ * This parameter can be one of the following values:
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_1_2
+ * @arg @ref UART_RXFIFO_THRESHOLD_3_4
+ * @arg @ref UART_RXFIFO_THRESHOLD_7_8
+ * @arg @ref UART_RXFIFO_THRESHOLD_8_8
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ uint32_t tmpcr1;
+
+ /* Check the parameters */
+ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+ assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Save actual UART configuration */
+ tmpcr1 = READ_REG(huart->Instance->CR1);
+
+ /* Disable UART */
+ __HAL_UART_DISABLE(huart);
+
+ /* Update RX threshold configuration */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+ /* Determine the number of data to process during RX/TX ISR execution */
+ UARTEx_SetNbDataToProcess(huart);
+
+ /* Restore UART configuration */
+ WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart UART handle.
+ * @param WakeUpSelection UART wake up from stop mode parameters.
+ * @retval None
+ */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+ /* Set the USART address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+ /* Set the USART address node */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+ * @brief Calculate the number of data to process in RX/TX ISR.
+ * @note The RX FIFO depth and the TX FIFO depth is extracted from
+ * the UART configuration registers.
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+ uint8_t rx_fifo_depth;
+ uint8_t tx_fifo_depth;
+ uint8_t rx_fifo_threshold;
+ uint8_t tx_fifo_threshold;
+ uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+ uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+ if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+ {
+ huart->NbTxDataToProcess = 1U;
+ huart->NbRxDataToProcess = 1U;
+ }
+ else
+ {
+ rx_fifo_depth = RX_FIFO_DEPTH;
+ tx_fifo_depth = TX_FIFO_DEPTH;
+ rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
+ huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c
new file mode 100644
index 0000000..2d4ac31
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c
@@ -0,0 +1,1071 @@
+/**
+ ******************************************************************************
+ * @file stm32mp1xx_ll_adc.c
+ * @author MCD Application Team
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_ll_adc.h"
+#include "stm32mp1xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32MP1xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+ * @{
+ */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
+/* not timeout values: */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
+/* values definition. */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent */
+/* of device clock setting. */
+/* In user application, ADC timeout values should be defined with */
+/* temporal values, in function of device clock settings. */
+/* Highest ratio CPU clock frequency vs ADC clock frequency: */
+/* - ADC clock from synchronous clock with AHB prescaler 512, */
+/* APB prescaler 16, ADC prescaler 4. */
+/* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
+/* with highest ratio CPU clock frequency vs HSI clock frequency */
+/* Unit: CPU cycles. */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
+ ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ )
+
+#define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
+ ( ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
+ || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
+ )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \
+ )
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
+ )
+
+#define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
+ ( ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
+ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
+ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
+ || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \
+ )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
+ ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
+ ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
+ )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* multimode. */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
+ ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
+ )
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
+ ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \
+ )
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
+ ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5) \
+ )
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
+ ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
+ )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @note This function is performing a hard reset, using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 serie, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * To de-initialize only 1 ADC instance, use
+ * function @ref LL_ADC_DeInit().
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ /* Force reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
+ if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
+ assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
+ /* On this STM32 serie, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - Set ADC clock (conversion clock) */
+ /* - multimode (if several ADC instances available on the */
+ /* selected device) */
+ /* - Set ADC multimode configuration */
+ /* - Set ADC multimode DMA transfer */
+ /* - Set ADC multimode: delay between 2 sampling phases */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE
+ | ADC_CCR_PRESC
+ | ADC_CCR_DUAL
+ | ADC_CCR_DAMDF
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | ADC_CommonInitStruct->Multimode
+ | ADC_CommonInitStruct->MultiDMATransfer
+ | ADC_CommonInitStruct->MultiTwoSamplingDelay
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE
+ | ADC_CCR_PRESC
+ | ADC_CCR_DUAL
+ | ADC_CCR_DAMDF
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | LL_ADC_MULTI_INDEPENDENT
+ );
+ }
+#else
+ LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+#endif
+ }
+ else
+ {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ /* Set ADC_CommonInitStruct fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Set fields of ADC multimode */
+ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
+ ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+ ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @note If this functions returns error status, it means that ADC instance
+ * is in an unknown state.
+ * In this case, perform a hard reset using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 serie, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * Refer to function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ __IO uint32_t timeout_cpu_cycles = 0UL;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 1UL)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group regular. */
+ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
+ {
+ if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
+ {
+ LL_ADC_REG_StopConversion(ADCx);
+ }
+ }
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group injected. */
+ if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
+ {
+ if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
+ {
+ LL_ADC_INJ_StopConversion(ADCx);
+ }
+ }
+
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
+ | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+
+ /* Flush group injected contexts queue (register JSQR): */
+ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
+ /* contexts queue is maintained with the last active context). */
+ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+
+ /* Wait for ADC instance is effectively disabled */
+ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+ while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
+ {
+ timeout_cpu_cycles--;
+ if (timeout_cpu_cycles == 0UL)
+ {
+ /* Time-out error */
+ status = ERROR;
+ break;
+ }
+ }
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ if (READ_BIT(ADCx->CR,
+ (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN)
+ )
+ == 0UL)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ CLEAR_BIT(ADCx->IER,
+ (LL_ADC_IT_ADRDY
+ | LL_ADC_IT_EOC
+ | LL_ADC_IT_EOS
+ | LL_ADC_IT_OVR
+ | LL_ADC_IT_EOSMP
+ | LL_ADC_IT_JEOC
+ | LL_ADC_IT_JEOS
+ | LL_ADC_IT_JQOVF
+ | LL_ADC_IT_AWD1
+ | LL_ADC_IT_AWD2
+ | LL_ADC_IT_AWD3
+ )
+ );
+
+ /* Reset register ISR */
+ SET_BIT(ADCx->ISR,
+ (LL_ADC_FLAG_ADRDY
+ | LL_ADC_FLAG_EOC
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_EOSMP
+ | LL_ADC_FLAG_JEOC
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_JQOVF
+ | LL_ADC_FLAG_AWD1
+ | LL_ADC_FLAG_AWD2
+ | LL_ADC_FLAG_AWD3
+ )
+ );
+
+ /* Reset register CR */
+ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
+ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
+ /* access mode "read-set": no direct reset applicable. */
+ /* - Reset Calibration mode to default setting (single ended). */
+ /* - Disable ADC internal voltage regulator. */
+ /* - Enable ADC deep power down. */
+ /* Note: ADC internal voltage regulator disable and ADC deep power */
+ /* down enable are conditioned to ADC state disabled: */
+ /* already done above. */
+ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+ SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(ADCx->CFGR,
+ ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
+ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
+ | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
+ | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
+ | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES
+ | ADC_CFGR_DMNGT )
+ );
+
+ SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
+
+ /* Reset register CFGR2 */
+ CLEAR_BIT(ADCx->CFGR2,
+ ( ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
+ | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
+ | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS
+ | ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1,
+ (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+ | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+ | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17
+ | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14
+ | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11
+ | ADC_SMPR2_SMP10)
+ );
+
+ /* Reset register TR1 */
+ CLEAR_BIT(ADCx->LTR1, ADC_LTR1_LT1);
+ SET_BIT(ADCx->HTR1, ADC_HTR1_HT1);
+
+ CLEAR_BIT(ADCx->LTR2, ADC_LTR2_LT2);
+ SET_BIT(ADCx->HTR2, ADC_HTR2_HT2);
+ CLEAR_BIT(ADCx->LTR3, ADC_LTR3_LT3);
+ SET_BIT(ADCx->HTR3, ADC_HTR3_HT3);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1,
+ (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
+ | ADC_SQR1_SQ1 | ADC_SQR1_L)
+ );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2,
+ (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
+ | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
+ );
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(ADCx->SQR3,
+ (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
+ | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
+ );
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ (ADC_JSQR_JL
+ | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
+ );
+
+ /* Reset register DR */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE);
+ /* Reset register OFR2 */
+ CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE);
+ /* Reset register OFR3 */
+ CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE);
+ /* Reset register OFR4 */
+ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+ /* Reset register CALFACT2 */
+ CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT);
+ }
+ else
+ {
+ /* ADC instance is in an unknown state */
+ /* Need to performing a hard reset of ADC instance, using high level */
+ /* clock source RCC ADC reset. */
+ /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+ assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift));
+ assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC data resolution */
+ /* - Set ADC conversion data alignment */
+ /* - Set ADC low power mode */
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_RES
+ | ADC_CFGR_AUTDLY
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->LowPowerMode
+ );
+
+ MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B;
+ ADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
+ ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
+ assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* - Set ADC group regular overrun behavior */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_EXTSEL
+ | ADC_CFGR_EXTEN
+ | ADC_CFGR_DISCEN
+ | ADC_CFGR_DISCNUM
+ | ADC_CFGR_CONT
+ | ADC_CFGR_DMNGT
+ | ADC_CFGR_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerDiscont
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DataTransferMode
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_EXTSEL
+ | ADC_CFGR_EXTEN
+ | ADC_CFGR_DISCEN
+ | ADC_CFGR_DISCNUM
+ | ADC_CFGR_CONT
+ | ADC_CFGR_DMNGT
+ | ADC_CFGR_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DataTransferMode
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+
+ /* Set ADC group regular sequencer length and scan direction */
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
+ ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if (LL_ADC_IsEnabled(ADCx) == 0UL)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_JDISCEN
+ | ADC_CFGR_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_JDISCEN
+ | ADC_CFGR_JAUTO
+ ,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(ADCx->JSQR,
+ ADC_JSQR_JEXTSEL
+ | ADC_JSQR_JEXTEN
+ | ADC_JSQR_JL
+ ,
+ ADC_INJ_InitStruct->TriggerSource
+ | ADC_INJ_InitStruct->SequencerLength
+ );
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ /* Set ADC_INJ_InitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h
new file mode 100644
index 0000000..6375df1
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h
@@ -0,0 +1,846 @@
+/*
+ * Copyright (c) 2013-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 10. January 2017
+ * $Revision: V2.1.0
+ *
+ * Project: CMSIS-RTOS API
+ * Title: cmsis_os.h FreeRTOS header file
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * Version 0.03
+ * osKernelStart added, optional feature: main started as thread
+ * osSemaphores have standard behavior
+ * osTimerCreate does not start the timer, added osTimerStart
+ * osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ * Support for C++ interface
+ * - const attribute removed from the osXxxxDef_t typedefs
+ * - const attribute added to the osXxxxDef macros
+ * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ * Added: osKernelInitialize
+ * Version 1.02
+ * Control functions for short timeouts in microsecond resolution:
+ * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ * Removed: osSignalGet
+ * Version 2.0.0
+ * OS objects creation without macros (dynamic creation and resource allocation):
+ * - added: osXxxxNew functions which replace osXxxxCreate
+ * - added: osXxxxAttr_t structures
+ * - deprecated: osXxxxCreate functions, osXxxxDef_t structures
+ * - deprecated: osXxxxDef and osXxxx macros
+ * osStatus codes simplified and renamed to osStatus_t
+ * osEvent return structure deprecated
+ * Kernel:
+ * - added: osKernelInfo_t and osKernelGetInfo
+ * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)
+ * - added: osKernelLock, osKernelUnlock
+ * - added: osKernelSuspend, osKernelResume
+ * - added: osKernelGetTickCount, osKernelGetTickFreq
+ * - renamed osKernelSysTick to osKernelGetSysTimerCount
+ * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq
+ * - deprecated osKernelSysTickMicroSec
+ * Thread:
+ * - extended number of thread priorities
+ * - renamed osPrioriry to osPrioriry_t
+ * - replaced osThreadCreate with osThreadNew
+ * - added: osThreadGetName
+ * - added: osThreadState_t and osThreadGetState
+ * - added: osThreadGetStackSize, osThreadGetStackSpace
+ * - added: osThreadSuspend, osThreadResume
+ * - added: osThreadJoin, osThreadDetach, osThreadExit
+ * - added: osThreadGetCount, osThreadEnumerate
+ * - added: Thread Flags (moved from Signals)
+ * Signals:
+ * - renamed osSignals to osThreadFlags (moved to Thread Flags)
+ * - changed return value of Set/Clear/Wait functions
+ * - Clear function limited to current running thread
+ * - extended Wait function (options)
+ * - added: osThreadFlagsGet
+ * Event Flags:
+ * - added new independent object for handling Event Flags
+ * Delay and Wait functions:
+ * - added: osDelayUntil
+ * - deprecated: osWait
+ * Timer:
+ * - replaced osTimerCreate with osTimerNew
+ * - added: osTimerGetName, osTimerIsRunning
+ * Mutex:
+ * - extended: attributes (Recursive, Priority Inherit, Robust)
+ * - replaced osMutexCreate with osMutexNew
+ * - renamed osMutexWait to osMutexAcquire
+ * - added: osMutexGetName, osMutexGetOwner
+ * Semaphore:
+ * - extended: maximum and initial token count
+ * - replaced osSemaphoreCreate with osSemaphoreNew
+ * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)
+ * - added: osSemaphoreGetName, osSemaphoreGetCount
+ * Memory Pool:
+ * - using osMemoryPool prefix instead of osPool
+ * - replaced osPoolCreate with osMemoryPoolNew
+ * - extended osMemoryPoolAlloc (timeout)
+ * - added: osMemoryPoolGetName
+ * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize
+ * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace
+ * - added: osMemoryPoolDelete
+ * - deprecated: osPoolCAlloc
+ * Message Queue:
+ * - extended: fixed size message instead of a single 32-bit value
+ * - using osMessageQueue prefix instead of osMessage
+ * - replaced osMessageCreate with osMessageQueueNew
+ * - updated: osMessageQueuePut, osMessageQueueGet
+ * - added: osMessageQueueGetName
+ * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
+ * - added: osMessageQueueGetCount, osMessageQueueGetSpace
+ * - added: osMessageQueueReset, osMessageQueueDelete
+ * Mail Queue:
+ * - deprecated (superseded by extended Message Queue functionality)
+ * Version 2.1.0
+ * Support for critical and uncritical sections (nesting safe):
+ * - updated: osKernelLock, osKernelUnlock
+ * - added: osKernelRestoreLock
+ * Updated Thread and Event Flags:
+ * - changed flags parameter and return type from int32_t to uint32_t
+ *---------------------------------------------------------------------------*/
+
+#ifndef CMSIS_OS_H_
+#define CMSIS_OS_H_
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define RTOS_ID_n ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR))
+#define RTOS_ID_s ("FreeRTOS " tskKERNEL_VERSION_NUMBER)
+
+#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0])
+
+#define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0])
+
+#define osKernelSystemId RTOS_ID_s ///< RTOS identification string
+
+#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available
+#define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
+#define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available
+#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
+#define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available
+
+#if defined(__CC_ARM)
+#define os_InRegs __value_in_regs
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define os_InRegs __attribute__((value_in_regs))
+#else
+#define os_InRegs
+#endif
+
+#include "cmsis_os2.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumerations, structures, defines ====
+
+/// Priority values.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+ osPriorityIdle = -3, ///< Priority: idle (lowest)
+ osPriorityLow = -2, ///< Priority: low
+ osPriorityBelowNormal = -1, ///< Priority: below normal
+ osPriorityNormal = 0, ///< Priority: normal (default)
+ osPriorityAboveNormal = +1, ///< Priority: above normal
+ osPriorityHigh = +2, ///< Priority: high
+ osPriorityRealtime = +3, ///< Priority: realtime (highest)
+ osPriorityError = 0x84, ///< System cannot determine priority or illegal priority.
+ osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osPriority;
+#else
+#define osPriority osPriority_t
+#endif
+
+/// Entry point of a thread.
+typedef void (*os_pthread) (void const *argument);
+
+/// Entry point of a timer call back function.
+typedef void (*os_ptimer) (void const *argument);
+
+/// Timer type.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+ osTimerOnce = 0, ///< One-shot timer.
+ osTimerPeriodic = 1 ///< Repeating timer.
+} os_timer_type;
+#else
+#define os_timer_type osTimerType_t
+#endif
+
+/// Timeout value.
+#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
+
+/// Status code values returned by CMSIS-RTOS functions.
+#if (osCMSIS < 0x20000U)
+typedef enum {
+ osOK = 0, ///< Function completed; no error or event occurred.
+ osEventSignal = 0x08, ///< Function completed; signal event occurred.
+ osEventMessage = 0x10, ///< Function completed; message event occurred.
+ osEventMail = 0x20, ///< Function completed; mail event occurred.
+ osEventTimeout = 0x40, ///< Function completed; timeout occurred.
+ osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.
+ osErrorResource = 0x81, ///< Resource not available: a specified resource was not available.
+ osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period.
+ osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+ osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object.
+ osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority.
+ osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+ osErrorValue = 0x86, ///< Value of a parameter is out of range.
+ osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits.
+ osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osStatus;
+#else
+typedef int32_t osStatus;
+#define osEventSignal (0x08)
+#define osEventMessage (0x10)
+#define osEventMail (0x20)
+#define osEventTimeout (0x40)
+#define osErrorOS osError
+#define osErrorTimeoutResource osErrorTimeout
+#define osErrorISRRecursive (-126)
+#define osErrorValue (-127)
+#define osErrorPriority (-128)
+#endif
+
+
+// >>> the following data type definitions may be adapted towards a specific RTOS
+
+/// Thread ID identifies the thread.
+#if (osCMSIS < 0x20000U)
+typedef void *osThreadId;
+#else
+#define osThreadId osThreadId_t
+#endif
+
+/// Timer ID identifies the timer.
+#if (osCMSIS < 0x20000U)
+typedef void *osTimerId;
+#else
+#define osTimerId osTimerId_t
+#endif
+
+/// Mutex ID identifies the mutex.
+#if (osCMSIS < 0x20000U)
+typedef void *osMutexId;
+#else
+#define osMutexId osMutexId_t
+#endif
+
+/// Semaphore ID identifies the semaphore.
+#if (osCMSIS < 0x20000U)
+typedef void *osSemaphoreId;
+#else
+#define osSemaphoreId osSemaphoreId_t
+#endif
+
+/// Pool ID identifies the memory pool.
+typedef void *osPoolId;
+
+/// Message ID identifies the message queue.
+typedef void *osMessageQId;
+
+/// Mail ID identifies the mail queue.
+typedef void *osMailQId;
+
+
+/// Thread Definition structure contains startup information of a thread.
+#if (osCMSIS < 0x20000U)
+typedef struct os_thread_def {
+ os_pthread pthread; ///< start address of thread function
+ osPriority tpriority; ///< initial thread priority
+ uint32_t instances; ///< maximum number of instances of that thread function
+ uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+#else
+typedef struct os_thread_def {
+ os_pthread pthread; ///< start address of thread function
+ osThreadAttr_t attr; ///< thread attributes
+} osThreadDef_t;
+#endif
+
+/// Timer Definition structure contains timer parameters.
+#if (osCMSIS < 0x20000U)
+typedef struct os_timer_def {
+ os_ptimer ptimer; ///< start address of a timer function
+} osTimerDef_t;
+#else
+typedef struct os_timer_def {
+ os_ptimer ptimer; ///< start address of a timer function
+ osTimerAttr_t attr; ///< timer attributes
+} osTimerDef_t;
+#endif
+
+/// Mutex Definition structure contains setup information for a mutex.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mutex_def {
+ uint32_t dummy; ///< dummy value
+} osMutexDef_t;
+#else
+#define osMutexDef_t osMutexAttr_t
+#endif
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+#if (osCMSIS < 0x20000U)
+typedef struct os_semaphore_def {
+ uint32_t dummy; ///< dummy value
+} osSemaphoreDef_t;
+#else
+#define osSemaphoreDef_t osSemaphoreAttr_t
+#endif
+
+/// Definition structure for memory block allocation.
+#if (osCMSIS < 0x20000U)
+typedef struct os_pool_def {
+ uint32_t pool_sz; ///< number of items (elements) in the pool
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< pointer to memory for pool
+} osPoolDef_t;
+#else
+typedef struct os_pool_def {
+ uint32_t pool_sz; ///< number of items (elements) in the pool
+ uint32_t item_sz; ///< size of an item
+ osMemoryPoolAttr_t attr; ///< memory pool attributes
+} osPoolDef_t;
+#endif
+
+/// Definition structure for message queue.
+#if (osCMSIS < 0x20000U)
+typedef struct os_messageQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ void *pool; ///< memory array for messages
+} osMessageQDef_t;
+#else
+typedef struct os_messageQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ osMessageQueueAttr_t attr; ///< message queue attributes
+} osMessageQDef_t;
+#endif
+
+/// Definition structure for mail queue.
+#if (osCMSIS < 0x20000U)
+typedef struct os_mailQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< memory array for mail
+} osMailQDef_t;
+#else
+typedef struct os_mailQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ uint32_t item_sz; ///< size of an item
+ void *mail; ///< pointer to mail
+ osMemoryPoolAttr_t mp_attr; ///< memory pool attributes
+ osMessageQueueAttr_t mq_attr; ///< message queue attributes
+} osMailQDef_t;
+#endif
+
+
+/// Event structure contains detailed information about an event.
+typedef struct {
+ osStatus status; ///< status code: event or error information
+ union {
+ uint32_t v; ///< message as 32-bit value
+ void *p; ///< message or mail as void pointer
+ int32_t signals; ///< signal flags
+ } value; ///< event value
+ union {
+ osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
+ osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
+ } def; ///< event definition
+} osEvent;
+
+
+// ==== Kernel Management Functions ====
+
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelInitialize (void);
+#endif
+
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osKernelStart (void);
+#endif
+
+/// Check if the RTOS kernel is already started.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+#if (osCMSIS < 0x20000U)
+int32_t osKernelRunning(void);
+#endif
+
+#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
+
+/// Get the RTOS kernel system timer counter.
+/// \return RTOS kernel system timer as 32-bit value
+#if (osCMSIS < 0x20000U)
+uint32_t osKernelSysTick (void);
+#else
+#define osKernelSysTick osKernelGetSysTimerCount
+#endif
+
+/// The RTOS kernel system timer frequency in Hz.
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickFrequency 100000000
+#endif
+
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param microsec time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+#if (osCMSIS < 0x20000U)
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+#else
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000)
+#endif
+
+#endif // System Timer available
+
+
+// ==== Thread Management Functions ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param name name of the thread function.
+/// \param priority initial priority of the thread function.
+/// \param instances number of possible thread instances.
+/// \param stacksz stack size (in bytes) requirements for the thread function.
+#if defined (osObjectsExternal) // object is external
+#define osThreadDef(name, priority, instances, stacksz) \
+extern const osThreadDef_t os_thread_def_##name
+#else // define the object
+#define osThreadDef(name, priority, instances, stacksz) \
+static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \
+static StaticTask_t os_thread_cb_##name; \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), \
+ { NULL, osThreadDetached, \
+ (instances == 1) ? (&os_thread_cb_##name) : NULL,\
+ (instances == 1) ? sizeof(StaticTask_t) : 0U, \
+ ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \
+ 8*((stacksz+7)/8), \
+ (priority), 0U, 0U } }
+#endif
+
+/// Access a Thread definition.
+/// \param name name of the thread definition object.
+#define osThread(name) \
+&os_thread_def_##name
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in] thread_def thread definition referenced with \ref osThread.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+#if (osCMSIS < 0x20000U)
+osThreadId osThreadGetId (void);
+#endif
+
+/// Change priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] priority new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+#endif
+
+/// Get current priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+#if (osCMSIS < 0x20000U)
+osPriority osThreadGetPriority (osThreadId thread_id);
+#endif
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadYield (void);
+#endif
+
+/// Terminate execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osThreadTerminate (osThreadId thread_id);
+#endif
+
+
+// ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flag information or error code.
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
+
+
+// ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osDelay (uint32_t millisec);
+#endif
+
+#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+os_InRegs osEvent osWait (uint32_t millisec);
+
+#endif // Generic Wait available
+
+
+// ==== Timer Management Functions ====
+
+/// Define a Timer object.
+/// \param name name of the timer object.
+/// \param function name of the timer call back function.
+#if defined (osObjectsExternal) // object is external
+#define osTimerDef(name, function) \
+extern const osTimerDef_t os_timer_def_##name
+#else // define the object
+#define osTimerDef(name, function) \
+static StaticTimer_t os_timer_cb_##name; \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } }
+#endif
+
+/// Access a Timer definition.
+/// \param name name of the timer object.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create and Initialize a timer.
+/// \param[in] timer_def timer object referenced with \ref osTimer.
+/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in] argument argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+#endif
+
+/// Stop a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerStop (osTimerId timer_id);
+#endif
+
+/// Delete a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osTimerDelete (osTimerId timer_id);
+#endif
+
+
+// ==== Mutex Management Functions ====
+
+/// Define a Mutex.
+/// \param name name of the mutex object.
+#if defined (osObjectsExternal) // object is external
+#define osMutexDef(name) \
+extern const osMutexDef_t os_mutex_def_##name
+#else // define the object
+#define osMutexDef(name) \
+static StaticSemaphore_t os_mutex_cb_##name; \
+const osMutexDef_t os_mutex_def_##name = \
+{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) }
+#endif
+
+/// Access a Mutex definition.
+/// \param name name of the mutex object.
+#define osMutex(name) \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object.
+/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+#else
+#define osMutexWait osMutexAcquire
+#endif
+
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexRelease (osMutexId mutex_id);
+#endif
+
+/// Delete a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osMutexDelete (osMutexId mutex_id);
+#endif
+
+
+// ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available
+
+/// Define a Semaphore object.
+/// \param name name of the semaphore object.
+#if defined (osObjectsExternal) // object is external
+#define osSemaphoreDef(name) \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else // define the object
+#define osSemaphoreDef(name) \
+static StaticSemaphore_t os_semaphore_cb_##name; \
+const osSemaphoreDef_t os_semaphore_def_##name = \
+{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) }
+#endif
+
+/// Access a Semaphore definition.
+/// \param name name of the semaphore object.
+#define osSemaphore(name) \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object.
+/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in] count maximum and initial number of available tokens.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+#endif
+
+/// Delete a Semaphore object.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+#if (osCMSIS < 0x20000U)
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+#endif
+
+#endif // Semaphore available
+
+
+// ==== Memory Pool Management Functions ====
+
+#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available
+
+/// \brief Define a Memory Pool.
+/// \param name name of the memory pool.
+/// \param no maximum number of blocks (objects) in the memory pool.
+/// \param type data type of a single block (object).
+#if defined (osObjectsExternal) // object is external
+#define osPoolDef(name, no, type) \
+extern const osPoolDef_t os_pool_def_##name
+#else // define the object
+#define osPoolDef(name, no, type) \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), {NULL} }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param name name of the memory pool
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a Memory Pool object.
+/// \param[in] pool_def memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a Memory Pool.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a Memory Pool and set memory block to zero.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in] block address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif // Memory Pool available
+
+
+// ==== Message Queue Management Functions ====
+
+#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available
+
+/// \brief Create a Message Queue Definition.
+/// \param name name of the queue.
+/// \param queue_sz maximum number of messages in the queue.
+/// \param type data type of a single message element (for debugger).
+#if defined (osObjectsExternal) // object is external
+#define osMessageQDef(name, queue_sz, type) \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else // define the object
+#define osMessageQDef(name, queue_sz, type) \
+static StaticQueue_t os_mq_cb_##name; \
+static uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), \
+ { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \
+ (&os_mq_data_##name), sizeof(os_mq_data_##name) } }
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param name name of the queue
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue object.
+/// \param[in] queue_def message queue definition referenced with \ref osMessageQ.
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] info message information.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+#endif // Message Queue available
+
+
+// ==== Mail Queue Management Functions ====
+
+#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available
+
+/// \brief Create a Mail Queue Definition.
+/// \param name name of the queue.
+/// \param queue_sz maximum number of mails in the queue.
+/// \param type data type of a single mail element.
+#if defined (osObjectsExternal) // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else // define the object
+#define osMailQDef(name, queue_sz, type) \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof(type), NULL }
+#endif
+
+/// \brief Access a Mail Queue Definition.
+/// \param name name of the queue
+#define osMailQ(name) \
+&os_mailQ_def_##name
+
+/// Create and Initialize a Mail Queue object.
+/// \param[in] queue_def mail queue definition referenced with \ref osMailQ.
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block for mail from a mail memory pool.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a Mail into a Queue.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail pointer to memory with mail to put into a queue.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailPut (osMailQId queue_id, const void *mail);
+
+/// Get a Mail from a Queue or timeout if Queue is empty.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+
+/// Free a memory block by returning it to a mail memory pool.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+
+#endif // Mail Queue available
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // CMSIS_OS_H_
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c
new file mode 100644
index 0000000..26f5fb1
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c
@@ -0,0 +1,1924 @@
+/* --------------------------------------------------------------------------
+ * Portions Copyright © 2019 STMicroelectronics International N.V. All rights reserved.
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name: cmsis_os2.c
+ * Purpose: CMSIS RTOS2 wrapper for FreeRTOS
+ *
+ *---------------------------------------------------------------------------*/
+
+#include <string.h>
+
+#include "cmsis_os2.h" // ::CMSIS:RTOS2
+#include "cmsis_compiler.h"
+
+#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core
+#include "task.h" // ARM.FreeRTOS::RTOS:Core
+#include "event_groups.h" // ARM.FreeRTOS::RTOS:Event Groups
+#include "semphr.h" // ARM.FreeRTOS::RTOS:Core
+
+/*---------------------------------------------------------------------------*/
+#ifndef __ARM_ARCH_6M__
+ #define __ARM_ARCH_6M__ 0
+#endif
+#ifndef __ARM_ARCH_7M__
+ #define __ARM_ARCH_7M__ 0
+#endif
+#ifndef __ARM_ARCH_7EM__
+ #define __ARM_ARCH_7EM__ 0
+#endif
+#ifndef __ARM_ARCH_8M_MAIN__
+ #define __ARM_ARCH_8M_MAIN__ 0
+#endif
+#ifndef __ARM_ARCH_7A__
+ #define __ARM_ARCH_7A__ 0
+#endif
+
+#if ((__ARM_ARCH_7M__ == 1U) || \
+ (__ARM_ARCH_7EM__ == 1U) || \
+ (__ARM_ARCH_8M_MAIN__ == 1U))
+#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))
+#elif (__ARM_ARCH_6M__ == 1U)
+#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U)
+#elif (__ARM_ARCH_7A__ == 1U)
+/* CPSR mask bits */
+#define CPSR_MASKBIT_I 0x80U
+
+#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U)
+#else
+#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U)
+#endif
+
+#if (__ARM_ARCH_7A__ == 1U)
+/* CPSR mode bitmasks */
+#define CPSR_MODE_USER 0x10U
+#define CPSR_MODE_SYSTEM 0x1FU
+
+#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM))
+#else
+#define IS_IRQ_MODE() (__get_IPSR() != 0U)
+#endif
+
+#define IS_IRQ() (IS_IRQ_MODE() || (IS_IRQ_MASKED() && (KernelState == osKernelRunning)))
+
+/* Limits */
+#define MAX_BITS_TASK_NOTIFY 31U
+#define MAX_BITS_EVENT_GROUPS 24U
+
+#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY) - 1U))
+#define EVENT_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U))
+
+/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */
+#define KERNEL_VERSION (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \
+ ((uint32_t)tskKERNEL_VERSION_MINOR * 10000UL) | \
+ ((uint32_t)tskKERNEL_VERSION_BUILD * 1UL))
+
+#define KERNEL_ID ("FreeRTOS " tskKERNEL_VERSION_NUMBER)
+
+/* Timer callback information structure definition */
+typedef struct {
+ osTimerFunc_t func;
+ void *arg;
+} TimerCallback_t;
+
+/* Kernel initialization state */
+static osKernelState_t KernelState = osKernelInactive;
+
+/*
+ Heap region definition used by heap_5 variant
+
+ Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if
+ heap regions are already defined and vPortDefineHeapRegions is called in application.
+
+ Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using
+ definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS
+ is possible by defining it globally or in FreeRTOSConfig.h.
+*/
+#if defined(USE_FREERTOS_HEAP_5)
+#if (configAPPLICATION_ALLOCATED_HEAP == 0)
+ /*
+ FreeRTOS heap is not defined by the application.
+ Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h)
+ is provided by default. Define configHEAP_5_REGIONS to provide custom
+ HeapRegion_t array.
+ */
+ #define HEAP_5_REGION_SETUP 1
+
+ #ifndef configHEAP_5_REGIONS
+ #define configHEAP_5_REGIONS xHeapRegions
+
+ static uint8_t ucHeap[configTOTAL_HEAP_SIZE];
+
+ static HeapRegion_t xHeapRegions[] = {
+ { ucHeap, configTOTAL_HEAP_SIZE },
+ { NULL, 0 }
+ };
+ #else
+ /* Global definition is provided to override default heap array */
+ extern HeapRegion_t configHEAP_5_REGIONS[];
+ #endif
+#else
+ /*
+ The application already defined the array used for the FreeRTOS heap and
+ called vPortDefineHeapRegions to initialize heap.
+ */
+ #define HEAP_5_REGION_SETUP 0
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+#endif /* USE_FREERTOS_HEAP_5 */
+
+#if defined(SysTick)
+#undef SysTick_Handler
+
+/* CMSIS SysTick interrupt handler prototype */
+extern void SysTick_Handler (void);
+/* FreeRTOS tick timer interrupt handler prototype */
+extern void xPortSysTickHandler (void);
+
+/*
+ SysTick handler implementation that also clears overflow flag.
+*/
+void SysTick_Handler (void) {
+ /* Clear overflow flag */
+ SysTick->CTRL;
+
+ if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
+ /* Call tick handler */
+ xPortSysTickHandler();
+ }
+}
+#endif /* SysTick */
+
+/*
+ Setup SVC to reset value.
+*/
+__STATIC_INLINE void SVC_Setup (void) {
+#if (__ARM_ARCH_7A__ == 0U)
+ /* Service Call interrupt might be configured before kernel start */
+ /* and when its priority is lower or equal to BASEPRI, svc intruction */
+ /* causes a Hard Fault. */
+
+ /*
+ * the call below has introduced a regression compared to revious release
+ * The issue was logged under:https://github.com/ARM-software/CMSIS-FreeRTOS/issues/35
+ * until it is correctly fixed, the code below is commented
+ */
+/* NVIC_SetPriority (SVCall_IRQn, 0U); */
+#endif
+}
+
+/*---------------------------------------------------------------------------*/
+
+osStatus_t osKernelInitialize (void) {
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else {
+ if (KernelState == osKernelInactive) {
+ #if defined(USE_FREERTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
+ vPortDefineHeapRegions (configHEAP_5_REGIONS);
+ #endif
+ KernelState = osKernelReady;
+ stat = osOK;
+ } else {
+ stat = osError;
+ }
+ }
+
+ return (stat);
+}
+
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
+
+ if (version != NULL) {
+ /* Version encoding is major.minor.rev: mmnnnrrrr dec */
+ version->api = KERNEL_VERSION;
+ version->kernel = KERNEL_VERSION;
+ }
+
+ if ((id_buf != NULL) && (id_size != 0U)) {
+ if (id_size > sizeof(KERNEL_ID)) {
+ id_size = sizeof(KERNEL_ID);
+ }
+ memcpy(id_buf, KERNEL_ID, id_size);
+ }
+
+ return (osOK);
+}
+
+osKernelState_t osKernelGetState (void) {
+ osKernelState_t state;
+
+ switch (xTaskGetSchedulerState()) {
+ case taskSCHEDULER_RUNNING:
+ state = osKernelRunning;
+ break;
+
+ case taskSCHEDULER_SUSPENDED:
+ state = osKernelLocked;
+ break;
+
+ case taskSCHEDULER_NOT_STARTED:
+ default:
+ if (KernelState == osKernelReady) {
+ state = osKernelReady;
+ } else {
+ state = osKernelInactive;
+ }
+ break;
+ }
+
+ return (state);
+}
+
+osStatus_t osKernelStart (void) {
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else {
+ if (KernelState == osKernelReady) {
+ /* Ensure SVC priority is at the reset value */
+ SVC_Setup();
+ /* Change state to enable IRQ masking check */
+ KernelState = osKernelRunning;
+ /* Start the kernel scheduler */
+ vTaskStartScheduler();
+ stat = osOK;
+ } else {
+ stat = osError;
+ }
+ }
+
+ return (stat);
+}
+
+int32_t osKernelLock (void) {
+ int32_t lock;
+
+ if (IS_IRQ()) {
+ lock = (int32_t)osErrorISR;
+ }
+ else {
+ switch (xTaskGetSchedulerState()) {
+ case taskSCHEDULER_SUSPENDED:
+ lock = 1;
+ break;
+
+ case taskSCHEDULER_RUNNING:
+ vTaskSuspendAll();
+ lock = 0;
+ break;
+
+ case taskSCHEDULER_NOT_STARTED:
+ default:
+ lock = (int32_t)osError;
+ break;
+ }
+ }
+
+ return (lock);
+}
+
+int32_t osKernelUnlock (void) {
+ int32_t lock;
+
+ if (IS_IRQ()) {
+ lock = (int32_t)osErrorISR;
+ }
+ else {
+ switch (xTaskGetSchedulerState()) {
+ case taskSCHEDULER_SUSPENDED:
+ lock = 1;
+
+ if (xTaskResumeAll() != pdTRUE) {
+ if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) {
+ lock = (int32_t)osError;
+ }
+ }
+ break;
+
+ case taskSCHEDULER_RUNNING:
+ lock = 0;
+ break;
+
+ case taskSCHEDULER_NOT_STARTED:
+ default:
+ lock = (int32_t)osError;
+ break;
+ }
+ }
+
+ return (lock);
+}
+
+int32_t osKernelRestoreLock (int32_t lock) {
+
+ if (IS_IRQ()) {
+ lock = (int32_t)osErrorISR;
+ }
+ else {
+ switch (xTaskGetSchedulerState()) {
+ case taskSCHEDULER_SUSPENDED:
+ case taskSCHEDULER_RUNNING:
+ if (lock == 1) {
+ vTaskSuspendAll();
+ }
+ else {
+ if (lock != 0) {
+ lock = (int32_t)osError;
+ }
+ else {
+ if (xTaskResumeAll() != pdTRUE) {
+ if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) {
+ lock = (int32_t)osError;
+ }
+ }
+ }
+ }
+ break;
+
+ case taskSCHEDULER_NOT_STARTED:
+ default:
+ lock = (int32_t)osError;
+ break;
+ }
+ }
+
+ return (lock);
+}
+
+uint32_t osKernelGetTickCount (void) {
+ TickType_t ticks;
+
+ if (IS_IRQ()) {
+ ticks = xTaskGetTickCountFromISR();
+ } else {
+ ticks = xTaskGetTickCount();
+ }
+
+ return (ticks);
+}
+
+uint32_t osKernelGetTickFreq (void) {
+ return (configTICK_RATE_HZ);
+}
+
+uint32_t osKernelGetSysTimerCount (void) {
+ uint32_t irqmask = IS_IRQ_MASKED();
+ TickType_t ticks;
+ uint32_t val;
+
+ __disable_irq();
+
+ ticks = xTaskGetTickCount();
+
+ val = ticks * ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+ if (irqmask == 0U) {
+ __enable_irq();
+ }
+
+ return (val);
+}
+
+uint32_t osKernelGetSysTimerFreq (void) {
+ return (configCPU_CLOCK_HZ);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
+ const char *name;
+ uint32_t stack;
+ TaskHandle_t hTask;
+ UBaseType_t prio;
+ int32_t mem;
+
+ hTask = NULL;
+
+ if (!IS_IRQ() && (func != NULL)) {
+ stack = configMINIMAL_STACK_SIZE;
+ prio = (UBaseType_t)osPriorityNormal;
+
+ name = NULL;
+ mem = -1;
+
+ if (attr != NULL) {
+ if (attr->name != NULL) {
+ name = attr->name;
+ }
+ if (attr->priority != osPriorityNone) {
+ prio = (UBaseType_t)attr->priority;
+ }
+
+ if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
+ return (NULL);
+ }
+
+ if (attr->stack_size > 0U) {
+ /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */
+ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
+ stack = attr->stack_size / sizeof(StackType_t);
+ }
+
+ if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
+ (attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
+ mem = 1;
+ }
+ else {
+ if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
+ mem = 0;
+ }
+ }
+ }
+ else {
+ mem = 0;
+ }
+
+ if (mem == 1) {
+ hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
+ (StaticTask_t *)attr->cb_mem);
+ }
+ else {
+ if (mem == 0) {
+ if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
+ hTask = NULL;
+ }
+ }
+ }
+ }
+
+ return ((osThreadId_t)hTask);
+}
+
+const char *osThreadGetName (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ const char *name;
+
+ if (IS_IRQ() || (hTask == NULL)) {
+ name = NULL;
+ } else {
+ name = pcTaskGetName (hTask);
+ }
+
+ return (name);
+}
+
+osThreadId_t osThreadGetId (void) {
+ osThreadId_t id;
+
+ id = (osThreadId_t)xTaskGetCurrentTaskHandle();
+
+ return (id);
+}
+
+osThreadState_t osThreadGetState (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ osThreadState_t state;
+
+ if (IS_IRQ() || (hTask == NULL)) {
+ state = osThreadError;
+ }
+ else {
+ switch (eTaskGetState (hTask)) {
+ case eRunning: state = osThreadRunning; break;
+ case eReady: state = osThreadReady; break;
+ case eBlocked:
+ case eSuspended: state = osThreadBlocked; break;
+ case eDeleted: state = osThreadTerminated; break;
+ case eInvalid:
+ default: state = osThreadError; break;
+ }
+ }
+
+ return (state);
+}
+
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ uint32_t sz;
+
+ if (IS_IRQ() || (hTask == NULL)) {
+ sz = 0U;
+ } else {
+ sz = (uint32_t)uxTaskGetStackHighWaterMark (hTask);
+ }
+
+ return (sz);
+}
+
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) {
+ stat = osErrorParameter;
+ }
+ else {
+ stat = osOK;
+ vTaskPrioritySet (hTask, (UBaseType_t)priority);
+ }
+
+ return (stat);
+}
+
+osPriority_t osThreadGetPriority (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ osPriority_t prio;
+
+ if (IS_IRQ() || (hTask == NULL)) {
+ prio = osPriorityError;
+ } else {
+ prio = (osPriority_t)uxTaskPriorityGet (hTask);
+ }
+
+ return (prio);
+}
+
+osStatus_t osThreadYield (void) {
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ } else {
+ stat = osOK;
+ taskYIELD();
+ }
+
+ return (stat);
+}
+
+osStatus_t osThreadSuspend (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hTask == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ stat = osOK;
+ vTaskSuspend (hTask);
+ }
+
+ return (stat);
+}
+
+osStatus_t osThreadResume (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hTask == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ stat = osOK;
+ vTaskResume (hTask);
+ }
+
+ return (stat);
+}
+
+__NO_RETURN void osThreadExit (void) {
+#ifndef USE_FreeRTOS_HEAP_1
+ vTaskDelete (NULL);
+#endif
+ for (;;);
+}
+
+osStatus_t osThreadTerminate (osThreadId_t thread_id) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ osStatus_t stat;
+#ifndef USE_FreeRTOS_HEAP_1
+ eTaskState tstate;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hTask == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ tstate = eTaskGetState (hTask);
+
+ if (tstate != eDeleted) {
+ stat = osOK;
+ vTaskDelete (hTask);
+ } else {
+ stat = osErrorResource;
+ }
+ }
+#else
+ stat = osError;
+#endif
+
+ return (stat);
+}
+
+uint32_t osThreadGetCount (void) {
+ uint32_t count;
+
+ if (IS_IRQ()) {
+ count = 0U;
+ } else {
+ count = uxTaskGetNumberOfTasks();
+ }
+
+ return (count);
+}
+
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
+ uint32_t i, count;
+ TaskStatus_t *task;
+
+ if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) {
+ count = 0U;
+ } else {
+ vTaskSuspendAll();
+
+ count = uxTaskGetNumberOfTasks();
+ task = pvPortMalloc (count * sizeof(TaskStatus_t));
+
+ if (task != NULL) {
+ count = uxTaskGetSystemState (task, count, NULL);
+
+ for (i = 0U; (i < count) && (i < array_items); i++) {
+ thread_array[i] = (osThreadId_t)task[i].xHandle;
+ }
+ count = i;
+ }
+ (void)xTaskResumeAll();
+
+ vPortFree (task);
+ }
+
+ return (count);
+}
+
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
+ TaskHandle_t hTask = (TaskHandle_t)thread_id;
+ uint32_t rflags;
+ BaseType_t yield;
+
+ if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) {
+ rflags = (uint32_t)osErrorParameter;
+ }
+ else {
+ rflags = (uint32_t)osError;
+
+ if (IS_IRQ()) {
+ yield = pdFALSE;
+
+ (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield);
+ (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL);
+
+ portYIELD_FROM_ISR (yield);
+ }
+ else {
+ (void)xTaskNotify (hTask, flags, eSetBits);
+ (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags);
+ }
+ }
+ /* Return flags after setting */
+ return (rflags);
+}
+
+uint32_t osThreadFlagsClear (uint32_t flags) {
+ TaskHandle_t hTask;
+ uint32_t rflags, cflags;
+
+ if (IS_IRQ()) {
+ rflags = (uint32_t)osErrorISR;
+ }
+ else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {
+ rflags = (uint32_t)osErrorParameter;
+ }
+ else {
+ hTask = xTaskGetCurrentTaskHandle();
+
+ if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) {
+ rflags = cflags;
+ cflags &= ~flags;
+
+ if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) {
+ rflags = (uint32_t)osError;
+ }
+ }
+ else {
+ rflags = (uint32_t)osError;
+ }
+ }
+
+ /* Return flags before clearing */
+ return (rflags);
+}
+
+uint32_t osThreadFlagsGet (void) {
+ TaskHandle_t hTask;
+ uint32_t rflags;
+
+ if (IS_IRQ()) {
+ rflags = (uint32_t)osErrorISR;
+ }
+ else {
+ hTask = xTaskGetCurrentTaskHandle();
+
+ if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) {
+ rflags = (uint32_t)osError;
+ }
+ }
+
+ return (rflags);
+}
+
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
+ uint32_t rflags, nval;
+ uint32_t clear;
+ TickType_t t0, td, tout;
+ BaseType_t rval;
+
+ if (IS_IRQ()) {
+ rflags = (uint32_t)osErrorISR;
+ }
+ else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {
+ rflags = (uint32_t)osErrorParameter;
+ }
+ else {
+ if ((options & osFlagsNoClear) == osFlagsNoClear) {
+ clear = 0U;
+ } else {
+ clear = flags;
+ }
+
+ rflags = 0U;
+ tout = timeout;
+
+ t0 = xTaskGetTickCount();
+ do {
+ rval = xTaskNotifyWait (0, clear, &nval, tout);
+
+ if (rval == pdPASS) {
+ rflags &= flags;
+ rflags |= nval;
+
+ if ((options & osFlagsWaitAll) == osFlagsWaitAll) {
+ if ((flags & rflags) == flags) {
+ break;
+ } else {
+ if (timeout == 0U) {
+ rflags = (uint32_t)osErrorResource;
+ break;
+ }
+ }
+ }
+ else {
+ if ((flags & rflags) != 0) {
+ break;
+ } else {
+ if (timeout == 0U) {
+ rflags = (uint32_t)osErrorResource;
+ break;
+ }
+ }
+ }
+
+ /* Update timeout */
+ td = xTaskGetTickCount() - t0;
+
+ if (td > tout) {
+ tout = 0;
+ } else {
+ tout -= td;
+ }
+ }
+ else {
+ if (timeout == 0) {
+ rflags = (uint32_t)osErrorResource;
+ } else {
+ rflags = (uint32_t)osErrorTimeout;
+ }
+ }
+ }
+ while (rval != pdFAIL);
+ }
+
+ /* Return flags before clearing */
+ return (rflags);
+}
+
+osStatus_t osDelay (uint32_t ticks) {
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else {
+ stat = osOK;
+
+ if (ticks != 0U) {
+ vTaskDelay(ticks);
+ }
+ }
+
+ return (stat);
+}
+
+osStatus_t osDelayUntil (uint32_t ticks) {
+ TickType_t tcnt, delay;
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else {
+ stat = osOK;
+ tcnt = xTaskGetTickCount();
+
+ /* Determine remaining number of ticks to delay */
+ delay = (TickType_t)ticks - tcnt;
+
+ /* Check if target tick has not expired */
+ if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) {
+ vTaskDelayUntil (&tcnt, delay);
+ }
+ else
+ {
+ /* No delay or already expired */
+ stat = osErrorParameter;
+ }
+ }
+
+ return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+
+static void TimerCallback (TimerHandle_t hTimer) {
+ TimerCallback_t *callb;
+
+ callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);
+
+ if (callb != NULL) {
+ callb->func (callb->arg);
+ }
+}
+
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
+ const char *name;
+ TimerHandle_t hTimer;
+ TimerCallback_t *callb;
+ UBaseType_t reload;
+ int32_t mem;
+
+ hTimer = NULL;
+
+ if (!IS_IRQ() && (func != NULL)) {
+ /* Allocate memory to store callback function and argument */
+ callb = pvPortMalloc (sizeof(TimerCallback_t));
+
+ if (callb != NULL) {
+ callb->func = func;
+ callb->arg = argument;
+
+ if (type == osTimerOnce) {
+ reload = pdFALSE;
+ } else {
+ reload = pdTRUE;
+ }
+
+ mem = -1;
+ name = NULL;
+
+ if (attr != NULL) {
+ if (attr->name != NULL) {
+ name = attr->name;
+ }
+
+ if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) {
+ mem = 1;
+ }
+ else {
+ if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+ mem = 0;
+ }
+ }
+ }
+ else {
+ mem = 0;
+ }
+
+ if (mem == 1) {
+ hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem);
+ }
+ else {
+ if (mem == 0) {
+ hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback);
+ }
+ }
+ }
+ }
+
+ return ((osTimerId_t)hTimer);
+}
+
+const char *osTimerGetName (osTimerId_t timer_id) {
+ TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+ const char *p;
+
+ if (IS_IRQ() || (hTimer == NULL)) {
+ p = NULL;
+ } else {
+ p = pcTimerGetName (hTimer);
+ }
+
+ return (p);
+}
+
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
+ TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hTimer == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) {
+ stat = osOK;
+ } else {
+ stat = osErrorResource;
+ }
+ }
+
+ return (stat);
+}
+
+osStatus_t osTimerStop (osTimerId_t timer_id) {
+ TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hTimer == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ if (xTimerIsTimerActive (hTimer) == pdFALSE) {
+ stat = osErrorResource;
+ }
+ else {
+ if (xTimerStop (hTimer, 0) == pdPASS) {
+ stat = osOK;
+ } else {
+ stat = osError;
+ }
+ }
+ }
+
+ return (stat);
+}
+
+uint32_t osTimerIsRunning (osTimerId_t timer_id) {
+ TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+ uint32_t running;
+
+ if (IS_IRQ() || (hTimer == NULL)) {
+ running = 0U;
+ } else {
+ running = (uint32_t)xTimerIsTimerActive (hTimer);
+ }
+
+ return (running);
+}
+
+osStatus_t osTimerDelete (osTimerId_t timer_id) {
+ TimerHandle_t hTimer = (TimerHandle_t)timer_id;
+ osStatus_t stat;
+#ifndef USE_FreeRTOS_HEAP_1
+ TimerCallback_t *callb;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hTimer == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);
+
+ if (xTimerDelete (hTimer, 0) == pdPASS) {
+ vPortFree (callb);
+ stat = osOK;
+ } else {
+ stat = osErrorResource;
+ }
+ }
+#else
+ stat = osError;
+#endif
+
+ return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {
+ EventGroupHandle_t hEventGroup;
+ int32_t mem;
+
+ hEventGroup = NULL;
+
+ if (!IS_IRQ()) {
+ mem = -1;
+
+ if (attr != NULL) {
+ if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) {
+ mem = 1;
+ }
+ else {
+ if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+ mem = 0;
+ }
+ }
+ }
+ else {
+ mem = 0;
+ }
+
+ if (mem == 1) {
+ hEventGroup = xEventGroupCreateStatic (attr->cb_mem);
+ }
+ else {
+ if (mem == 0) {
+ hEventGroup = xEventGroupCreate();
+ }
+ }
+ }
+
+ return ((osEventFlagsId_t)hEventGroup);
+}
+
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
+ EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+ uint32_t rflags;
+ BaseType_t yield;
+
+ if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {
+ rflags = (uint32_t)osErrorParameter;
+ }
+ else if (IS_IRQ()) {
+ yield = pdFALSE;
+
+ if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) {
+ rflags = (uint32_t)osErrorResource;
+ } else {
+ rflags = flags;
+ portYIELD_FROM_ISR (yield);
+ }
+ }
+ else {
+ rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags);
+ }
+
+ return (rflags);
+}
+
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
+ EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+ uint32_t rflags;
+
+ if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {
+ rflags = (uint32_t)osErrorParameter;
+ }
+ else if (IS_IRQ()) {
+ rflags = xEventGroupGetBitsFromISR (hEventGroup);
+
+ if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) {
+ rflags = (uint32_t)osErrorResource;
+ }
+ }
+ else {
+ rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags);
+ }
+
+ return (rflags);
+}
+
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {
+ EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+ uint32_t rflags;
+
+ if (ef_id == NULL) {
+ rflags = 0U;
+ }
+ else if (IS_IRQ()) {
+ rflags = xEventGroupGetBitsFromISR (hEventGroup);
+ }
+ else {
+ rflags = xEventGroupGetBits (hEventGroup);
+ }
+
+ return (rflags);
+}
+
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
+ EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+ BaseType_t wait_all;
+ BaseType_t exit_clr;
+ uint32_t rflags;
+
+ if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {
+ rflags = (uint32_t)osErrorParameter;
+ }
+ else if (IS_IRQ()) {
+ rflags = (uint32_t)osErrorISR;
+ }
+ else {
+ if (options & osFlagsWaitAll) {
+ wait_all = pdTRUE;
+ } else {
+ wait_all = pdFAIL;
+ }
+
+ if (options & osFlagsNoClear) {
+ exit_clr = pdFAIL;
+ } else {
+ exit_clr = pdTRUE;
+ }
+
+ rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout);
+
+ if (options & osFlagsWaitAll) {
+ if (flags != rflags) {
+ if (timeout > 0U) {
+ rflags = (uint32_t)osErrorTimeout;
+ } else {
+ rflags = (uint32_t)osErrorResource;
+ }
+ }
+ }
+ else {
+ if ((flags & rflags) == 0U) {
+ if (timeout > 0U) {
+ rflags = (uint32_t)osErrorTimeout;
+ } else {
+ rflags = (uint32_t)osErrorResource;
+ }
+ }
+ }
+ }
+
+ return (rflags);
+}
+
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {
+ EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;
+ osStatus_t stat;
+
+#ifndef USE_FreeRTOS_HEAP_1
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hEventGroup == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ stat = osOK;
+ vEventGroupDelete (hEventGroup);
+ }
+#else
+ stat = osError;
+#endif
+
+ return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
+ SemaphoreHandle_t hMutex;
+ uint32_t type;
+ uint32_t rmtx;
+ int32_t mem;
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ const char *name;
+ #endif
+
+ hMutex = NULL;
+
+ if (!IS_IRQ()) {
+ if (attr != NULL) {
+ type = attr->attr_bits;
+ } else {
+ type = 0U;
+ }
+
+ if ((type & osMutexRecursive) == osMutexRecursive) {
+ rmtx = 1U;
+ } else {
+ rmtx = 0U;
+ }
+
+ if ((type & osMutexRobust) != osMutexRobust) {
+ mem = -1;
+
+ if (attr != NULL) {
+ if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
+ mem = 1;
+ }
+ else {
+ if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+ mem = 0;
+ }
+ }
+ }
+ else {
+ mem = 0;
+ }
+
+ if (mem == 1) {
+ if (rmtx != 0U) {
+ hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);
+ }
+ else {
+ hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);
+ }
+ }
+ else {
+ if (mem == 0) {
+ if (rmtx != 0U) {
+ hMutex = xSemaphoreCreateRecursiveMutex ();
+ } else {
+ hMutex = xSemaphoreCreateMutex ();
+ }
+ }
+ }
+
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ if (hMutex != NULL) {
+ if (attr != NULL) {
+ name = attr->name;
+ } else {
+ name = NULL;
+ }
+ vQueueAddToRegistry (hMutex, name);
+ }
+ #endif
+
+ if ((hMutex != NULL) && (rmtx != 0U)) {
+ hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);
+ }
+ }
+ }
+
+ return ((osMutexId_t)hMutex);
+}
+
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
+ SemaphoreHandle_t hMutex;
+ osStatus_t stat;
+ uint32_t rmtx;
+
+ hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+ rmtx = (uint32_t)mutex_id & 1U;
+
+ stat = osOK;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hMutex == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ if (rmtx != 0U) {
+ if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {
+ if (timeout != 0U) {
+ stat = osErrorTimeout;
+ } else {
+ stat = osErrorResource;
+ }
+ }
+ }
+ else {
+ if (xSemaphoreTake (hMutex, timeout) != pdPASS) {
+ if (timeout != 0U) {
+ stat = osErrorTimeout;
+ } else {
+ stat = osErrorResource;
+ }
+ }
+ }
+ }
+
+ return (stat);
+}
+
+osStatus_t osMutexRelease (osMutexId_t mutex_id) {
+ SemaphoreHandle_t hMutex;
+ osStatus_t stat;
+ uint32_t rmtx;
+
+ hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+ rmtx = (uint32_t)mutex_id & 1U;
+
+ stat = osOK;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hMutex == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ if (rmtx != 0U) {
+ if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {
+ stat = osErrorResource;
+ }
+ }
+ else {
+ if (xSemaphoreGive (hMutex) != pdPASS) {
+ stat = osErrorResource;
+ }
+ }
+ }
+
+ return (stat);
+}
+
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {
+ SemaphoreHandle_t hMutex;
+ osThreadId_t owner;
+
+ hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+ if (IS_IRQ() || (hMutex == NULL)) {
+ owner = NULL;
+ } else {
+ owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex);
+ }
+
+ return (owner);
+}
+
+osStatus_t osMutexDelete (osMutexId_t mutex_id) {
+ osStatus_t stat;
+#ifndef USE_FreeRTOS_HEAP_1
+ SemaphoreHandle_t hMutex;
+
+ hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hMutex == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ vQueueUnregisterQueue (hMutex);
+ #endif
+ stat = osOK;
+ vSemaphoreDelete (hMutex);
+ }
+#else
+ stat = osError;
+#endif
+
+ return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
+ SemaphoreHandle_t hSemaphore;
+ int32_t mem;
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ const char *name;
+ #endif
+
+ hSemaphore = NULL;
+
+ if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) {
+ mem = -1;
+
+ if (attr != NULL) {
+ if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {
+ mem = 1;
+ }
+ else {
+ if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {
+ mem = 0;
+ }
+ }
+ }
+ else {
+ mem = 0;
+ }
+
+ if (mem != -1) {
+ if (max_count == 1U) {
+ if (mem == 1) {
+ hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem);
+ }
+ else {
+ hSemaphore = xSemaphoreCreateBinary();
+ }
+
+ if ((hSemaphore != NULL) && (initial_count != 0U)) {
+ if (xSemaphoreGive (hSemaphore) != pdPASS) {
+ vSemaphoreDelete (hSemaphore);
+ hSemaphore = NULL;
+ }
+ }
+ }
+ else {
+ if (mem == 1) {
+ hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem);
+ }
+ else {
+ hSemaphore = xSemaphoreCreateCounting (max_count, initial_count);
+ }
+ }
+
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ if (hSemaphore != NULL) {
+ if (attr != NULL) {
+ name = attr->name;
+ } else {
+ name = NULL;
+ }
+ vQueueAddToRegistry (hSemaphore, name);
+ }
+ #endif
+ }
+ }
+
+ return ((osSemaphoreId_t)hSemaphore);
+}
+
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
+ SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+ osStatus_t stat;
+ BaseType_t yield;
+
+ stat = osOK;
+
+ if (hSemaphore == NULL) {
+ stat = osErrorParameter;
+ }
+ else if (IS_IRQ()) {
+ if (timeout != 0U) {
+ stat = osErrorParameter;
+ }
+ else {
+ yield = pdFALSE;
+
+ if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) {
+ stat = osErrorResource;
+ } else {
+ portYIELD_FROM_ISR (yield);
+ }
+ }
+ }
+ else {
+ if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) {
+ if (timeout != 0U) {
+ stat = osErrorTimeout;
+ } else {
+ stat = osErrorResource;
+ }
+ }
+ }
+
+ return (stat);
+}
+
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
+ SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+ osStatus_t stat;
+ BaseType_t yield;
+
+ stat = osOK;
+
+ if (hSemaphore == NULL) {
+ stat = osErrorParameter;
+ }
+ else if (IS_IRQ()) {
+ yield = pdFALSE;
+
+ if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) {
+ stat = osErrorResource;
+ } else {
+ portYIELD_FROM_ISR (yield);
+ }
+ }
+ else {
+ if (xSemaphoreGive (hSemaphore) != pdPASS) {
+ stat = osErrorResource;
+ }
+ }
+
+ return (stat);
+}
+
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
+ SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+ uint32_t count;
+
+ if (hSemaphore == NULL) {
+ count = 0U;
+ }
+ else if (IS_IRQ()) {
+ count = uxQueueMessagesWaitingFromISR (hSemaphore);
+ } else {
+ count = (uint32_t)uxSemaphoreGetCount (hSemaphore);
+ }
+
+ return (count);
+}
+
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {
+ SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;
+ osStatus_t stat;
+
+#ifndef USE_FreeRTOS_HEAP_1
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hSemaphore == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ vQueueUnregisterQueue (hSemaphore);
+ #endif
+
+ stat = osOK;
+ vSemaphoreDelete (hSemaphore);
+ }
+#else
+ stat = osError;
+#endif
+
+ return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
+ QueueHandle_t hQueue;
+ int32_t mem;
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ const char *name;
+ #endif
+
+ hQueue = NULL;
+
+ if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) {
+ mem = -1;
+
+ if (attr != NULL) {
+ if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&
+ (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {
+ mem = 1;
+ }
+ else {
+ if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&
+ (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {
+ mem = 0;
+ }
+ }
+ }
+ else {
+ mem = 0;
+ }
+
+ if (mem == 1) {
+ hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);
+ }
+ else {
+ if (mem == 0) {
+ hQueue = xQueueCreate (msg_count, msg_size);
+ }
+ }
+
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ if (hQueue != NULL) {
+ if (attr != NULL) {
+ name = attr->name;
+ } else {
+ name = NULL;
+ }
+ vQueueAddToRegistry (hQueue, name);
+ }
+ #endif
+
+ }
+
+ return ((osMessageQueueId_t)hQueue);
+}
+
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+ osStatus_t stat;
+ BaseType_t yield;
+
+ (void)msg_prio; /* Message priority is ignored */
+
+ stat = osOK;
+
+ if (IS_IRQ()) {
+ if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
+ stat = osErrorParameter;
+ }
+ else {
+ yield = pdFALSE;
+
+ if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {
+ stat = osErrorResource;
+ } else {
+ portYIELD_FROM_ISR (yield);
+ }
+ }
+ }
+ else {
+ if ((hQueue == NULL) || (msg_ptr == NULL)) {
+ stat = osErrorParameter;
+ }
+ else {
+ if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
+ if (timeout != 0U) {
+ stat = osErrorTimeout;
+ } else {
+ stat = osErrorResource;
+ }
+ }
+ }
+ }
+
+ return (stat);
+}
+
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+ osStatus_t stat;
+ BaseType_t yield;
+
+ (void)msg_prio; /* Message priority is ignored */
+
+ stat = osOK;
+
+ if (IS_IRQ()) {
+ if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {
+ stat = osErrorParameter;
+ }
+ else {
+ yield = pdFALSE;
+
+ if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {
+ stat = osErrorResource;
+ } else {
+ portYIELD_FROM_ISR (yield);
+ }
+ }
+ }
+ else {
+ if ((hQueue == NULL) || (msg_ptr == NULL)) {
+ stat = osErrorParameter;
+ }
+ else {
+ if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {
+ if (timeout != 0U) {
+ stat = osErrorTimeout;
+ } else {
+ stat = osErrorResource;
+ }
+ }
+ }
+ }
+
+ return (stat);
+}
+
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
+ StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+ uint32_t capacity;
+
+ if (mq == NULL) {
+ capacity = 0U;
+ } else {
+ /* capacity = pxQueue->uxLength */
+ capacity = mq->uxDummy4[1];
+ }
+
+ return (capacity);
+}
+
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
+ StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+ uint32_t size;
+
+ if (mq == NULL) {
+ size = 0U;
+ } else {
+ /* size = pxQueue->uxItemSize */
+ size = mq->uxDummy4[2];
+ }
+
+ return (size);
+}
+
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+ UBaseType_t count;
+
+ if (hQueue == NULL) {
+ count = 0U;
+ }
+ else if (IS_IRQ()) {
+ count = uxQueueMessagesWaitingFromISR (hQueue);
+ }
+ else {
+ count = uxQueueMessagesWaiting (hQueue);
+ }
+
+ return ((uint32_t)count);
+}
+
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {
+ StaticQueue_t *mq = (StaticQueue_t *)mq_id;
+ uint32_t space;
+ uint32_t isrm;
+
+ if (mq == NULL) {
+ space = 0U;
+ }
+ else if (IS_IRQ()) {
+ isrm = taskENTER_CRITICAL_FROM_ISR();
+
+ /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */
+ space = mq->uxDummy4[1] - mq->uxDummy4[0];
+
+ taskEXIT_CRITICAL_FROM_ISR(isrm);
+ }
+ else {
+ space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq);
+ }
+
+ return (space);
+}
+
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+ osStatus_t stat;
+
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hQueue == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ stat = osOK;
+ (void)xQueueReset (hQueue);
+ }
+
+ return (stat);
+}
+
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {
+ QueueHandle_t hQueue = (QueueHandle_t)mq_id;
+ osStatus_t stat;
+
+#ifndef USE_FreeRTOS_HEAP_1
+ if (IS_IRQ()) {
+ stat = osErrorISR;
+ }
+ else if (hQueue == NULL) {
+ stat = osErrorParameter;
+ }
+ else {
+ #if (configQUEUE_REGISTRY_SIZE > 0)
+ vQueueUnregisterQueue (hQueue);
+ #endif
+
+ stat = osOK;
+ vQueueDelete (hQueue);
+ }
+#else
+ stat = osError;
+#endif
+
+ return (stat);
+}
+
+/*---------------------------------------------------------------------------*/
+
+/* Callback function prototypes */
+extern void vApplicationIdleHook (void);
+extern void vApplicationTickHook (void);
+extern void vApplicationMallocFailedHook (void);
+extern void vApplicationDaemonTaskStartupHook (void);
+extern void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName);
+
+/**
+ Dummy implementation of the callback function vApplicationIdleHook().
+*/
+#if (configUSE_IDLE_HOOK == 1)
+__WEAK void vApplicationIdleHook (void){}
+#endif
+
+/**
+ Dummy implementation of the callback function vApplicationTickHook().
+*/
+#if (configUSE_TICK_HOOK == 1)
+ __WEAK void vApplicationTickHook (void){}
+#endif
+
+/**
+ Dummy implementation of the callback function vApplicationMallocFailedHook().
+*/
+#if (configUSE_MALLOC_FAILED_HOOK == 1)
+__WEAK void vApplicationMallocFailedHook (void){}
+#endif
+
+/**
+ Dummy implementation of the callback function vApplicationDaemonTaskStartupHook().
+*/
+#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1)
+__WEAK void vApplicationDaemonTaskStartupHook (void){}
+#endif
+
+/**
+ Dummy implementation of the callback function vApplicationStackOverflowHook().
+*/
+#if (configCHECK_FOR_STACK_OVERFLOW > 0)
+__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName) {
+ (void)xTask;
+ (void)pcTaskName;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+/* External Idle and Timer task static memory allocation functions */
+extern void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize);
+extern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize);
+
+/* Idle task control block and stack */
+static StaticTask_t Idle_TCB;
+static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
+
+/* Timer task control block and stack */
+static StaticTask_t Timer_TCB;
+static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
+
+/*
+ vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
+ equals to 1 and is required for static memory allocation support.
+*/
+void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
+ *ppxIdleTaskTCBBuffer = &Idle_TCB;
+ *ppxIdleTaskStackBuffer = &Idle_Stack[0];
+ *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
+}
+
+/*
+ vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
+ equals to 1 and is required for static memory allocation support.
+*/
+void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
+ *ppxTimerTaskTCBBuffer = &Timer_TCB;
+ *ppxTimerTaskStackBuffer = &Timer_Stack[0];
+ *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h
new file mode 100644
index 0000000..0d3634d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h
@@ -0,0 +1,734 @@
+/* --------------------------------------------------------------------------
+ * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.
+ * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ * --------------------------------------------------------------------------
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name: cmsis_os2.h
+ * Purpose: CMSIS RTOS2 wrapper for FreeRTOS
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef CMSIS_OS2_H_
+#define CMSIS_OS2_H_
+
+#ifndef __NO_RETURN
+#if defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((__noreturn__))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumerations, structures, defines ====
+
+/// Version information.
+typedef struct {
+ uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec).
+ uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec).
+} osVersion_t;
+
+/// Kernel state.
+typedef enum {
+ osKernelInactive = 0, ///< Inactive.
+ osKernelReady = 1, ///< Ready.
+ osKernelRunning = 2, ///< Running.
+ osKernelLocked = 3, ///< Locked.
+ osKernelSuspended = 4, ///< Suspended.
+ osKernelError = -1, ///< Error.
+ osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.
+} osKernelState_t;
+
+/// Thread state.
+typedef enum {
+ osThreadInactive = 0, ///< Inactive.
+ osThreadReady = 1, ///< Ready.
+ osThreadRunning = 2, ///< Running.
+ osThreadBlocked = 3, ///< Blocked.
+ osThreadTerminated = 4, ///< Terminated.
+ osThreadError = -1, ///< Error.
+ osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osThreadState_t;
+
+/// Priority values.
+typedef enum {
+ osPriorityNone = 0, ///< No priority (not initialized).
+ osPriorityIdle = 1, ///< Reserved for Idle thread.
+ osPriorityLow = 8, ///< Priority: low
+ osPriorityLow1 = 8+1, ///< Priority: low + 1
+ osPriorityLow2 = 8+2, ///< Priority: low + 2
+ osPriorityLow3 = 8+3, ///< Priority: low + 3
+ osPriorityLow4 = 8+4, ///< Priority: low + 4
+ osPriorityLow5 = 8+5, ///< Priority: low + 5
+ osPriorityLow6 = 8+6, ///< Priority: low + 6
+ osPriorityLow7 = 8+7, ///< Priority: low + 7
+ osPriorityBelowNormal = 16, ///< Priority: below normal
+ osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1
+ osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2
+ osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3
+ osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4
+ osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5
+ osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6
+ osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7
+ osPriorityNormal = 24, ///< Priority: normal
+ osPriorityNormal1 = 24+1, ///< Priority: normal + 1
+ osPriorityNormal2 = 24+2, ///< Priority: normal + 2
+ osPriorityNormal3 = 24+3, ///< Priority: normal + 3
+ osPriorityNormal4 = 24+4, ///< Priority: normal + 4
+ osPriorityNormal5 = 24+5, ///< Priority: normal + 5
+ osPriorityNormal6 = 24+6, ///< Priority: normal + 6
+ osPriorityNormal7 = 24+7, ///< Priority: normal + 7
+ osPriorityAboveNormal = 32, ///< Priority: above normal
+ osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1
+ osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2
+ osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3
+ osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4
+ osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5
+ osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6
+ osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7
+ osPriorityHigh = 40, ///< Priority: high
+ osPriorityHigh1 = 40+1, ///< Priority: high + 1
+ osPriorityHigh2 = 40+2, ///< Priority: high + 2
+ osPriorityHigh3 = 40+3, ///< Priority: high + 3
+ osPriorityHigh4 = 40+4, ///< Priority: high + 4
+ osPriorityHigh5 = 40+5, ///< Priority: high + 5
+ osPriorityHigh6 = 40+6, ///< Priority: high + 6
+ osPriorityHigh7 = 40+7, ///< Priority: high + 7
+ osPriorityRealtime = 48, ///< Priority: realtime
+ osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1
+ osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2
+ osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3
+ osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4
+ osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5
+ osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6
+ osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7
+ osPriorityISR = 56, ///< Reserved for ISR deferred thread.
+ osPriorityError = -1, ///< System cannot determine priority or illegal priority.
+ osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osPriority_t;
+
+/// Entry point of a thread.
+typedef void (*osThreadFunc_t) (void *argument);
+
+/// Timer callback function.
+typedef void (*osTimerFunc_t) (void *argument);
+
+/// Timer type.
+typedef enum {
+ osTimerOnce = 0, ///< One-shot timer.
+ osTimerPeriodic = 1 ///< Repeating timer.
+} osTimerType_t;
+
+// Timeout value.
+#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
+
+// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait).
+#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default).
+#define osFlagsWaitAll 0x00000001U ///< Wait for all flags.
+#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for.
+
+// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).
+#define osFlagsError 0x80000000U ///< Error indicator.
+#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1).
+#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2).
+#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3).
+#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).
+#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6).
+
+// Thread attributes (attr_bits in \ref osThreadAttr_t).
+#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default)
+#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode
+
+// Mutex attributes (attr_bits in \ref osMutexAttr_t).
+#define osMutexRecursive 0x00000001U ///< Recursive mutex.
+#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol.
+#define osMutexRobust 0x00000008U ///< Robust mutex.
+
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+ osOK = 0, ///< Operation completed successfully.
+ osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits.
+ osErrorTimeout = -2, ///< Operation not completed within the timeout period.
+ osErrorResource = -3, ///< Resource not available.
+ osErrorParameter = -4, ///< Parameter error.
+ osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.
+ osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.
+ osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization.
+} osStatus_t;
+
+
+/// \details Thread ID identifies the thread.
+typedef void *osThreadId_t;
+
+/// \details Timer ID identifies the timer.
+typedef void *osTimerId_t;
+
+/// \details Event Flags ID identifies the event flags.
+typedef void *osEventFlagsId_t;
+
+/// \details Mutex ID identifies the mutex.
+typedef void *osMutexId_t;
+
+/// \details Semaphore ID identifies the semaphore.
+typedef void *osSemaphoreId_t;
+
+/// \details Memory Pool ID identifies the memory pool.
+typedef void *osMemoryPoolId_t;
+
+/// \details Message Queue ID identifies the message queue.
+typedef void *osMessageQueueId_t;
+
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+
+/// Attributes structure for thread.
+typedef struct {
+ const char *name; ///< name of the thread
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *stack_mem; ///< memory for stack
+ uint32_t stack_size; ///< size of stack
+ osPriority_t priority; ///< initial thread priority (default: osPriorityNormal)
+ TZ_ModuleId_t tz_module; ///< TrustZone module identifier
+ uint32_t reserved; ///< reserved (must be 0)
+} osThreadAttr_t;
+
+/// Attributes structure for timer.
+typedef struct {
+ const char *name; ///< name of the timer
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osTimerAttr_t;
+
+/// Attributes structure for event flags.
+typedef struct {
+ const char *name; ///< name of the event flags
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osEventFlagsAttr_t;
+
+/// Attributes structure for mutex.
+typedef struct {
+ const char *name; ///< name of the mutex
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osMutexAttr_t;
+
+/// Attributes structure for semaphore.
+typedef struct {
+ const char *name; ///< name of the semaphore
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+} osSemaphoreAttr_t;
+
+/// Attributes structure for memory pool.
+typedef struct {
+ const char *name; ///< name of the memory pool
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *mp_mem; ///< memory for data storage
+ uint32_t mp_size; ///< size of provided memory for data storage
+} osMemoryPoolAttr_t;
+
+/// Attributes structure for message queue.
+typedef struct {
+ const char *name; ///< name of the message queue
+ uint32_t attr_bits; ///< attribute bits
+ void *cb_mem; ///< memory for control block
+ uint32_t cb_size; ///< size of provided memory for control block
+ void *mq_mem; ///< memory for data storage
+ uint32_t mq_size; ///< size of provided memory for data storage
+} osMessageQueueAttr_t;
+
+
+// ==== Kernel Management Functions ====
+
+/// Initialize the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelInitialize (void);
+
+/// Get RTOS Kernel Information.
+/// \param[out] version pointer to buffer for retrieving version information.
+/// \param[out] id_buf pointer to buffer for retrieving kernel identification string.
+/// \param[in] id_size size of buffer for kernel identification string.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);
+
+/// Get the current RTOS Kernel state.
+/// \return current RTOS Kernel state.
+osKernelState_t osKernelGetState (void);
+
+/// Start the RTOS Kernel scheduler.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osKernelStart (void);
+
+/// Lock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelLock (void);
+
+/// Unlock the RTOS Kernel scheduler.
+/// \return previous lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelUnlock (void);
+
+/// Restore the RTOS Kernel scheduler lock state.
+/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock.
+/// \return new lock state (1 - locked, 0 - not locked, error code if negative).
+int32_t osKernelRestoreLock (int32_t lock);
+
+/// Suspend the RTOS Kernel scheduler.
+/// \return time in ticks, for how long the system can sleep or power-down.
+uint32_t osKernelSuspend (void);
+
+/// Resume the RTOS Kernel scheduler.
+/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode.
+void osKernelResume (uint32_t sleep_ticks);
+
+/// Get the RTOS kernel tick count.
+/// \return RTOS kernel current tick count.
+uint32_t osKernelGetTickCount (void);
+
+/// Get the RTOS kernel tick frequency.
+/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second.
+uint32_t osKernelGetTickFreq (void);
+
+/// Get the RTOS kernel system timer count.
+/// \return RTOS kernel current system timer count as 32-bit value.
+uint32_t osKernelGetSysTimerCount (void);
+
+/// Get the RTOS kernel system timer frequency.
+/// \return frequency of the system timer in hertz, i.e. timer ticks per second.
+uint32_t osKernelGetSysTimerFreq (void);
+
+
+// ==== Thread Management Functions ====
+
+/// Create a thread and add it to Active Threads.
+/// \param[in] func thread function.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \param[in] attr thread attributes; NULL: default values.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);
+
+/// Get name of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return name as NULL terminated string.
+const char *osThreadGetName (osThreadId_t thread_id);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId_t osThreadGetId (void);
+
+/// Get current thread state of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current thread state of the specified thread.
+osThreadState_t osThreadGetState (osThreadId_t thread_id);
+
+/// Get stack size of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return stack size in bytes.
+uint32_t osThreadGetStackSize (osThreadId_t thread_id);
+
+/// Get available stack space of a thread based on stack watermark recording during execution.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return remaining stack space in bytes.
+uint32_t osThreadGetStackSpace (osThreadId_t thread_id);
+
+/// Change priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in] priority new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);
+
+/// Get current priority of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return current priority value of the specified thread.
+osPriority_t osThreadGetPriority (osThreadId_t thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadYield (void);
+
+/// Suspend execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadSuspend (osThreadId_t thread_id);
+
+/// Resume execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadResume (osThreadId_t thread_id);
+
+/// Detach a thread (thread storage can be reclaimed when thread terminates).
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadDetach (osThreadId_t thread_id);
+
+/// Wait for specified thread to terminate.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadJoin (osThreadId_t thread_id);
+
+/// Terminate execution of current running thread.
+__NO_RETURN void osThreadExit (void);
+
+/// Terminate execution of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osThreadTerminate (osThreadId_t thread_id);
+
+/// Get number of active threads.
+/// \return number of active threads.
+uint32_t osThreadGetCount (void);
+
+/// Enumerate active threads.
+/// \param[out] thread_array pointer to array for retrieving thread IDs.
+/// \param[in] array_items maximum number of items in array for retrieving thread IDs.
+/// \return number of enumerated threads.
+uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);
+
+
+// ==== Thread Flags Functions ====
+
+/// Set the specified Thread Flags of a thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId.
+/// \param[in] flags specifies the flags of the thread that shall be set.
+/// \return thread flags after setting or error code if highest bit set.
+uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);
+
+/// Clear the specified Thread Flags of current running thread.
+/// \param[in] flags specifies the flags of the thread that shall be cleared.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsClear (uint32_t flags);
+
+/// Get the current Thread Flags of current running thread.
+/// \return current thread flags.
+uint32_t osThreadFlagsGet (void);
+
+/// Wait for one or more Thread Flags of the current running thread to become signaled.
+/// \param[in] flags specifies the flags to wait for.
+/// \param[in] options specifies flags options (osFlagsXxxx).
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return thread flags before clearing or error code if highest bit set.
+uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);
+
+
+// ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelay (uint32_t ticks);
+
+/// Wait until specified time.
+/// \param[in] ticks absolute time in ticks
+/// \return status code that indicates the execution status of the function.
+osStatus_t osDelayUntil (uint32_t ticks);
+
+
+// ==== Timer Management Functions ====
+
+/// Create and Initialize a timer.
+/// \param[in] func function pointer to callback function.
+/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior.
+/// \param[in] argument argument to the timer callback function.
+/// \param[in] attr timer attributes; NULL: default values.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);
+
+/// Get name of a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return name as NULL terminated string.
+const char *osTimerGetName (osTimerId_t timer_id);
+
+/// Start or restart a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);
+
+/// Stop a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerStop (osTimerId_t timer_id);
+
+/// Check if a timer is running.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return 0 not running, 1 running.
+uint32_t osTimerIsRunning (osTimerId_t timer_id);
+
+/// Delete a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osTimerDelete (osTimerId_t timer_id);
+
+
+// ==== Event Flags Management Functions ====
+
+/// Create and Initialize an Event Flags object.
+/// \param[in] attr event flags attributes; NULL: default values.
+/// \return event flags ID for reference by other functions or NULL in case of error.
+osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);
+
+/// Get name of an Event Flags object.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return name as NULL terminated string.
+const char *osEventFlagsGetName (osEventFlagsId_t ef_id);
+
+/// Set the specified Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags that shall be set.
+/// \return event flags after setting or error code if highest bit set.
+uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Clear the specified Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags that shall be cleared.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);
+
+/// Get the current Event Flags.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return current event flags.
+uint32_t osEventFlagsGet (osEventFlagsId_t ef_id);
+
+/// Wait for one or more Event Flags to become signaled.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \param[in] flags specifies the flags to wait for.
+/// \param[in] options specifies flags options (osFlagsXxxx).
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flags before clearing or error code if highest bit set.
+uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);
+
+/// Delete an Event Flags object.
+/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);
+
+
+// ==== Mutex Management Functions ====
+
+/// Create and Initialize a Mutex object.
+/// \param[in] attr mutex attributes; NULL: default values.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId_t osMutexNew (const osMutexAttr_t *attr);
+
+/// Get name of a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return name as NULL terminated string.
+const char *osMutexGetName (osMutexId_t mutex_id);
+
+/// Acquire a Mutex or timeout if it is locked.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);
+
+/// Release a Mutex that was acquired by \ref osMutexAcquire.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexRelease (osMutexId_t mutex_id);
+
+/// Get Thread which owns a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return thread ID of owner thread or NULL when mutex was not acquired.
+osThreadId_t osMutexGetOwner (osMutexId_t mutex_id);
+
+/// Delete a Mutex object.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMutexDelete (osMutexId_t mutex_id);
+
+
+// ==== Semaphore Management Functions ====
+
+/// Create and Initialize a Semaphore object.
+/// \param[in] max_count maximum number of available tokens.
+/// \param[in] initial_count initial number of available tokens.
+/// \param[in] attr semaphore attributes; NULL: default values.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);
+
+/// Get name of a Semaphore object.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return name as NULL terminated string.
+const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);
+
+/// Acquire a Semaphore token or timeout if no tokens are available.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);
+
+/// Release a Semaphore token up to the initial maximum count.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);
+
+/// Get current Semaphore token count.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return number of tokens available.
+uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);
+
+/// Delete a Semaphore object.
+/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);
+
+
+// ==== Memory Pool Management Functions ====
+
+/// Create and Initialize a Memory Pool object.
+/// \param[in] block_count maximum number of memory blocks in memory pool.
+/// \param[in] block_size memory block size in bytes.
+/// \param[in] attr memory pool attributes; NULL: default values.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);
+
+/// Get name of a Memory Pool object.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return name as NULL terminated string.
+const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);
+
+/// Allocate a memory block from a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return address of the allocated memory block or NULL in case of no memory is available.
+void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);
+
+/// Return an allocated memory block back to a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \param[in] block address of the allocated memory block to be returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);
+
+/// Get maximum number of memory blocks in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return maximum number of memory blocks.
+uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);
+
+/// Get memory block size in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return memory block size in bytes.
+uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks used in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks used.
+uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);
+
+/// Get number of memory blocks available in a Memory Pool.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return number of memory blocks available.
+uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);
+
+/// Delete a Memory Pool object.
+/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);
+
+
+// ==== Message Queue Management Functions ====
+
+/// Create and Initialize a Message Queue object.
+/// \param[in] msg_count maximum number of messages in queue.
+/// \param[in] msg_size maximum message size in bytes.
+/// \param[in] attr message queue attributes; NULL: default values.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
+
+/// Get name of a Message Queue object.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return name as NULL terminated string.
+const char *osMessageQueueGetName (osMessageQueueId_t mq_id);
+
+/// Put a Message into a Queue or timeout if Queue is full.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \param[in] msg_ptr pointer to buffer with message to put into a queue.
+/// \param[in] msg_prio message priority.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);
+
+/// Get a Message from a Queue or timeout if Queue is empty.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \param[out] msg_ptr pointer to buffer for message to get from a queue.
+/// \param[out] msg_prio pointer to buffer for message priority or NULL.
+/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);
+
+/// Get maximum number of messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum number of messages.
+uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);
+
+/// Get maximum message size in a Memory Pool.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return maximum message size in bytes.
+uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);
+
+/// Get number of queued messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of queued messages.
+uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);
+
+/// Get number of available slots for messages in a Message Queue.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return number of available slots for messages.
+uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);
+
+/// Reset a Message Queue to initial empty state.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);
+
+/// Delete a Message Queue object.
+/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew.
+/// \return status code that indicates the execution status of the function.
+osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // CMSIS_OS2_H_
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
new file mode 100644
index 0000000..565691b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/croutine.c
@@ -0,0 +1,353 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+ #define static
+#endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
+static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */
+static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */
+static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+CRCB_t * pxCurrentCoRoutine = NULL;
+static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+#define corINITIAL_STATE ( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority. It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+#define prvAddCoRoutineToReadyQueue( pxCRCB ) \
+{ \
+ if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \
+ { \
+ uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \
+ } \
+ vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \
+}
+
+/*
+ * Utility to ready all the lists used by the scheduler. This is called
+ * automatically upon the creation of the first co-routine.
+ */
+static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion). Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
+{
+BaseType_t xReturn;
+CRCB_t *pxCoRoutine;
+
+ /* Allocate the memory that will store the co-routine control block. */
+ pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+ if( pxCoRoutine )
+ {
+ /* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+ be created and the co-routine data structures need initialising. */
+ if( pxCurrentCoRoutine == NULL )
+ {
+ pxCurrentCoRoutine = pxCoRoutine;
+ prvInitialiseCoRoutineLists();
+ }
+
+ /* Check the priority is within limits. */
+ if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+ {
+ uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+ }
+
+ /* Fill out the co-routine control block from the function parameters. */
+ pxCoRoutine->uxState = corINITIAL_STATE;
+ pxCoRoutine->uxPriority = uxPriority;
+ pxCoRoutine->uxIndex = uxIndex;
+ pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+ /* Initialise all the other co-routine control block parameters. */
+ vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+ vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+ /* Set the co-routine control block as a link back from the ListItem_t.
+ This is so we can get back to the containing CRCB from a generic item
+ in a list. */
+ listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+ listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+ /* Event lists are always in priority order. */
+ listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+ /* Now the co-routine has been initialised it can be added to the ready
+ list at the correct priority. */
+ prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
+{
+TickType_t xTimeToWake;
+
+ /* Calculate the time to wake - this may overflow but this is
+ not a problem. */
+ xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+ /* We must remove ourselves from the ready list before adding
+ ourselves to the blocked list as the same list item is used for
+ both lists. */
+ ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+ /* The list item will be inserted in wake time order. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+ if( xTimeToWake < xCoRoutineTickCount )
+ {
+ /* Wake time has overflowed. Place this item in the
+ overflow list. */
+ vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+ }
+ else
+ {
+ /* The wake time has not overflowed, so we can use the
+ current block list. */
+ vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+ }
+
+ if( pxEventList )
+ {
+ /* Also add the co-routine to an event list. If this is done then the
+ function must be called with interrupts disabled. */
+ vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckPendingReadyList( void )
+{
+ /* Are there any co-routines waiting to get moved to the ready list? These
+ are co-routines that have been readied by an ISR. The ISR cannot access
+ the ready lists itself. */
+ while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+ {
+ CRCB_t *pxUnblockedCRCB;
+
+ /* The pending ready list can be accessed by an ISR. */
+ portDISABLE_INTERRUPTS();
+ {
+ pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
+ ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+ }
+ portENABLE_INTERRUPTS();
+
+ ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+ prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckDelayedList( void )
+{
+CRCB_t *pxCRCB;
+
+ xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+ while( xPassedTicks )
+ {
+ xCoRoutineTickCount++;
+ xPassedTicks--;
+
+ /* If the tick count has overflowed we need to swap the ready lists. */
+ if( xCoRoutineTickCount == 0 )
+ {
+ List_t * pxTemp;
+
+ /* Tick count has overflowed so we need to swap the delay lists. If there are
+ any items in pxDelayedCoRoutineList here then there is an error! */
+ pxTemp = pxDelayedCoRoutineList;
+ pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+ pxOverflowDelayedCoRoutineList = pxTemp;
+ }
+
+ /* See if this tick has made a timeout expire. */
+ while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+ {
+ pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+ if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+ {
+ /* Timeout not yet expired. */
+ break;
+ }
+
+ portDISABLE_INTERRUPTS();
+ {
+ /* The event could have occurred just before this critical
+ section. If this is the case then the generic list item will
+ have been moved to the pending ready list and the following
+ line is still valid. Also the pvContainer parameter will have
+ been set to NULL so the following lines are also valid. */
+ ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+ /* Is the co-routine waiting on an event also? */
+ if( pxCRCB->xEventListItem.pxContainer )
+ {
+ ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ prvAddCoRoutineToReadyQueue( pxCRCB );
+ }
+ }
+
+ xLastTickCount = xCoRoutineTickCount;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineSchedule( void )
+{
+ /* See if any co-routines readied by events need moving to the ready lists. */
+ prvCheckPendingReadyList();
+
+ /* See if any delayed co-routines have timed out. */
+ prvCheckDelayedList();
+
+ /* Find the highest priority queue that contains ready co-routines. */
+ while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+ {
+ if( uxTopCoRoutineReadyPriority == 0 )
+ {
+ /* No more co-routines to check. */
+ return;
+ }
+ --uxTopCoRoutineReadyPriority;
+ }
+
+ /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+ of the same priority get an equal share of the processor time. */
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+ /* Call the co-routine. */
+ ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+
+ return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCoRoutineLists( void )
+{
+UBaseType_t uxPriority;
+
+ for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+ {
+ vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+ }
+
+ vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+ vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+ vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+ /* Start with pxDelayedCoRoutineList using list1 and the
+ pxOverflowDelayedCoRoutineList using list2. */
+ pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+ pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
+{
+CRCB_t *pxUnblockedCRCB;
+BaseType_t xReturn;
+
+ /* This function is called from within an interrupt. It can only access
+ event lists and the pending ready list. This function assumes that a
+ check has already been made to ensure pxEventList is not empty. */
+ pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+ ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+ vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+ if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+}
+
+#endif /* configUSE_CO_ROUTINES == 0 */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
new file mode 100644
index 0000000..81c1965
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c
@@ -0,0 +1,753 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
+
+/* The following bit fields convey control information in a task's event list
+item value. It is important they don't clash with the
+taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if configUSE_16_BIT_TICKS == 1
+ #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U
+ #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U
+ #define eventWAIT_FOR_ALL_BITS 0x0400U
+ #define eventEVENT_BITS_CONTROL_BYTES 0xff00U
+#else
+ #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL
+ #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL
+ #define eventWAIT_FOR_ALL_BITS 0x04000000UL
+ #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL
+#endif
+
+typedef struct EventGroupDef_t
+{
+ EventBits_t uxEventBits;
+ List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
+
+ #if( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxEventGroupNumber;
+ #endif
+
+ #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+ #endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+ {
+ EventGroup_t *pxEventBits;
+
+ /* A StaticEventGroup_t object must be provided. */
+ configASSERT( pxEventGroupBuffer );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* Sanity check that the size of the structure used to declare a
+ variable of type StaticEventGroup_t equals the size of the real
+ event group structure. */
+ volatile size_t xSize = sizeof( StaticEventGroup_t );
+ configASSERT( xSize == sizeof( EventGroup_t ) );
+ } /*lint !e529 xSize is referenced if configASSERT() is defined. */
+ #endif /* configASSERT_DEFINED */
+
+ /* The user has provided a statically allocated event group - use it. */
+ pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+
+ if( pxEventBits != NULL )
+ {
+ pxEventBits->uxEventBits = 0;
+ vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* Both static and dynamic allocation can be used, so note that
+ this event group was created statically in case the event group
+ is later deleted. */
+ pxEventBits->ucStaticallyAllocated = pdTRUE;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+ traceEVENT_GROUP_CREATE( pxEventBits );
+ }
+ else
+ {
+ /* xEventGroupCreateStatic should only ever be called with
+ pxEventGroupBuffer pointing to a pre-allocated (compile time
+ allocated) StaticEventGroup_t variable. */
+ traceEVENT_GROUP_CREATE_FAILED();
+ }
+
+ return pxEventBits;
+ }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+ EventGroupHandle_t xEventGroupCreate( void )
+ {
+ EventGroup_t *pxEventBits;
+
+ /* Allocate the event group. Justification for MISRA deviation as
+ follows: pvPortMalloc() always ensures returned memory blocks are
+ aligned per the requirements of the MCU stack. In this case
+ pvPortMalloc() must return a pointer that is guaranteed to meet the
+ alignment requirements of the EventGroup_t structure - which (if you
+ follow it through) is the alignment requirements of the TickType_t type
+ (EventBits_t being of TickType_t itself). Therefore, whenever the
+ stack alignment requirements are greater than or equal to the
+ TickType_t alignment requirements the cast is safe. In other cases,
+ where the natural word size of the architecture is less than
+ sizeof( TickType_t ), the TickType_t variables will be accessed in two
+ or more reads operations, and the alignment requirements is only that
+ of each individual read. */
+ pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
+
+ if( pxEventBits != NULL )
+ {
+ pxEventBits->uxEventBits = 0;
+ vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ /* Both static and dynamic allocation can be used, so note this
+ event group was allocated statically in case the event group is
+ later deleted. */
+ pxEventBits->ucStaticallyAllocated = pdFALSE;
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ traceEVENT_GROUP_CREATE( pxEventBits );
+ }
+ else
+ {
+ traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
+ }
+
+ return pxEventBits;
+ }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+{
+EventBits_t uxOriginalBitValue, uxReturn;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+ configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+ configASSERT( uxBitsToWaitFor != 0 );
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+ vTaskSuspendAll();
+ {
+ uxOriginalBitValue = pxEventBits->uxEventBits;
+
+ ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+ if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+ {
+ /* All the rendezvous bits are now set - no need to block. */
+ uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+ /* Rendezvous always clear the bits. They will have been cleared
+ already unless this is the only task in the rendezvous. */
+ pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+ xTicksToWait = 0;
+ }
+ else
+ {
+ if( xTicksToWait != ( TickType_t ) 0 )
+ {
+ traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+ /* Store the bits that the calling task is waiting for in the
+ task's event list item so the kernel knows when a match is
+ found. Then enter the blocked state. */
+ vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+ /* This assignment is obsolete as uxReturn will get set after
+ the task unblocks, but some compilers mistakenly generate a
+ warning about uxReturn being returned without being set if the
+ assignment is omitted. */
+ uxReturn = 0;
+ }
+ else
+ {
+ /* The rendezvous bits were not set, but no block time was
+ specified - just return the current event bit value. */
+ uxReturn = pxEventBits->uxEventBits;
+ xTimeoutOccurred = pdTRUE;
+ }
+ }
+ }
+ xAlreadyYielded = xTaskResumeAll();
+
+ if( xTicksToWait != ( TickType_t ) 0 )
+ {
+ if( xAlreadyYielded == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The task blocked to wait for its required bits to be set - at this
+ point either the required bits were set or the block time expired. If
+ the required bits were set they will have been stored in the task's
+ event list item, and they should now be retrieved then cleared. */
+ uxReturn = uxTaskResetEventItemValue();
+
+ if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+ {
+ /* The task timed out, just return the current event bit value. */
+ taskENTER_CRITICAL();
+ {
+ uxReturn = pxEventBits->uxEventBits;
+
+ /* Although the task got here because it timed out before the
+ bits it was waiting for were set, it is possible that since it
+ unblocked another task has set the bits. If this is the case
+ then it needs to clear the bits before exiting. */
+ if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+ {
+ pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ xTimeoutOccurred = pdTRUE;
+ }
+ else
+ {
+ /* The task unblocked because the bits were set. */
+ }
+
+ /* Control bits might be set as the task had blocked should not be
+ returned. */
+ uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+ }
+
+ traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xTimeoutOccurred;
+
+ return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn, uxControlBits = 0;
+BaseType_t xWaitConditionMet, xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+ /* Check the user is not attempting to wait on the bits used by the kernel
+ itself, and that at least one bit is being requested. */
+ configASSERT( xEventGroup );
+ configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+ configASSERT( uxBitsToWaitFor != 0 );
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+ vTaskSuspendAll();
+ {
+ const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+ /* Check to see if the wait condition is already met or not. */
+ xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+ if( xWaitConditionMet != pdFALSE )
+ {
+ /* The wait condition has already been met so there is no need to
+ block. */
+ uxReturn = uxCurrentEventBits;
+ xTicksToWait = ( TickType_t ) 0;
+
+ /* Clear the wait bits if requested to do so. */
+ if( xClearOnExit != pdFALSE )
+ {
+ pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* The wait condition has not been met, but no block time was
+ specified, so just return the current value. */
+ uxReturn = uxCurrentEventBits;
+ xTimeoutOccurred = pdTRUE;
+ }
+ else
+ {
+ /* The task is going to block to wait for its required bits to be
+ set. uxControlBits are used to remember the specified behaviour of
+ this call to xEventGroupWaitBits() - for use when the event bits
+ unblock the task. */
+ if( xClearOnExit != pdFALSE )
+ {
+ uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xWaitForAllBits != pdFALSE )
+ {
+ uxControlBits |= eventWAIT_FOR_ALL_BITS;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Store the bits that the calling task is waiting for in the
+ task's event list item so the kernel knows when a match is
+ found. Then enter the blocked state. */
+ vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+ /* This is obsolete as it will get set after the task unblocks, but
+ some compilers mistakenly generate a warning about the variable
+ being returned without being set if it is not done. */
+ uxReturn = 0;
+
+ traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+ }
+ }
+ xAlreadyYielded = xTaskResumeAll();
+
+ if( xTicksToWait != ( TickType_t ) 0 )
+ {
+ if( xAlreadyYielded == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The task blocked to wait for its required bits to be set - at this
+ point either the required bits were set or the block time expired. If
+ the required bits were set they will have been stored in the task's
+ event list item, and they should now be retrieved then cleared. */
+ uxReturn = uxTaskResetEventItemValue();
+
+ if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* The task timed out, just return the current event bit value. */
+ uxReturn = pxEventBits->uxEventBits;
+
+ /* It is possible that the event bits were updated between this
+ task leaving the Blocked state and running again. */
+ if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+ {
+ if( xClearOnExit != pdFALSE )
+ {
+ pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ xTimeoutOccurred = pdTRUE;
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ /* The task unblocked because the bits were set. */
+ }
+
+ /* The task blocked so control bits may have been set. */
+ uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+ }
+ traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+ /* Prevent compiler warnings when trace macros are not used. */
+ ( void ) xTimeoutOccurred;
+
+ return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+ /* Check the user is not attempting to clear the bits used by the kernel
+ itself. */
+ configASSERT( xEventGroup );
+ configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+ taskENTER_CRITICAL();
+ {
+ traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+ /* The value returned is the event group value prior to the bits being
+ cleared. */
+ uxReturn = pxEventBits->uxEventBits;
+
+ /* Clear the bits. */
+ pxEventBits->uxEventBits &= ~uxBitsToClear;
+ }
+ taskEXIT_CRITICAL();
+
+ return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+ BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+ {
+ BaseType_t xReturn;
+
+ traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+ xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+ return xReturn;
+ }
+
+#endif
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+UBaseType_t uxSavedInterruptStatus;
+EventGroup_t const * const pxEventBits = xEventGroup;
+EventBits_t uxReturn;
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ uxReturn = pxEventBits->uxEventBits;
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return uxReturn;
+} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+{
+ListItem_t *pxListItem, *pxNext;
+ListItem_t const *pxListEnd;
+List_t const * pxList;
+EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+EventGroup_t *pxEventBits = xEventGroup;
+BaseType_t xMatchFound = pdFALSE;
+
+ /* Check the user is not attempting to set the bits used by the kernel
+ itself. */
+ configASSERT( xEventGroup );
+ configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+ pxList = &( pxEventBits->xTasksWaitingForBits );
+ pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ vTaskSuspendAll();
+ {
+ traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+ pxListItem = listGET_HEAD_ENTRY( pxList );
+
+ /* Set the bits. */
+ pxEventBits->uxEventBits |= uxBitsToSet;
+
+ /* See if the new bit value should unblock any tasks. */
+ while( pxListItem != pxListEnd )
+ {
+ pxNext = listGET_NEXT( pxListItem );
+ uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+ xMatchFound = pdFALSE;
+
+ /* Split the bits waited for from the control bits. */
+ uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+ uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+ if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+ {
+ /* Just looking for single bit being set. */
+ if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+ {
+ xMatchFound = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+ {
+ /* All bits are set. */
+ xMatchFound = pdTRUE;
+ }
+ else
+ {
+ /* Need all bits to be set, but not all the bits were set. */
+ }
+
+ if( xMatchFound != pdFALSE )
+ {
+ /* The bits match. Should the bits be cleared on exit? */
+ if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+ {
+ uxBitsToClear |= uxBitsWaitedFor;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Store the actual event flag value in the task's event list
+ item before removing the task from the event list. The
+ eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+ that is was unblocked due to its required bits matching, rather
+ than because it timed out. */
+ vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+ }
+
+ /* Move onto the next list item. Note pxListItem->pxNext is not
+ used here as the list item may have been removed from the event list
+ and inserted into the ready/pending reading list. */
+ pxListItem = pxNext;
+ }
+
+ /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+ bit was set in the control word. */
+ pxEventBits->uxEventBits &= ~uxBitsToClear;
+ }
+ ( void ) xTaskResumeAll();
+
+ return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+EventGroup_t *pxEventBits = xEventGroup;
+const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+ vTaskSuspendAll();
+ {
+ traceEVENT_GROUP_DELETE( xEventGroup );
+
+ while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+ {
+ /* Unblock the task, returning 0 as the event list is being deleted
+ and cannot therefore have any bits set. */
+ configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+ vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+ }
+
+ #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+ {
+ /* The event group can only have been allocated dynamically - free
+ it again. */
+ vPortFree( pxEventBits );
+ }
+ #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ {
+ /* The event group could have been allocated statically or
+ dynamically, so check before attempting to free the memory. */
+ if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+ {
+ vPortFree( pxEventBits );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ }
+ ( void ) xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+an interrupt. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
+{
+ ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+an interrupt. */
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
+{
+ ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
+{
+BaseType_t xWaitConditionMet = pdFALSE;
+
+ if( xWaitForAllBits == pdFALSE )
+ {
+ /* Task only has to wait for one bit within uxBitsToWaitFor to be
+ set. Is one already set? */
+ if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+ {
+ xWaitConditionMet = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+ Are they set already? */
+ if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+ {
+ xWaitConditionMet = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+ BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
+ {
+ BaseType_t xReturn;
+
+ traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+ xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+ return xReturn;
+ }
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if (configUSE_TRACE_FACILITY == 1)
+
+ UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
+ {
+ UBaseType_t xReturn;
+ EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+
+ if( xEventGroup == NULL )
+ {
+ xReturn = 0;
+ }
+ else
+ {
+ xReturn = pxEventBits->uxEventGroupNumber;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )
+ {
+ ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
new file mode 100644
index 0000000..45c778a
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h
@@ -0,0 +1,1278 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+/*
+ * Include the generic headers required for the FreeRTOS port being used.
+ */
+#include <stddef.h>
+
+/*
+ * If stdint.h cannot be located then:
+ * + If using GCC ensure the -nostdint options is *not* being used.
+ * + Ensure the project's include path includes the directory in which your
+ * compiler stores stdint.h.
+ * + Set any compiler options necessary for it to support C99, as technically
+ * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
+ * other way).
+ * + The FreeRTOS download includes a simple stdint.h definition that can be
+ * used in cases where none is provided by the compiler. The files only
+ * contains the typedefs required to build FreeRTOS. Read the instructions
+ * in FreeRTOS/source/stdint.readme for more information.
+ */
+#include <stdint.h> /* READ COMMENT ABOVE. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
+#ifndef configUSE_NEWLIB_REENTRANT
+ #define configUSE_NEWLIB_REENTRANT 0
+#endif
+
+/* Required if struct _reent is used. */
+#if ( configUSE_NEWLIB_REENTRANT == 1 )
+ #include <reent.h>
+#endif
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+ #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+ #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if configMAX_PRIORITIES < 1
+ #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef configUSE_PREEMPTION
+ #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+ #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+ #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+ #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+ #define configUSE_CO_ROUTINES 0
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+ #define INCLUDE_vTaskPrioritySet 0
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+ #define INCLUDE_uxTaskPriorityGet 0
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+ #define INCLUDE_vTaskDelete 0
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+ #define INCLUDE_vTaskSuspend 0
+#endif
+
+#ifndef INCLUDE_vTaskDelayUntil
+ #define INCLUDE_vTaskDelayUntil 0
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+ #define INCLUDE_vTaskDelay 0
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+ #define INCLUDE_xTaskGetIdleTaskHandle 0
+#endif
+
+#ifndef INCLUDE_xTaskAbortDelay
+ #define INCLUDE_xTaskAbortDelay 0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+ #define INCLUDE_xQueueGetMutexHolder 0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+ #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_xTaskGetHandle
+ #define INCLUDE_xTaskGetHandle 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+ #define INCLUDE_uxTaskGetStackHighWaterMark 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+ #define INCLUDE_uxTaskGetStackHighWaterMark2 0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+ #define INCLUDE_eTaskGetState 0
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+ #define INCLUDE_xTaskResumeFromISR 1
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+ #define INCLUDE_xTimerPendFunctionCall 0
+#endif
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+ #define INCLUDE_xTaskGetSchedulerState 0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+ #define INCLUDE_xTaskGetCurrentTaskHandle 0
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+ #ifndef configMAX_CO_ROUTINE_PRIORITIES
+ #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+ #endif
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+ #define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+ #define configUSE_APPLICATION_TASK_TAG 0
+#endif
+
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+ #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+ #define configUSE_RECURSIVE_MUTEXES 0
+#endif
+
+#ifndef configUSE_MUTEXES
+ #define configUSE_MUTEXES 0
+#endif
+
+#ifndef configUSE_TIMERS
+ #define configUSE_TIMERS 0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+ #define configUSE_COUNTING_SEMAPHORES 0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+ #define configUSE_ALTERNATIVE_API 0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+ #define portCRITICAL_NESTING_IN_TCB 0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+ #define configMAX_TASK_NAME_LEN 16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+ #define configIDLE_SHOULD_YIELD 1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+ #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef configASSERT
+ #define configASSERT( x )
+ #define configASSERT_DEFINED 0
+#else
+ #define configASSERT_DEFINED 1
+#endif
+
+#ifndef portMEMORY_BARRIER
+ #define portMEMORY_BARRIER()
+#endif
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+ #ifndef configTIMER_TASK_PRIORITY
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+ #endif /* configTIMER_TASK_PRIORITY */
+
+ #ifndef configTIMER_QUEUE_LENGTH
+ #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+ #endif /* configTIMER_QUEUE_LENGTH */
+
+ #ifndef configTIMER_TASK_STACK_DEPTH
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+ #endif /* configTIMER_TASK_STACK_DEPTH */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+ #define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#endif
+
+#ifndef portCLEAN_UP_TCB
+ #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+ #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+ #define portSETUP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+ #define configQUEUE_REGISTRY_SIZE 0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+ #define vQueueAddToRegistry( xQueue, pcName )
+ #define vQueueUnregisterQueue( xQueue )
+ #define pcQueueGetName( xQueue )
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+ #define portPOINTER_SIZE_TYPE uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+ /* Used to perform any necessary initialisation - for example, open a file
+ into which trace is to be written. */
+ #define traceSTART()
+#endif
+
+#ifndef traceEND
+ /* Use to close a trace, for example close a file into which trace has been
+ written. */
+ #define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+ /* Called after a task has been selected to run. pxCurrentTCB holds a pointer
+ to the task control block of the selected task. */
+ #define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+ /* Called before stepping the tick count after waking from tickless idle
+ sleep. */
+ #define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+ /* Called immediately before entering tickless idle. */
+ #define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef traceLOW_POWER_IDLE_END
+ /* Called when returning to the Idle task after a tickless idle. */
+ #define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+ /* Called before a task has been selected to run. pxCurrentTCB holds a pointer
+ to the task control block of the task being switched out. */
+ #define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+ /* Called when a task attempts to take a mutex that is already held by a
+ lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task
+ that holds the mutex. uxInheritedPriority is the priority the mutex holder
+ will inherit (the priority of the task that is attempting to obtain the
+ muted. */
+ #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+ /* Called when a task releases a mutex, the holding of which had resulted in
+ the task inheriting the priority of a higher priority task.
+ pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+ mutex. uxOriginalPriority is the task's configured (base) priority. */
+ #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+ /* Task is about to block because it cannot read from a
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore
+ upon which the read was attempted. pxCurrentTCB points to the TCB of the
+ task that attempted the read. */
+ #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_PEEK
+ /* Task is about to block because it cannot read from a
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore
+ upon which the read was attempted. pxCurrentTCB points to the TCB of the
+ task that attempted the read. */
+ #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+ /* Task is about to block because it cannot write to a
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore
+ upon which the write was attempted. pxCurrentTCB points to the TCB of the
+ task that attempted the write. */
+ #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+ #define configCHECK_FOR_STACK_OVERFLOW 0
+#endif
+
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+ #define configRECORD_STACK_HIGH_ADDRESS 0
+#endif
+
+#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
+ #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+ #define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
+ #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceQUEUE_CREATE
+ #define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+ #define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+ #define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+ #define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+ #define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+ #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+ #define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+ #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+ #define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+ #define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SEND
+ #define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+ #define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+ #define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+ #define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FAILED
+ #define traceQUEUE_PEEK_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+ #define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+ #define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+ #define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+ #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+ #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+ #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+ #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+ #define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+ #define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+ #define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+ #define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+ #define traceTASK_DELAY_UNTIL( x )
+#endif
+
+#ifndef traceTASK_DELAY
+ #define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+ #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+ #define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+ #define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+ #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+ #define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+ #define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+ #define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+ #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+ #define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+ #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+ #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+ #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+ #define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+ #define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+ #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+ #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+ #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+ #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+ #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+ #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+ #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+ #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+ #define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+ #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+ #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+ #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE_BLOCK
+ #define traceTASK_NOTIFY_TAKE_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE
+ #define traceTASK_NOTIFY_TAKE()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT_BLOCK
+ #define traceTASK_NOTIFY_WAIT_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT
+ #define traceTASK_NOTIFY_WAIT()
+#endif
+
+#ifndef traceTASK_NOTIFY
+ #define traceTASK_NOTIFY()
+#endif
+
+#ifndef traceTASK_NOTIFY_FROM_ISR
+ #define traceTASK_NOTIFY_FROM_ISR()
+#endif
+
+#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
+ #define traceTASK_NOTIFY_GIVE_FROM_ISR()
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_FAILED
+ #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
+ #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE
+ #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_DELETE
+ #define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RESET
+ #define traceSTREAM_BUFFER_RESET( xStreamBuffer )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
+ #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND
+ #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FAILED
+ #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
+ #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
+ #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE
+ #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
+ #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
+ #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+ #define configGENERATE_RUN_TIME_STATS 0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+ #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+ #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+ #ifndef portGET_RUN_TIME_COUNTER_VALUE
+ #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+ #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information.
+ #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+ #endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+ #define configUSE_MALLOC_FAILED_HOOK 0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+ #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+ #define portYIELD_WITHIN_API portYIELD
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+ #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+ #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+ #define configUSE_TICKLESS_IDLE 0
+#endif
+
+#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
+ #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+ #define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+ #define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+ #define configUSE_QUEUE_SETS 0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+ #define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef portALLOCATE_SECURE_CONTEXT
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portDONT_DISCARD
+ #define portDONT_DISCARD
+#endif
+
+#ifndef configUSE_TIME_SLICING
+ #define configUSE_TIME_SLICING 1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+ #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+ #define configUSE_STATS_FORMATTING_FUNCTIONS 0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+ #define configUSE_TRACE_FACILITY 0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef mtCOVERAGE_TEST_DELAY
+ #define mtCOVERAGE_TEST_DELAY()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+ #define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#endif
+
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+ #define configAPPLICATION_ALLOCATED_HEAP 0
+#endif
+
+#ifndef configUSE_TASK_NOTIFICATIONS
+ #define configUSE_TASK_NOTIFICATIONS 1
+#endif
+
+#ifndef configUSE_POSIX_ERRNO
+ #define configUSE_POSIX_ERRNO 0
+#endif
+
+#ifndef portTICK_TYPE_IS_ATOMIC
+ #define portTICK_TYPE_IS_ATOMIC 0
+#endif
+
+#ifndef configSUPPORT_STATIC_ALLOCATION
+ /* Defaults to 0 for backward compatibility. */
+ #define configSUPPORT_STATIC_ALLOCATION 0
+#endif
+
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+ /* Defaults to 1 for backward compatibility. */
+ #define configSUPPORT_DYNAMIC_ALLOCATION 1
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+ /* Defaults to uint16_t for backward compatibility, but can be overridden
+ in FreeRTOSConfig.h if uint16_t is too restrictive. */
+ #define configSTACK_DEPTH_TYPE uint16_t
+#endif
+
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+ /* Defaults to size_t for backward compatibility, but can be overridden
+ in FreeRTOSConfig.h if lengths will always be less than the number of bytes
+ in a size_t. */
+ #define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+#endif
+
+/* Sanity check the configuration. */
+#if( configUSE_TICKLESS_IDLE != 0 )
+ #if( INCLUDE_vTaskSuspend != 1 )
+ #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
+ #endif /* INCLUDE_vTaskSuspend */
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+ #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
+#endif
+
+#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
+ #error configUSE_MUTEXES must be set to 1 to use recursive mutexes
+#endif
+
+#ifndef configINITIAL_TICK_COUNT
+ #define configINITIAL_TICK_COUNT 0
+#endif
+
+#if( portTICK_TYPE_IS_ATOMIC == 0 )
+ /* Either variables of tick type cannot be read atomically, or
+ portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
+ the tick count is returned to the standard critical section macros. */
+ #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()
+ #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()
+ #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+ #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
+#else
+ /* The tick type can be read atomically, so critical sections used when the
+ tick count is returned can be defined away. */
+ #define portTICK_TYPE_ENTER_CRITICAL()
+ #define portTICK_TYPE_EXIT_CRITICAL()
+ #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
+ #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x
+#endif
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+ #define configENABLE_BACKWARD_COMPATIBILITY 1
+#endif
+
+#ifndef configPRINTF
+ /* configPRINTF() was not defined, so define it away to nothing. To use
+ configPRINTF() then define it as follows (where MyPrintFunction() is
+ provided by the application writer):
+
+ void MyPrintFunction(const char *pcFormat, ... );
+ #define configPRINTF( X ) MyPrintFunction X
+
+ Then call like a standard printf() function, but placing brackets around
+ all parameters so they are passed as a single parameter. For example:
+ configPRINTF( ("Value = %d", MyVariable) ); */
+ #define configPRINTF( X )
+#endif
+
+#ifndef configMAX
+ /* The application writer has not provided their own MAX macro, so define
+ the following generic implementation. */
+ #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#ifndef configMIN
+ /* The application writer has not provided their own MAX macro, so define
+ the following generic implementation. */
+ #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+ #define eTaskStateGet eTaskGetState
+ #define portTickType TickType_t
+ #define xTaskHandle TaskHandle_t
+ #define xQueueHandle QueueHandle_t
+ #define xSemaphoreHandle SemaphoreHandle_t
+ #define xQueueSetHandle QueueSetHandle_t
+ #define xQueueSetMemberHandle QueueSetMemberHandle_t
+ #define xTimeOutType TimeOut_t
+ #define xMemoryRegion MemoryRegion_t
+ #define xTaskParameters TaskParameters_t
+ #define xTaskStatusType TaskStatus_t
+ #define xTimerHandle TimerHandle_t
+ #define xCoRoutineHandle CoRoutineHandle_t
+ #define pdTASK_HOOK_CODE TaskHookFunction_t
+ #define portTICK_RATE_MS portTICK_PERIOD_MS
+ #define pcTaskGetTaskName pcTaskGetName
+ #define pcTimerGetTimerName pcTimerGetName
+ #define pcQueueGetQueueName pcQueueGetName
+ #define vTaskGetTaskInfo vTaskGetInfo
+
+ /* Backward compatibility within the scheduler code only - these definitions
+ are not really required but are included for completeness. */
+ #define tmrTIMER_CALLBACK TimerCallbackFunction_t
+ #define pdTASK_CODE TaskFunction_t
+ #define xListItem ListItem_t
+ #define xList List_t
+
+ /* For libraries that break the list data hiding, and access list structure
+ members directly (which is not supposed to be done). */
+ #define pxContainer pvContainer
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#if( configUSE_ALTERNATIVE_API != 0 )
+ #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
+#endif
+
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+if floating point hardware is otherwise supported by the FreeRTOS port in use.
+This constant is not supported by all FreeRTOS ports that include floating
+point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+ #define configUSE_TASK_FPU_SUPPORT 1
+#endif
+
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+ #define configENABLE_MPU 0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+ #define configENABLE_FPU 1
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+ #define configENABLE_TRUSTZONE 1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+ #define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed. Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM. Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free |
+ * | | | | | | Static Possible | |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes |
+ * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No |
+ * | | | | xTaskCreateRestrictedStatic | | | |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes |
+ * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes |
+ * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | |
+ * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | |
+ * | | | | xTaskCreateRestrictedStatic | | | |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+ ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
+/*
+ * In line with software engineering best practice, FreeRTOS implements a strict
+ * data hiding policy, so the real structures used by FreeRTOS to maintain the
+ * state of tasks, queues, semaphores, etc. are not accessible to the application
+ * code. However, if the application writer wants to statically allocate such
+ * an object then the size of the object needs to be know. Dummy structures
+ * that are guaranteed to have the same size and alignment requirements of the
+ * real objects are used for this purpose. The dummy list and list item
+ * structures below are used for inclusion in such a dummy structure.
+ */
+struct xSTATIC_LIST_ITEM
+{
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy1;
+ #endif
+ TickType_t xDummy2;
+ void *pvDummy3[ 4 ];
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy4;
+ #endif
+};
+typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+struct xSTATIC_MINI_LIST_ITEM
+{
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy1;
+ #endif
+ TickType_t xDummy2;
+ void *pvDummy3[ 2 ];
+};
+typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+typedef struct xSTATIC_LIST
+{
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy1;
+ #endif
+ UBaseType_t uxDummy2;
+ void *pvDummy3;
+ StaticMiniListItem_t xDummy4;
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy5;
+ #endif
+} StaticList_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy. This means the Task structure used internally by
+ * FreeRTOS is not accessible to application code. However, if the application
+ * writer wants to statically allocate the memory required to create a task then
+ * the size of the task object needs to be know. The StaticTask_t structure
+ * below is provided for this purpose. Its sizes and alignment requirements are
+ * guaranteed to match those of the genuine structure, no matter which
+ * architecture is being used, and no matter how the values in FreeRTOSConfig.h
+ * are set. Its contents are somewhat obfuscated in the hope users will
+ * recognise that it would be unwise to make direct use of the structure members.
+ */
+typedef struct xSTATIC_TCB
+{
+ void *pxDummy1;
+ #if ( portUSING_MPU_WRAPPERS == 1 )
+ xMPU_SETTINGS xDummy2;
+ #endif
+ StaticListItem_t xDummy3[ 2 ];
+ UBaseType_t uxDummy5;
+ void *pxDummy6;
+ uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];
+ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+ void *pxDummy8;
+ #endif
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+ UBaseType_t uxDummy9;
+ #endif
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxDummy10[ 2 ];
+ #endif
+ #if ( configUSE_MUTEXES == 1 )
+ UBaseType_t uxDummy12[ 2 ];
+ #endif
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ void *pxDummy14;
+ #endif
+ #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+ void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+ #endif
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ uint32_t ulDummy16;
+ #endif
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ struct _reent xDummy17;
+ #endif
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ uint32_t ulDummy18;
+ uint8_t ucDummy19;
+ #endif
+ #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+ uint8_t uxDummy20;
+ #endif
+
+ #if( INCLUDE_xTaskAbortDelay == 1 )
+ uint8_t ucDummy21;
+ #endif
+ #if ( configUSE_POSIX_ERRNO == 1 )
+ int iDummy22;
+ #endif
+} StaticTask_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy. This means the Queue structure used internally by
+ * FreeRTOS is not accessible to application code. However, if the application
+ * writer wants to statically allocate the memory required to create a queue
+ * then the size of the queue object needs to be know. The StaticQueue_t
+ * structure below is provided for this purpose. Its sizes and alignment
+ * requirements are guaranteed to match those of the genuine structure, no
+ * matter which architecture is being used, and no matter how the values in
+ * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope
+ * users will recognise that it would be unwise to make direct use of the
+ * structure members.
+ */
+typedef struct xSTATIC_QUEUE
+{
+ void *pvDummy1[ 3 ];
+
+ union
+ {
+ void *pvDummy2;
+ UBaseType_t uxDummy2;
+ } u;
+
+ StaticList_t xDummy3[ 2 ];
+ UBaseType_t uxDummy4[ 3 ];
+ uint8_t ucDummy5[ 2 ];
+
+ #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ uint8_t ucDummy6;
+ #endif
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ void *pvDummy7;
+ #endif
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxDummy8;
+ uint8_t ucDummy9;
+ #endif
+
+} StaticQueue_t;
+typedef StaticQueue_t StaticSemaphore_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy. This means the event group structure used
+ * internally by FreeRTOS is not accessible to application code. However, if
+ * the application writer wants to statically allocate the memory required to
+ * create an event group then the size of the event group object needs to be
+ * know. The StaticEventGroup_t structure below is provided for this purpose.
+ * Its sizes and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set. Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_EVENT_GROUP
+{
+ TickType_t xDummy1;
+ StaticList_t xDummy2;
+
+ #if( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxDummy3;
+ #endif
+
+ #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ uint8_t ucDummy4;
+ #endif
+
+} StaticEventGroup_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy. This means the software timer structure used
+ * internally by FreeRTOS is not accessible to application code. However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a software timer then the size of the queue object needs to be know.
+ * The StaticTimer_t structure below is provided for this purpose. Its sizes
+ * and alignment requirements are guaranteed to match those of the genuine
+ * structure, no matter which architecture is being used, and no matter how the
+ * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in
+ * the hope users will recognise that it would be unwise to make direct use of
+ * the structure members.
+ */
+typedef struct xSTATIC_TIMER
+{
+ void *pvDummy1;
+ StaticListItem_t xDummy2;
+ TickType_t xDummy3;
+ void *pvDummy5;
+ TaskFunction_t pvDummy6;
+ #if( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxDummy7;
+ #endif
+ uint8_t ucDummy8;
+
+} StaticTimer_t;
+
+/*
+* In line with software engineering best practice, especially when supplying a
+* library that is likely to change in future versions, FreeRTOS implements a
+* strict data hiding policy. This means the stream buffer structure used
+* internally by FreeRTOS is not accessible to application code. However, if
+* the application writer wants to statically allocate the memory required to
+* create a stream buffer then the size of the stream buffer object needs to be
+* know. The StaticStreamBuffer_t structure below is provided for this purpose.
+* Its size and alignment requirements are guaranteed to match those of the
+* genuine structure, no matter which architecture is being used, and no matter
+* how the values in FreeRTOSConfig.h are set. Its contents are somewhat
+* obfuscated in the hope users will recognise that it would be unwise to make
+* direct use of the structure members.
+*/
+typedef struct xSTATIC_STREAM_BUFFER
+{
+ size_t uxDummy1[ 4 ];
+ void * pvDummy2[ 3 ];
+ uint8_t ucDummy3;
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxDummy4;
+ #endif
+} StaticStreamBuffer_t;
+
+/* Message buffers are built on stream buffers. */
+typedef StaticStreamBuffer_t StaticMessageBuffer_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INC_FREERTOS_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
new file mode 100644
index 0000000..000d866
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
+ #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released.
+#endif
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten. Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+ /* Only the current stack state is to be checked. */
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+ /* Only the current stack state is to be checked. */
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
+ const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \
+ \
+ if( ( pulStack[ 0 ] != ulCheckValue ) || \
+ ( pulStack[ 1 ] != ulCheckValue ) || \
+ ( pulStack[ 2 ] != ulCheckValue ) || \
+ ( pulStack[ 3 ] != ulCheckValue ) ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \
+ static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+ \
+ \
+ pcEndOfStack -= sizeof( ucExpectedStackBytes ); \
+ \
+ /* Has the extremity of the task stack ever been written over? */ \
+ if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+ #define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
new file mode 100644
index 0000000..a781749
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h
@@ -0,0 +1,720 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Used to hide the implementation of the co-routine control block. The
+control block structure however has to be included in the header due to
+the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+ crCOROUTINE_CODE pxCoRoutineFunction;
+ ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */
+ ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */
+ UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */
+ UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+ uint16_t uxState; /*< Used internally by the co-routine implementation. */
+} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ *<pre>
+ BaseType_t xCoRoutineCreate(
+ crCOROUTINE_CODE pxCoRoutineCode,
+ UBaseType_t uxPriority,
+ UBaseType_t uxIndex
+ );</pre>
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ * the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function. See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+ <pre>
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // This co-routine just delays for a fixed period, then toggles
+ // an LED. Two co-routines are created using this function, so
+ // the uxIndex parameter is used to tell the co-routine which
+ // LED to flash and how int32_t to delay. This assumes xQueue has
+ // already been created.
+ vParTestToggleLED( cLedToFlash[ uxIndex ] );
+ crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+ // Create two co-routines at priority 0. The first is given index 0
+ // so (from the code above) toggles LED 5 every 200 ticks. The second
+ // is given index 1 so toggles LED 6 every 400 ticks.
+ for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+ {
+ xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+ }
+ }
+ </pre>
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ *<pre>
+ void vCoRoutineSchedule( void );</pre>
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run. The co-routine will execute until it either blocks, yields or is
+ * preempted by a task. Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+ <pre>
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+ vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+ for( ;; )
+ {
+ vCoRoutineSchedule();
+ }
+ }
+ </pre>
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * <pre>
+ crSTART( CoRoutineHandle_t xHandle );</pre>
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+ <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Co-routine functionality goes here.
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ * <pre>
+ crEND();</pre>
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+ <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Co-routine functionality goes here.
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only. The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *<pre>
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function. This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay. This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for. The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+ <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Delay for 200ms.
+ crDELAY( xHandle, xDelayTime );
+
+ // Do something here.
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }</pre>
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay ) \
+ if( ( xTicksToDelay ) > 0 ) \
+ { \
+ vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
+ } \
+ crSET_STATE0( ( xHandle ) );
+
+/**
+ * <pre>
+ crQUEUE_SEND(
+ CoRoutineHandle_t xHandle,
+ QueueHandle_t pxQueue,
+ void *pvItemToQueue,
+ TickType_t xTicksToWait,
+ BaseType_t *pxResult
+ )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function. This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine. This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created. This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+ <pre>
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+ // Co-routines must begin with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // This assumes the queue has already been created.
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+ if( xResult != pdPASS )
+ {
+ // The message was not posted!
+ }
+
+ // Increment the number to be posted onto the queue.
+ xNumberToPost++;
+
+ // Delay for 100 ticks.
+ crDELAY( xHandle, 100 );
+ }
+
+ // Co-routines must end with a call to crEND().
+ crEND();
+ }</pre>
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \
+{ \
+ *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \
+ { \
+ crSET_STATE0( ( xHandle ) ); \
+ *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \
+ } \
+ if( *pxResult == errQUEUE_YIELD ) \
+ { \
+ crSET_STATE1( ( xHandle ) ); \
+ *pxResult = pdPASS; \
+ } \
+}
+
+/**
+ * croutine. h
+ * <pre>
+ crQUEUE_RECEIVE(
+ CoRoutineHandle_t xHandle,
+ QueueHandle_t pxQueue,
+ void *pvBuffer,
+ TickType_t xTicksToWait,
+ BaseType_t *pxResult
+ )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function. This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine. This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created. This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine receives the number of an LED to flash from a queue. It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+ // All co-routines must start with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Wait for data to become available on the queue.
+ crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+ if( xResult == pdPASS )
+ {
+ // We received the LED to flash - flash it!
+ vParTestToggleLED( uxLEDToFlash );
+ }
+ }
+
+ crEND();
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \
+{ \
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \
+ { \
+ crSET_STATE0( ( xHandle ) ); \
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \
+ } \
+ if( *( pxResult ) == errQUEUE_YIELD ) \
+ { \
+ crSET_STATE1( ( xHandle ) ); \
+ *( pxResult ) = pdPASS; \
+ } \
+}
+
+/**
+ * croutine. h
+ * <pre>
+ crQUEUE_SEND_FROM_ISR(
+ QueueHandle_t pxQueue,
+ void *pvItemToQueue,
+ BaseType_t xCoRoutinePreviouslyWoken
+ )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt. The first call
+ * should always pass in pdFALSE. Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue. This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+ // All co-routines must start with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Wait for data to become available on the queue. This assumes the
+ // queue xCommsRxQueue has already been created!
+ crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+ // Was a character received?
+ if( xResult == pdPASS )
+ {
+ // Process the character here.
+ }
+ }
+
+ // All co-routines must end with a call to crEND().
+ crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+ // We loop around reading characters until there are none left in the UART.
+ while( UART_RX_REG_NOT_EMPTY() )
+ {
+ // Obtain the character from the UART.
+ cRxedChar = UART_RX_REG;
+
+ // Post the character onto a queue. xCRWokenByPost will be pdFALSE
+ // the first time around the loop. If the post causes a co-routine
+ // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+ // In this manner we can ensure that if more than one co-routine is
+ // blocked on the queue only one is woken by this ISR no matter how
+ // many characters are posted to the queue.
+ xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+ }
+ }</pre>
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * <pre>
+ crQUEUE_SEND_FROM_ISR(
+ QueueHandle_t pxQueue,
+ void *pvBuffer,
+ BaseType_t * pxCoRoutineWoken
+ )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period. The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+ // All co-routines must start with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Send the next character to the queue.
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+ if( xResult == pdPASS )
+ {
+ // The character was successfully posted to the queue.
+ }
+ else
+ {
+ // Could not post the character to the queue.
+ }
+
+ // Enable the UART Tx interrupt to cause an interrupt in this
+ // hypothetical UART. The interrupt will obtain the character
+ // from the queue and send it.
+ ENABLE_RX_INTERRUPT();
+
+ // Increment to the next character then block for a fixed period.
+ // cCharToTx will maintain its value across the delay as it is
+ // declared static.
+ cCharToTx++;
+ if( cCharToTx > 'x' )
+ {
+ cCharToTx = 'a';
+ }
+ crDELAY( 100 );
+ }
+
+ // All co-routines must end with a call to crEND().
+ crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+ while( UART_TX_REG_EMPTY() )
+ {
+ // Are there any characters in the queue waiting to be sent?
+ // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+ // is woken by the post - ensuring that only a single co-routine is
+ // woken no matter how many times we go around this loop.
+ if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+ {
+ SEND_CHARACTER( cCharToTx );
+ }
+ }
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here. The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CO_ROUTINE_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h
new file mode 100644
index 0000000..4d0ce01
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h
@@ -0,0 +1,279 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file. Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used. That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used. The
+definitions below remain in the code for backward compatibility only. New
+projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+ #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+ #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+ #include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+ #include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+ #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+ #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+ #include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+ #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+ #include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+ #include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+ #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+ #include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+ #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+ #include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+ #include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+ #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+ #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+ #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+ #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+ #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+ #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+ #include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+ #include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+ #include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+ #include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+ #include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+ #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+ #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+ #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+ #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+ #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+ #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+ #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+ #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+ #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+ #include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+ #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+ #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+ #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+ #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+ #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+ #include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+ /* A short file name has to be used in place of the normal
+ FreeRTOSConfig.h when using the Borland compiler. */
+ #include "frconfig.h"
+ #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+ /* A short file name has to be used in place of the normal
+ FreeRTOSConfig.h when using the Borland compiler. */
+ #include "frconfig.h"
+ #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef __GNUC__
+ #ifdef __AVR32_AVR32A__
+ #include "portmacro.h"
+ #endif
+#endif
+
+#ifdef __ICCAVR32__
+ #ifdef __CORE__
+ #if __CORE__ == __AVR32A__
+ #include "portmacro.h"
+ #endif
+ #endif
+#endif
+
+#ifdef __91467D
+ #include "portmacro.h"
+#endif
+
+#ifdef __96340
+ #include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+ #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+ #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
new file mode 100644
index 0000000..522b0b6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h
@@ -0,0 +1,757 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning. For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc. A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active. To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose. This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced. For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+struct EventGroupDef_t;
+typedef struct EventGroupDef_t * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t EventBits_t;
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreate( void );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored. If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html). If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned. If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned. See http://www.freertos.org/a00111.html
+ *
+ * Example usage:
+ <pre>
+ // Declare a variable to hold the created event group.
+ EventGroupHandle_t xCreatedEventGroup;
+
+ // Attempt to create the event group.
+ xCreatedEventGroup = xEventGroupCreate();
+
+ // Was the event group created successfully?
+ if( xCreatedEventGroup == NULL )
+ {
+ // The event group was not created because there was insufficient
+ // FreeRTOS heap available.
+ }
+ else
+ {
+ // The event group was created.
+ }
+ </pre>
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored. If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html). If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned. If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ // StaticEventGroup_t is a publicly accessible structure that has the same
+ // size and alignment requirements as the real event group structure. It is
+ // provided as a mechanism for applications to know the size of the event
+ // group (which is dependent on the architecture and configuration file
+ // settings) without breaking the strict data hiding policy by exposing the
+ // real event group internals. This StaticEventGroup_t variable is passed
+ // into the xSemaphoreCreateEventGroupStatic() function and is used to store
+ // the event group's data structures
+ StaticEventGroup_t xEventGroupBuffer;
+
+ // Create the event group without dynamically allocating any memory.
+ xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+ </pre>
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xClearOnExit,
+ const BaseType_t xWaitForAllBits,
+ const TickType_t xTicksToWait );
+ </pre>
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested. The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group. For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07. Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout). If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires. If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires. The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired. Test the return value to know
+ * which bits were set. If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set. If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+ <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ void aFunction( EventGroupHandle_t xEventGroup )
+ {
+ EventBits_t uxBits;
+ const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+ // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+ // the event group. Clear the bits before exiting.
+ uxBits = xEventGroupWaitBits(
+ xEventGroup, // The event group being tested.
+ BIT_0 | BIT_4, // The bits within the event group to wait for.
+ pdTRUE, // BIT_0 and BIT_4 should be cleared before returning.
+ pdFALSE, // Don't wait for both bits, either bit will do.
+ xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
+
+ if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ {
+ // xEventGroupWaitBits() returned because both bits were set.
+ }
+ else if( ( uxBits & BIT_0 ) != 0 )
+ {
+ // xEventGroupWaitBits() returned because just BIT_0 was set.
+ }
+ else if( ( uxBits & BIT_4 ) != 0 )
+ {
+ // xEventGroupWaitBits() returned because just BIT_4 was set.
+ }
+ else
+ {
+ // xEventGroupWaitBits() returned because xTicksToWait ticks passed
+ // without either BIT_0 or BIT_4 becoming set.
+ }
+ }
+ </pre>
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ </pre>
+ *
+ * Clear bits within an event group. This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group. For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+ <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ void aFunction( EventGroupHandle_t xEventGroup )
+ {
+ EventBits_t uxBits;
+
+ // Clear bit 0 and bit 4 in xEventGroup.
+ uxBits = xEventGroupClearBits(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 );// The bits being cleared.
+
+ if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ {
+ // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+ // called. Both will now be clear (not set).
+ }
+ else if( ( uxBits & BIT_0 ) != 0 )
+ {
+ // Bit 0 was set before xEventGroupClearBits() was called. It will
+ // now be clear.
+ }
+ else if( ( uxBits & BIT_4 ) != 0 )
+ {
+ // Bit 4 was set before xEventGroupClearBits() was called. It will
+ // now be clear.
+ }
+ else
+ {
+ // Neither bit 0 nor bit 4 were set in the first place.
+ }
+ }
+ </pre>
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+ BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set. FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts. As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+ <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ // An event group which it is assumed has already been created by a call to
+ // xEventGroupCreate().
+ EventGroupHandle_t xEventGroup;
+
+ void anInterruptHandler( void )
+ {
+ // Clear bit 0 and bit 4 in xEventGroup.
+ xResult = xEventGroupClearBitsFromISR(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 ); // The bits being set.
+
+ if( xResult == pdPASS )
+ {
+ // The message was posted successfully.
+ }
+ }
+ </pre>
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+ BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+#else
+ #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns. There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared. First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+ <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ void aFunction( EventGroupHandle_t xEventGroup )
+ {
+ EventBits_t uxBits;
+
+ // Set bit 0 and bit 4 in xEventGroup.
+ uxBits = xEventGroupSetBits(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 );// The bits being set.
+
+ if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ {
+ // Both bit 0 and bit 4 remained set when the function returned.
+ }
+ else if( ( uxBits & BIT_0 ) != 0 )
+ {
+ // Bit 0 remained set when the function returned, but bit 4 was
+ // cleared. It might be that bit 4 was cleared automatically as a
+ // task that was waiting for bit 4 was removed from the Blocked
+ // state.
+ }
+ else if( ( uxBits & BIT_4 ) != 0 )
+ {
+ // Bit 4 remained set when the function returned, but bit 0 was
+ // cleared. It might be that bit 0 was cleared automatically as a
+ // task that was waiting for bit 0 was removed from the Blocked
+ // state.
+ }
+ else
+ {
+ // Neither bit 0 nor bit 4 remained set. It might be that a task
+ // was waiting for both of the bits to be set, and the bits were
+ // cleared as the task left the Blocked state.
+ }
+ }
+ </pre>
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+ BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ </pre>
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set. FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task. If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits. For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+ <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ // An event group which it is assumed has already been created by a call to
+ // xEventGroupCreate().
+ EventGroupHandle_t xEventGroup;
+
+ void anInterruptHandler( void )
+ {
+ BaseType_t xHigherPriorityTaskWoken, xResult;
+
+ // xHigherPriorityTaskWoken must be initialised to pdFALSE.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Set bit 0 and bit 4 in xEventGroup.
+ xResult = xEventGroupSetBitsFromISR(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 // The bits being set.
+ &xHigherPriorityTaskWoken );
+
+ // Was the message posted successfully?
+ if( xResult == pdPASS )
+ {
+ // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ // switch should be requested. The macro used is port specific and
+ // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ // refer to the documentation page for the port being used.
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ }
+ }
+ </pre>
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+ BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+ #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait );
+ </pre>
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group. This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time. In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested. The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group. For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07. Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired. Test the return value to know
+ * which bits were set. If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set. If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ <pre>
+ // Bits used by the three tasks.
+ #define TASK_0_BIT ( 1 << 0 )
+ #define TASK_1_BIT ( 1 << 1 )
+ #define TASK_2_BIT ( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks. It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+ for( ;; )
+ {
+ // Perform task functionality here.
+
+ // Set bit 0 in the event flag to note this task has reached the
+ // sync point. The other two tasks will set the other two bits defined
+ // by ALL_SYNC_BITS. All three tasks have reached the synchronisation
+ // point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms
+ // for this to happen.
+ uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+ if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+ {
+ // All three tasks reached the synchronisation point before the call
+ // to xEventGroupSync() timed out.
+ }
+ }
+ }
+
+ void vTask1( void *pvParameters )
+ {
+ for( ;; )
+ {
+ // Perform task functionality here.
+
+ // Set bit 1 in the event flag to note this task has reached the
+ // synchronisation point. The other two tasks will set the other two
+ // bits defined by ALL_SYNC_BITS. All three tasks have reached the
+ // synchronisation point when all the ALL_SYNC_BITS are set. Wait
+ // indefinitely for this to happen.
+ xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+ // xEventGroupSync() was called with an indefinite block time, so
+ // this task will only reach here if the syncrhonisation was made by all
+ // three tasks, so there is no need to test the return value.
+ }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+ for( ;; )
+ {
+ // Perform task functionality here.
+
+ // Set bit 2 in the event flag to note this task has reached the
+ // synchronisation point. The other two tasks will set the other two
+ // bits defined by ALL_SYNC_BITS. All three tasks have reached the
+ // synchronisation point when all the ALL_SYNC_BITS are set. Wait
+ // indefinitely for this to happen.
+ xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+ // xEventGroupSync() was called with an indefinite block time, so
+ // this task will only reach here if the syncrhonisation was made by all
+ // three tasks, so there is no need to test the return value.
+ }
+ }
+
+ </pre>
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ *<pre>
+ EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Returns the current value of the bits in an event group. This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ *<pre>
+ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+ void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate(). Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if (configUSE_TRACE_FACILITY == 1)
+ UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;
+ void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_GROUPS_H */
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
new file mode 100644
index 0000000..b2bb46d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/list.h
@@ -0,0 +1,412 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * This is the list implementation used by the scheduler. While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a
+ * numeric value (xItemValue). Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item. The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker. The list member pxHead always
+ * points to this marker - even though it is at the tail of the list. This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it. These later two
+ * pointers are included for efficiency of list manipulation. There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+#ifndef INC_FREERTOS_H
+ #error FreeRTOS.h must be included before list.h
+#endif
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile. However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable. Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour. The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended. That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation. It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler. If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+ #define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Macros that can be used to place known values within the list structures,
+then check that the known values do not get corrupted during the execution of
+the application. These may catch the list data structures being overwritten in
+memory. They will not catch data errors caused by incorrect configuration or
+use of FreeRTOS.*/
+#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+ /* Define the macros to do nothing. */
+ #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+ #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+ #define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+ #define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+ #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+ #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+ #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+ #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+ #define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+ #define listTEST_LIST_INTEGRITY( pxList )
+#else
+ /* Define macros that add new members into the list structures. */
+ #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1;
+ #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2;
+ #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1;
+ #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2;
+
+ /* Define macros that set the new structure members to known values. */
+ #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+ #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+ #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+ #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+ /* Define macros that will assert if one of the structure members does not
+ contain its expected value. */
+ #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+ #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST;
+struct xLIST_ITEM
+{
+ listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+ configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */
+ struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */
+ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */
+ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */
+ struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */
+ listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+ listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+ configLIST_VOLATILE TickType_t xItemValue;
+ struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+ listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+ volatile UBaseType_t uxNumberOfItems;
+ ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+ MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+ listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item. The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item. The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item. In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item. The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items. The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list. Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter. Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item. In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \
+{ \
+List_t * const pxConstList = ( pxList ); \
+ /* Increment the index to the next item and return the item, ensuring */ \
+ /* we don't return the marker used at the end of the list. */ \
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
+ if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
+ { \
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
+ } \
+ ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \
+}
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list. Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item. In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list. The list item maintains a
+ * "container" pointer that points to the list it is in. All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used! This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used. This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list. The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list. The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list. Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex. This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list. The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed. The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
new file mode 100644
index 0000000..9ee3f4d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h
@@ -0,0 +1,799 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Message buffers build functionality on top of FreeRTOS stream buffers.
+ * Whereas stream buffers are used to send a continuous stream of data from one
+ * task or interrupt to another, message buffers are used to send variable
+ * length discrete messages from one task or interrupt to another. Their
+ * implementation is light weight, making them particularly suited for interrupt
+ * to task and core to core communication scenarios.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * timeout to 0.
+ *
+ * Message buffers hold variable length messages. To enable that, when a
+ * message is written to the message buffer an additional sizeof( size_t ) bytes
+ * are also written to store the message's length (that happens internally, with
+ * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so writing a 10 byte message to a message buffer on a 32-bit
+ * architecture will actually reduce the available space in the message buffer
+ * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
+ * of the message).
+ */
+
+#ifndef FREERTOS_MESSAGE_BUFFER_H
+#define FREERTOS_MESSAGE_BUFFER_H
+
+/* Message buffers are built onto of stream buffers. */
+#include "stream_buffer.h"
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which message buffers are referenced. For example, a call to
+ * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
+ * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
+ * etc.
+ */
+typedef void * MessageBufferHandle_t;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * message_buffer.h
+ *
+<pre>
+MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+</pre>
+ *
+ * Creates a new message buffer using dynamically allocated memory. See
+ * xMessageBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes (not messages) the message
+ * buffer will be able to hold at any one time. When a message is written to
+ * the message buffer an additional sizeof( size_t ) bytes are also written to
+ * store the message's length. sizeof( size_t ) is typically 4 bytes on a
+ * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
+ * take up 14 bytes of message buffer space.
+ *
+ * @return If NULL is returned, then the message buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the message buffer data structures and storage area. A non-NULL value being
+ * returned indicates that the message buffer has been created successfully -
+ * the returned value should be stored as the handle to the created message
+ * buffer.
+ *
+ * Example use:
+<pre>
+
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+ // Create a message buffer that can hold 100 bytes. The memory used to hold
+ // both the message buffer structure and the messages themselves is allocated
+ // dynamically. Each message added to the buffer consumes an additional 4
+ // bytes which are used to hold the lengh of the message.
+ xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+ if( xMessageBuffer == NULL )
+ {
+ // There was not enough heap memory space available to create the
+ // message buffer.
+ }
+ else
+ {
+ // The message buffer was created successfully and can now be used.
+ }
+
+</pre>
+ * \defgroup xMessageBufferCreate xMessageBufferCreate
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+ uint8_t *pucMessageBufferStorageArea,
+ StaticMessageBuffer_t *pxStaticMessageBuffer );
+</pre>
+ * Creates a new message buffer using statically allocated memory. See
+ * xMessageBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucMessageBufferStorageArea parameter. When a message is written to the
+ * message buffer an additional sizeof( size_t ) bytes are also written to store
+ * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so on most 32-bit architecture a 10 byte message will take up
+ * 14 bytes of message buffer space. The maximum number of bytes that can be
+ * stored in the message buffer is actually (xBufferSizeBytes - 1).
+ *
+ * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big. This is the array to which messages are
+ * copied when they are written to the message buffer.
+ *
+ * @param pxStaticMessageBuffer Must point to a variable of type
+ * StaticMessageBuffer_t, which will be used to hold the message buffer's data
+ * structure.
+ *
+ * @return If the message buffer is created successfully then a handle to the
+ * created message buffer is returned. If either pucMessageBufferStorageArea or
+ * pxStaticmessageBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+<pre>
+
+// Used to dimension the array used to hold the messages. The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+ xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+ ucBufferStorage,
+ &xMessageBufferStruct );
+
+ // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+ // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+ // reference the created message buffer in other message buffer API calls.
+
+ // Other code that uses the message buffer can go here.
+}
+
+</pre>
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait );
+<pre>
+ *
+ * Sends a discrete message to the message buffer. The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task. Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message. That is, the number of
+ * bytes to copy from pvTxData into the message buffer. When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length. sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called. The calling task will never block if
+ * xTicksToWait is zero. The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency. The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer. If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned. If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+<pre>
+void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+ // Send an array to the message buffer, blocking for a maximum of 100ms to
+ // wait for enough space to be available in the message buffer.
+ xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+ if( xBytesSent != sizeof( ucArrayToSend ) )
+ {
+ // The call to xMessageBufferSend() times out before there was enough
+ // space in the buffer for the data to be written.
+ }
+
+ // Send the string to the message buffer. Return immediately if there is
+ // not enough space in the buffer.
+ xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+ if( xBytesSent != strlen( pcStringToSend ) )
+ {
+ // The string could not be added to the message buffer because there was
+ // not enough free space in the buffer.
+ }
+}
+</pre>
+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ BaseType_t *pxHigherPriorityTaskWoken );
+<pre>
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer. The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task. Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message. That is, the number of
+ * bytes to copy from pvTxData into the message buffer. When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length. sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken It is possible that a message buffer will
+ * have a task blocked on it waiting for data. Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state. If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE. If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited. This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function. See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer. If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+<pre>
+// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+ // Attempt to send the string to the message buffer.
+ xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+ ( void * ) pcStringToSend,
+ strlen( pcStringToSend ),
+ &xHigherPriorityTaskWoken );
+
+ if( xBytesSent != strlen( pcStringToSend ) )
+ {
+ // The string could not be added to the message buffer because there was
+ // not enough free space in the buffer.
+ }
+
+ // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ // xMessageBufferSendFromISR() then a task that has a priority above the
+ // priority of the currently executing task was unblocked and a context
+ // switch should be performed to ensure the ISR returns to the unblocked
+ // task. In most FreeRTOS ports this is done by simply passing
+ // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ // variables value, and perform the context switch if necessary. Check the
+ // documentation for the port in use for port specific instructions.
+ taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait );
+</pre>
+ *
+ * Receives a discrete message from a message buffer. Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task. Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter. This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty. The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency. The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any. If xMessageBufferReceive() times out before a message became available
+ * then zero is returned. If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+<pre>
+void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+ // Receive the next message from the message buffer. Wait in the Blocked
+ // state (so not using any CPU processing time) for a maximum of 100ms for
+ // a message to become available.
+ xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+ ( void * ) ucRxData,
+ sizeof( ucRxData ),
+ xBlockTime );
+
+ if( xReceivedBytes > 0 )
+ {
+ // A ucRxData contains a message that is xReceivedBytes long. Process
+ // the message here....
+ }
+}
+</pre>
+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+<pre>
+size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer. Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task. Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter. This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available. Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state. If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited. That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function. See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+<pre>
+// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+ // Receive the next message from the message buffer.
+ xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+ ( void * ) ucRxData,
+ sizeof( ucRxData ),
+ &xHigherPriorityTaskWoken );
+
+ if( xReceivedBytes > 0 )
+ {
+ // A ucRxData contains a message that is xReceivedBytes long. Process
+ // the message here....
+ }
+
+ // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ // xMessageBufferReceiveFromISR() then a task that has a priority above the
+ // priority of the currently executing task was unblocked and a context
+ // switch should be performed to ensure the ISR returns to the unblocked
+ // task. In most FreeRTOS ports this is done by simply passing
+ // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ // variables value, and perform the context switch if necessary. Check the
+ // documentation for the port in use for port specific instructions.
+ taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+</pre>
+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ *
+ * Tests to see if a message buffer is full. A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned. Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned. Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+<pre>
+BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+</pre>
+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned. If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+<pre>
+size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+</pre>
+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full. When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ <pre>
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ </pre>
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+<pre>
+BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer. If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state. xMessageBufferSendCompletedFromISR() does the same
+ * thing. It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR(). If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+<pre>
+BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer. If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR()
+ * does the same thing. It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR(). If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..f0b3337
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,157 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files. This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..56d9c7e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,186 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+ /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+ included from queue.c or task.c to prevent it from having an effect within
+ those files. */
+ #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+ /*
+ * Map standard (non MPU) API functions to equivalents that start
+ * "MPU_". This will cause the application code to call the MPU_
+ * version, which wraps the non-MPU version with privilege promoting
+ * then demoting code, so the kernel code always runs will full
+ * privileges.
+ */
+
+ /* Map standard tasks.h API functions to the MPU equivalents. */
+ #define xTaskCreate MPU_xTaskCreate
+ #define xTaskCreateStatic MPU_xTaskCreateStatic
+ #define xTaskCreateRestricted MPU_xTaskCreateRestricted
+ #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions
+ #define vTaskDelete MPU_vTaskDelete
+ #define vTaskDelay MPU_vTaskDelay
+ #define vTaskDelayUntil MPU_vTaskDelayUntil
+ #define xTaskAbortDelay MPU_xTaskAbortDelay
+ #define uxTaskPriorityGet MPU_uxTaskPriorityGet
+ #define eTaskGetState MPU_eTaskGetState
+ #define vTaskGetInfo MPU_vTaskGetInfo
+ #define vTaskPrioritySet MPU_vTaskPrioritySet
+ #define vTaskSuspend MPU_vTaskSuspend
+ #define vTaskResume MPU_vTaskResume
+ #define vTaskSuspendAll MPU_vTaskSuspendAll
+ #define xTaskResumeAll MPU_xTaskResumeAll
+ #define xTaskGetTickCount MPU_xTaskGetTickCount
+ #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks
+ #define pcTaskGetName MPU_pcTaskGetName
+ #define xTaskGetHandle MPU_xTaskGetHandle
+ #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark
+ #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2
+ #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag
+ #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag
+ #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer
+ #define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer
+ #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook
+ #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle
+ #define uxTaskGetSystemState MPU_uxTaskGetSystemState
+ #define vTaskList MPU_vTaskList
+ #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats
+ #define xTaskGetIdleRunTimeCounter MPU_xTaskGetIdleRunTimeCounter
+ #define xTaskGenericNotify MPU_xTaskGenericNotify
+ #define xTaskNotifyWait MPU_xTaskNotifyWait
+ #define ulTaskNotifyTake MPU_ulTaskNotifyTake
+ #define xTaskNotifyStateClear MPU_xTaskNotifyStateClear
+
+ #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle
+ #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState
+ #define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut
+ #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState
+
+ /* Map standard queue.h API functions to the MPU equivalents. */
+ #define xQueueGenericSend MPU_xQueueGenericSend
+ #define xQueueReceive MPU_xQueueReceive
+ #define xQueuePeek MPU_xQueuePeek
+ #define xQueueSemaphoreTake MPU_xQueueSemaphoreTake
+ #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting
+ #define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable
+ #define vQueueDelete MPU_vQueueDelete
+ #define xQueueCreateMutex MPU_xQueueCreateMutex
+ #define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic
+ #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore
+ #define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic
+ #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder
+ #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive
+ #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive
+ #define xQueueGenericCreate MPU_xQueueGenericCreate
+ #define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic
+ #define xQueueCreateSet MPU_xQueueCreateSet
+ #define xQueueAddToSet MPU_xQueueAddToSet
+ #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet
+ #define xQueueSelectFromSet MPU_xQueueSelectFromSet
+ #define xQueueGenericReset MPU_xQueueGenericReset
+
+ #if( configQUEUE_REGISTRY_SIZE > 0 )
+ #define vQueueAddToRegistry MPU_vQueueAddToRegistry
+ #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue
+ #define pcQueueGetName MPU_pcQueueGetName
+ #endif
+
+ /* Map standard timer.h API functions to the MPU equivalents. */
+ #define xTimerCreate MPU_xTimerCreate
+ #define xTimerCreateStatic MPU_xTimerCreateStatic
+ #define pvTimerGetTimerID MPU_pvTimerGetTimerID
+ #define vTimerSetTimerID MPU_vTimerSetTimerID
+ #define xTimerIsTimerActive MPU_xTimerIsTimerActive
+ #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle
+ #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall
+ #define pcTimerGetName MPU_pcTimerGetName
+ #define vTimerSetReloadMode MPU_vTimerSetReloadMode
+ #define xTimerGetPeriod MPU_xTimerGetPeriod
+ #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime
+ #define xTimerGenericCommand MPU_xTimerGenericCommand
+
+ /* Map standard event_group.h API functions to the MPU equivalents. */
+ #define xEventGroupCreate MPU_xEventGroupCreate
+ #define xEventGroupCreateStatic MPU_xEventGroupCreateStatic
+ #define xEventGroupWaitBits MPU_xEventGroupWaitBits
+ #define xEventGroupClearBits MPU_xEventGroupClearBits
+ #define xEventGroupSetBits MPU_xEventGroupSetBits
+ #define xEventGroupSync MPU_xEventGroupSync
+ #define vEventGroupDelete MPU_vEventGroupDelete
+
+ /* Map standard message/stream_buffer.h API functions to the MPU
+ equivalents. */
+ #define xStreamBufferSend MPU_xStreamBufferSend
+ #define xStreamBufferReceive MPU_xStreamBufferReceive
+ #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes
+ #define vStreamBufferDelete MPU_vStreamBufferDelete
+ #define xStreamBufferIsFull MPU_xStreamBufferIsFull
+ #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty
+ #define xStreamBufferReset MPU_xStreamBufferReset
+ #define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable
+ #define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable
+ #define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel
+ #define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate
+ #define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic
+
+
+ /* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+ macro so applications can place data in privileged access sections
+ (useful when using statically allocated objects). */
+ #define PRIVILEGED_FUNCTION
+ #define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+ #define FREERTOS_SYSTEM_CALL
+
+ #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+ /* Ensure API functions go in the privileged execution section. */
+ #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+ #define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+ #define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+ #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+ #define PRIVILEGED_FUNCTION
+ #define PRIVILEGED_DATA
+ #define FREERTOS_SYSTEM_CALL
+ #define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..a1bb449
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API. Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file. Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used. That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here. In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+ #include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+ #define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+ #define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+ #define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+ #define portBYTE_ALIGNMENT_MASK ( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+ #define portBYTE_ALIGNMENT_MASK ( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+ #define portBYTE_ALIGNMENT_MASK ( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+ #error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+ #define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+ #define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+ #define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control. The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+ #else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+ #endif
+#else
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+ #else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+ #endif
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+ uint8_t *pucStartAddress;
+ size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c. This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap. The array is
+ * terminated by a HeapRegions_t structure that has a size of 0. The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control. This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+ struct xMEMORY_REGION;
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..dbcf9bb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform. Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks. This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+ #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE ( ( BaseType_t ) 0 )
+#define pdTRUE ( ( BaseType_t ) 1 )
+
+#define pdPASS ( pdTRUE )
+#define pdFAIL ( pdFALSE )
+#define errQUEUE_EMPTY ( ( BaseType_t ) 0 )
+#define errQUEUE_FULL ( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )
+#define errQUEUE_BLOCKED ( -4 )
+#define errQUEUE_YIELD ( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+ #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ #define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+ #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE 0 /* No errors */
+#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */
+#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */
+#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */
+#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */
+#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */
+#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */
+#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */
+#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */
+#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */
+#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */
+#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */
+#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */
+#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */
+#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */
+#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */
+#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */
+#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */
+#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */
+#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */
+#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */
+#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */
+#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */
+#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */
+#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */
+#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */
+#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */
+#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */
+#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */
+#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */
+#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */
+#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */
+#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */
+#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */
+#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */
+#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */
+#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */
+#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */
+#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN 0
+#define pdFREERTOS_BIG_ENDIAN 1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..5072c45
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced. For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced. For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define queueSEND_TO_BACK ( ( BaseType_t ) 0 )
+#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 )
+#define queueOVERWRITE ( ( BaseType_t ) 2 )
+
+/* For internal use only. These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreate(
+ UBaseType_t uxQueueLength,
+ UBaseType_t uxItemSize
+ );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory. The first block is used to hold the queue's data structures. The
+ * second block is used to hold items placed into the queue. If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function. (see
+ * http://www.freertos.org/a00111.html). If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue. xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item. Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned. If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ if( xQueue1 == 0 )
+ {
+ // Queue was not created and must not be used.
+ }
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ if( xQueue2 == 0 )
+ {
+ // Queue was not created and must not be used.
+ }
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreateStatic(
+ UBaseType_t uxQueueLength,
+ UBaseType_t uxItemSize,
+ uint8_t *pucQueueStorageBuffer,
+ StaticQueue_t *pxQueueBuffer
+ );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory. The first block is used to hold the queue's data structures. The
+ * second block is used to hold items placed into the queue. If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function. (see
+ * http://www.freertos.org/a00111.html). If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue. xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item. Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned. If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue. Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+ ITEM_SIZE // The size of each item in the queue
+ &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+ &xQueueBuffer ); // The buffer that will hold the queue structure.
+
+ // The queue is guaranteed to be created successfully as no dynamic memory
+ // allocation is used. Therefore xQueue1 is now a handle to a valid queue.
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToToFront(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ TickType_t xTicksToWait
+ );
+ * </pre>
+ *
+ * Post an item to the front of a queue. The item is queued by copy, not by
+ * reference. This function must not be called from an interrupt service
+ * routine. See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the
+ * queue is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ }
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBack(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ TickType_t xTicksToWait
+ );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue. The item is queued by copy, not by
+ * reference. This function must not be called from an interrupt service
+ * routine. See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the queue
+ * is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ }
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSend(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ TickType_t xTicksToWait
+ );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend(). It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros. It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue. The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the
+ * queue is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ }
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwrite(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue
+ );
+ * </pre>
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue. If the queue is already full then overwrite the
+ * value held in the queue. The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront(). However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+ <pre>
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+ // Create a queue to hold one uint32_t value. It is strongly
+ // recommended *not* to use xQueueOverwrite() on queues that can
+ // contain more than one value, and doing so will trigger an assertion
+ // if configASSERT() is defined.
+ xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+ // Write the value 10 to the queue using xQueueOverwrite().
+ ulVarToSend = 10;
+ xQueueOverwrite( xQueue, &ulVarToSend );
+
+ // Peeking the queue should now return 10, but leave the value 10 in
+ // the queue. A block time of zero is used as it is known that the
+ // queue holds a value.
+ ulValReceived = 0;
+ xQueuePeek( xQueue, &ulValReceived, 0 );
+
+ if( ulValReceived != 10 )
+ {
+ // Error unless the item was removed by a different task.
+ }
+
+ // The queue is still full. Use xQueueOverwrite() to overwrite the
+ // value held in the queue with 100.
+ ulVarToSend = 100;
+ xQueueOverwrite( xQueue, &ulVarToSend );
+
+ // This time read from the queue, leaving the queue empty once more.
+ // A block time of 0 is used again.
+ xQueueReceive( xQueue, &ulValReceived, 0 );
+
+ // The value read should be the last value written, even though the
+ // queue was already full when the value was written.
+ if( ulValReceived != 100 )
+ {
+ // Error!
+ }
+
+ // ...
+}
+ </pre>
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSend(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ TickType_t xTicksToWait
+ BaseType_t xCopyPosition
+ );
+ * </pre>
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue. The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the
+ * queue is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+ }
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeek(
+ QueueHandle_t xQueue,
+ void * const pvBuffer,
+ TickType_t xTicksToWait
+ );</pre>
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided. The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine. See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ if( xQueue == 0 )
+ {
+ // Failed to create the queue.
+ }
+
+ // ...
+
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+ // ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+ if( xQueue != 0 )
+ {
+ // Peek a message on the created queue. Block for 10 ticks if a
+ // message is not immediately available.
+ if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ {
+ // pcRxedMessage now points to the struct AMessage variable posted
+ // by vATask, but the item still remains on the queue.
+ }
+ }
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeekFromISR(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ );</pre>
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided. The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceive(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ TickType_t xTicksToWait
+ );</pre>
+ *
+ * Receive an item from a queue. The item is received by copy so a buffer of
+ * adequate size must be provided. The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine. See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty. The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ <pre>
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ if( xQueue == 0 )
+ {
+ // Failed to create the queue.
+ }
+
+ // ...
+
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+ // ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+ if( xQueue != 0 )
+ {
+ // Receive a message on the created queue. Block for 10 ticks if a
+ // message is not immediately available.
+ if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ {
+ // pcRxedMessage now points to the struct AMessage variable posted
+ // by vATask.
+ }
+ }
+
+ // ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of free spaces available in a queue. This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToFrontFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue. It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post the byte.
+ xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary.
+ if( xHigherPriorityTaskWoken )
+ {
+ taskYIELD ();
+ }
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBackFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue. It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post the byte.
+ xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary.
+ if( xHigherPriorityTaskWoken )
+ {
+ taskYIELD ();
+ }
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwriteFromISR(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+ * </pre>
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue. If the queue is already full then overwrite the
+ * value held in the queue. The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+ <pre>
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ // Create a queue to hold one uint32_t value. It is strongly
+ // recommended *not* to use xQueueOverwriteFromISR() on queues that can
+ // contain more than one value, and doing so will trigger an assertion
+ // if configASSERT() is defined.
+ xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+ // Write the value 10 to the queue using xQueueOverwriteFromISR().
+ ulVarToSend = 10;
+ xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+ // The queue is full, but calling xQueueOverwriteFromISR() again will still
+ // pass because the value held in the queue will be overwritten with the
+ // new value.
+ ulVarToSend = 100;
+ xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+ // Reading from the queue will now return 100.
+
+ // ...
+
+ if( xHigherPrioritytaskWoken == pdTRUE )
+ {
+ // Writing to the queue caused a task to unblock and the unblocked task
+ // has a priority higher than or equal to the priority of the currently
+ // executing task (the task this interrupt interrupted). Perform a context
+ // switch so this interrupt returns directly to the unblocked task.
+ portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ }
+}
+ </pre>
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR(). It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue. It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post the byte.
+ xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary.
+ if( xHigherPriorityTaskWoken )
+ {
+ // Actual macro used here is port specific.
+ portYIELD_FROM_ISR ();
+ }
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSendFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken,
+ BaseType_t xCopyPosition
+ );
+ </pre>
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly. xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue. It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWokenByPost = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post each byte.
+ xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary. Note that the
+ // name of the yield function required is port specific.
+ if( xHigherPriorityTaskWokenByPost )
+ {
+ taskYIELD_YIELD_FROM_ISR();
+ }
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceiveFromISR(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ BaseType_t *pxTaskWoken
+ );
+ * </pre>
+ *
+ * Receive an item from a queue. It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue. If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ <pre>
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+ // Create a queue capable of containing 10 characters.
+ xQueue = xQueueCreate( 10, sizeof( char ) );
+ if( xQueue == 0 )
+ {
+ // Failed to create the queue.
+ }
+
+ // ...
+
+ // Post some characters that will be used within an ISR. If the queue
+ // is full then this task will block for xTicksToWait ticks.
+ cValueToPost = 'a';
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ cValueToPost = 'b';
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+ // ... keep posting characters ... this task may block when the queue
+ // becomes full.
+
+ cValueToPost = 'c';
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+ while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+ {
+ // A character was received. Output the character now.
+ vOutputCharacter( cRxedChar );
+
+ // If removing the character from the queue woke the task that was
+ // posting onto the queue cTaskWokenByReceive will have been set to
+ // pdTRUE. No matter how many times this loop iterates only one
+ // task will be woken.
+ }
+
+ if( cTaskWokenByPost != ( char ) pdFALSE;
+ {
+ taskYIELD ();
+ }
+ }
+ </pre>
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR. These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks. The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code. Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only. Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only. Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state. The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger. If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available. Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry. This
+ * is the handle returned by a call to xQueueCreate(). Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle. This is the
+ * name that the kernel aware debugger will display. The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+ void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register. If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+ void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes. Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned. If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+ const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation. This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation. This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used. Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2: Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3: An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set. Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4: A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set. uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once. To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value. Examples:
+ * + If a queue set is to hold a queue of length 5, another queue of length 12,
+ * and a binary semaphore, then uxEventQueueLength should be set to
+ * (5 + 12 + 1), or 18.
+ * + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ * should be set to (1 + 1 + 1 ), or 3.
+ * + If a queue set is to hold a counting semaphore that has a maximum count of
+ * 5, and a counting semaphore that has a maximum count of 3, then
+ * uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned. Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1: A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned. If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set. A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned. If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore). xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2: Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3: A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..32b4e5e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function. Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore. The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task. The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore. For this reason this type of
+ * semaphore does not use a priority inheritance mechanism. For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+ // This is a macro so pass the variable in directly.
+ vSemaphoreCreateBinary( xSemaphore );
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+ </pre>
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #define vSemaphoreCreateBinary( xSemaphore ) \
+ { \
+ ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \
+ if( ( xSemaphore ) != NULL ) \
+ { \
+ ( void ) xSemaphoreGive( ( xSemaphore ) ); \
+ } \
+ }
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored. If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function. (see http://www.freertos.org/a00111.html). If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function. Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task. The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore. For this reason this type of
+ * semaphore does not use a priority inheritance mechanism. For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ // This is a macro so pass the variable in directly.
+ xSemaphore = xSemaphoreCreateBinary();
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored. If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function. (see http://www.freertos.org/a00111.html). If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task. The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore. For this reason this type of
+ * semaphore does not use a priority inheritance mechanism. For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned. If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ // The semaphore's data structures will be placed in the xSemaphoreBuffer
+ // variable, the address of which is passed into the function. The
+ // function's parameter is not NULL, so the function will not attempt any
+ // dynamic memory allocation, and therefore the function will not return
+ // return NULL.
+ xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+ // Rest of task code goes here.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreTake(
+ * SemaphoreHandle_t xSemaphore,
+ * TickType_t xBlockTime
+ * )</pre>
+ *
+ * <i>Macro</i> to obtain a semaphore. The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available. The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time. A block time of zero can be used to poll the semaphore. A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained. pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+ // Create the semaphore to guard a shared resource.
+ xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+ // ... Do other things.
+
+ if( xSemaphore != NULL )
+ {
+ // See if we can obtain the semaphore. If the semaphore is not available
+ // wait 10 ticks to see if it becomes free.
+ if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ {
+ // We were able to obtain the semaphore and can now access the
+ // shared resource.
+
+ // ...
+
+ // We have finished accessing the shared resource. Release the
+ // semaphore.
+ xSemaphoreGive( xSemaphore );
+ }
+ else
+ {
+ // We could not obtain the semaphore and can therefore not access
+ // the shared resource safely.
+ }
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ * SemaphoreHandle_t xMutex,
+ * TickType_t xBlockTime
+ * )
+ *
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also 'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained. This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available. The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time. A block time of zero can be used to poll the semaphore. If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+ // Create the mutex to guard a shared resource.
+ xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+ // ... Do other things.
+
+ if( xMutex != NULL )
+ {
+ // See if we can obtain the mutex. If the mutex is not available
+ // wait 10 ticks to see if it becomes free.
+ if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ {
+ // We were able to obtain the mutex and can now access the
+ // shared resource.
+
+ // ...
+ // For some reason due to the nature of the code further calls to
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real
+ // code these would not be just sequential calls as this would make
+ // no sense. Instead the calls are likely to be buried inside
+ // a more complex call structure.
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+ // The mutex has now been 'taken' three times, so will not be
+ // available to another task until it has also been given back
+ // three times. Again it is unlikely that real code would have
+ // these calls sequentially, but instead buried in a more complex
+ // call structure. This is just for illustrative purposes.
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+
+ // Now the mutex can be taken by other tasks.
+ }
+ else
+ {
+ // We could not obtain the mutex and can therefore not access
+ // the shared resource safely.
+ }
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+ #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * <i>Macro</i> to release a semaphore. The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released. This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred.
+ * Semaphores are implemented using queues. An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+ // Create the semaphore to guard a shared resource.
+ xSemaphore = vSemaphoreCreateBinary();
+
+ if( xSemaphore != NULL )
+ {
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ {
+ // We would expect this call to fail because we cannot give
+ // a semaphore without first "taking" it!
+ }
+
+ // Obtain the semaphore - don't block if the semaphore is not
+ // immediately available.
+ if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+ {
+ // We now have the semaphore and can access the shared resource.
+
+ // ...
+
+ // We have finished accessing the shared resource so can free the
+ // semaphore.
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ {
+ // We would not expect this call to fail because we must have
+ // obtained the semaphore to get here.
+ }
+ }
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>
+ *
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also 'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'. This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+ // Create the mutex to guard a shared resource.
+ xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+ // ... Do other things.
+
+ if( xMutex != NULL )
+ {
+ // See if we can obtain the mutex. If the mutex is not available
+ // wait 10 ticks to see if it becomes free.
+ if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+ {
+ // We were able to obtain the mutex and can now access the
+ // shared resource.
+
+ // ...
+ // For some reason due to the nature of the code further calls to
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real
+ // code these would not be just sequential calls as this would make
+ // no sense. Instead the calls are likely to be buried inside
+ // a more complex call structure.
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+ // The mutex has now been 'taken' three times, so will not be
+ // available to another task until it has also been given back
+ // three times. Again it is unlikely that real code would have
+ // these calls sequentially, it would be more likely that the calls
+ // to xSemaphoreGiveRecursive() would be called as a call stack
+ // unwound. This is just for demonstrative purposes.
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+
+ // Now the mutex can be taken by other tasks.
+ }
+ else
+ {
+ // We could not obtain the mutex and can therefore not access
+ // the shared resource safely.
+ }
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+ #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreGiveFromISR(
+ SemaphoreHandle_t xSemaphore,
+ BaseType_t *pxHigherPriorityTaskWoken
+ )</pre>
+ *
+ * <i>Macro</i> to release a semaphore. The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released. This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT 10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // We want this task to run every 10 ticks of a timer. The semaphore
+ // was created before this task was started.
+
+ // Block waiting for the semaphore to become available.
+ if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+ {
+ // It is time to execute.
+
+ // ...
+
+ // We have finished our task. Return to the top of the loop where
+ // we will block on the semaphore until it is time to execute
+ // again. Note when using the semaphore for synchronisation with an
+ // ISR in this manner there is no need to 'give' the semaphore back.
+ }
+ }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+ // A timer tick has occurred.
+
+ // ... Do other time functions.
+
+ // Is it time for vATask () to run?
+ xHigherPriorityTaskWoken = pdFALSE;
+ ucLocalTickCount++;
+ if( ucLocalTickCount >= TICKS_TO_WAIT )
+ {
+ // Unblock the task by releasing the semaphore.
+ xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+ // Reset the count so we release the semaphore again in 10 ticks time.
+ ucLocalTickCount = 0;
+ }
+
+ if( xHigherPriorityTaskWoken != pdFALSE )
+ {
+ // We can force a context switch here. Context switching from an
+ // ISR uses port specific syntax. Check the demo task for your port
+ // to find the syntax required.
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreTakeFromISR(
+ SemaphoreHandle_t xSemaphore,
+ BaseType_t *pxHigherPriorityTaskWoken
+ )</pre>
+ *
+ * <i>Macro</i> to take a semaphore from an ISR. The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation. It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken. This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored. If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function. (see
+ * http://www.freertos.org/a00111.html). If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned. If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ // This is a macro so pass the variable in directly.
+ xSemaphore = xSemaphoreCreateMutex();
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored. If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function. (see
+ * http://www.freertos.org/a00111.html). If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned. If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ // A mutex cannot be used before it has been created. xMutexBuffer is
+ // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+ // attempted.
+ xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+ // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored. If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function. (see
+ * http://www.freertos.org/a00111.html). If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also 'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore. Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ // This is a macro so pass the variable in directly.
+ xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+ #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored. If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function. (see
+ * http://www.freertos.org/a00111.html). If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also 'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned. If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ // A recursive semaphore cannot be used before it is created. Here a
+ // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+ // The address of xMutexBuffer is passed into the function, and will hold
+ // the mutexes data structures - so no dynamic memory allocation will be
+ // attempted.
+ xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+ // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+ #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored. If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function. (see
+ * http://www.freertos.org/a00111.html). If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore. xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ * In this usage scenario an event handler will 'give' a semaphore each time
+ * an event occurs (incrementing the semaphore count value), and a handler
+ * task will 'take' a semaphore each time it processes an event
+ * (decrementing the semaphore count value). The count value is therefore
+ * the difference between the number of events that have occurred and the
+ * number that have been processed. In this case it is desirable for the
+ * initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ * In this usage scenario the count value indicates the number of resources
+ * available. To obtain control of a resource a task must first obtain a
+ * semaphore - decrementing the semaphore count value. When the count value
+ * reaches zero there are no free resources. When a task finishes with the
+ * resource it 'gives' the semaphore back - incrementing the semaphore count
+ * value. In this case it is desirable for the initial count value to be
+ * equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached. When the
+ * semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ * created.
+ *
+ * @return Handle to the created semaphore. Null if the semaphore could not be
+ * created.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+ // The max value to which the semaphore can count should be 10, and the
+ // initial value assigned to the count should be 0.
+ xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored. If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function. (see
+ * http://www.freertos.org/a00111.html). If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory. xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ * In this usage scenario an event handler will 'give' a semaphore each time
+ * an event occurs (incrementing the semaphore count value), and a handler
+ * task will 'take' a semaphore each time it processes an event
+ * (decrementing the semaphore count value). The count value is therefore
+ * the difference between the number of events that have occurred and the
+ * number that have been processed. In this case it is desirable for the
+ * initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ * In this usage scenario the count value indicates the number of resources
+ * available. To obtain control of a resource a task must first obtain a
+ * semaphore - decrementing the semaphore count value. When the count value
+ * reaches zero there are no free resources. When a task finishes with the
+ * resource it 'gives' the semaphore back - incrementing the semaphore count
+ * value. In this case it is desirable for the initial count value to be
+ * equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached. When the
+ * semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ * created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned. If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Counting semaphore cannot be used before they have been created. Create
+ // a counting semaphore using xSemaphoreCreateCountingStatic(). The max
+ // value to which the semaphore can count is 10, and the initial value
+ // assigned to the count will be 0. The address of xSemaphoreBuffer is
+ // passed in and will be used to hold the semaphore structure, so no dynamic
+ // memory allocation will be used.
+ xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+ // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+ // is no need to check its value.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * Delete a semaphore. This function must be used with care. For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );</pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value. If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..fb5ed15
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten. Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+ /* Only the current stack state is to be checked. */
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+ /* Only the current stack state is to be checked. */
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
+ const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \
+ \
+ if( ( pulStack[ 0 ] != ulCheckValue ) || \
+ ( pulStack[ 1 ] != ulCheckValue ) || \
+ ( pulStack[ 2 ] != ulCheckValue ) || \
+ ( pulStack[ 3 ] != ulCheckValue ) ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+ #define taskCHECK_FOR_STACK_OVERFLOW() \
+ { \
+ int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \
+ static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+ \
+ \
+ pcEndOfStack -= sizeof( ucExpectedStackBytes ); \
+ \
+ /* Has the extremity of the task stack ever been written over? */ \
+ if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+ #define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..5f9e012
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,855 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another. Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced. For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+<pre>
+StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+</pre>
+ *
+ * Creates a new stream buffer using dynamically allocated memory. See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state. For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires. As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires. If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available. Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used. It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area. A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+<pre>
+
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+ // Create a stream buffer that can hold 100 bytes. The memory used to hold
+ // both the stream buffer structure and the data in the stream buffer is
+ // allocated dynamically.
+ xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+ if( xStreamBuffer == NULL )
+ {
+ // There was not enough heap memory space available to create the
+ // stream buffer.
+ }
+ else
+ {
+ // The stream buffer was created successfully and can now be used.
+ }
+}
+</pre>
+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ uint8_t *pucStreamBufferStorageArea,
+ StaticStreamBuffer_t *pxStaticStreamBuffer );
+</pre>
+ * Creates a new stream buffer using statically allocated memory. See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state. For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires. As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires. If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available. Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used. It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big. This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+<pre>
+
+// Used to dimension the array used to hold the streams. The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+ xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+ xTriggerLevel,
+ ucBufferStorage,
+ &xStreamBufferStruct );
+
+ // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+ // reference the created stream buffer in other stream buffer API calls.
+
+ // Other code that uses the stream buffer can go here.
+}
+
+</pre>
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait );
+</pre>
+ *
+ * Sends bytes to a stream buffer. The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task. Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes. The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency. The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible. A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer. If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+<pre>
+void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+ // Send an array to the stream buffer, blocking for a maximum of 100ms to
+ // wait for enough space to be available in the stream buffer.
+ xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+ if( xBytesSent != sizeof( ucArrayToSend ) )
+ {
+ // The call to xStreamBufferSend() times out before there was enough
+ // space in the buffer for the data to be written, but it did
+ // successfully write xBytesSent bytes.
+ }
+
+ // Send the string to the stream buffer. Return immediately if there is not
+ // enough space in the buffer.
+ xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+ if( xBytesSent != strlen( pcStringToSend ) )
+ {
+ // The entire string could not be added to the stream buffer because
+ // there was not enough free space in the buffer, but xBytesSent bytes
+ // were sent. Could try again to send the remaining bytes.
+ }
+}
+</pre>
+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task. Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will
+ * have a task blocked on it waiting for data. Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state. If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE. If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited. This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function. See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+<pre>
+// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+ // Attempt to send the string to the stream buffer.
+ xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+ ( void * ) pcStringToSend,
+ strlen( pcStringToSend ),
+ &xHigherPriorityTaskWoken );
+
+ if( xBytesSent != strlen( pcStringToSend ) )
+ {
+ // There was not enough free space in the stream buffer for the entire
+ // string to be written, ut xBytesSent bytes were written.
+ }
+
+ // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ // xStreamBufferSendFromISR() then a task that has a priority above the
+ // priority of the currently executing task was unblocked and a context
+ // switch should be performed to ensure the ISR returns to the unblocked
+ // task. In most FreeRTOS ports this is done by simply passing
+ // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ // variables value, and perform the context switch if necessary. Check the
+ // documentation for the port in use for port specific instructions.
+ taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait );
+</pre>
+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader). It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers. If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0. Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task. Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter. This sets the maximum number of bytes to receive in one
+ * call. xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty. xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero. The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h. A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+<pre>
+void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+ // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+ // Wait in the Blocked state (so not using any CPU processing time) for a
+ // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+ // available.
+ xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+ ( void * ) ucRxData,
+ sizeof( ucRxData ),
+ xBlockTime );
+
+ if( xReceivedBytes > 0 )
+ {
+ // A ucRxData contains another xRecievedBytes bytes of data, which can
+ // be processed here....
+ }
+}
+</pre>
+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter. This sets the maximum number of bytes to receive in one
+ * call. xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available. Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state. If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited. That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function. See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+<pre>
+// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+ // Receive the next stream from the stream buffer.
+ xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+ ( void * ) ucRxData,
+ sizeof( ucRxData ),
+ &xHigherPriorityTaskWoken );
+
+ if( xReceivedBytes > 0 )
+ {
+ // ucRxData contains xReceivedBytes read from the stream buffer.
+ // Process the stream here....
+ }
+
+ // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ // xStreamBufferReceiveFromISR() then a task that has a priority above the
+ // priority of the currently executing task was unblocked and a context
+ // switch should be performed to ensure the ISR returns to the unblocked
+ // task. In most FreeRTOS ports this is done by simply passing
+ // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ // variables value, and perform the context switch if necessary. Check the
+ // documentation for the port in use for port specific instructions.
+ taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+</pre>
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see if it is full. A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned. Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see if it is empty. A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned. Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Resets a stream buffer to its initial, empty, state. Any data that was in
+ * the stream buffer is discarded. A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned. If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+</pre>
+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+</pre>
+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state. For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires. As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires. If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available. Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used. It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned. Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer. If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state. xStreamBufferSendCompletedFromISR() does the same
+ * thing. It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR(). If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+<pre>
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+</pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer. If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR()
+ * does the same thing. It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR(). If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ BaseType_t xIsMessageBuffer,
+ uint8_t * const pucStreamBufferStorageArea,
+ StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+ void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+ UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+ uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif /* !defined( STREAM_BUFFER_H ) */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..4041bbf
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2421 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.2.0"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 2
+#define tskKERNEL_VERSION_BUILD 0
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced. For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+ eRunning = 0, /* A task is querying the state of itself, so must be running. */
+ eReady, /* The task being queried is in a read or pending ready list. */
+ eBlocked, /* The task being queried is in the Blocked state. */
+ eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+ eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */
+ eInvalid /* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+ eNoAction = 0, /* Notify the task without updating its notify value. */
+ eSetBits, /* Set bits in the task's notification value. */
+ eIncrement, /* Increment the task's notification value. */
+ eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+ eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+ BaseType_t xOverflowCount;
+ TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+ void *pvBaseAddress;
+ uint32_t ulLengthInBytes;
+ uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+ TaskFunction_t pvTaskCode;
+ const char * const pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ configSTACK_DEPTH_TYPE usStackDepth;
+ void *pvParameters;
+ UBaseType_t uxPriority;
+ StackType_t *puxStackBuffer;
+ MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+ #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ StaticTask_t * const pxTaskBuffer;
+ #endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+ TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */
+ const char *pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ UBaseType_t xTaskNumber; /* A number unique to the task. */
+ eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */
+ UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */
+ UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+ uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See http://www.freertos.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+ StackType_t *pxStackBase; /* Points to the lowest address of the task's stack area. */
+ configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+ eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+ eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */
+ eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task. This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD() portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region. Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL() portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region. Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL() portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreate(
+ TaskFunction_t pvTaskCode,
+ const char * const pcName,
+ configSTACK_DEPTH_TYPE usStackDepth,
+ void *pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t *pvCreatedTask
+ );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory. The first block is used to hold the task's data structures. The
+ * second block is used by the task as its stack. If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function. (see
+ * http://www.freertos.org/a00111.html). If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory. xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map. Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function. Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task. This is mainly used to
+ * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes. For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run. Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ <pre>
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+ }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+ // Create the task, storing the handle. Note that the passed parameter ucParameterToPass
+ // must exist for the lifetime of the task, so in this case is declared static. If it was just an
+ // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+ // the new task attempts to access it.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+ configASSERT( xHandle );
+
+ // Use the handle to delete the task.
+ if( xHandle != NULL )
+ {
+ vTaskDelete( xHandle );
+ }
+ }
+ </pre>
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+ const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const configSTACK_DEPTH_TYPE usStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+ const char * const pcName,
+ uint32_t ulStackDepth,
+ void *pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t *pxStackBuffer,
+ StaticTask_t *pxTaskBuffer );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory. The first block is used to hold the task's data structures. The
+ * second block is used by the task as its stack. If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function. (see
+ * http://www.freertos.org/a00111.html). If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory. xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function. Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task. This is mainly used to
+ * facilitate debugging. The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes. For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned. If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+ <pre>
+
+ // Dimensions the buffer that the task being created will use as its stack.
+ // NOTE: This is the number of words the stack will hold, not the number of
+ // bytes. For example, if each stack item is 32-bits, and this is set to 100,
+ // then 400 bytes (100 * 32-bits) will be allocated.
+ #define STACK_SIZE 200
+
+ // Structure that will hold the TCB of the task being created.
+ StaticTask_t xTaskBuffer;
+
+ // Buffer that the task being created will use as its stack. Note this is
+ // an array of StackType_t variables. The size of StackType_t is dependent on
+ // the RTOS port.
+ StackType_t xStack[ STACK_SIZE ];
+
+ // Function that implements the task being created.
+ void vTaskCode( void * pvParameters )
+ {
+ // The parameter value is expected to be 1 as 1 is passed in the
+ // pvParameters value in the call to xTaskCreateStatic().
+ configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+ for( ;; )
+ {
+ // Task code goes here.
+ }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle = NULL;
+
+ // Create the task without using any dynamic memory allocation.
+ xHandle = xTaskCreateStatic(
+ vTaskCode, // Function that implements the task.
+ "NAME", // Text name for the task.
+ STACK_SIZE, // Stack size in words, not bytes.
+ ( void * ) 1, // Parameter passed into the task.
+ tskIDLE_PRIORITY,// Priority at which the task is created.
+ xStack, // Array to use as the task's stack.
+ &xTaskBuffer ); // Variable to hold the task's data structure.
+
+ // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+ // been created, and xHandle will be the task's handle. Use the handle
+ // to suspend the task.
+ vTaskSuspend( xHandle );
+ }
+ </pre>
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+ const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const uint32_t ulStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>
+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ <pre>
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+ vATask, // pvTaskCode - the function that implements the task.
+ "ATask", // pcName - just a text name for the task to assist debugging.
+ 100, // usStackDepth - the stack size DEFINED IN WORDS.
+ NULL, // pvParameters - passed into the task function as the function parameters.
+ ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+ // xRegions - Allocate up to three separate memory regions for access by
+ // the task, with appropriate access permissions. Different processors have
+ // different memory alignment requirements - refer to the FreeRTOS documentation
+ // for full information.
+ {
+ // Base address Length Parameters
+ { cReadWriteArray, 32, portMPU_REGION_READ_WRITE },
+ { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY },
+ { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE }
+ }
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+ // Create a task from the const structure defined above. The task handle
+ // is requested (the second parameter is not NULL) but in this case just for
+ // demonstration purposes as its not actually used.
+ xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+ // Start the scheduler.
+ vTaskStartScheduler();
+
+ // Will only get here if there was insufficient memory to create the idle
+ // and/or timer task.
+ for( ;; );
+}
+ </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+ BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>
+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory. The first block is used to hold the task's data structures. The
+ * second block is used by the task as its stack. If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function. If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions. If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ <pre>
+// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1. The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+ vATask, // pvTaskCode - the function that implements the task.
+ "ATask", // pcName - just a text name for the task to assist debugging.
+ 100, // usStackDepth - the stack size DEFINED IN WORDS.
+ NULL, // pvParameters - passed into the task function as the function parameters.
+ ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+ // xRegions - Allocate up to three separate memory regions for access by
+ // the task, with appropriate access permissions. Different processors have
+ // different memory alignment requirements - refer to the FreeRTOS documentation
+ // for full information.
+ {
+ // Base address Length Parameters
+ { cReadWriteArray, 32, portMPU_REGION_READ_WRITE },
+ { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY },
+ { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE }
+ }
+
+ &xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+ // Create a task from the const structure defined above. The task handle
+ // is requested (the second parameter is not NULL) but in this case just for
+ // demonstration purposes as its not actually used.
+ xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+ // Start the scheduler.
+ vTaskStartScheduler();
+
+ // Will only get here if there was insufficient memory to create the idle
+ // and/or timer task.
+ for( ;; );
+}
+ </pre>
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted(). These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+ <pre>
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array. The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+ // Base address Length Parameters
+ { ucOneKByte, 1024, portMPU_REGION_READ_WRITE },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
+};
+
+void vATask( void *pvParameters )
+{
+ // This task was created such that it has access to certain regions of
+ // memory as defined by the MPU configuration. At some point it is
+ // desired that these MPU regions are replaced with that defined in the
+ // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions()
+ // for this purpose. NULL is used as the task handle to indicate that this
+ // function should modify the MPU regions of the calling task.
+ vTaskAllocateMPURegions( NULL, xAltRegions );
+
+ // Now the task can continue its function, but from this point on can only
+ // access its stack and the ucOneKByte array (unless any other statically
+ // defined or shared regions have been declared elsewhere).
+}
+ </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management. The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE: The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted. It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete (). Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted. Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+ <pre>
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create the task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // Use the handle to delete the task.
+ vTaskDelete( xHandle );
+ }
+ </pre>
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a task for a given number of ticks. The actual time that the
+ * task remains blocked depends on the tick rate. The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called. For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes. See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution. It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+ for( ;; )
+ {
+ // Simply toggle the LED every 500ms, blocking between each toggle.
+ vToggleLED();
+ vTaskDelay( xDelay );
+ }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>
+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time. This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked. The variable must be initialised with the current time
+ * prior to its first use (see the example below). Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period. The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+ <pre>
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+ // Initialise the xLastWakeTime variable with the current time.
+ xLastWakeTime = xTaskGetTickCount ();
+ for( ;; )
+ {
+ // Wait for the next cycle.
+ vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+ // Perform action here.
+ }
+ }
+ </pre>
+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskAbortDelay( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event. The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called. If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned. Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried. Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+ <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to obtain the priority of the created task.
+ // It was created with tskIDLE_PRIORITY, but may have changed
+ // it itself.
+ if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+ {
+ // The task has changed it's priority.
+ }
+
+ // ...
+
+ // Is our priority higher than the created task?
+ if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+ {
+ // Our priority (obtained using NULL handle) is higher.
+ }
+ }
+ </pre>
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );</pre>
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task. States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called. Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );</pre>
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available. See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried. If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried. Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped. The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried. Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure. To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+ <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+ // Obtain the handle of a task from its name.
+ xHandle = xTaskGetHandle( "Task_Name" );
+
+ // Check the handle is not NULL.
+ configASSERT( xHandle );
+
+ // Use the handle to obtain further information about the task.
+ vTaskGetInfo( xHandle,
+ &xTaskDetails,
+ pdTRUE, // Include the high water mark in xTaskDetails.
+ eInvalid ); // Include the task state in xTaskDetails.
+ }
+ </pre>
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+ <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to raise the priority of the created task.
+ vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+ // ...
+
+ // Use a NULL handle to raise our priority to the same value.
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+ </pre>
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task. When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+ <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to suspend the created task.
+ vTaskSuspend( xHandle );
+
+ // ...
+
+ // The created task will not run during this period, unless
+ // another task calls vTaskResume( xHandle ).
+
+ //...
+
+
+ // Suspend ourselves.
+ vTaskSuspend( NULL );
+
+ // We cannot get here unless another task calls vTaskResume
+ // with our handle as the parameter.
+ }
+ </pre>
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+ <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to suspend the created task.
+ vTaskSuspend( xHandle );
+
+ // ...
+
+ // The created task will not run during this period, unless
+ // another task calls vTaskResume( xHandle ).
+
+ //...
+
+
+ // Resume the suspended task ourselves.
+ vTaskResume( xHandle );
+
+ // The created task will once again get microcontroller processing
+ // time in accordance with its priority within the system.
+ }
+ </pre>
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available. See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskStartScheduler( void );</pre>
+ *
+ * Starts the real time kernel tick processing. After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+ <pre>
+ void vAFunction( void )
+ {
+ // Create at least one task before starting the kernel.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+ // Start the real time kernel with preemption.
+ vTaskStartScheduler ();
+
+ // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+ </pre>
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskEndScheduler( void );</pre>
+ *
+ * NOTE: At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick. All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop. Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port). This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+ <pre>
+ void vTaskCode( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+
+ // At some point we want to end the real time kernel processing
+ // so call ...
+ vTaskEndScheduler ();
+ }
+ }
+
+ void vAFunction( void )
+ {
+ // Create at least one task before starting the kernel.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+ // Start the real time kernel with preemption.
+ vTaskStartScheduler ();
+
+ // Will only get here when the vTaskCode () task has called
+ // vTaskEndScheduler (). When we get here we are back to single task
+ // execution.
+ }
+ </pre>
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspendAll( void );</pre>
+ *
+ * Suspends the scheduler without disabling interrupts. Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+ <pre>
+ void vTask1( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+
+ // ...
+
+ // At some point the task wants to perform a long operation during
+ // which it does not want to get swapped out. It cannot use
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ // operation may cause interrupts to be missed - including the
+ // ticks.
+
+ // Prevent the real time kernel swapping out the task.
+ vTaskSuspendAll ();
+
+ // Perform the operation here. There is no need to use critical
+ // sections as we have all the microcontroller processing time.
+ // During this time interrupts will still operate and the kernel
+ // tick count will be maintained.
+
+ // ...
+
+ // The operation is complete. Restart the kernel.
+ xTaskResumeAll ();
+ }
+ }
+ </pre>
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskResumeAll( void );</pre>
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ * returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ <pre>
+ void vTask1( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+
+ // ...
+
+ // At some point the task wants to perform a long operation during
+ // which it does not want to get swapped out. It cannot use
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ // operation may cause interrupts to be missed - including the
+ // ticks.
+
+ // Prevent the real time kernel swapping out the task.
+ vTaskSuspendAll ();
+
+ // Perform the operation here. There is no need to use critical
+ // sections as we have all the microcontroller processing time.
+ // During this time interrupts will still operate and the real
+ // time kernel tick count will be maintained.
+
+ // ...
+
+ // The operation is complete. Restart the kernel. We want to force
+ // a context switch - but there is no point if resuming the scheduler
+ // caused a context switch already.
+ if( !xTaskResumeAll () )
+ {
+ taskYIELD ();
+ }
+ }
+ }
+ </pre>
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCount( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks. A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>char *pcTaskGetName( TaskHandle_t xTaskToQuery );</PRE>
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery. A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );</PRE>
+ *
+ * NOTE: This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found. INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask. That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started. The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type. Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type. It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask. That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started. The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type. Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type. It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error. This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+ #if configUSE_APPLICATION_TASK_TAG == 1
+ /**
+ * task.h
+ * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>
+ *
+ * Sets pxHookFunction to be the task hook function used by the task xTask.
+ * Passing xTask as NULL has the effect of setting the calling tasks hook
+ * function.
+ */
+ void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+ /**
+ * task.h
+ * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>
+ *
+ * Returns the pxHookFunction value assigned to the task xTask. Do not
+ * call from an interrupt service routine - call
+ * xTaskGetApplicationTaskTagFromISR() instead.
+ */
+ TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+ /**
+ * task.h
+ * <pre>void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );</pre>
+ *
+ * Returns the pxHookFunction value assigned to the task xTask. Can
+ * be called from an interrupt service routine.
+ */
+ TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+ #endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+ /* Each task contains an array of pointers that is dimensioned by the
+ configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The
+ kernel does not use the pointers itself, so the application writer can use
+ the pointers for any purpose they wish. The following two functions are
+ used to set and query a pointer respectively. */
+ void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+ void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>
+ *
+ * Calls the hook function associated with xTask. Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants. The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task. It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system. TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task. See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE: This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS. The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter. The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState(). This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+ <pre>
+ // This example demonstrates how a human readable table of run time stats
+ // information is generated from raw data provided by uxTaskGetSystemState().
+ // The human readable table is written to pcWriteBuffer
+ void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ {
+ TaskStatus_t *pxTaskStatusArray;
+ volatile UBaseType_t uxArraySize, x;
+ uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+ // Make sure the write buffer does not contain a string.
+ *pcWriteBuffer = 0x00;
+
+ // Take a snapshot of the number of tasks in case it changes while this
+ // function is executing.
+ uxArraySize = uxTaskGetNumberOfTasks();
+
+ // Allocate a TaskStatus_t structure for each task. An array could be
+ // allocated statically at compile time.
+ pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+ if( pxTaskStatusArray != NULL )
+ {
+ // Generate raw status information about each task.
+ uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+ // For percentage calculations.
+ ulTotalRunTime /= 100UL;
+
+ // Avoid divide by zero errors.
+ if( ulTotalRunTime > 0 )
+ {
+ // For each populated position in the pxTaskStatusArray array,
+ // format the raw data as human readable ASCII data
+ for( x = 0; x < uxArraySize; x++ )
+ {
+ // What percentage of the total run time has the task used?
+ // This will always be rounded down to the nearest integer.
+ // ulTotalRunTimeDiv100 has already been divided by 100.
+ ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+ if( ulStatsAsPercentage > 0UL )
+ {
+ sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ }
+ else
+ {
+ // If the percentage is zero here then the task has
+ // consumed less than 1% of the total run time.
+ sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
+
+ pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+ }
+ }
+
+ // The array is no longer needed, free the memory it consumes.
+ vPortFree( pxTaskStatusArray );
+ }
+ }
+ </pre>
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available. See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration. It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications. Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms. An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form. This buffer is assumed to be large
+ * enough to contain the generated report. Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available. The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively. The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration. It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task. The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications. Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms. An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form. This buffer is assumed to be large enough to
+ * contain the generated report. Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* <PRE>TickType_t xTaskGetIdleRunTimeCounter( void );</PRE>
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available. The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively. The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task. The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task. This is the amount of time the
+* idle task has actually been executing. The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object. Examples of such
+ * objects are queues, semaphores, mutexes and event groups. Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value. In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value. The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified. The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification. How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all. Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue. xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented. ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending). xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS. If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated. ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * pulPreviousNotificationValue -
+ * Can be used to pass out the subject task's notification value before any
+ * bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction. See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object. Examples of such
+ * objects are queues, semaphores, mutexes and event groups. Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value. In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value. The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified. The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification. How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all. Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue. xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented. ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending). xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS. If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated. ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task. If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited. How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction. See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object. Examples of such
+ * objects are queues, semaphores, mutexes and event groups. Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value. In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake(). If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value. The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0. Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter. Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared). Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits. Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function. Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called. The task
+ * will not consume any processing time while it is in the Blocked state. This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned. Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object. Examples of such
+ * objects are queues, semaphores, mutexes and event groups. Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value. In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified. The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object. Examples of such
+ * objects are queues, semaphores, mutexes and event groups. Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value. In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified. The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task. If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited. How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object. Examples of such
+ * objects are queues, semaphores, mutexes and event groups. Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value. In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative. Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero. The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits. In this way the
+ * notification value acts like a counting semaphore. If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits. In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called. The task will not consume any processing
+ * time while it is in the Blocked state. This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );</pre>
+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered. Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list. If a non-zero value is returned then a context switch is
+ * required because either:
+ * + A task was removed from a blocked list because its timeout had expired,
+ * or
+ * + Time slicing is in use and there is a task of equal priority to the
+ * currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks. The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur. This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order. It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority. In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods. When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section. It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered. eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only. Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only. Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..5abb7f1
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1295 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue. These are to
+be used solely through the macros that make up the public software timer API,
+as defined below. The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET ( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP ( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced. For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( const char * const pcTimerName,
+ * TickType_t xTimerPeriodInTicks,
+ * UBaseType_t uxAutoReload,
+ * void * pvTimerID,
+ * TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored. If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function. (see
+ * http://www.freertos.org/a00111.html). If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer. xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer. This is done
+ * purely to assist debugging. The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period. The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds. For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned. If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * // Optionally do something if the pxTimer parameter is NULL.
+ * configASSERT( pxTimer );
+ *
+ * // Which timer expired?
+ * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ * // Increment the number of times that pxTimer has expired.
+ * lExpireCounters[ lArrayIndex ] += 1;
+ *
+ * // If the timer has expired 10 times then stop it from running.
+ * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ * {
+ * // Do not use a block time if calling a timer API function from a
+ * // timer callback function, as doing so could cause a deadlock!
+ * xTimerStop( pxTimer, 0 );
+ * }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ * // Create then start some timers. Starting the timers before the scheduler
+ * // has been started means the timers will start running immediately that
+ * // the scheduler starts.
+ * for( x = 0; x < NUM_TIMERS; x++ )
+ * {
+ * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel.
+ * ( 100 * x ), // The timer period in ticks.
+ * pdTRUE, // The timers will auto-reload themselves when they expire.
+ * ( void * ) x, // Assign each timer a unique id equal to its array index.
+ * vTimerCallback // Each timer calls the same callback when it expires.
+ * );
+ *
+ * if( xTimers[ x ] == NULL )
+ * {
+ * // The timer was not created.
+ * }
+ * else
+ * {
+ * // Start the timer. No block time is specified, and even if one was
+ * // it would be ignored because the scheduler has not yet been
+ * // started.
+ * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ * {
+ * // The timer could not be set into the Active state.
+ * }
+ * }
+ * }
+ *
+ * // ...
+ * // Create tasks here.
+ * // ...
+ *
+ * // Starting the scheduler will start the timers running as they have already
+ * // been set into the active state.
+ * vTaskStartScheduler();
+ *
+ * // Should not reach here.
+ * for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const TickType_t xTimerPeriodInTicks,
+ const UBaseType_t uxAutoReload,
+ void * const pvTimerID,
+ TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * TickType_t xTimerPeriodInTicks,
+ * UBaseType_t uxAutoReload,
+ * void * pvTimerID,
+ * TimerCallbackFunction_t pxCallbackFunction,
+ * StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored. If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function. (see
+ * http://www.freertos.org/a00111.html). If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer. xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer. This is done
+ * purely to assist debugging. The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period. The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds. For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned. If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created. After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ * // Obtain the address of the variable to increment from the timer ID.
+ * puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ * // Increment the variable to show the timer callback has executed.
+ * ( *puxVariableToIncrement )++;
+ *
+ * // If this callback has executed the required number of times, stop the
+ * // timer.
+ * if( *puxVariableToIncrement == 5 )
+ * {
+ * // This is called from a timer callback so must not block.
+ * xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ * }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ * // Create the software time. xTimerCreateStatic() has an extra parameter
+ * // than the normal xTimerCreate() API function. The parameter is a pointer
+ * // to the StaticTimer_t structure that will hold the software timer
+ * // structure. If the parameter is passed as NULL then the structure will be
+ * // allocated dynamically, just as if xTimerCreate() had been called.
+ * xTimer = xTimerCreateStatic( "T1", // Text name for the task. Helps debugging only. Not used by FreeRTOS.
+ * xTimerPeriod, // The period of the timer in ticks.
+ * pdTRUE, // This is an auto-reload timer.
+ * ( void * ) &uxVariableToIncrement, // A variable incremented by the software timer's callback function
+ * prvTimerCallback, // The function to execute when the timer expires.
+ * &xTimerBuffer ); // The buffer that will hold the software timer structure.
+ *
+ * // The scheduler has not started yet so a block time is not used.
+ * xReturned = xTimerStart( xTimer, 0 );
+ *
+ * // ...
+ * // Create tasks here.
+ * // ...
+ *
+ * // Starting the scheduler will start the timers running as they have already
+ * // been set into the active state.
+ * vTaskStartScheduler();
+ *
+ * // Should not reach here.
+ * for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const TickType_t xTimerPeriodInTicks,
+ const UBaseType_t uxAutoReload,
+ void * const pvTimerID,
+ TimerCallbackFunction_t pxCallbackFunction,
+ StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ * 1) It has been created but not started, or
+ * 2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant. A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ * {
+ * // xTimer is active, do something.
+ * }
+ * else
+ * {
+ * // xTimer is not active, do something else.
+ * }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task. It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function. If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state. If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called. xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called. The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called. xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system. The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( TimerHandle_t xTimer,
+ * TickType_t xNewPeriod,
+ * TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds. For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called. xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue. When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system. The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created. If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted. If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ * {
+ * // xTimer is already active - delete it.
+ * xTimerDelete( xTimer );
+ * }
+ * else
+ * {
+ * // xTimer is not active, change its period to 500ms. This will also
+ * // cause the timer to start. Block for a maximum of 100 ticks if the
+ * // change period command cannot immediately be sent to the timer
+ * // command queue.
+ * if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ * {
+ * // The command was successfully sent.
+ * }
+ * else
+ * {
+ * // The command could not be sent, even after waiting for 100 ticks
+ * // to pass. Take appropriate action here.
+ * }
+ * }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called. xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system. The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function. If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called. If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state. If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called. xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called. The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off. In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer. In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * // The timer expired, therefore 5 seconds must have passed since a key
+ * // was pressed. Switch off the LCD back-light.
+ * vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ * // Ensure the LCD back-light is on, then reset the timer that is
+ * // responsible for turning the back-light off after 5 seconds of
+ * // key inactivity. Wait 10 ticks for the command to be successfully sent
+ * // if it cannot be sent immediately.
+ * vSetBacklightState( BACKLIGHT_ON );
+ * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ * {
+ * // The reset command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ * // Create then start the one-shot timer that is responsible for turning
+ * // the back-light off if no keys are pressed within a 5 second period.
+ * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel.
+ * ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ * pdFALSE, // The timer is a one-shot timer.
+ * 0, // The id is not used by the callback so can take any value.
+ * vBacklightTimerCallback // The callback function that switches the LCD back-light off.
+ * );
+ *
+ * if( xBacklightTimer == NULL )
+ * {
+ * // The timer was not created.
+ * }
+ * else
+ * {
+ * // Start the timer. No block time is specified, and even if one was
+ * // it would be ignored because the scheduler has not yet been
+ * // started.
+ * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ * {
+ * // The timer could not be set into the Active state.
+ * }
+ * }
+ *
+ * // ...
+ * // Create tasks here.
+ * // ...
+ *
+ * // Starting the scheduler will start the timer running as it has already
+ * // been set into the active state.
+ * vTaskStartScheduler();
+ *
+ * // Should not reach here.
+ * for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( TimerHandle_t xTimer,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state. If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function. If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue. pdPASS will be returned if the command was
+ * successfully sent to the timer command queue. When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called. The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created. When a
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off. In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer. In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * // The timer expired, therefore 5 seconds must have passed since a key
+ * // was pressed. Switch off the LCD back-light.
+ * vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // Ensure the LCD back-light is on, then restart the timer that is
+ * // responsible for turning the back-light off after 5 seconds of
+ * // key inactivity. This is an interrupt service routine so can only
+ * // call FreeRTOS API functions that end in "FromISR".
+ * vSetBacklightState( BACKLIGHT_ON );
+ *
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ * // as both cause the timer to re-calculate its expiry time.
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ * // declared (in this function).
+ * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The start command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // Perform the rest of the key processing here.
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( TimerHandle_t xTimer,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state. If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function. If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue. pdPASS will be returned if the command was
+ * successfully sent to the timer command queue. When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system. The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started. When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // The interrupt has occurred - simply stop the timer.
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ * // (within this function). As this is an interrupt service routine, only
+ * // FreeRTOS API functions that end in "FromISR" can be used.
+ * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The stop command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ * TickType_t xNewPeriod,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds. For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue. pdPASS will be returned if the
+ * command was successfully sent to the timer command queue. When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system. The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started. When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // The interrupt has occurred - change the period of xTimer to 500ms.
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ * // (within this function). As this is an interrupt service routine, only
+ * // FreeRTOS API functions that end in "FromISR" can be used.
+ * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The command to change the timers period was not executed
+ * // successfully. Take appropriate action here.
+ * }
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( TimerHandle_t xTimer,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state. If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function. If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue. pdPASS will be returned if the command was
+ * successfully sent to the timer command queue. When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called. The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created. When a
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off. In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer. In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * // The timer expired, therefore 5 seconds must have passed since a key
+ * // was pressed. Switch off the LCD back-light.
+ * vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // Ensure the LCD back-light is on, then reset the timer that is
+ * // responsible for turning the back-light off after 5 seconds of
+ * // key inactivity. This is an interrupt service routine so can only
+ * // call FreeRTOS API functions that end in "FromISR".
+ * vSetBacklightState( BACKLIGHT_ON );
+ *
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ * // as both cause the timer to re-calculate its expiry time.
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ * // declared (in this function).
+ * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The reset command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // Perform the rest of the key processing here.
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ * void *pvParameter1,
+ * uint32_t ulParameter2,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic. In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function. This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task. The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task. If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits. For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The callback function that will execute in the context of the daemon task.
+ * // Note callback functions must all use this same prototype.
+ * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ * {
+ * BaseType_t xInterfaceToService;
+ *
+ * // The interface that requires servicing is passed in the second
+ * // parameter. The first parameter is not used in this case.
+ * xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ * // ...Perform the processing here...
+ * }
+ *
+ * // An ISR that receives data packets from multiple interfaces
+ * void vAnISR( void )
+ * {
+ * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ * // Query the hardware to determine which interface needs processing.
+ * xInterfaceToService = prvCheckInterfaces();
+ *
+ * // The actual processing is to be deferred to a task. Request the
+ * // vProcessInterface() callback function is executed, passing in the
+ * // number of the interface that needs processing. The interface to
+ * // service is passed in the second parameter. The first parameter is
+ * // not used in this case.
+ * xHigherPriorityTaskWoken = pdFALSE;
+ * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ * // switch should be requested. The macro used is port specific and will
+ * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ * // the documentation page for the port being used.
+ * portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+ * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+ * void *pvParameter1,
+ * uint32_t ulParameter2,
+ * TickType_t xTicksToWait );
+ *
+ *
+ * Used to defer the execution of a function to the RTOS daemon task (the timer
+ * service task, hence this function is implemented in timers.c and is prefixed
+ * with 'Timer').
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task. The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param xTicksToWait Calling this function will result in a message being
+ * sent to the timer daemon task on a queue. xTicksToWait is the amount of
+ * time the calling task should remain in the Blocked state (so not using any
+ * processing time) for space to become available on the timer queue if the
+ * queue is found to be full.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an autoreload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire. If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned. If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+ void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+ UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/list.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..9875b90
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include <stdlib.h>
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+ /* The list structure contains a list item which is used to mark the
+ end of the list. To initialise the list the list end is inserted
+ as the only list entry. */
+ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+
+ /* The list end value is the highest possible value in the list to
+ ensure it remains at the end of the list. */
+ pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+ /* The list end next and previous pointers point to itself so we know
+ when the list is empty. */
+ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+
+ pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+ /* Write known values into the list if
+ configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+ listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+ /* Make sure the list item is not recorded as being on a list. */
+ pxItem->pxContainer = NULL;
+
+ /* Write known values into the list item if
+ configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+ listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+ /* Only effective when configASSERT() is also defined, these tests may catch
+ the list data structures being overwritten in memory. They will not catch
+ data errors caused by incorrect configuration or use of FreeRTOS. */
+ listTEST_LIST_INTEGRITY( pxList );
+ listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+ /* Insert a new list item into pxList, but rather than sort the list,
+ makes the new list item the last item to be removed by a call to
+ listGET_OWNER_OF_NEXT_ENTRY(). */
+ pxNewListItem->pxNext = pxIndex;
+ pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+ /* Only used during decision coverage testing. */
+ mtCOVERAGE_TEST_DELAY();
+
+ pxIndex->pxPrevious->pxNext = pxNewListItem;
+ pxIndex->pxPrevious = pxNewListItem;
+
+ /* Remember which list the item is in. */
+ pxNewListItem->pxContainer = pxList;
+
+ ( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+ /* Only effective when configASSERT() is also defined, these tests may catch
+ the list data structures being overwritten in memory. They will not catch
+ data errors caused by incorrect configuration or use of FreeRTOS. */
+ listTEST_LIST_INTEGRITY( pxList );
+ listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+ /* Insert the new list item into the list, sorted in xItemValue order.
+
+ If the list already contains a list item with the same item value then the
+ new list item should be placed after it. This ensures that TCBs which are
+ stored in ready lists (all of which have the same xItemValue value) get a
+ share of the CPU. However, if the xItemValue is the same as the back marker
+ the iteration loop below will not end. Therefore the value is checked
+ first, and the algorithm slightly modified if necessary. */
+ if( xValueOfInsertion == portMAX_DELAY )
+ {
+ pxIterator = pxList->xListEnd.pxPrevious;
+ }
+ else
+ {
+ /* *** NOTE ***********************************************************
+ If you find your application is crashing here then likely causes are
+ listed below. In addition see https://www.freertos.org/FAQHelp.html for
+ more tips, and ensure configASSERT() is defined!
+ https://www.freertos.org/a00110.html#configASSERT
+
+ 1) Stack overflow -
+ see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+ 2) Incorrect interrupt priority assignment, especially on Cortex-M
+ parts where numerically high priority values denote low actual
+ interrupt priorities, which can seem counter intuitive. See
+ https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+ of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+ https://www.freertos.org/a00110.html
+ 3) Calling an API function from within a critical section or when
+ the scheduler is suspended, or calling an API function that does
+ not end in "FromISR" from an interrupt.
+ 4) Using a queue or semaphore before it has been initialised or
+ before the scheduler has been started (are interrupts firing
+ before vTaskStartScheduler() has been called?).
+ **********************************************************************/
+
+ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+ {
+ /* There is nothing to do here, just iterating to the wanted
+ insertion position. */
+ }
+ }
+
+ pxNewListItem->pxNext = pxIterator->pxNext;
+ pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+ pxNewListItem->pxPrevious = pxIterator;
+ pxIterator->pxNext = pxNewListItem;
+
+ /* Remember which list the item is in. This allows fast removal of the
+ item later. */
+ pxNewListItem->pxContainer = pxList;
+
+ ( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in. Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+ pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+ pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+ /* Only used during decision coverage testing. */
+ mtCOVERAGE_TEST_DELAY();
+
+ /* Make sure the index is left pointing to a valid item. */
+ if( pxList->pxIndex == pxItemToRemove )
+ {
+ pxList->pxIndex = pxItemToRemove->pxPrevious;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ pxItemToRemove->pxContainer = NULL;
+ ( pxList->uxNumberOfItems )--;
+
+ return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
new file mode 100644
index 0000000..79e51b8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+ #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#else
+ /* The way the SysTick is clocked is not modified in case it is not the same
+ as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )
+#endif
+
+/* Constants required to manipulate the core. Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000 )
+#define portINITIAL_EXC_RETURN ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR ( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+ static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ interrupt. */
+
+ /* Offset added to account for the way the MCU uses the stack on entry/exit
+ of interrupts, and to ensure alignment. */
+ pxTopOfStack--;
+
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+
+ /* Save code space by skipping register initialisation. */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+ /* A save method is being used that requires each task to maintain its
+ own exec return value. */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
+
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( uxCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ started to remove a compiler warning about the function being defined
+ but never called. ulDummy is used purely to quieten other warnings
+ about code appearing after this function is called - making ulDummy
+ volatile makes the compiler think the function could return and
+ therefore not output an 'unreachable code' warning for code that appears
+ after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ __asm volatile (
+ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
+ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+ " msr psp, r0 \n" /* Restore the task stack pointer. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+ /* Start the first task. This also clears the bit that indicates the FPU is
+ in use in case the FPU was used before the scheduler was started - which
+ would otherwise result in the unnecessary leaving of space in the SVC stack
+ for lazy saving of FPU registers. */
+ __asm volatile(
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
+ " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+ " msr control, r0 \n"
+ " cpsie i \n" /* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc 0 \n" /* System call to start first task. */
+ " nop \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+ /* This port can be used on all revisions of the Cortex-M7 core other than
+ the r0p1 parts. r0p1 parts should use the port from the
+ /source/portable/GCC/ARM_CM7/r0p1 directory. */
+ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ functions can be called. ISR safe functions are those that end in
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ ensure interrupt entry is as fast and simple as possible.
+
+ Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
+ /* Shift the priority group value back to its position within the AIRCR
+ register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* conifgASSERT_DEFINED */
+
+ /* Make PendSV and SysTick the lowest priority interrupts. */
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Ensure the VFP is enabled - it should be anyway. */
+ vPortEnableVFP();
+
+ /* Lazy save always. */
+ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+ /* Start the first task. */
+ prvPortStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing! Call the task
+ exit error function to prevent compiler warnings about a static function
+ not being called in the case that the application writer overrides this
+ functionality by defining configTASK_RETURN_ADDRESS. Call
+ vTaskSwitchContext() so link time optimisation does not remove the
+ symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( uxCriticalNesting == 1 )
+ {
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " isb \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n"
+ " \n"
+ " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r0, r3} \n"
+ " mov r0, %0 \n"
+ " msr basepri, r0 \n"
+ " dsb \n"
+ " isb \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r0, r3} \n"
+ " \n"
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldr r0, [r1] \n"
+ " \n"
+ " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
+ " \n"
+ " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n"
+ " \n"
+ " msr psp, r0 \n"
+ " isb \n"
+ " \n"
+ #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+ #if WORKAROUND_PMU_CM001 == 1
+ " push { r14 } \n"
+ " pop { pc } \n"
+ #endif
+ #endif
+ " \n"
+ " bx r14 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+ executes all interrupts must be unmasked. There is therefore no need to
+ save and then restore the interrupt mask value as its value is already
+ known. */
+ portDISABLE_INTERRUPTS();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* A context switch is required. Context switching is performed in
+ the PendSV interrupt. Pend the PendSV interrupt. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+ __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ is accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ tick periods. -1 is used because this code will execute part way
+ through one of the tick periods. */
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile( "cpsid i" ::: "memory" );
+ __asm volatile( "dsb" );
+ __asm volatile( "isb" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Restart from whatever is left in the count register to complete
+ this tick period. */
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Reset the reload register to the value required for normal tick
+ periods. */
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+ /* Re-enable interrupts - see comments above the cpsid instruction()
+ above. */
+ __asm volatile( "cpsie i" ::: "memory" );
+ }
+ else
+ {
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ set its parameter to 0 to indicate that its implementation contains
+ its own wait for interrupt or wait for event instruction, and so wfi
+ should not be executed again. However, the original expected idle
+ time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( &xModifiableIdleTime );
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "wfi" );
+ __asm volatile( "isb" );
+ }
+ configPOST_SLEEP_PROCESSING( &xExpectedIdleTime );
+
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ out of sleep mode to execute immediately. see comments above
+ __disable_interrupt() call above. */
+ __asm volatile( "cpsie i" ::: "memory" );
+ __asm volatile( "dsb" );
+ __asm volatile( "isb" );
+
+ /* Disable interrupts again because the clock is about to be stopped
+ and interrupts that execute while the clock is stopped will increase
+ any slippage between the time maintained by the RTOS and calendar
+ time. */
+ __asm volatile( "cpsid i" ::: "memory" );
+ __asm volatile( "dsb" );
+ __asm volatile( "isb" );
+
+ /* Disable the SysTick clock without reading the
+ portNVIC_SYSTICK_CTRL_REG register to ensure the
+ portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ the time the SysTick is stopped for is accounted for as best it can
+ be, but using the tickless mode will inevitably result in some tiny
+ drift of the time maintained by the kernel with respect to calendar
+ time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine if the SysTick clock has already counted to zero and
+ been set back to the current reload value (the reload back being
+ correct for the entire expected idle time) or if the SysTick is yet
+ to count to zero (in which case an interrupt other than the SysTick
+ must have brought the system out of sleep mode). */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt is already pending, and the SysTick count
+ reloaded with ulReloadValue. Reset the
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+ period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ underflowed because the post sleep hook did something
+ that took too long. */
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* As the pending tick will be processed as soon as this
+ function exits, the tick value maintained by the tick is stepped
+ forward by one less than the time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep.
+ Work out how long the sleep lasted rounded to complete tick
+ periods (not the ulReload value which accounted for part
+ ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ /* How many complete tick periods passed while the processor
+ was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+ value. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ vTaskStepTick( ulCompleteTickPeriods );
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+ /* Exit with interrpts enabled. */
+ __asm volatile( "cpsie i" ::: "memory" );
+ }
+ }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if( configUSE_TICKLESS_IDLE == 1 )
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+ __asm volatile
+ (
+ " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
+ " ldr r1, [r0] \n"
+ " \n"
+ " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
+ " str r1, [r0] \n"
+ " bx r14 "
+ );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ Interrupts that use the FreeRTOS API must not be left at their
+ default priority of zero as that is the highest possible priority,
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ and therefore also guaranteed to be invalid.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible.
+
+ The following links provide detailed information:
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html
+ http://www.freertos.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ If the application only uses CMSIS libraries for interrupt
+ configuration then the correct setting can be achieved on all Cortex-M
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ scheduler. Note however that some vendor specific peripheral libraries
+ assume a non-zero priority group setting, in which cases using a value
+ of zero will result in unpredictable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..868d384
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -0,0 +1,243 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() \
+{ \
+ /* Set a PendSV to request a context switch. */ \
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+ \
+ /* Barriers are normally not required but do ensure the code is completely \
+ within the specified behaviour for the architecture. */ \
+ __asm volatile( "dsb" ::: "memory" ); \
+ __asm volatile( "isb" ); \
+}
+
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0)
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not necessary for to use this port. They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+ return ucReturn;
+ }
+
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE __inline
+
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+ if( ulCurrentInterrupt == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+
+ return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mov %0, %1 \n" \
+ " msr basepri, %0 \n" \
+ " isb \n" \
+ " dsb \n" \
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+ __asm volatile
+ (
+ " mrs %0, basepri \n" \
+ " mov %1, %2 \n" \
+ " msr basepri, %1 \n" \
+ " isb \n" \
+ " dsb \n" \
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ warnings. */
+ return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+ __asm volatile
+ (
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..23714eb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,436 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+ #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+ /* The application writer has already defined the array used for the RTOS
+ heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+ static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure. This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */
+ size_t xBlockSize; /*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks. The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application. When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+ vTaskSuspendAll();
+ {
+ /* If this is the first call to malloc then the heap will require
+ initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is
+ set. The top bit of the block size member of the BlockLink_t structure
+ is used to determine who owns the block - the application or the
+ kernel, so it must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number
+ of bytes. */
+ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+ configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size
+ was not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ block following the number of bytes requested. The void
+ cast is used to prevent byte alignment warnings from the
+ compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the
+ single block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned
+ by the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+ }
+ ( void ) xTaskResumeAll();
+
+ #if( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ vTaskSuspendAll();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ ( void ) xTaskResumeAll();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+ /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( portBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ before and the block after, then it's pxNextFreeBlock pointer will have
+ already been set, and should not be set here as that would make it point
+ to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..6f79c92
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -0,0 +1,2941 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+ #include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED ( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED ( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area. When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any). Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained. The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType pcHead
+#define queueQUEUE_IS_MUTEX NULL
+
+typedef struct QueuePointers
+{
+ int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+ int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+ TaskHandle_t xMutexHolder; /*< The handle of the task that holds the mutex. */
+ UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+ /* If the cooperative scheduler is being used then a yield should not be
+ performed just because a higher priority task has been woken. */
+ #define queueYIELD_IF_USING_PREEMPTION()
+#else
+ #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference. See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+ int8_t *pcHead; /*< Points to the beginning of the queue storage area. */
+ int8_t *pcWriteTo; /*< Points to the free next place in the storage area. */
+
+ union
+ {
+ QueuePointers_t xQueue; /*< Data required exclusively when this structure is used as a queue. */
+ SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+ } u;
+
+ List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */
+ List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */
+
+ volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+ UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+ UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */
+
+ volatile int8_t cRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
+ volatile int8_t cTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
+
+ #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+ uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+ #endif
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ struct QueueDefinition *pxQueueSetContainer;
+ #endif
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxQueueNumber;
+ uint8_t ucQueueType;
+ #endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures. It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ /* The type stored within the queue registry array. This allows a name
+ to be assigned to each queue making kernel aware debugging a little
+ more user friendly. */
+ typedef struct QUEUE_REGISTRY_ITEM
+ {
+ const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ QueueHandle_t xHandle;
+ } xQueueRegistryItem;
+
+ /* The old xQueueRegistryItem name is maintained above then typedefed to the
+ new xQueueRegistryItem name below to enable the use of older kernel aware
+ debuggers. */
+ typedef xQueueRegistryItem QueueRegistryItem_t;
+
+ /* The queue registry is simply an array of QueueRegistryItem_t structures.
+ The pcQueueName member of a structure being NULL is indicative of the
+ array position being vacant. */
+ PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists. If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking. When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+ /*
+ * Checks to see if a queue is a member of a queue set, and if so, notifies
+ * the queue set that the queue contains data.
+ */
+ static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue. When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+ static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+ /*
+ * If a task waiting for a mutex causes the mutex holder to inherit a
+ * priority, but the waiting task times out, then the holder should
+ * disinherit the priority - but only down to the highest priority of any
+ * other tasks that are waiting for the same mutex. This function returns
+ * that priority.
+ */
+ static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked. Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue ) \
+ taskENTER_CRITICAL(); \
+ { \
+ if( ( pxQueue )->cRxLock == queueUNLOCKED ) \
+ { \
+ ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \
+ } \
+ if( ( pxQueue )->cTxLock == queueUNLOCKED ) \
+ { \
+ ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \
+ } \
+ } \
+ taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+
+ taskENTER_CRITICAL();
+ {
+ pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+ pxQueue->pcWriteTo = pxQueue->pcHead;
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+ pxQueue->cRxLock = queueUNLOCKED;
+ pxQueue->cTxLock = queueUNLOCKED;
+
+ if( xNewQueue == pdFALSE )
+ {
+ /* If there are tasks blocked waiting to read from the queue, then
+ the tasks will remain blocked as after this function exits the queue
+ will still be empty. If there are tasks blocked waiting to write to
+ the queue, then one should be unblocked as after this function exits
+ it will be possible to write to it. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Ensure the event queues start in the correct state. */
+ vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+ vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* A value is returned for calling semantic consistency with previous
+ versions. */
+ return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+ {
+ Queue_t *pxNewQueue;
+
+ configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+ /* The StaticQueue_t structure and the queue storage area must be
+ supplied. */
+ configASSERT( pxStaticQueue != NULL );
+
+ /* A queue storage area should be provided if the item size is not 0, and
+ should not be provided if the item size is 0. */
+ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+ configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* Sanity check that the size of the structure used to declare a
+ variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+ the real queue and semaphore structures. */
+ volatile size_t xSize = sizeof( StaticQueue_t );
+ configASSERT( xSize == sizeof( Queue_t ) );
+ ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* The address of a statically allocated queue was passed in, use it.
+ The address of a statically allocated storage area was also passed in
+ but is already set. */
+ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+ if( pxNewQueue != NULL )
+ {
+ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* Queues can be allocated wither statically or dynamically, so
+ note this queue was allocated statically in case the queue is
+ later deleted. */
+ pxNewQueue->ucStaticallyAllocated = pdTRUE;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+ }
+ else
+ {
+ traceQUEUE_CREATE_FAILED( ucQueueType );
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return pxNewQueue;
+ }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+ QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+ {
+ Queue_t *pxNewQueue;
+ size_t xQueueSizeInBytes;
+ uint8_t *pucQueueStorage;
+
+ configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+ if( uxItemSize == ( UBaseType_t ) 0 )
+ {
+ /* There is not going to be a queue storage area. */
+ xQueueSizeInBytes = ( size_t ) 0;
+ }
+ else
+ {
+ /* Allocate enough space to hold the maximum number of items that
+ can be in the queue at any time. */
+ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ }
+
+ /* Allocate the queue and storage area. Justification for MISRA
+ deviation as follows: pvPortMalloc() always ensures returned memory
+ blocks are aligned per the requirements of the MCU stack. In this case
+ pvPortMalloc() must return a pointer that is guaranteed to meet the
+ alignment requirements of the Queue_t structure - which in this case
+ is an int8_t *. Therefore, whenever the stack alignment requirements
+ are greater than or equal to the pointer to char requirements the cast
+ is safe. In other cases alignment requirements are not strict (one or
+ two bytes). */
+ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+ if( pxNewQueue != NULL )
+ {
+ /* Jump past the queue structure to find the location of the queue
+ storage area. */
+ pucQueueStorage = ( uint8_t * ) pxNewQueue;
+ pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ /* Queues can be created either statically or dynamically, so
+ note this task was created dynamically in case it is later
+ deleted. */
+ pxNewQueue->ucStaticallyAllocated = pdFALSE;
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+ }
+ else
+ {
+ traceQUEUE_CREATE_FAILED( ucQueueType );
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return pxNewQueue;
+ }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+ /* Remove compiler warnings about unused parameters should
+ configUSE_TRACE_FACILITY not be set to 1. */
+ ( void ) ucQueueType;
+
+ if( uxItemSize == ( UBaseType_t ) 0 )
+ {
+ /* No RAM was allocated for the queue storage area, but PC head cannot
+ be set to NULL because NULL is used as a key to say the queue is used as
+ a mutex. Therefore just set pcHead to point to the queue as a benign
+ value that is known to be within the memory map. */
+ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+ }
+ else
+ {
+ /* Set the head to the start of the queue storage area. */
+ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+ }
+
+ /* Initialise the queue members as described where the queue type is
+ defined. */
+ pxNewQueue->uxLength = uxQueueLength;
+ pxNewQueue->uxItemSize = uxItemSize;
+ ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ pxNewQueue->ucQueueType = ucQueueType;
+ }
+ #endif /* configUSE_TRACE_FACILITY */
+
+ #if( configUSE_QUEUE_SETS == 1 )
+ {
+ pxNewQueue->pxQueueSetContainer = NULL;
+ }
+ #endif /* configUSE_QUEUE_SETS */
+
+ traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+ static void prvInitialiseMutex( Queue_t *pxNewQueue )
+ {
+ if( pxNewQueue != NULL )
+ {
+ /* The queue create function will set all the queue structure members
+ correctly for a generic queue, but this function is creating a
+ mutex. Overwrite those members that need to be set differently -
+ in particular the information required for priority inheritance. */
+ pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+ pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+ /* In case this is a recursive mutex. */
+ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+ traceCREATE_MUTEX( pxNewQueue );
+
+ /* Start with the semaphore in the expected state. */
+ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+ }
+ else
+ {
+ traceCREATE_MUTEX_FAILED();
+ }
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+ QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+ {
+ QueueHandle_t xNewQueue;
+ const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+ xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+ prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+ return xNewQueue;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+ QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+ {
+ QueueHandle_t xNewQueue;
+ const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+ /* Prevent compiler warnings about unused parameters if
+ configUSE_TRACE_FACILITY does not equal 1. */
+ ( void ) ucQueueType;
+
+ xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+ prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+ return xNewQueue;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+ TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+ {
+ TaskHandle_t pxReturn;
+ Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+ /* This function is called by xSemaphoreGetMutexHolder(), and should not
+ be called directly. Note: This is a good way of determining if the
+ calling task is the mutex holder, but not a good way of determining the
+ identity of the mutex holder, as the holder may change between the
+ following critical section exiting and the function returning. */
+ taskENTER_CRITICAL();
+ {
+ if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+ }
+ else
+ {
+ pxReturn = NULL;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return pxReturn;
+ } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+ TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+ {
+ TaskHandle_t pxReturn;
+
+ configASSERT( xSemaphore );
+
+ /* Mutexes cannot be used in interrupt service routines, so the mutex
+ holder should not change in an ISR, and therefore a critical section is
+ not required here. */
+ if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+ }
+ else
+ {
+ pxReturn = NULL;
+ }
+
+ return pxReturn;
+ } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+ configASSERT( pxMutex );
+
+ /* If this is the task that holds the mutex then xMutexHolder will not
+ change outside of this task. If this task does not hold the mutex then
+ pxMutexHolder can never coincidentally equal the tasks handle, and as
+ this is the only condition we are interested in it does not matter if
+ pxMutexHolder is accessed simultaneously by another task. Therefore no
+ mutual exclusion is required to test the pxMutexHolder variable. */
+ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+ {
+ traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+ /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+ the task handle, therefore no underflow check is required. Also,
+ uxRecursiveCallCount is only modified by the mutex holder, and as
+ there can only be one, no mutual exclusion is required to modify the
+ uxRecursiveCallCount member. */
+ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+ /* Has the recursive call count unwound to 0? */
+ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+ {
+ /* Return the mutex. This will automatically unblock any other
+ task that might be waiting to access the mutex. */
+ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* The mutex cannot be given because the calling task is not the
+ holder. */
+ xReturn = pdFAIL;
+
+ traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+ configASSERT( pxMutex );
+
+ /* Comments regarding mutual exclusion as per those within
+ xQueueGiveMutexRecursive(). */
+
+ traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+ {
+ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+ /* pdPASS will only be returned if the mutex was successfully
+ obtained. The calling task may have entered the Blocked state
+ before reaching here. */
+ if( xReturn != pdFAIL )
+ {
+ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+ }
+ else
+ {
+ traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+ }
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+ QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+ {
+ QueueHandle_t xHandle;
+
+ configASSERT( uxMaxCount != 0 );
+ configASSERT( uxInitialCount <= uxMaxCount );
+
+ xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+ if( xHandle != NULL )
+ {
+ ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+ traceCREATE_COUNTING_SEMAPHORE();
+ }
+ else
+ {
+ traceCREATE_COUNTING_SEMAPHORE_FAILED();
+ }
+
+ return xHandle;
+ }
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+ QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+ {
+ QueueHandle_t xHandle;
+
+ configASSERT( uxMaxCount != 0 );
+ configASSERT( uxInitialCount <= uxMaxCount );
+
+ xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+ if( xHandle != NULL )
+ {
+ ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+ traceCREATE_COUNTING_SEMAPHORE();
+ }
+ else
+ {
+ traceCREATE_COUNTING_SEMAPHORE_FAILED();
+ }
+
+ return xHandle;
+ }
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+
+ /*lint -save -e904 This function relaxes the coding standard somewhat to
+ allow return statements within the function itself. This is done in the
+ interest of execution time efficiency. */
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* Is there room on the queue now? The running task must be the
+ highest priority task wanting to access the queue. If the head item
+ in the queue is to be overwritten then it does not matter if the
+ queue is full. */
+ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ {
+ traceQUEUE_SEND( pxQueue );
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+ if( pxQueue->pxQueueSetContainer != NULL )
+ {
+ if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+ {
+ /* Do not notify the queue set as an existing item
+ was overwritten in the queue so the number of items
+ in the queue has not changed. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+ {
+ /* The queue is a member of a queue set, and posting
+ to the queue set caused a higher priority task to
+ unblock. A context switch is required. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* If there was a task waiting for data to arrive on the
+ queue then unblock it now. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The unblocked task has a priority higher than
+ our own so yield immediately. Yes it is ok to
+ do this from within the critical section - the
+ kernel takes care of that. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( xYieldRequired != pdFALSE )
+ {
+ /* This path is a special case that will only get
+ executed if the task was holding multiple mutexes
+ and the mutexes were given back in an order that is
+ different to that in which they were taken. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+ /* If there was a task waiting for data to arrive on the
+ queue then unblock it now. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The unblocked task has a priority higher than
+ our own so yield immediately. Yes it is ok to do
+ this from within the critical section - the kernel
+ takes care of that. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( xYieldRequired != pdFALSE )
+ {
+ /* This path is a special case that will only get
+ executed if the task was holding multiple mutexes and
+ the mutexes were given back in an order that is
+ different to that in which they were taken. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_QUEUE_SETS */
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* The queue was full and no block time is specified (or
+ the block time has expired) so leave now. */
+ taskEXIT_CRITICAL();
+
+ /* Return to the original privilege level before exiting
+ the function. */
+ traceQUEUE_SEND_FAILED( pxQueue );
+ return errQUEUE_FULL;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ /* The queue was full and a block time was specified so
+ configure the timeout structure. */
+ vTaskInternalSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ else
+ {
+ /* Entry time was already set. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* Interrupts and other tasks can send to and receive from the queue
+ now the critical section has been exited. */
+
+ vTaskSuspendAll();
+ prvLockQueue( pxQueue );
+
+ /* Update the timeout state to see if it has expired yet. */
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+ /* Unlocking the queue means queue events can effect the
+ event list. It is possible that interrupts occurring now
+ remove this task from the event list again - but as the
+ scheduler is suspended the task will go onto the pending
+ ready last instead of the actual ready list. */
+ prvUnlockQueue( pxQueue );
+
+ /* Resuming the scheduler will move tasks from the pending
+ ready list into the ready list - so it is feasible that this
+ task is already in a ready list before it yields - in which
+ case the yield will not cause a context switch unless there
+ is also a higher priority task in the pending ready list. */
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ }
+ else
+ {
+ /* Try again. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+ }
+ }
+ else
+ {
+ /* The timeout has expired. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+
+ traceQUEUE_SEND_FAILED( pxQueue );
+ return errQUEUE_FULL;
+ }
+ } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ /* Similar to xQueueGenericSend, except without blocking if there is no room
+ in the queue. Also don't directly wake a task that was blocked on a queue
+ read, instead return a flag to say whether a context switch is required or
+ not (i.e. has a task with a higher priority than us been woken by this
+ post). */
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ {
+ const int8_t cTxLock = pxQueue->cTxLock;
+
+ traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+ /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+ semaphore or mutex. That means prvCopyDataToQueue() cannot result
+ in a task disinheriting a priority and prvCopyDataToQueue() can be
+ called here even though the disinherit function does not check if
+ the scheduler is suspended before accessing the ready lists. */
+ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+ /* The event list is not altered if the queue is locked. This will
+ be done when the queue is unlocked later. */
+ if( cTxLock == queueUNLOCKED )
+ {
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
+ {
+ if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+ {
+ /* The queue is a member of a queue set, and posting
+ to the queue set caused a higher priority task to
+ unblock. A context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so
+ record that a context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_QUEUE_SETS */
+ }
+ else
+ {
+ /* Increment the lock count so the task that unlocks the queue
+ knows that data was posted while it was locked. */
+ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+ xReturn = errQUEUE_FULL;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+ /* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+ item size is 0. Don't directly wake a task that was blocked on a queue
+ read, instead return a flag to say whether a context switch is required or
+ not (i.e. has a task with a higher priority than us been woken by this
+ post). */
+
+ configASSERT( pxQueue );
+
+ /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+ if the item size is not 0. */
+ configASSERT( pxQueue->uxItemSize == 0 );
+
+ /* Normally a mutex would not be given from an interrupt, especially if
+ there is a mutex holder, as priority inheritance makes no sense for an
+ interrupts, only tasks. */
+ configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ /* When the queue is used to implement a semaphore no data is ever
+ moved through the queue but it is still valid to see if the queue 'has
+ space'. */
+ if( uxMessagesWaiting < pxQueue->uxLength )
+ {
+ const int8_t cTxLock = pxQueue->cTxLock;
+
+ traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+ /* A task can only have an inherited priority if it is a mutex
+ holder - and if there is a mutex holder then the mutex cannot be
+ given from an ISR. As this is the ISR version of the function it
+ can be assumed there is no mutex holder and no need to determine if
+ priority disinheritance is needed. Simply increase the count of
+ messages (semaphores) available. */
+ pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+ /* The event list is not altered if the queue is locked. This will
+ be done when the queue is unlocked later. */
+ if( cTxLock == queueUNLOCKED )
+ {
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
+ {
+ if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+ {
+ /* The semaphore is a member of a queue set, and
+ posting to the queue set caused a higher priority
+ task to unblock. A context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so
+ record that a context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_QUEUE_SETS */
+ }
+ else
+ {
+ /* Increment the lock count so the task that unlocks the queue
+ knows that data was posted while it was locked. */
+ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+ xReturn = errQUEUE_FULL;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+ /* Check the pointer is not NULL. */
+ configASSERT( ( pxQueue ) );
+
+ /* The buffer into which data is received can only be NULL if the data size
+ is zero (so no data is copied into the buffer. */
+ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+ /* Cannot block if the scheduler is suspended. */
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+
+ /*lint -save -e904 This function relaxes the coding standard somewhat to
+ allow return statements within the function itself. This is done in the
+ interest of execution time efficiency. */
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ /* Is there data in the queue now? To be running the calling task
+ must be the highest priority task wanting to access the queue. */
+ if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Data available, remove one item. */
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+ traceQUEUE_RECEIVE( pxQueue );
+ pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+ /* There is now space in the queue, were any tasks waiting to
+ post to the queue? If so, unblock the highest priority waiting
+ task. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* The queue was empty and no block time is specified (or
+ the block time has expired) so leave now. */
+ taskEXIT_CRITICAL();
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ /* The queue was empty and a block time was specified so
+ configure the timeout structure. */
+ vTaskInternalSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ else
+ {
+ /* Entry time was already set. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* Interrupts and other tasks can send to and receive from the queue
+ now the critical section has been exited. */
+
+ vTaskSuspendAll();
+ prvLockQueue( pxQueue );
+
+ /* Update the timeout state to see if it has expired yet. */
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ /* The timeout has not expired. If the queue is still empty place
+ the task on the list of tasks waiting to receive from the queue. */
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ prvUnlockQueue( pxQueue );
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* The queue contains data again. Loop back to try and read the
+ data. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+ }
+ }
+ else
+ {
+ /* Timed out. If there is no data in the queue exit, otherwise loop
+ back and attempt to read the data. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+ BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+ /* Check the queue pointer is not NULL. */
+ configASSERT( ( pxQueue ) );
+
+ /* Check this really is a semaphore, in which case the item size will be
+ 0. */
+ configASSERT( pxQueue->uxItemSize == 0 );
+
+ /* Cannot block if the scheduler is suspended. */
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+
+ /*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+ statements within the function itself. This is done in the interest
+ of execution time efficiency. */
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* Semaphores are queues with an item size of 0, and where the
+ number of messages in the queue is the semaphore's count value. */
+ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+ /* Is there data in the queue now? To be running the calling task
+ must be the highest priority task wanting to access the queue. */
+ if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+ {
+ traceQUEUE_RECEIVE( pxQueue );
+
+ /* Semaphores are queues with a data size of zero and where the
+ messages waiting is the semaphore's count. Reduce the count. */
+ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ /* Record the information required to implement
+ priority inheritance should it become necessary. */
+ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_MUTEXES */
+
+ /* Check to see if other tasks are blocked waiting to give the
+ semaphore, and if so, unblock the highest priority such task. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* For inheritance to have occurred there must have been an
+ initial timeout, and an adjusted timeout cannot become 0, as
+ if it were 0 the function would have exited. */
+ #if( configUSE_MUTEXES == 1 )
+ {
+ configASSERT( xInheritanceOccurred == pdFALSE );
+ }
+ #endif /* configUSE_MUTEXES */
+
+ /* The semaphore count was 0 and no block time is specified
+ (or the block time has expired) so exit now. */
+ taskEXIT_CRITICAL();
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ /* The semaphore count was 0 and a block time was specified
+ so configure the timeout structure ready to block. */
+ vTaskInternalSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ else
+ {
+ /* Entry time was already set. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* Interrupts and other tasks can give to and take from the semaphore
+ now the critical section has been exited. */
+
+ vTaskSuspendAll();
+ prvLockQueue( pxQueue );
+
+ /* Update the timeout state to see if it has expired yet. */
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ /* A block time is specified and not expired. If the semaphore
+ count is 0 then enter the Blocked state to wait for a semaphore to
+ become available. As semaphores are implemented with queues the
+ queue being empty is equivalent to the semaphore count being 0. */
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ taskENTER_CRITICAL();
+ {
+ xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ prvUnlockQueue( pxQueue );
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* There was no timeout and the semaphore count was not 0, so
+ attempt to take the semaphore again. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+ }
+ }
+ else
+ {
+ /* Timed out. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+
+ /* If the semaphore count is 0 exit now as the timeout has
+ expired. Otherwise return to attempt to take the semaphore that is
+ known to be available. As semaphores are implemented by queues the
+ queue being empty is equivalent to the semaphore count being 0. */
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ /* xInheritanceOccurred could only have be set if
+ pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+ test the mutex type again to check it is actually a mutex. */
+ if( xInheritanceOccurred != pdFALSE )
+ {
+ taskENTER_CRITICAL();
+ {
+ UBaseType_t uxHighestWaitingPriority;
+
+ /* This task blocking on the mutex caused another
+ task to inherit this task's priority. Now this task
+ has timed out the priority should be disinherited
+ again, but only as low as the next highest priority
+ task that is waiting for the same mutex. */
+ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+ vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+ }
+ taskEXIT_CRITICAL();
+ }
+ }
+ #endif /* configUSE_MUTEXES */
+
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+ /* Check the pointer is not NULL. */
+ configASSERT( ( pxQueue ) );
+
+ /* The buffer into which data is received can only be NULL if the data size
+ is zero (so no data is copied into the buffer. */
+ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+ /* Cannot block if the scheduler is suspended. */
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+
+ /*lint -save -e904 This function relaxes the coding standard somewhat to
+ allow return statements within the function itself. This is done in the
+ interest of execution time efficiency. */
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ /* Is there data in the queue now? To be running the calling task
+ must be the highest priority task wanting to access the queue. */
+ if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Remember the read position so it can be reset after the data
+ is read from the queue as this function is only peeking the
+ data, not removing it. */
+ pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+ traceQUEUE_PEEK( pxQueue );
+
+ /* The data is not being removed, so reset the read pointer. */
+ pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+ /* The data is being left in the queue, so see if there are
+ any other tasks waiting for the data. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority than this task. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* The queue was empty and no block time is specified (or
+ the block time has expired) so leave now. */
+ taskEXIT_CRITICAL();
+ traceQUEUE_PEEK_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ /* The queue was empty and a block time was specified so
+ configure the timeout structure ready to enter the blocked
+ state. */
+ vTaskInternalSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ else
+ {
+ /* Entry time was already set. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* Interrupts and other tasks can send to and receive from the queue
+ now the critical section has been exited. */
+
+ vTaskSuspendAll();
+ prvLockQueue( pxQueue );
+
+ /* Update the timeout state to see if it has expired yet. */
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ /* Timeout has not expired yet, check to see if there is data in the
+ queue now, and if not enter the Blocked state to wait for data. */
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ prvUnlockQueue( pxQueue );
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* There is data in the queue now, so don't enter the blocked
+ state, instead return to try and obtain the data. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+ }
+ }
+ else
+ {
+ /* The timeout has expired. If there is still no data in the queue
+ exit, otherwise go back and try to read the data again. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ traceQUEUE_PEEK_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ /* Cannot block in an ISR, so check there is data available. */
+ if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ const int8_t cRxLock = pxQueue->cRxLock;
+
+ traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+ pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+ /* If the queue is locked the event list will not be modified.
+ Instead update the lock count so the task that unlocks the queue
+ will know that an ISR has removed data while the queue was
+ locked. */
+ if( cRxLock == queueUNLOCKED )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority than us so
+ force a context switch. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Increment the lock count so the task that unlocks the queue
+ knows that data was removed while it was locked. */
+ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Cannot block in an ISR, so check there is data available. */
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+ /* Remember the read position so it can be reset as nothing is
+ actually being removed from the queue. */
+ pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+ pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+ configASSERT( xQueue );
+
+ taskENTER_CRITICAL();
+ {
+ uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+ }
+ taskEXIT_CRITICAL();
+
+ return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+
+ taskENTER_CRITICAL();
+ {
+ uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+ }
+ taskEXIT_CRITICAL();
+
+ return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ uxReturn = pxQueue->uxMessagesWaiting;
+
+ return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ traceQUEUE_DELETE( pxQueue );
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+ {
+ vQueueUnregisterQueue( pxQueue );
+ }
+ #endif
+
+ #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+ {
+ /* The queue can only have been allocated dynamically - free it
+ again. */
+ vPortFree( pxQueue );
+ }
+ #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+ {
+ /* The queue could have been allocated statically or dynamically, so
+ check before attempting to free the memory. */
+ if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+ {
+ vPortFree( pxQueue );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #else
+ {
+ /* The queue must have been statically allocated, so is not going to be
+ deleted. Avoid compiler warnings about the unused parameter. */
+ ( void ) pxQueue;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+ {
+ return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+ {
+ ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+ {
+ return ( ( Queue_t * ) xQueue )->ucQueueType;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+ static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+ {
+ UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+ /* If a task waiting for a mutex causes the mutex holder to inherit a
+ priority, but the waiting task times out, then the holder should
+ disinherit the priority - but only down to the highest priority of any
+ other tasks that are waiting for the same mutex. For this purpose,
+ return the priority of the highest priority task that is waiting for the
+ mutex. */
+ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+ {
+ uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+ }
+ else
+ {
+ uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+ }
+
+ return uxHighestPriorityOfWaitingTasks;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+ /* This function is called from a critical section. */
+
+ uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+ {
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ /* The mutex is no longer being held. */
+ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+ pxQueue->u.xSemaphore.xMutexHolder = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_MUTEXES */
+ }
+ else if( xPosition == queueSEND_TO_BACK )
+ {
+ ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ {
+ pxQueue->pcWriteTo = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
+ pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+ if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ {
+ pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xPosition == queueOVERWRITE )
+ {
+ if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* An item is not being added but overwritten, so subtract
+ one from the recorded number of items in the queue so when
+ one is added again below the number of recorded items remains
+ correct. */
+ --uxMessagesWaiting;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+ if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+ {
+ pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+ {
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+ /* The lock counts contains the number of extra data items placed or
+ removed from the queue while the queue was locked. When a queue is
+ locked items can be added or removed, but the event lists cannot be
+ updated. */
+ taskENTER_CRITICAL();
+ {
+ int8_t cTxLock = pxQueue->cTxLock;
+
+ /* See if data was added to the queue while it was locked. */
+ while( cTxLock > queueLOCKED_UNMODIFIED )
+ {
+ /* Data was posted while the queue was locked. Are any tasks
+ blocked waiting for data to become available? */
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
+ {
+ if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+ {
+ /* The queue is a member of a queue set, and posting to
+ the queue set caused a higher priority task to unblock.
+ A context switch is required. */
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Tasks that are removed from the event list will get
+ added to the pending ready list as the scheduler is still
+ suspended. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ context switch is required. */
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ /* Tasks that are removed from the event list will get added to
+ the pending ready list as the scheduler is still suspended. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that
+ a context switch is required. */
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+ #endif /* configUSE_QUEUE_SETS */
+
+ --cTxLock;
+ }
+
+ pxQueue->cTxLock = queueUNLOCKED;
+ }
+ taskEXIT_CRITICAL();
+
+ /* Do the same for the Rx lock. */
+ taskENTER_CRITICAL();
+ {
+ int8_t cRxLock = pxQueue->cRxLock;
+
+ while( cRxLock > queueLOCKED_UNMODIFIED )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ --cRxLock;
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ pxQueue->cRxLock = queueUNLOCKED;
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+ taskENTER_CRITICAL();
+ {
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+ taskENTER_CRITICAL();
+ {
+ if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+ configASSERT( pxQueue );
+ if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueue = xQueue;
+
+ /* If the queue is already full we may have to block. A critical section
+ is required to prevent an interrupt removing something from the queue
+ between the check to see if the queue is full and blocking on the queue. */
+ portDISABLE_INTERRUPTS();
+ {
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )
+ {
+ /* The queue is full - do we want to block or just leave without
+ posting? */
+ if( xTicksToWait > ( TickType_t ) 0 )
+ {
+ /* As this is called from a coroutine we cannot block directly, but
+ return indicating that we need to block. */
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+ portENABLE_INTERRUPTS();
+ return errQUEUE_BLOCKED;
+ }
+ else
+ {
+ portENABLE_INTERRUPTS();
+ return errQUEUE_FULL;
+ }
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ portDISABLE_INTERRUPTS();
+ {
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+ {
+ /* There is room in the queue, copy the data into the queue. */
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+ xReturn = pdPASS;
+
+ /* Were any co-routines waiting for data to become available? */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ /* In this instance the co-routine could be placed directly
+ into the ready list as we are within a critical section.
+ Instead the same pending ready list mechanism is used as if
+ the event were caused from within an interrupt. */
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The co-routine waiting has a higher priority so record
+ that a yield might be appropriate. */
+ xReturn = errQUEUE_YIELD;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xReturn = errQUEUE_FULL;
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueue = xQueue;
+
+ /* If the queue is already empty we may have to block. A critical section
+ is required to prevent an interrupt adding something to the queue
+ between the check to see if the queue is empty and blocking on the queue. */
+ portDISABLE_INTERRUPTS();
+ {
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+ {
+ /* There are no messages in the queue, do we want to block or just
+ leave with nothing? */
+ if( xTicksToWait > ( TickType_t ) 0 )
+ {
+ /* As this is a co-routine we cannot block directly, but return
+ indicating that we need to block. */
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+ portENABLE_INTERRUPTS();
+ return errQUEUE_BLOCKED;
+ }
+ else
+ {
+ portENABLE_INTERRUPTS();
+ return errQUEUE_FULL;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ portDISABLE_INTERRUPTS();
+ {
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Data is available from the queue. */
+ pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+ if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+ {
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ --( pxQueue->uxMessagesWaiting );
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+ xReturn = pdPASS;
+
+ /* Were any co-routines waiting for space to become available? */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ /* In this instance the co-routine could be placed directly
+ into the ready list as we are within a critical section.
+ Instead the same pending ready list mechanism is used as if
+ the event were caused from within an interrupt. */
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ xReturn = errQUEUE_YIELD;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+ {
+ Queue_t * const pxQueue = xQueue;
+
+ /* Cannot block within an ISR so if there is no space on the queue then
+ exit without doing anything. */
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+ {
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+ /* We only want to wake one co-routine per ISR, so check that a
+ co-routine has not already been woken. */
+ if( xCoRoutinePreviouslyWoken == pdFALSE )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ return pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xCoRoutinePreviouslyWoken;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueue = xQueue;
+
+ /* We cannot block from an ISR, so check there is data available. If
+ not then just leave without doing anything. */
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Copy the data from the queue. */
+ pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+ if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+ {
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ --( pxQueue->uxMessagesWaiting );
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+ if( ( *pxCoRoutineWoken ) == pdFALSE )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ *pxCoRoutineWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ {
+ UBaseType_t ux;
+
+ /* See if there is an empty space in the registry. A NULL name denotes
+ a free slot. */
+ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ {
+ if( xQueueRegistry[ ux ].pcQueueName == NULL )
+ {
+ /* Store the information on this queue. */
+ xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+ xQueueRegistry[ ux ].xHandle = xQueue;
+
+ traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ {
+ UBaseType_t ux;
+ const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+ /* Note there is nothing here to protect against another task adding or
+ removing entries from the registry while it is being searched. */
+ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ {
+ if( xQueueRegistry[ ux ].xHandle == xQueue )
+ {
+ pcReturn = xQueueRegistry[ ux ].pcQueueName;
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ return pcReturn;
+ } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void vQueueUnregisterQueue( QueueHandle_t xQueue )
+ {
+ UBaseType_t ux;
+
+ /* See if the handle of the queue being unregistered in actually in the
+ registry. */
+ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ {
+ if( xQueueRegistry[ ux ].xHandle == xQueue )
+ {
+ /* Set the name to NULL to show that this slot if free again. */
+ xQueueRegistry[ ux ].pcQueueName = NULL;
+
+ /* Set the handle to NULL to ensure the same queue handle cannot
+ appear in the registry twice if it is added, removed, then
+ added again. */
+ xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+ void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+ {
+ Queue_t * const pxQueue = xQueue;
+
+ /* This function should not be called by application code hence the
+ 'Restricted' in its name. It is not part of the public API. It is
+ designed for use by kernel code, and has special calling requirements.
+ It can result in vListInsert() being called on a list that can only
+ possibly ever have one item in it, so the list will be fast, but even
+ so it should be called with the scheduler locked and not from a critical
+ section. */
+
+ /* Only do anything if there are no messages in the queue. This function
+ will not actually cause the task to block, just place it on a blocked
+ list. It will not block until the scheduler is unlocked - at which
+ time a yield will be performed. If an item is added to the queue while
+ the queue is locked, and the calling task blocks on the queue, then the
+ calling task will be immediately unblocked when the queue is unlocked. */
+ prvLockQueue( pxQueue );
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+ {
+ /* There is nothing in the queue, block for the specified period. */
+ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ prvUnlockQueue( pxQueue );
+ }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+ QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+ {
+ QueueSetHandle_t pxQueue;
+
+ pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+ return pxQueue;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+ {
+ BaseType_t xReturn;
+
+ taskENTER_CRITICAL();
+ {
+ if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+ {
+ /* Cannot add a queue/semaphore to more than one queue set. */
+ xReturn = pdFAIL;
+ }
+ else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+ {
+ /* Cannot add a queue/semaphore to a queue set if there are already
+ items in the queue/semaphore. */
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+ xReturn = pdPASS;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+ if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+ {
+ /* The queue was not a member of the set. */
+ xReturn = pdFAIL;
+ }
+ else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+ {
+ /* It is dangerous to remove a queue from a set when the queue is
+ not empty because the queue set will still hold pending events for
+ the queue. */
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ taskENTER_CRITICAL();
+ {
+ /* The queue is no longer contained in the set. */
+ pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+ }
+ taskEXIT_CRITICAL();
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
+ } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+ {
+ QueueSetMemberHandle_t xReturn = NULL;
+
+ ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+ {
+ QueueSetMemberHandle_t xReturn = NULL;
+
+ ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
+ {
+ Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+ BaseType_t xReturn = pdFALSE;
+
+ /* This function must be called form a critical section. */
+
+ configASSERT( pxQueueSetContainer );
+ configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+ if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+ {
+ const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+ traceQUEUE_SEND( pxQueueSetContainer );
+
+ /* The data copied is the handle of the queue that contains data. */
+ xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
+
+ if( cTxLock == queueUNLOCKED )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority. */
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..8cda238
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+ #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+ #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \
+ vTaskSuspendAll(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
+ { \
+ ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
+ ( uint32_t ) 0, \
+ eNoAction ); \
+ ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \
+ } \
+ } \
+ ( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+ #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \
+ pxHigherPriorityTaskWoken ) \
+ { \
+ UBaseType_t uxSavedInterruptStatus; \
+ \
+ uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \
+ { \
+ ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
+ ( uint32_t ) 0, \
+ eNoAction, \
+ pxHigherPriorityTaskWoken ); \
+ ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \
+ } \
+ } \
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
+ }
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+ #define sbSEND_COMPLETED( pxStreamBuffer ) \
+ vTaskSuspendAll(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
+ { \
+ ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+ ( uint32_t ) 0, \
+ eNoAction ); \
+ ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \
+ } \
+ } \
+ ( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+ #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \
+ { \
+ UBaseType_t uxSavedInterruptStatus; \
+ \
+ uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \
+ { \
+ if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \
+ { \
+ ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+ ( uint32_t ) 0, \
+ eNoAction, \
+ pxHigherPriorityTaskWoken ); \
+ ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \
+ } \
+ } \
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \
+ }
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+ volatile size_t xTail; /* Index to the next item to read within the buffer. */
+ volatile size_t xHead; /* Index to the next item to write within the buffer. */
+ size_t xLength; /* The length of the buffer pointed to by pucBuffer. */
+ size_t xTriggerLevelBytes; /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+ volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+ volatile TaskHandle_t xTaskWaitingToSend; /* Holds the handle of a task waiting to send data to a message buffer that is full. */
+ uint8_t *pucBuffer; /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+ uint8_t ucFlags;
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */
+ #endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer. If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ size_t xBytesAvailable,
+ size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer. If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ size_t xSpace,
+ size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+ uint8_t *pucData,
+ size_t xMaxCount,
+ size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+ uint8_t * const pucBuffer,
+ size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+ StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+ {
+ uint8_t *pucAllocatedMemory;
+ uint8_t ucFlags;
+
+ /* In case the stream buffer is going to be used as a message buffer
+ (that is, it will hold discrete messages with a little meta data that
+ says how big the next message is) check the buffer will be large enough
+ to hold at least one message. */
+ if( xIsMessageBuffer == pdTRUE )
+ {
+ /* Is a message buffer but not statically allocated. */
+ ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+ configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+ }
+ else
+ {
+ /* Not a message buffer and not statically allocated. */
+ ucFlags = 0;
+ configASSERT( xBufferSizeBytes > 0 );
+ }
+ configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+ /* A trigger level of 0 would cause a waiting task to unblock even when
+ the buffer was empty. */
+ if( xTriggerLevelBytes == ( size_t ) 0 )
+ {
+ xTriggerLevelBytes = ( size_t ) 1;
+ }
+
+ /* A stream buffer requires a StreamBuffer_t structure and a buffer.
+ Both are allocated in a single call to pvPortMalloc(). The
+ StreamBuffer_t structure is placed at the start of the allocated memory
+ and the buffer follows immediately after. The requested size is
+ incremented so the free space is returned as the user would expect -
+ this is a quirk of the implementation that means otherwise the free
+ space would be reported as one byte smaller than would be logically
+ expected. */
+ xBufferSizeBytes++;
+ pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+ if( pucAllocatedMemory != NULL )
+ {
+ prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+ pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+ xBufferSizeBytes,
+ xTriggerLevelBytes,
+ ucFlags );
+
+ traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+ }
+ else
+ {
+ traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+ }
+
+ return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+ }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ BaseType_t xIsMessageBuffer,
+ uint8_t * const pucStreamBufferStorageArea,
+ StaticStreamBuffer_t * const pxStaticStreamBuffer )
+ {
+ StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+ StreamBufferHandle_t xReturn;
+ uint8_t ucFlags;
+
+ configASSERT( pucStreamBufferStorageArea );
+ configASSERT( pxStaticStreamBuffer );
+ configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+ /* A trigger level of 0 would cause a waiting task to unblock even when
+ the buffer was empty. */
+ if( xTriggerLevelBytes == ( size_t ) 0 )
+ {
+ xTriggerLevelBytes = ( size_t ) 1;
+ }
+
+ if( xIsMessageBuffer != pdFALSE )
+ {
+ /* Statically allocated message buffer. */
+ ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+ }
+ else
+ {
+ /* Statically allocated stream buffer. */
+ ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+ }
+
+ /* In case the stream buffer is going to be used as a message buffer
+ (that is, it will hold discrete messages with a little meta data that
+ says how big the next message is) check the buffer will be large enough
+ to hold at least one message. */
+ configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* Sanity check that the size of the structure used to declare a
+ variable of type StaticStreamBuffer_t equals the size of the real
+ message buffer structure. */
+ volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+ configASSERT( xSize == sizeof( StreamBuffer_t ) );
+ } /*lint !e529 xSize is referenced is configASSERT() is defined. */
+ #endif /* configASSERT_DEFINED */
+
+ if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+ {
+ prvInitialiseNewStreamBuffer( pxStreamBuffer,
+ pucStreamBufferStorageArea,
+ xBufferSizeBytes,
+ xTriggerLevelBytes,
+ ucFlags );
+
+ /* Remember this was statically allocated in case it is ever deleted
+ again. */
+ pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+ traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+ xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+ }
+ else
+ {
+ xReturn = NULL;
+ traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+ }
+
+ return xReturn;
+ }
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+ configASSERT( pxStreamBuffer );
+
+ traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+ {
+ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* Both the structure and the buffer were allocated using a single call
+ to pvPortMalloc(), hence only one call to vPortFree() is required. */
+ vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+ }
+ #else
+ {
+ /* Should not be possible to get here, ucFlags must be corrupt.
+ Force an assert. */
+ configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+ }
+ #endif
+ }
+ else
+ {
+ /* The structure and buffer were not allocated dynamically and cannot be
+ freed - just scrub the structure so future use will assert. */
+ ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+ }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxStreamBufferNumber;
+#endif
+
+ configASSERT( pxStreamBuffer );
+
+ #if( configUSE_TRACE_FACILITY == 1 )
+ {
+ /* Store the stream buffer number so it can be restored after the
+ reset. */
+ uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+ }
+ #endif
+
+ /* Can only reset a message buffer if there are no tasks blocked on it. */
+ taskENTER_CRITICAL();
+ {
+ if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+ {
+ if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+ {
+ prvInitialiseNewStreamBuffer( pxStreamBuffer,
+ pxStreamBuffer->pucBuffer,
+ pxStreamBuffer->xLength,
+ pxStreamBuffer->xTriggerLevelBytes,
+ pxStreamBuffer->ucFlags );
+ xReturn = pdPASS;
+
+ #if( configUSE_TRACE_FACILITY == 1 )
+ {
+ pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+ }
+ #endif
+
+ traceSTREAM_BUFFER_RESET( xStreamBuffer );
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+ configASSERT( pxStreamBuffer );
+
+ /* It is not valid for the trigger level to be 0. */
+ if( xTriggerLevel == ( size_t ) 0 )
+ {
+ xTriggerLevel = ( size_t ) 1;
+ }
+
+ /* The trigger level is the number of bytes that must be in the stream
+ buffer before a task that is waiting for data is unblocked. */
+ if( xTriggerLevel <= pxStreamBuffer->xLength )
+ {
+ pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+ configASSERT( pxStreamBuffer );
+
+ xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+ xSpace -= pxStreamBuffer->xHead;
+ xSpace -= ( size_t ) 1;
+
+ if( xSpace >= pxStreamBuffer->xLength )
+ {
+ xSpace -= pxStreamBuffer->xLength;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+ configASSERT( pxStreamBuffer );
+
+ xReturn = prvBytesInBuffer( pxStreamBuffer );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+ configASSERT( pvTxData );
+ configASSERT( pxStreamBuffer );
+
+ /* This send function is used to write to both message buffers and stream
+ buffers. If this is a message buffer then the space needed must be
+ increased by the amount of bytes needed to store the length of the
+ message. */
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ {
+ xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+ /* Overflow? */
+ configASSERT( xRequiredSpace > xDataLengthBytes );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xTicksToWait != ( TickType_t ) 0 )
+ {
+ vTaskSetTimeOutState( &xTimeOut );
+
+ do
+ {
+ /* Wait until the required number of bytes are free in the message
+ buffer. */
+ taskENTER_CRITICAL();
+ {
+ xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+ if( xSpace < xRequiredSpace )
+ {
+ /* Clear notification state as going to wait for space. */
+ ( void ) xTaskNotifyStateClear( NULL );
+
+ /* Should only be one writer. */
+ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+ pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+ }
+ else
+ {
+ taskEXIT_CRITICAL();
+ break;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+ ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+ pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+ } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xSpace == ( size_t ) 0 )
+ {
+ xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+ if( xReturn > ( size_t ) 0 )
+ {
+ traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+ /* Was a task waiting for the data? */
+ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+ {
+ sbSEND_COMPLETED( pxStreamBuffer );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ const void *pvTxData,
+ size_t xDataLengthBytes,
+ BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+ configASSERT( pvTxData );
+ configASSERT( pxStreamBuffer );
+
+ /* This send function is used to write to both message buffers and stream
+ buffers. If this is a message buffer then the space needed must be
+ increased by the amount of bytes needed to store the length of the
+ message. */
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ {
+ xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+ xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+ if( xReturn > ( size_t ) 0 )
+ {
+ /* Was a task waiting for the data? */
+ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+ {
+ sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+ const void * pvTxData,
+ size_t xDataLengthBytes,
+ size_t xSpace,
+ size_t xRequiredSpace )
+{
+ BaseType_t xShouldWrite;
+ size_t xReturn;
+
+ if( xSpace == ( size_t ) 0 )
+ {
+ /* Doesn't matter if this is a stream buffer or a message buffer, there
+ is no space to write. */
+ xShouldWrite = pdFALSE;
+ }
+ else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+ {
+ /* This is a stream buffer, as opposed to a message buffer, so writing a
+ stream of bytes rather than discrete messages. Write as many bytes as
+ possible. */
+ xShouldWrite = pdTRUE;
+ xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+ }
+ else if( xSpace >= xRequiredSpace )
+ {
+ /* This is a message buffer, as opposed to a stream buffer, and there
+ is enough space to write both the message length and the message itself
+ into the buffer. Start by writing the length of the data, the data
+ itself will be written later in this function. */
+ xShouldWrite = pdTRUE;
+ ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+ }
+ else
+ {
+ /* There is space available, but not enough space. */
+ xShouldWrite = pdFALSE;
+ }
+
+ if( xShouldWrite != pdFALSE )
+ {
+ /* Writes the data itself. */
+ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+ }
+ else
+ {
+ xReturn = 0;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+ configASSERT( pvRxData );
+ configASSERT( pxStreamBuffer );
+
+ /* This receive function is used by both message buffers, which store
+ discrete messages, and stream buffers, which store a continuous stream of
+ bytes. Discrete messages include an additional
+ sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+ message. */
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ {
+ xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+ }
+ else
+ {
+ xBytesToStoreMessageLength = 0;
+ }
+
+ if( xTicksToWait != ( TickType_t ) 0 )
+ {
+ /* Checking if there is data and clearing the notification state must be
+ performed atomically. */
+ taskENTER_CRITICAL();
+ {
+ xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+ /* If this function was invoked by a message buffer read then
+ xBytesToStoreMessageLength holds the number of bytes used to hold
+ the length of the next discrete message. If this function was
+ invoked by a stream buffer read then xBytesToStoreMessageLength will
+ be 0. */
+ if( xBytesAvailable <= xBytesToStoreMessageLength )
+ {
+ /* Clear notification state as going to wait for data. */
+ ( void ) xTaskNotifyStateClear( NULL );
+
+ /* Should only be one reader. */
+ configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+ pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ if( xBytesAvailable <= xBytesToStoreMessageLength )
+ {
+ /* Wait for data to be available. */
+ traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+ ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+ pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+ /* Recheck the data available after blocking. */
+ xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+ }
+
+ /* Whether receiving a discrete message (where xBytesToStoreMessageLength
+ holds the number of bytes used to store the message length) or a stream of
+ bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+ available must be greater than xBytesToStoreMessageLength to be able to
+ read bytes from the buffer. */
+ if( xBytesAvailable > xBytesToStoreMessageLength )
+ {
+ xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+ /* Was a task waiting for space in the buffer? */
+ if( xReceivedLength != ( size_t ) 0 )
+ {
+ traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+ sbRECEIVE_COMPLETED( pxStreamBuffer );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+ configASSERT( pxStreamBuffer );
+
+ /* Ensure the stream buffer is being used as a message buffer. */
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ {
+ xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+ if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+ {
+ /* The number of bytes available is greater than the number of bytes
+ required to hold the length of the next message, so another message
+ is available. Return its length without removing the length bytes
+ from the buffer. A copy of the tail is stored so the buffer can be
+ returned to its prior state as the message is not actually being
+ removed from the buffer. */
+ xOriginalTail = pxStreamBuffer->xTail;
+ ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+ xReturn = ( size_t ) xTempReturn;
+ pxStreamBuffer->xTail = xOriginalTail;
+ }
+ else
+ {
+ /* The minimum amount of bytes in a message buffer is
+ ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+ less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+ value is 0. */
+ configASSERT( xBytesAvailable == 0 );
+ xReturn = 0;
+ }
+ }
+ else
+ {
+ xReturn = 0;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+ configASSERT( pvRxData );
+ configASSERT( pxStreamBuffer );
+
+ /* This receive function is used by both message buffers, which store
+ discrete messages, and stream buffers, which store a continuous stream of
+ bytes. Discrete messages include an additional
+ sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+ message. */
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ {
+ xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+ }
+ else
+ {
+ xBytesToStoreMessageLength = 0;
+ }
+
+ xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+ /* Whether receiving a discrete message (where xBytesToStoreMessageLength
+ holds the number of bytes used to store the message length) or a stream of
+ bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+ available must be greater than xBytesToStoreMessageLength to be able to
+ read bytes from the buffer. */
+ if( xBytesAvailable > xBytesToStoreMessageLength )
+ {
+ xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+ /* Was a task waiting for space in the buffer? */
+ if( xReceivedLength != ( size_t ) 0 )
+ {
+ sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+ return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+ void *pvRxData,
+ size_t xBufferLengthBytes,
+ size_t xBytesAvailable,
+ size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+ if( xBytesToStoreMessageLength != ( size_t ) 0 )
+ {
+ /* A discrete message is being received. First receive the length
+ of the message. A copy of the tail is stored so the buffer can be
+ returned to its prior state if the length of the message is too
+ large for the provided buffer. */
+ xOriginalTail = pxStreamBuffer->xTail;
+ ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+ xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+ /* Reduce the number of bytes available by the number of bytes just
+ read out. */
+ xBytesAvailable -= xBytesToStoreMessageLength;
+
+ /* Check there is enough space in the buffer provided by the
+ user. */
+ if( xNextMessageLength > xBufferLengthBytes )
+ {
+ /* The user has provided insufficient space to read the message
+ so return the buffer to its previous state (so the length of
+ the message is in the buffer again). */
+ pxStreamBuffer->xTail = xOriginalTail;
+ xNextMessageLength = 0;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* A stream of bytes is being received (as opposed to a discrete
+ message), so read as many bytes as possible. */
+ xNextMessageLength = xBufferLengthBytes;
+ }
+
+ /* Read the actual data. */
+ xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+ return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+ configASSERT( pxStreamBuffer );
+
+ /* True if no bytes are available. */
+ xTail = pxStreamBuffer->xTail;
+ if( pxStreamBuffer->xHead == xTail )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+ configASSERT( pxStreamBuffer );
+
+ /* This generic version of the receive function is used by both message
+ buffers, which store discrete messages, and stream buffers, which store a
+ continuous stream of bytes. Discrete messages include an additional
+ sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ {
+ xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+ }
+ else
+ {
+ xBytesToStoreMessageLength = 0;
+ }
+
+ /* True if the available space equals zero. */
+ if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+ configASSERT( pxStreamBuffer );
+
+ uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+ {
+ ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+ ( uint32_t ) 0,
+ eNoAction,
+ pxHigherPriorityTaskWoken );
+ ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+ configASSERT( pxStreamBuffer );
+
+ uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+ {
+ ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+ ( uint32_t ) 0,
+ eNoAction,
+ pxHigherPriorityTaskWoken );
+ ( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+ configASSERT( xCount > ( size_t ) 0 );
+
+ xNextHead = pxStreamBuffer->xHead;
+
+ /* Calculate the number of bytes that can be added in the first write -
+ which may be less than the total number of bytes that need to be added if
+ the buffer will wrap back to the beginning. */
+ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+ /* Write as many bytes as can be written in the first write. */
+ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+ ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+ /* If the number of bytes written was less than the number that could be
+ written in the first write... */
+ if( xCount > xFirstLength )
+ {
+ /* ...then write the remaining bytes to the start of the buffer. */
+ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+ ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xNextHead += xCount;
+ if( xNextHead >= pxStreamBuffer->xLength )
+ {
+ xNextHead -= pxStreamBuffer->xLength;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ pxStreamBuffer->xHead = xNextHead;
+
+ return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+ /* Use the minimum of the wanted bytes and the available bytes. */
+ xCount = configMIN( xBytesAvailable, xMaxCount );
+
+ if( xCount > ( size_t ) 0 )
+ {
+ xNextTail = pxStreamBuffer->xTail;
+
+ /* Calculate the number of bytes that can be read - which may be
+ less than the number wanted if the data wraps around to the start of
+ the buffer. */
+ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+ /* Obtain the number of bytes it is possible to obtain in the first
+ read. Asserts check bounds of read and write. */
+ configASSERT( xFirstLength <= xMaxCount );
+ configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+ ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+ /* If the total number of wanted bytes is greater than the number
+ that could be read in the first read... */
+ if( xCount > xFirstLength )
+ {
+ /*...then read the remaining bytes from the start of the buffer. */
+ configASSERT( xCount <= xMaxCount );
+ ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Move the tail pointer to effectively remove the data read from
+ the buffer. */
+ xNextTail += xCount;
+
+ if( xNextTail >= pxStreamBuffer->xLength )
+ {
+ xNextTail -= pxStreamBuffer->xLength;
+ }
+
+ pxStreamBuffer->xTail = xNextTail;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+ xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+ xCount -= pxStreamBuffer->xTail;
+ if ( xCount >= pxStreamBuffer->xLength )
+ {
+ xCount -= pxStreamBuffer->xLength;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+ uint8_t * const pucBuffer,
+ size_t xBufferSizeBytes,
+ size_t xTriggerLevelBytes,
+ uint8_t ucFlags )
+{
+ /* Assert here is deliberately writing to the entire buffer to ensure it can
+ be written to without generating exceptions, and is setting the buffer to a
+ known value to assist in development/debugging. */
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* The value written just has to be identifiable when looking at the
+ memory. Don't use 0xA5 as that is the stack fill value and could
+ result in confusion as to what is actually being observed. */
+ const BaseType_t xWriteValue = 0x55;
+ configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+ } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+ #endif
+
+ ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+ pxStreamBuffer->pucBuffer = pucBuffer;
+ pxStreamBuffer->xLength = xBufferSizeBytes;
+ pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+ pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+ {
+ return xStreamBuffer->uxStreamBufferNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+ {
+ xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+ {
+ return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..f9c4eb6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5214 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+ /* At the bottom of this file are two optional functions that can be used
+ to generate human readable text from the raw data generated by the
+ uxTaskGetSystemState() function. Note the formatting functions are provided
+ for convenience only, and are NOT considered part of the kernel. */
+ #include <stdio.h>
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+ /* If the cooperative scheduler is being used then a yield should not be
+ performed just because a higher priority task has been woken. */
+ #define taskYIELD_IF_USING_PREEMPTION()
+#else
+ #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION ( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED ( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created. This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE ( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined. If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+ #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1
+#else
+ #define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR ( 'X' )
+#define tskBLOCKED_CHAR ( 'B' )
+#define tskREADY_CHAR ( 'R' )
+#define tskDELETED_CHAR ( 'D' )
+#define tskSUSPENDED_CHAR ( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+ #define static
+#endif
+
+/* The name allocated to the Idle task. This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+ #define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+ /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+ performed in a generic way that is not optimised to any particular
+ microcontroller architecture. */
+
+ /* uxTopReadyPriority holds the priority of the highest priority ready
+ state task. */
+ #define taskRECORD_READY_PRIORITY( uxPriority ) \
+ { \
+ if( ( uxPriority ) > uxTopReadyPriority ) \
+ { \
+ uxTopReadyPriority = ( uxPriority ); \
+ } \
+ } /* taskRECORD_READY_PRIORITY */
+
+ /*-----------------------------------------------------------*/
+
+ #define taskSELECT_HIGHEST_PRIORITY_TASK() \
+ { \
+ UBaseType_t uxTopPriority = uxTopReadyPriority; \
+ \
+ /* Find the highest priority queue that contains ready tasks. */ \
+ while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \
+ { \
+ configASSERT( uxTopPriority ); \
+ --uxTopPriority; \
+ } \
+ \
+ /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
+ the same priority get an equal share of the processor time. */ \
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
+ uxTopReadyPriority = uxTopPriority; \
+ } /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+ /*-----------------------------------------------------------*/
+
+ /* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+ they are only required when a port optimised method of task selection is
+ being used. */
+ #define taskRESET_READY_PRIORITY( uxPriority )
+ #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+ /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+ performed in a way that is tailored to the particular microcontroller
+ architecture being used. */
+
+ /* A port optimised version is provided. Call the port defined macros. */
+ #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+ /*-----------------------------------------------------------*/
+
+ #define taskSELECT_HIGHEST_PRIORITY_TASK() \
+ { \
+ UBaseType_t uxTopPriority; \
+ \
+ /* Find the highest priority list that contains ready tasks. */ \
+ portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \
+ configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
+ } /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+ /*-----------------------------------------------------------*/
+
+ /* A port optimised version is provided, call it only if the TCB being reset
+ is being referenced from a ready list. If it is referenced from a delayed
+ or suspended list then it won't be in a ready list. */
+ #define taskRESET_READY_PRIORITY( uxPriority ) \
+ { \
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \
+ { \
+ portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \
+ } \
+ }
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS() \
+{ \
+ List_t *pxTemp; \
+ \
+ /* The delayed tasks list should be empty when the lists are switched. */ \
+ configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \
+ \
+ pxTemp = pxDelayedTaskList; \
+ pxDelayedTaskList = pxOverflowDelayedTaskList; \
+ pxOverflowDelayedTaskList = pxTemp; \
+ xNumOfOverflows++; \
+ prvResetNextTaskUnblockTime(); \
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task. It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB ) \
+ traceMOVED_TASK_TO_READY_STATE( pxTCB ); \
+ taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \
+ vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+ tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter. This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order). However, it is occasionally borrowed for other purposes. It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose. The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+ #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U
+#else
+ #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL
+#endif
+
+/*
+ * Task control block. A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+ volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+ #if ( portUSING_MPU_WRAPPERS == 1 )
+ xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+ #endif
+
+ ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+ ListItem_t xEventListItem; /*< Used to reference a task from an event list. */
+ UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */
+ StackType_t *pxStack; /*< Points to the start of the stack. */
+ char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+ #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+ StackType_t *pxEndOfStack; /*< Points to the highest valid address for the stack. */
+ #endif
+
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+ UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+ #endif
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */
+ UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
+ #endif
+
+ #if ( configUSE_MUTEXES == 1 )
+ UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+ UBaseType_t uxMutexesHeld;
+ #endif
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ TaskHookFunction_t pxTaskTag;
+ #endif
+
+ #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+ void *pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+ #endif
+
+ #if( configGENERATE_RUN_TIME_STATS == 1 )
+ uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
+ #endif
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ /* Allocate a Newlib reent structure that is specific to this task.
+ Note Newlib support has been included by popular demand, but is not
+ used by the FreeRTOS maintainers themselves. FreeRTOS is not
+ responsible for resulting newlib operation. User must be familiar with
+ newlib and must provide system-wide implementations of the necessary
+ stubs. Be warned that (at the time of writing) the current newlib design
+ implements a system-wide malloc() that must be provided with locks. */
+ struct _reent xNewLib_reent;
+ #endif
+
+ #if( configUSE_TASK_NOTIFICATIONS == 1 )
+ volatile uint32_t ulNotifiedValue;
+ volatile uint8_t ucNotifyState;
+ #endif
+
+ /* See the comments in FreeRTOS.h with the definition of
+ tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+ uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+ #endif
+
+ #if( INCLUDE_xTaskAbortDelay == 1 )
+ uint8_t ucDelayAborted;
+ #endif
+
+ #if( configUSE_POSIX_ERRNO == 1 )
+ int iTaskErrno;
+ #endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = { 0 };/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1 = { 0 }; /*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2 = { 0 }; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL; /*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList = { 0 }; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+PRIVILEGED_DATA static List_t xTasksWaitingTermination = { 0 }; /*< Tasks that have been deleted - but their memory not yet freed. */
+ PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ PRIVILEGED_DATA static List_t xSuspendedTaskList = { 0 }; /*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+ int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended. Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended. The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ /* Do not move these variables to function scope as doing so prevents the
+ code working with debuggers that need to remove the static qualifier. */
+ PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */
+ PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if( configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+ extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+ extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler. This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions. The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+ static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task. This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted. If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state. Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+ static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+ static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+ static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+ /*
+ * Helper function used to pad task names with spaces when printing out
+ * human readable tables of task information.
+ */
+ static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
+ const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const uint32_t ulStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * const pxCreatedTask,
+ TCB_t *pxNewTCB,
+ const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+ static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+ const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const uint32_t ulStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ StackType_t * const puxStackBuffer,
+ StaticTask_t * const pxTaskBuffer )
+ {
+ TCB_t *pxNewTCB;
+ TaskHandle_t xReturn;
+
+ configASSERT( puxStackBuffer != NULL );
+ configASSERT( pxTaskBuffer != NULL );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* Sanity check that the size of the structure used to declare a
+ variable of type StaticTask_t equals the size of the real task
+ structure. */
+ volatile size_t xSize = sizeof( StaticTask_t );
+ configASSERT( xSize == sizeof( TCB_t ) );
+ ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+ }
+ #endif /* configASSERT_DEFINED */
+
+
+ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+ {
+ /* The memory used for the task's TCB and stack are passed into this
+ function - use them. */
+ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+ {
+ /* Tasks can be created statically or dynamically, so note this
+ task was created statically in case the task is later deleted. */
+ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+ }
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+ prvAddNewTaskToReadyList( pxNewTCB );
+ }
+ else
+ {
+ xReturn = NULL;
+ }
+
+ return xReturn;
+ }
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+ BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+ {
+ TCB_t *pxNewTCB;
+ BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+ configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+ configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+ if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+ {
+ /* Allocate space for the TCB. Where the memory comes from depends
+ on the implementation of the port malloc function and whether or
+ not static allocation is being used. */
+ pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+ /* Store the stack location in the TCB. */
+ pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+ {
+ /* Tasks can be created statically or dynamically, so note this
+ task was created statically in case the task is later deleted. */
+ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+ }
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+ prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
+ pxTaskDefinition->pcName,
+ ( uint32_t ) pxTaskDefinition->usStackDepth,
+ pxTaskDefinition->pvParameters,
+ pxTaskDefinition->uxPriority,
+ pxCreatedTask, pxNewTCB,
+ pxTaskDefinition->xRegions );
+
+ prvAddNewTaskToReadyList( pxNewTCB );
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
+ }
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+ BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+ {
+ TCB_t *pxNewTCB;
+ BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+ configASSERT( pxTaskDefinition->puxStackBuffer );
+
+ if( pxTaskDefinition->puxStackBuffer != NULL )
+ {
+ /* Allocate space for the TCB. Where the memory comes from depends
+ on the implementation of the port malloc function and whether or
+ not static allocation is being used. */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+ if( pxNewTCB != NULL )
+ {
+ /* Store the stack location in the TCB. */
+ pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+ {
+ /* Tasks can be created statically or dynamically, so note
+ this task had a statically allocated stack in case it is
+ later deleted. The TCB was allocated dynamically. */
+ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+ }
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+ prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
+ pxTaskDefinition->pcName,
+ ( uint32_t ) pxTaskDefinition->usStackDepth,
+ pxTaskDefinition->pvParameters,
+ pxTaskDefinition->uxPriority,
+ pxCreatedTask, pxNewTCB,
+ pxTaskDefinition->xRegions );
+
+ prvAddNewTaskToReadyList( pxNewTCB );
+ xReturn = pdPASS;
+ }
+ }
+
+ return xReturn;
+ }
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+ BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+ const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const configSTACK_DEPTH_TYPE usStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * const pxCreatedTask )
+ {
+ TCB_t *pxNewTCB;
+ BaseType_t xReturn;
+
+ /* If the stack grows down then allocate the stack then the TCB so the stack
+ does not grow into the TCB. Likewise if the stack grows up then allocate
+ the TCB then the stack. */
+ #if( portSTACK_GROWTH > 0 )
+ {
+ /* Allocate space for the TCB. Where the memory comes from depends on
+ the implementation of the port malloc function and whether or not static
+ allocation is being used. */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+ if( pxNewTCB != NULL )
+ {
+ /* Allocate space for the stack used by the task being created.
+ The base of the stack memory stored in the TCB so the task can
+ be deleted later if required. */
+ pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ if( pxNewTCB->pxStack == NULL )
+ {
+ /* Could not allocate the stack. Delete the allocated TCB. */
+ vPortFree( pxNewTCB );
+ pxNewTCB = NULL;
+ }
+ }
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ StackType_t *pxStack;
+
+ /* Allocate space for the stack used by the task being created. */
+ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+ if( pxStack != NULL )
+ {
+ /* Allocate space for the TCB. */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+ if( pxNewTCB != NULL )
+ {
+ /* Store the stack location in the TCB. */
+ pxNewTCB->pxStack = pxStack;
+ }
+ else
+ {
+ /* The stack cannot be used as the TCB was not created. Free
+ it again. */
+ vPortFree( pxStack );
+ }
+ }
+ else
+ {
+ pxNewTCB = NULL;
+ }
+ }
+ #endif /* portSTACK_GROWTH */
+
+ if( pxNewTCB != NULL )
+ {
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+ {
+ /* Tasks can be created statically or dynamically, so note this
+ task was created dynamically in case it is later deleted. */
+ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+ }
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+ prvAddNewTaskToReadyList( pxNewTCB );
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
+ const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const uint32_t ulStackDepth,
+ void * const pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t * const pxCreatedTask,
+ TCB_t *pxNewTCB,
+ const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+ #if( portUSING_MPU_WRAPPERS == 1 )
+ /* Should the task be created in privileged mode? */
+ BaseType_t xRunPrivileged;
+ if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+ {
+ xRunPrivileged = pdTRUE;
+ }
+ else
+ {
+ xRunPrivileged = pdFALSE;
+ }
+ uxPriority &= ~portPRIVILEGE_BIT;
+ #endif /* portUSING_MPU_WRAPPERS == 1 */
+
+ /* Avoid dependency on memset() if it is not required. */
+ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+ {
+ /* Fill the stack with a known value to assist debugging. */
+ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+ }
+ #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+ /* Calculate the top of stack address. This depends on whether the stack
+ grows from high memory to low (as per the 80x86) or vice versa.
+ portSTACK_GROWTH is used to make the result positive or negative as required
+ by the port. */
+ #if( portSTACK_GROWTH < 0 )
+ {
+ pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+ pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
+
+ /* Check the alignment of the calculated top of stack is correct. */
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+ #if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+ {
+ /* Also record the stack's high address, which may assist
+ debugging. */
+ pxNewTCB->pxEndOfStack = pxTopOfStack;
+ }
+ #endif /* configRECORD_STACK_HIGH_ADDRESS */
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxTopOfStack = pxNewTCB->pxStack;
+
+ /* Check the alignment of the stack buffer is correct. */
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+ /* The other extreme of the stack space is required if stack checking is
+ performed. */
+ pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+ }
+ #endif /* portSTACK_GROWTH */
+
+ /* Store the task name in the TCB. */
+ if( pcName != NULL )
+ {
+ for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ {
+ pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+ /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+ configMAX_TASK_NAME_LEN characters just in case the memory after the
+ string is not accessible (extremely unlikely). */
+ if( pcName[ x ] == ( char ) 0x00 )
+ {
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* Ensure the name string is terminated in the case that the string length
+ was greater or equal to configMAX_TASK_NAME_LEN. */
+ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+ }
+ else
+ {
+ /* The task has not been given a name, so just ensure there is a NULL
+ terminator when it is read out. */
+ pxNewTCB->pcTaskName[ 0 ] = 0x00;
+ }
+
+ /* This is used as an array index so must ensure it's not too large. First
+ remove the privilege bit if one is present. */
+ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+ {
+ uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ pxNewTCB->uxPriority = uxPriority;
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ pxNewTCB->uxBasePriority = uxPriority;
+ pxNewTCB->uxMutexesHeld = 0;
+ }
+ #endif /* configUSE_MUTEXES */
+
+ vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+ vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+ /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
+ back to the containing TCB from a generic item in a list. */
+ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+ /* Event lists are always in priority order. */
+ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+ {
+ pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+ }
+ #endif /* portCRITICAL_NESTING_IN_TCB */
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ {
+ pxNewTCB->pxTaskTag = NULL;
+ }
+ #endif /* configUSE_APPLICATION_TASK_TAG */
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ pxNewTCB->ulRunTimeCounter = 0UL;
+ }
+ #endif /* configGENERATE_RUN_TIME_STATS */
+
+ #if ( portUSING_MPU_WRAPPERS == 1 )
+ {
+ vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+ }
+ #else
+ {
+ /* Avoid compiler warning about unreferenced parameter. */
+ ( void ) xRegions;
+ }
+ #endif
+
+ #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+ {
+ for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+ {
+ pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+ }
+ }
+ #endif
+
+ #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+ {
+ pxNewTCB->ulNotifiedValue = 0;
+ pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+ }
+ #endif
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ /* Initialise this task's Newlib reent structure. */
+ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+ }
+ #endif
+
+ #if( INCLUDE_xTaskAbortDelay == 1 )
+ {
+ pxNewTCB->ucDelayAborted = pdFALSE;
+ }
+ #endif
+
+ /* Initialize the TCB stack to look as if the task was already running,
+ but had been interrupted by the scheduler. The return address is set
+ to the start of the task function. Once the stack has been initialised
+ the top of stack variable is updated. */
+ #if( portUSING_MPU_WRAPPERS == 1 )
+ {
+ /* If the port has capability to detect stack overflow,
+ pass the stack end address to the stack initialization
+ function as well. */
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ {
+ #if( portSTACK_GROWTH < 0 )
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #endif /* portSTACK_GROWTH */
+ }
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+ }
+ #else /* portUSING_MPU_WRAPPERS */
+ {
+ /* If the port has capability to detect stack overflow,
+ pass the stack end address to the stack initialization
+ function as well. */
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ {
+ #if( portSTACK_GROWTH < 0 )
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+ }
+ #endif /* portSTACK_GROWTH */
+ }
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+ }
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+ }
+ #endif /* portUSING_MPU_WRAPPERS */
+
+ if( pxCreatedTask != NULL )
+ {
+ /* Pass the handle out in an anonymous way. The handle can be used to
+ change the created task's priority, delete the created task, etc.*/
+ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+ /* Ensure interrupts don't access the task lists while the lists are being
+ updated. */
+ taskENTER_CRITICAL();
+ {
+ uxCurrentNumberOfTasks++;
+ if( pxCurrentTCB == NULL )
+ {
+ /* There are no other tasks, or all the other tasks are in
+ the suspended state - make this the current task. */
+ pxCurrentTCB = pxNewTCB;
+
+ if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+ {
+ /* This is the first task to be created so do the preliminary
+ initialisation required. We will not recover if this call
+ fails, but we will report the failure. */
+ prvInitialiseTaskLists();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* If the scheduler is not already running, make this task the
+ current task if it is the highest priority task to be created
+ so far. */
+ if( xSchedulerRunning == pdFALSE )
+ {
+ if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+ {
+ pxCurrentTCB = pxNewTCB;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ uxTaskNumber++;
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ /* Add a counter into the TCB for tracing only. */
+ pxNewTCB->uxTCBNumber = uxTaskNumber;
+ }
+ #endif /* configUSE_TRACE_FACILITY */
+ traceTASK_CREATE( pxNewTCB );
+
+ prvAddTaskToReadyList( pxNewTCB );
+
+ portSETUP_TCB( pxNewTCB );
+ }
+ taskEXIT_CRITICAL();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* If the created task is of a higher priority than the current task
+ then it should run now. */
+ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+ {
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+ void vTaskDelete( TaskHandle_t xTaskToDelete )
+ {
+ TCB_t *pxTCB;
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the calling task that is
+ being deleted. */
+ pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+ /* Remove task from the ready list. */
+ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Is the task waiting on an event also? */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Increment the uxTaskNumber also so kernel aware debuggers can
+ detect that the task lists need re-generating. This is done before
+ portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+ not return. */
+ uxTaskNumber++;
+
+ if( pxTCB == pxCurrentTCB )
+ {
+ /* A task is deleting itself. This cannot complete within the
+ task itself, as a context switch to another task is required.
+ Place the task in the termination list. The idle task will
+ check the termination list and free up any memory allocated by
+ the scheduler for the TCB and stack of the deleted task. */
+ vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+ /* Increment the ucTasksDeleted variable so the idle task knows
+ there is a task that has been deleted and that it should therefore
+ check the xTasksWaitingTermination list. */
+ ++uxDeletedTasksWaitingCleanUp;
+
+ /* The pre-delete hook is primarily for the Windows simulator,
+ in which Windows specific clean up operations are performed,
+ after which it is not possible to yield away from this task -
+ hence xYieldPending is used to latch that a context switch is
+ required. */
+ portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+ }
+ else
+ {
+ --uxCurrentNumberOfTasks;
+ prvDeleteTCB( pxTCB );
+
+ /* Reset the next expected unblock time in case it referred to
+ the task that has just been deleted. */
+ prvResetNextTaskUnblockTime();
+ }
+
+ traceTASK_DELETE( pxTCB );
+ }
+ taskEXIT_CRITICAL();
+
+ /* Force a reschedule if it is the currently running task that has just
+ been deleted. */
+ if( xSchedulerRunning != pdFALSE )
+ {
+ if( pxTCB == pxCurrentTCB )
+ {
+ configASSERT( uxSchedulerSuspended == 0 );
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+ void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+ {
+ TickType_t xTimeToWake;
+ BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+ configASSERT( pxPreviousWakeTime );
+ configASSERT( ( xTimeIncrement > 0U ) );
+ configASSERT( uxSchedulerSuspended == 0 );
+
+ vTaskSuspendAll();
+ {
+ /* Minor optimisation. The tick count cannot change in this
+ block. */
+ const TickType_t xConstTickCount = xTickCount;
+
+ /* Generate the tick time at which the task wants to wake. */
+ xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+ if( xConstTickCount < *pxPreviousWakeTime )
+ {
+ /* The tick count has overflowed since this function was
+ lasted called. In this case the only time we should ever
+ actually delay is if the wake time has also overflowed,
+ and the wake time is greater than the tick time. When this
+ is the case it is as if neither time had overflowed. */
+ if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+ {
+ xShouldDelay = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* The tick time has not overflowed. In this case we will
+ delay if either the wake time has overflowed, and/or the
+ tick time is less than the wake time. */
+ if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+ {
+ xShouldDelay = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* Update the wake time ready for the next call. */
+ *pxPreviousWakeTime = xTimeToWake;
+
+ if( xShouldDelay != pdFALSE )
+ {
+ traceTASK_DELAY_UNTIL( xTimeToWake );
+
+ /* prvAddCurrentTaskToDelayedList() needs the block time, not
+ the time to wake, so subtract the current tick count. */
+ prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ xAlreadyYielded = xTaskResumeAll();
+
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may
+ have put ourselves to sleep. */
+ if( xAlreadyYielded == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+ void vTaskDelay( const TickType_t xTicksToDelay )
+ {
+ BaseType_t xAlreadyYielded = pdFALSE;
+
+ /* A delay time of zero just forces a reschedule. */
+ if( xTicksToDelay > ( TickType_t ) 0U )
+ {
+ configASSERT( uxSchedulerSuspended == 0 );
+ vTaskSuspendAll();
+ {
+ traceTASK_DELAY();
+
+ /* A task that is removed from the event list while the
+ scheduler is suspended will not get placed in the ready
+ list or removed from the blocked list until the scheduler
+ is resumed.
+
+ This task cannot be in an event list as it is the currently
+ executing task. */
+ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+ }
+ xAlreadyYielded = xTaskResumeAll();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may
+ have put ourselves to sleep. */
+ if( xAlreadyYielded == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+ eTaskState eTaskGetState( TaskHandle_t xTask )
+ {
+ eTaskState eReturn;
+ List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+ const TCB_t * const pxTCB = xTask;
+
+ configASSERT( pxTCB );
+
+ if( pxTCB == pxCurrentTCB )
+ {
+ /* The task calling this function is querying its own state. */
+ eReturn = eRunning;
+ }
+ else
+ {
+ taskENTER_CRITICAL();
+ {
+ pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+ pxDelayedList = pxDelayedTaskList;
+ pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+ }
+ taskEXIT_CRITICAL();
+
+ if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+ {
+ /* The task being queried is referenced from one of the Blocked
+ lists. */
+ eReturn = eBlocked;
+ }
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ else if( pxStateList == &xSuspendedTaskList )
+ {
+ /* The task being queried is referenced from the suspended
+ list. Is it genuinely suspended or is it blocked
+ indefinitely? */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+ {
+ #if( configUSE_TASK_NOTIFICATIONS == 1 )
+ {
+ /* The task does not appear on the event list item of
+ and of the RTOS objects, but could still be in the
+ blocked state if it is waiting on its notification
+ rather than waiting on an object. */
+ if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+ {
+ eReturn = eBlocked;
+ }
+ else
+ {
+ eReturn = eSuspended;
+ }
+ }
+ #else
+ {
+ eReturn = eSuspended;
+ }
+ #endif
+ }
+ else
+ {
+ eReturn = eBlocked;
+ }
+ }
+ #endif
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+ {
+ /* The task being queried is referenced from the deleted
+ tasks list, or it is not referenced from any lists at
+ all. */
+ eReturn = eDeleted;
+ }
+ #endif
+
+ else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+ {
+ /* If the task is not in any other state, it must be in the
+ Ready (including pending ready) state. */
+ eReturn = eReady;
+ }
+ }
+
+ return eReturn;
+ } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+ UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+ {
+ TCB_t const *pxTCB;
+ UBaseType_t uxReturn;
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the priority of the task
+ that called uxTaskPriorityGet() that is being queried. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+ uxReturn = pxTCB->uxPriority;
+ }
+ taskEXIT_CRITICAL();
+
+ return uxReturn;
+ }
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+ UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+ {
+ TCB_t const *pxTCB;
+ UBaseType_t uxReturn, uxSavedInterruptState;
+
+ /* RTOS ports that support interrupt nesting have the concept of a
+ maximum system call (or maximum API call) interrupt priority.
+ Interrupts that are above the maximum system call priority are keep
+ permanently enabled, even when the RTOS kernel is in a critical section,
+ but cannot make any calls to FreeRTOS API functions. If configASSERT()
+ is defined in FreeRTOSConfig.h then
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has
+ been assigned a priority above the configured maximum system call
+ priority. Only FreeRTOS functions that end in FromISR can be called
+ from interrupts that have been assigned a priority at or (logically)
+ below the maximum system call interrupt priority. FreeRTOS maintains a
+ separate interrupt safe API to ensure interrupt entry is as fast and as
+ simple as possible. More information (albeit Cortex-M specific) is
+ provided on the following link:
+ https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* If null is passed in here then it is the priority of the calling
+ task that is being queried. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+ uxReturn = pxTCB->uxPriority;
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+ return uxReturn;
+ }
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+ void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+ {
+ TCB_t *pxTCB;
+ UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+ BaseType_t xYieldRequired = pdFALSE;
+
+ configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+ /* Ensure the new priority is valid. */
+ if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+ {
+ uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the priority of the calling
+ task that is being changed. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ uxCurrentBasePriority = pxTCB->uxBasePriority;
+ }
+ #else
+ {
+ uxCurrentBasePriority = pxTCB->uxPriority;
+ }
+ #endif
+
+ if( uxCurrentBasePriority != uxNewPriority )
+ {
+ /* The priority change may have readied a task of higher
+ priority than the calling task. */
+ if( uxNewPriority > uxCurrentBasePriority )
+ {
+ if( pxTCB != pxCurrentTCB )
+ {
+ /* The priority of a task other than the currently
+ running task is being raised. Is the priority being
+ raised above that of the running task? */
+ if( uxNewPriority >= pxCurrentTCB->uxPriority )
+ {
+ xYieldRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* The priority of the running task is being raised,
+ but the running task must already be the highest
+ priority task able to run so no yield is required. */
+ }
+ }
+ else if( pxTCB == pxCurrentTCB )
+ {
+ /* Setting the priority of the running task down means
+ there may now be another task of higher priority that
+ is ready to execute. */
+ xYieldRequired = pdTRUE;
+ }
+ else
+ {
+ /* Setting the priority of any other task down does not
+ require a yield as the running task must be above the
+ new priority of the task being modified. */
+ }
+
+ /* Remember the ready list the task might be referenced from
+ before its uxPriority member is changed so the
+ taskRESET_READY_PRIORITY() macro can function correctly. */
+ uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ /* Only change the priority being used if the task is not
+ currently using an inherited priority. */
+ if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+ {
+ pxTCB->uxPriority = uxNewPriority;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The base priority gets set whatever. */
+ pxTCB->uxBasePriority = uxNewPriority;
+ }
+ #else
+ {
+ pxTCB->uxPriority = uxNewPriority;
+ }
+ #endif
+
+ /* Only reset the event list item value if the value is not
+ being used for anything else. */
+ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ {
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* If the task is in the blocked or suspended list we need do
+ nothing more than change its priority variable. However, if
+ the task is in a ready list it needs to be removed and placed
+ in the list appropriate to its new priority. */
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+ {
+ /* The task is currently in its ready list - remove before
+ adding it to it's new ready list. As we are in a critical
+ section we can do this even if the scheduler is suspended. */
+ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* It is known that the task is in its ready list so
+ there is no need to check again and the port level
+ reset macro can be called directly. */
+ portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xYieldRequired != pdFALSE )
+ {
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Remove compiler warning about unused variables when the port
+ optimised task selection is not being used. */
+ ( void ) uxPriorityUsedOnEntry;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+ {
+ TCB_t *pxTCB;
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the running task that is
+ being suspended. */
+ pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+ traceTASK_SUSPEND( pxTCB );
+
+ /* Remove task from the ready/delayed list and place in the
+ suspended list. */
+ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Is the task waiting on an event also? */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+ #if( configUSE_TASK_NOTIFICATIONS == 1 )
+ {
+ if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+ {
+ /* The task was blocked to wait for a notification, but is
+ now suspended, so no notification was received. */
+ pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+ }
+ }
+ #endif
+ }
+ taskEXIT_CRITICAL();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* Reset the next expected unblock time in case it referred to the
+ task that is now in the Suspended state. */
+ taskENTER_CRITICAL();
+ {
+ prvResetNextTaskUnblockTime();
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( pxTCB == pxCurrentTCB )
+ {
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* The current task has just been suspended. */
+ configASSERT( uxSchedulerSuspended == 0 );
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ /* The scheduler is not running, but the task that was pointed
+ to by pxCurrentTCB has just been suspended and pxCurrentTCB
+ must be adjusted to point to a different task. */
+ if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+ {
+ /* No other tasks are ready, so set pxCurrentTCB back to
+ NULL so when the next task is created pxCurrentTCB will
+ be set to point to it no matter what its relative priority
+ is. */
+ pxCurrentTCB = NULL;
+ }
+ else
+ {
+ vTaskSwitchContext();
+ }
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+ {
+ BaseType_t xReturn = pdFALSE;
+ const TCB_t * const pxTCB = xTask;
+
+ /* Accesses xPendingReadyList so must be called from a critical
+ section. */
+
+ /* It does not make sense to check if the calling task is suspended. */
+ configASSERT( xTask );
+
+ /* Is the task being resumed actually in the suspended list? */
+ if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+ {
+ /* Has the task already been resumed from within an ISR? */
+ if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+ {
+ /* Is it in the suspended list because it is in the Suspended
+ state, or because is is blocked with no timeout? */
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961. The cast is only redundant when NULL is used. */
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+ } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ void vTaskResume( TaskHandle_t xTaskToResume )
+ {
+ TCB_t * const pxTCB = xTaskToResume;
+
+ /* It does not make sense to resume the calling task. */
+ configASSERT( xTaskToResume );
+
+ /* The parameter cannot be NULL as it is impossible to resume the
+ currently executing task. */
+ if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+ {
+ taskENTER_CRITICAL();
+ {
+ if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+ {
+ traceTASK_RESUME( pxTCB );
+
+ /* The ready list can be accessed even if the scheduler is
+ suspended because this is inside a critical section. */
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+
+ /* A higher priority task may have just been resumed. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ /* This yield may not cause the task just resumed to run,
+ but will leave the lists in the correct state for the
+ next yield. */
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+ BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+ {
+ BaseType_t xYieldRequired = pdFALSE;
+ TCB_t * const pxTCB = xTaskToResume;
+ UBaseType_t uxSavedInterruptStatus;
+
+ configASSERT( xTaskToResume );
+
+ /* RTOS ports that support interrupt nesting have the concept of a
+ maximum system call (or maximum API call) interrupt priority.
+ Interrupts that are above the maximum system call priority are keep
+ permanently enabled, even when the RTOS kernel is in a critical section,
+ but cannot make any calls to FreeRTOS API functions. If configASSERT()
+ is defined in FreeRTOSConfig.h then
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has
+ been assigned a priority above the configured maximum system call
+ priority. Only FreeRTOS functions that end in FromISR can be called
+ from interrupts that have been assigned a priority at or (logically)
+ below the maximum system call interrupt priority. FreeRTOS maintains a
+ separate interrupt safe API to ensure interrupt entry is as fast and as
+ simple as possible. More information (albeit Cortex-M specific) is
+ provided on the following link:
+ https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+ {
+ traceTASK_RESUME_FROM_ISR( pxTCB );
+
+ /* Check the ready lists can be accessed. */
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ /* Ready lists can be accessed so move the task from the
+ suspended list to the ready list directly. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ xYieldRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ /* The delayed or ready lists cannot be accessed so the task
+ is held in the pending ready list until the scheduler is
+ unsuspended. */
+ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xYieldRequired;
+ }
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+ /* Add the idle task at the lowest priority. */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+ StackType_t *pxIdleTaskStackBuffer = NULL;
+ uint32_t ulIdleTaskStackSize;
+
+ /* The Idle task is created using user provided RAM - obtain the
+ address of the RAM then create the idle task. */
+ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+ xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
+ configIDLE_TASK_NAME,
+ ulIdleTaskStackSize,
+ ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+ pxIdleTaskStackBuffer,
+ pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+ if( xIdleTaskHandle != NULL )
+ {
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ #else
+ {
+ /* The Idle task is being created using dynamically allocated RAM. */
+ xReturn = xTaskCreate( prvIdleTask,
+ configIDLE_TASK_NAME,
+ configMINIMAL_STACK_SIZE,
+ ( void * ) NULL,
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+ &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+ #if ( configUSE_TIMERS == 1 )
+ {
+ if( xReturn == pdPASS )
+ {
+ xReturn = xTimerCreateTimerTask();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_TIMERS */
+
+ if( xReturn == pdPASS )
+ {
+ /* freertos_tasks_c_additions_init() should only be called if the user
+ definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+ the only macro called by the function. */
+ #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+ {
+ freertos_tasks_c_additions_init();
+ }
+ #endif
+
+ /* Interrupts are turned off here, to ensure a tick does not occur
+ before or during the call to xPortStartScheduler(). The stacks of
+ the created tasks contain a status word with interrupts switched on
+ so interrupts will automatically get re-enabled when the first task
+ starts to run. */
+ portDISABLE_INTERRUPTS();
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ /* Switch Newlib's _impure_ptr variable to point to the _reent
+ structure specific to the task that will run first. */
+ _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+ }
+ #endif /* configUSE_NEWLIB_REENTRANT */
+
+ xNextTaskUnblockTime = portMAX_DELAY;
+ xSchedulerRunning = pdTRUE;
+ xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+ /* If configGENERATE_RUN_TIME_STATS is defined then the following
+ macro must be defined to configure the timer/counter used to generate
+ the run time counter time base. NOTE: If configGENERATE_RUN_TIME_STATS
+ is set to 0 and the following line fails to build then ensure you do not
+ have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+ FreeRTOSConfig.h file. */
+ portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+ traceTASK_SWITCHED_IN();
+
+ /* Setting up the timer tick is hardware specific and thus in the
+ portable interface. */
+ if( xPortStartScheduler() != pdFALSE )
+ {
+ /* Should not reach here as if the scheduler is running the
+ function will not return. */
+ }
+ else
+ {
+ /* Should only reach here if a task calls xTaskEndScheduler(). */
+ }
+ }
+ else
+ {
+ /* This line will only be reached if the kernel could not be started,
+ because there was not enough FreeRTOS heap to create the idle task
+ or the timer task. */
+ configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+ }
+
+ /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+ meaning xIdleTaskHandle is not used anywhere else. */
+ ( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+ /* Stop the scheduler interrupts and call the portable scheduler end
+ routine so the original ISRs can be restored if necessary. The port
+ layer must ensure interrupts enable bit is left in the correct state. */
+ portDISABLE_INTERRUPTS();
+ xSchedulerRunning = pdFALSE;
+ vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+ /* A critical section is not required as the variable is of type
+ BaseType_t. Please read Richard Barry's reply in the following link to a
+ post in the FreeRTOS support forum before reporting this as a bug! -
+ http://goo.gl/wu4acr */
+ ++uxSchedulerSuspended;
+ portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+ static TickType_t prvGetExpectedIdleTime( void )
+ {
+ TickType_t xReturn;
+ UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+ /* uxHigherPriorityReadyTasks takes care of the case where
+ configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+ task that are in the Ready state, even though the idle task is
+ running. */
+ #if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+ {
+ if( uxTopReadyPriority > tskIDLE_PRIORITY )
+ {
+ uxHigherPriorityReadyTasks = pdTRUE;
+ }
+ }
+ #else
+ {
+ const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+ /* When port optimised task selection is used the uxTopReadyPriority
+ variable is used as a bit map. If bits other than the least
+ significant bit are set then there are tasks that have a priority
+ above the idle priority that are in the Ready state. This takes
+ care of the case where the co-operative scheduler is in use. */
+ if( uxTopReadyPriority > uxLeastSignificantBit )
+ {
+ uxHigherPriorityReadyTasks = pdTRUE;
+ }
+ }
+ #endif
+
+ if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+ {
+ xReturn = 0;
+ }
+ else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+ {
+ /* There are other idle priority tasks in the ready state. If
+ time slicing is used then the very next tick interrupt must be
+ processed. */
+ xReturn = 0;
+ }
+ else if( uxHigherPriorityReadyTasks != pdFALSE )
+ {
+ /* There are tasks in the Ready state that have a priority above the
+ idle priority. This path can only be reached if
+ configUSE_PREEMPTION is 0. */
+ xReturn = 0;
+ }
+ else
+ {
+ xReturn = xNextTaskUnblockTime - xTickCount;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+ /* If uxSchedulerSuspended is zero then this function does not match a
+ previous call to vTaskSuspendAll(). */
+ configASSERT( uxSchedulerSuspended );
+
+ /* It is possible that an ISR caused a task to be removed from an event
+ list while the scheduler was suspended. If this was the case then the
+ removed task will have been added to the xPendingReadyList. Once the
+ scheduler has been resumed it is safe to move all the pending ready
+ tasks from this list into their appropriate ready list. */
+ taskENTER_CRITICAL();
+ {
+ --uxSchedulerSuspended;
+
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+ {
+ /* Move any readied tasks from the pending list into the
+ appropriate ready list. */
+ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+ {
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+
+ /* If the moved task has a priority higher than the current
+ task then a yield must be performed. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ if( pxTCB != NULL )
+ {
+ /* A task was unblocked while the scheduler was suspended,
+ which may have prevented the next unblock time from being
+ re-calculated, in which case re-calculate it now. Mainly
+ important for low power tickless implementations, where
+ this can prevent an unnecessary exit from low power
+ state. */
+ prvResetNextTaskUnblockTime();
+ }
+
+ /* If any ticks occurred while the scheduler was suspended then
+ they should be processed now. This ensures the tick count does
+ not slip, and that any delayed tasks are resumed at the correct
+ time. */
+ {
+ UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
+
+ if( uxPendedCounts > ( UBaseType_t ) 0U )
+ {
+ do
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ --uxPendedCounts;
+ } while( uxPendedCounts > ( UBaseType_t ) 0U );
+
+ uxPendedTicks = 0;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ if( xYieldPending != pdFALSE )
+ {
+ #if( configUSE_PREEMPTION != 0 )
+ {
+ xAlreadyYielded = pdTRUE;
+ }
+ #endif
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+ /* Critical section required if running on a 16 bit processor. */
+ portTICK_TYPE_ENTER_CRITICAL();
+ {
+ xTicks = xTickCount;
+ }
+ portTICK_TYPE_EXIT_CRITICAL();
+
+ return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+ {
+ xReturn = xTickCount;
+ }
+ portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+ /* A critical section is not required because the variables are of type
+ BaseType_t. */
+ return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+ /* If null is passed in here then the name of the calling task is being
+ queried. */
+ pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+ configASSERT( pxTCB );
+ return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+ static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+ {
+ TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+ UBaseType_t x;
+ char cNextChar;
+ BaseType_t xBreakLoop;
+
+ /* This function is called with the scheduler suspended. */
+
+ if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+ {
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+ do
+ {
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+ /* Check each character in the name looking for a match or
+ mismatch. */
+ xBreakLoop = pdFALSE;
+ for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ {
+ cNextChar = pxNextTCB->pcTaskName[ x ];
+
+ if( cNextChar != pcNameToQuery[ x ] )
+ {
+ /* Characters didn't match. */
+ xBreakLoop = pdTRUE;
+ }
+ else if( cNextChar == ( char ) 0x00 )
+ {
+ /* Both strings terminated, a match must have been
+ found. */
+ pxReturn = pxNextTCB;
+ xBreakLoop = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xBreakLoop != pdFALSE )
+ {
+ break;
+ }
+ }
+
+ if( pxReturn != NULL )
+ {
+ /* The handle has been found. */
+ break;
+ }
+
+ } while( pxNextTCB != pxFirstTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return pxReturn;
+ }
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ {
+ UBaseType_t uxQueue = configMAX_PRIORITIES;
+ TCB_t* pxTCB;
+
+ /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+ configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+ vTaskSuspendAll();
+ {
+ /* Search the ready lists. */
+ do
+ {
+ uxQueue--;
+ pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+ if( pxTCB != NULL )
+ {
+ /* Found the handle. */
+ break;
+ }
+
+ } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ /* Search the delayed lists. */
+ if( pxTCB == NULL )
+ {
+ pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+ }
+
+ if( pxTCB == NULL )
+ {
+ pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+ }
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ if( pxTCB == NULL )
+ {
+ /* Search the suspended list. */
+ pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+ }
+ }
+ #endif
+
+ #if( INCLUDE_vTaskDelete == 1 )
+ {
+ if( pxTCB == NULL )
+ {
+ /* Search the deleted list. */
+ pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+ }
+ }
+ #endif
+ }
+ ( void ) xTaskResumeAll();
+
+ return pxTCB;
+ }
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+ {
+ UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+ vTaskSuspendAll();
+ {
+ /* Is there a space in the array for each task in the system? */
+ if( uxArraySize >= uxCurrentNumberOfTasks )
+ {
+ /* Fill in an TaskStatus_t structure with information on each
+ task in the Ready state. */
+ do
+ {
+ uxQueue--;
+ uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+ } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ /* Fill in an TaskStatus_t structure with information on each
+ task in the Blocked state. */
+ uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+ uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+ #if( INCLUDE_vTaskDelete == 1 )
+ {
+ /* Fill in an TaskStatus_t structure with information on
+ each task that has been deleted but not yet cleaned up. */
+ uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+ }
+ #endif
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ /* Fill in an TaskStatus_t structure with information on
+ each task in the Suspended state. */
+ uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+ }
+ #endif
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1)
+ {
+ if( pulTotalRunTime != NULL )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+ #else
+ *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+ }
+ }
+ #else
+ {
+ if( pulTotalRunTime != NULL )
+ {
+ *pulTotalRunTime = 0;
+ }
+ }
+ #endif
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ ( void ) xTaskResumeAll();
+
+ return uxTask;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+ TaskHandle_t xTaskGetIdleTaskHandle( void )
+ {
+ /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+ started, then xIdleTaskHandle will be NULL. */
+ configASSERT( ( xIdleTaskHandle != NULL ) );
+ return xIdleTaskHandle;
+ }
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+ void vTaskStepTick( const TickType_t xTicksToJump )
+ {
+ /* Correct the tick count value after a period during which the tick
+ was suppressed. Note this does *not* call the tick hook function for
+ each stepped tick. */
+ configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+ xTickCount += xTicksToJump;
+ traceINCREASE_TICK_COUNT( xTicksToJump );
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+ BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB = xTask;
+ BaseType_t xReturn;
+
+ configASSERT( pxTCB );
+
+ vTaskSuspendAll();
+ {
+ /* A task can only be prematurely removed from the Blocked state if
+ it is actually in the Blocked state. */
+ if( eTaskGetState( xTask ) == eBlocked )
+ {
+ xReturn = pdPASS;
+
+ /* Remove the reference to the task from the blocked list. An
+ interrupt won't touch the xStateListItem because the
+ scheduler is suspended. */
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+ /* Is the task waiting on an event also? If so remove it from
+ the event list too. Interrupts can touch the event list item,
+ even though the scheduler is suspended, so a critical section
+ is used. */
+ taskENTER_CRITICAL();
+ {
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ pxTCB->ucDelayAborted = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* Place the unblocked task into the appropriate ready list. */
+ prvAddTaskToReadyList( pxTCB );
+
+ /* A task being unblocked cannot cause an immediate context
+ switch if preemption is turned off. */
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ /* Preemption is on, but a context switch should only be
+ performed if the unblocked task has a priority that is
+ equal to or higher than the currently executing task. */
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* Pend the yield to be performed when the scheduler
+ is unsuspended. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_PREEMPTION */
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ ( void ) xTaskResumeAll();
+
+ return xReturn;
+ }
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+ /* Called by the portable layer each time a tick interrupt occurs.
+ Increments the tick then checks to see if the new tick value will cause any
+ tasks to be unblocked. */
+ traceTASK_INCREMENT_TICK( xTickCount );
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ /* Minor optimisation. The tick count cannot change in this
+ block. */
+ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+ /* Increment the RTOS tick, switching the delayed and overflowed
+ delayed lists if it wraps to 0. */
+ xTickCount = xConstTickCount;
+
+ if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+ {
+ taskSWITCH_DELAYED_LISTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* See if this tick has made a timeout expire. Tasks are stored in
+ the queue in the order of their wake time - meaning once one task
+ has been found whose block time has not expired there is no need to
+ look any further down the list. */
+ if( xConstTickCount >= xNextTaskUnblockTime )
+ {
+ for( ;; )
+ {
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ {
+ /* The delayed list is empty. Set xNextTaskUnblockTime
+ to the maximum possible value so it is extremely
+ unlikely that the
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass
+ next time through. */
+ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ break;
+ }
+ else
+ {
+ /* The delayed list is not empty, get the value of the
+ item at the head of the delayed list. This is the time
+ at which the task at the head of the delayed list must
+ be removed from the Blocked state. */
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+ if( xConstTickCount < xItemValue )
+ {
+ /* It is not time to unblock this item yet, but the
+ item value is the time at which the task at the head
+ of the blocked list must be removed from the Blocked
+ state - so record the item value in
+ xNextTaskUnblockTime. */
+ xNextTaskUnblockTime = xItemValue;
+ break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* It is time to remove the item from the Blocked state. */
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+ /* Is the task waiting on an event also? If so remove
+ it from the event list. */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Place the unblocked task into the appropriate ready
+ list. */
+ prvAddTaskToReadyList( pxTCB );
+
+ /* A task being unblocked cannot cause an immediate
+ context switch if preemption is turned off. */
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ /* Preemption is on, but a context switch should
+ only be performed if the unblocked task has a
+ priority that is equal to or higher than the
+ currently executing task. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_PREEMPTION */
+ }
+ }
+ }
+
+ /* Tasks of equal priority to the currently running task will share
+ processing time (time slice) if preemption is on, and the application
+ writer has not explicitly turned time slicing off. */
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+ {
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+ #if ( configUSE_TICK_HOOK == 1 )
+ {
+ /* Guard against the tick hook being called when the pended tick
+ count is being unwound (when the scheduler is being unlocked). */
+ if( uxPendedTicks == ( UBaseType_t ) 0U )
+ {
+ vApplicationTickHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_TICK_HOOK */
+ }
+ else
+ {
+ ++uxPendedTicks;
+
+ /* The tick hook gets called at regular intervals, even if the
+ scheduler is locked. */
+ #if ( configUSE_TICK_HOOK == 1 )
+ {
+ vApplicationTickHook();
+ }
+ #endif
+ }
+
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ if( xYieldPending != pdFALSE )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_PREEMPTION */
+
+ return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+ {
+ TCB_t *xTCB;
+
+ /* If xTask is NULL then it is the task hook of the calling task that is
+ getting set. */
+ if( xTask == NULL )
+ {
+ xTCB = ( TCB_t * ) pxCurrentTCB;
+ }
+ else
+ {
+ xTCB = xTask;
+ }
+
+ /* Save the hook function in the TCB. A critical section is required as
+ the value can be accessed from an interrupt. */
+ taskENTER_CRITICAL();
+ {
+ xTCB->pxTaskTag = pxHookFunction;
+ }
+ taskEXIT_CRITICAL();
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ TaskHookFunction_t xReturn;
+
+ /* If xTask is NULL then set the calling task's hook. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ /* Save the hook function in the TCB. A critical section is required as
+ the value can be accessed from an interrupt. */
+ taskENTER_CRITICAL();
+ {
+ xReturn = pxTCB->pxTaskTag;
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ TaskHookFunction_t xReturn;
+ UBaseType_t uxSavedInterruptStatus;
+
+ /* If xTask is NULL then set the calling task's hook. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ /* Save the hook function in the TCB. A critical section is required as
+ the value can be accessed from an interrupt. */
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ xReturn = pxTCB->pxTaskTag;
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+ {
+ TCB_t *xTCB;
+ BaseType_t xReturn;
+
+ /* If xTask is NULL then we are calling our own task hook. */
+ if( xTask == NULL )
+ {
+ xTCB = pxCurrentTCB;
+ }
+ else
+ {
+ xTCB = xTask;
+ }
+
+ if( xTCB->pxTaskTag != NULL )
+ {
+ xReturn = xTCB->pxTaskTag( pvParameter );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+ if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+ {
+ /* The scheduler is currently suspended - do not allow a context
+ switch. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ xYieldPending = pdFALSE;
+ traceTASK_SWITCHED_OUT();
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+ #else
+ ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ /* Add the amount of time the task has been running to the
+ accumulated time so far. The time the task started running was
+ stored in ulTaskSwitchedInTime. Note that there is no overflow
+ protection here so count values are only valid until the timer
+ overflows. The guard against negative values is to protect
+ against suspect run time stat counter implementations - which
+ are provided by the application, not the kernel. */
+ if( ulTotalRunTime > ulTaskSwitchedInTime )
+ {
+ pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ ulTaskSwitchedInTime = ulTotalRunTime;
+ }
+ #endif /* configGENERATE_RUN_TIME_STATS */
+
+ /* Check for stack overflow, if configured. */
+ taskCHECK_FOR_STACK_OVERFLOW();
+
+ /* Before the currently running task is switched out, save its errno. */
+ #if( configUSE_POSIX_ERRNO == 1 )
+ {
+ pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+ }
+ #endif
+
+ /* Select a new task to run using either the generic C or port
+ optimised asm code. */
+ taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ traceTASK_SWITCHED_IN();
+
+ /* After the new task is switched in, update the global errno. */
+ #if( configUSE_POSIX_ERRNO == 1 )
+ {
+ FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+ }
+ #endif
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ /* Switch Newlib's _impure_ptr variable to point to the _reent
+ structure specific to this task. */
+ _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+ }
+ #endif /* configUSE_NEWLIB_REENTRANT */
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+ configASSERT( pxEventList );
+
+ /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+ SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+ /* Place the event list item of the TCB in the appropriate event list.
+ This is placed in the list in priority order so the highest priority task
+ is the first to be woken by the event. The queue that contains the event
+ list is locked, preventing simultaneous access from interrupts. */
+ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+ prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+ configASSERT( pxEventList );
+
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
+ the event groups implementation. */
+ configASSERT( uxSchedulerSuspended != 0 );
+
+ /* Store the item value in the event list item. It is safe to access the
+ event list item here as interrupts won't access the event list item of a
+ task that is not in the Blocked state. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+ /* Place the event list item of the TCB at the end of the appropriate event
+ list. It is safe to access the event list here because it is part of an
+ event group implementation - and interrupts don't access event groups
+ directly (instead they access them indirectly by pending function calls to
+ the task level). */
+ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+ prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+ void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+ {
+ configASSERT( pxEventList );
+
+ /* This function should not be called by application code hence the
+ 'Restricted' in its name. It is not part of the public API. It is
+ designed for use by kernel code, and has special calling requirements -
+ it should be called with the scheduler suspended. */
+
+
+ /* Place the event list item of the TCB in the appropriate event list.
+ In this case it is assume that this is the only task that is going to
+ be waiting on this event list, so the faster vListInsertEnd() function
+ can be used in place of vListInsert. */
+ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+ /* If the task should block indefinitely then set the block time to a
+ value that will be recognised as an indefinite delay inside the
+ prvAddCurrentTaskToDelayedList() function. */
+ if( xWaitIndefinitely != pdFALSE )
+ {
+ xTicksToWait = portMAX_DELAY;
+ }
+
+ traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+ prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+ }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+ /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be
+ called from a critical section within an ISR. */
+
+ /* The event list is sorted in priority order, so the first in the list can
+ be removed as it is known to be the highest priority. Remove the TCB from
+ the delayed list, and add it to the ready list.
+
+ If an event is for a queue that is locked then this function will never
+ get called - the lock count on the queue will get modified instead. This
+ means exclusive access to the event list is guaranteed here.
+
+ This function assumes that a check has already been made to ensure that
+ pxEventList is not empty. */
+ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ configASSERT( pxUnblockedTCB );
+ ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxUnblockedTCB );
+
+ #if( configUSE_TICKLESS_IDLE != 0 )
+ {
+ /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+ might be set to the blocked task's time out time. If the task is
+ unblocked for a reason other than a timeout xNextTaskUnblockTime is
+ normally left unchanged, because it is automatically reset to a new
+ value when the tick count equals xNextTaskUnblockTime. However if
+ tickless idling is used it might be more important to enter sleep mode
+ at the earliest possible time - so reset xNextTaskUnblockTime here to
+ ensure it is updated at the earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
+ #endif
+ }
+ else
+ {
+ /* The delayed and ready lists cannot be accessed, so hold this task
+ pending until the scheduler is resumed. */
+ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+ }
+
+ if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* Return true if the task removed from the event list has a higher
+ priority than the calling task. This allows the calling task to know if
+ it should force a context switch now. */
+ xReturn = pdTRUE;
+
+ /* Mark that a yield is pending in case the user is not using the
+ "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
+ the event flags implementation. */
+ configASSERT( uxSchedulerSuspended != pdFALSE );
+
+ /* Store the new item value in the event list. */
+ listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+ /* Remove the event list form the event flag. Interrupts do not access
+ event flags. */
+ pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ configASSERT( pxUnblockedTCB );
+ ( void ) uxListRemove( pxEventListItem );
+
+ /* Remove the task from the delayed list and add it to the ready list. The
+ scheduler is suspended so interrupts will not be accessing the ready
+ lists. */
+ ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxUnblockedTCB );
+
+ if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* The unblocked task has a priority above that of the calling task, so
+ a context switch is required. This function is called with the
+ scheduler suspended so xYieldPending is set so the context switch
+ occurs immediately that the scheduler is resumed (unsuspended). */
+ xYieldPending = pdTRUE;
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+ configASSERT( pxTimeOut );
+ taskENTER_CRITICAL();
+ {
+ pxTimeOut->xOverflowCount = xNumOfOverflows;
+ pxTimeOut->xTimeOnEntering = xTickCount;
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+ /* For internal use only as it does not use a critical section. */
+ pxTimeOut->xOverflowCount = xNumOfOverflows;
+ pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+ configASSERT( pxTimeOut );
+ configASSERT( pxTicksToWait );
+
+ taskENTER_CRITICAL();
+ {
+ /* Minor optimisation. The tick count cannot change in this block. */
+ const TickType_t xConstTickCount = xTickCount;
+ const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+ #if( INCLUDE_xTaskAbortDelay == 1 )
+ if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+ {
+ /* The delay was aborted, which is not the same as a time out,
+ but has the same result. */
+ pxCurrentTCB->ucDelayAborted = pdFALSE;
+ xReturn = pdTRUE;
+ }
+ else
+ #endif
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ if( *pxTicksToWait == portMAX_DELAY )
+ {
+ /* If INCLUDE_vTaskSuspend is set to 1 and the block time
+ specified is the maximum block time then the task should block
+ indefinitely, and therefore never time out. */
+ xReturn = pdFALSE;
+ }
+ else
+ #endif
+
+ if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+ {
+ /* The tick count is greater than the time at which
+ vTaskSetTimeout() was called, but has also overflowed since
+ vTaskSetTimeOut() was called. It must have wrapped all the way
+ around and gone past again. This passed since vTaskSetTimeout()
+ was called. */
+ xReturn = pdTRUE;
+ }
+ else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+ {
+ /* Not a genuine timeout. Adjust parameters for time remaining. */
+ *pxTicksToWait -= xElapsedTime;
+ vTaskInternalSetTimeOutState( pxTimeOut );
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ *pxTicksToWait = 0;
+ xReturn = pdTRUE;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+ xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+ {
+ UBaseType_t uxReturn;
+ TCB_t const *pxTCB;
+
+ if( xTask != NULL )
+ {
+ pxTCB = xTask;
+ uxReturn = pxTCB->uxTaskNumber;
+ }
+ else
+ {
+ uxReturn = 0U;
+ }
+
+ return uxReturn;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+ {
+ TCB_t * pxTCB;
+
+ if( xTask != NULL )
+ {
+ pxTCB = xTask;
+ pxTCB->uxTaskNumber = uxHandle;
+ }
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions. The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+ /* Stop warnings. */
+ ( void ) pvParameters;
+
+ /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+ SCHEDULER IS STARTED. **/
+
+ /* In case a task that has a secure context deletes itself, in which case
+ the idle task is responsible for deleting the task's secure context, if
+ any. */
+ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+ for( ;; )
+ {
+ /* See if any tasks have deleted themselves - if so then the idle task
+ is responsible for freeing the deleted task's TCB and stack. */
+ prvCheckTasksWaitingTermination();
+
+ #if ( configUSE_PREEMPTION == 0 )
+ {
+ /* If we are not using preemption we keep forcing a task switch to
+ see if any other task has become available. If we are using
+ preemption we don't need to do this as any task becoming available
+ will automatically get the processor anyway. */
+ taskYIELD();
+ }
+ #endif /* configUSE_PREEMPTION */
+
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+ {
+ /* When using preemption tasks of equal priority will be
+ timesliced. If a task that is sharing the idle priority is ready
+ to run then the idle task should yield before the end of the
+ timeslice.
+
+ A critical region is not required here as we are just reading from
+ the list, and an occasional incorrect value will not matter. If
+ the ready list at the idle priority contains more than one task
+ then a task other than the idle task is ready to execute. */
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+ {
+ taskYIELD();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+ #if ( configUSE_IDLE_HOOK == 1 )
+ {
+ extern void vApplicationIdleHook( void );
+
+ /* Call the user defined function from within the idle task. This
+ allows the application designer to add background functionality
+ without the overhead of a separate task.
+ NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+ CALL A FUNCTION THAT MIGHT BLOCK. */
+ vApplicationIdleHook();
+ }
+ #endif /* configUSE_IDLE_HOOK */
+
+ /* This conditional compilation should use inequality to 0, not equality
+ to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+ user defined low power mode implementations require
+ configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+ #if ( configUSE_TICKLESS_IDLE != 0 )
+ {
+ TickType_t xExpectedIdleTime;
+
+ /* It is not desirable to suspend then resume the scheduler on
+ each iteration of the idle task. Therefore, a preliminary
+ test of the expected idle time is performed without the
+ scheduler suspended. The result here is not necessarily
+ valid. */
+ xExpectedIdleTime = prvGetExpectedIdleTime();
+
+ if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ {
+ vTaskSuspendAll();
+ {
+ /* Now the scheduler is suspended, the expected idle
+ time can be sampled again, and this time its value can
+ be used. */
+ configASSERT( xNextTaskUnblockTime >= xTickCount );
+ xExpectedIdleTime = prvGetExpectedIdleTime();
+
+ /* Define the following macro to set xExpectedIdleTime to 0
+ if the application does not want
+ portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+ configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ {
+ traceLOW_POWER_IDLE_BEGIN();
+ portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+ traceLOW_POWER_IDLE_END();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ ( void ) xTaskResumeAll();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+ eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+ {
+ /* The idle task exists in addition to the application tasks. */
+ const UBaseType_t uxNonApplicationTasks = 1;
+ eSleepModeStatus eReturn = eStandardSleep;
+
+ if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+ {
+ /* A task was made ready while the scheduler was suspended. */
+ eReturn = eAbortSleep;
+ }
+ else if( xYieldPending != pdFALSE )
+ {
+ /* A yield was pended while the scheduler was suspended. */
+ eReturn = eAbortSleep;
+ }
+ else
+ {
+ /* If all the tasks are in the suspended list (which might mean they
+ have an infinite block time rather than actually being suspended)
+ then it is safe to turn all clocks off and just wait for external
+ interrupts. */
+ if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+ {
+ eReturn = eNoTasksWaitingTimeout;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ return eReturn;
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+ {
+ TCB_t *pxTCB;
+
+ if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+ {
+ pxTCB = prvGetTCBFromHandle( xTaskToSet );
+ pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+ }
+ }
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+ void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+ {
+ void *pvReturn = NULL;
+ TCB_t *pxTCB;
+
+ if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+ {
+ pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+ pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+ }
+ else
+ {
+ pvReturn = NULL;
+ }
+
+ return pvReturn;
+ }
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+ void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+ {
+ TCB_t *pxTCB;
+
+ /* If null is passed in here then we are modifying the MPU settings of
+ the calling task. */
+ pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+ }
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+ for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+ {
+ vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+ }
+
+ vListInitialise( &xDelayedTaskList1 );
+ vListInitialise( &xDelayedTaskList2 );
+ vListInitialise( &xPendingReadyList );
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ {
+ vListInitialise( &xTasksWaitingTermination );
+ }
+ #endif /* INCLUDE_vTaskDelete */
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ vListInitialise( &xSuspendedTaskList );
+ }
+ #endif /* INCLUDE_vTaskSuspend */
+
+ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+ using list2. */
+ pxDelayedTaskList = &xDelayedTaskList1;
+ pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+ /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ {
+ TCB_t *pxTCB;
+
+ /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+ being called too often in the idle task. */
+ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+ {
+ taskENTER_CRITICAL();
+ {
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ --uxCurrentNumberOfTasks;
+ --uxDeletedTasksWaitingCleanUp;
+ }
+ taskEXIT_CRITICAL();
+
+ prvDeleteTCB( pxTCB );
+ }
+ }
+ #endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+ void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+ {
+ TCB_t *pxTCB;
+
+ /* xTask is NULL then get the state of the calling task. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+ pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+ pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+ pxTaskStatus->pxStackBase = pxTCB->pxStack;
+ pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+ }
+ #else
+ {
+ pxTaskStatus->uxBasePriority = 0;
+ }
+ #endif
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+ }
+ #else
+ {
+ pxTaskStatus->ulRunTimeCounter = 0;
+ }
+ #endif
+
+ /* Obtaining the task state is a little fiddly, so is only done if the
+ value of eState passed into this function is eInvalid - otherwise the
+ state is just set to whatever is passed in. */
+ if( eState != eInvalid )
+ {
+ if( pxTCB == pxCurrentTCB )
+ {
+ pxTaskStatus->eCurrentState = eRunning;
+ }
+ else
+ {
+ pxTaskStatus->eCurrentState = eState;
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ /* If the task is in the suspended list then there is a
+ chance it is actually just blocked indefinitely - so really
+ it should be reported as being in the Blocked state. */
+ if( eState == eSuspended )
+ {
+ vTaskSuspendAll();
+ {
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ pxTaskStatus->eCurrentState = eBlocked;
+ }
+ }
+ ( void ) xTaskResumeAll();
+ }
+ }
+ #endif /* INCLUDE_vTaskSuspend */
+ }
+ }
+ else
+ {
+ pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+ }
+
+ /* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+ parameter is provided to allow it to be skipped. */
+ if( xGetFreeStackSpace != pdFALSE )
+ {
+ #if ( portSTACK_GROWTH > 0 )
+ {
+ pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+ }
+ #else
+ {
+ pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+ }
+ #endif
+ }
+ else
+ {
+ pxTaskStatus->usStackHighWaterMark = 0;
+ }
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+ {
+ configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+ UBaseType_t uxTask = 0;
+
+ if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+ {
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+ /* Populate an TaskStatus_t structure within the
+ pxTaskStatusArray array for each task that is referenced from
+ pxList. See the definition of TaskStatus_t in task.h for the
+ meaning of each TaskStatus_t structure member. */
+ do
+ {
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+ uxTask++;
+ } while( pxNextTCB != pxFirstTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return uxTask;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+ static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+ {
+ uint32_t ulCount = 0U;
+
+ while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+ {
+ pucStackByte -= portSTACK_GROWTH;
+ ulCount++;
+ }
+
+ ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+ return ( configSTACK_DEPTH_TYPE ) ulCount;
+ }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+ /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ same except for their return type. Using configSTACK_DEPTH_TYPE allows the
+ user to determine the return type. It gets around the problem of the value
+ overflowing on 8-bit types without breaking backward compatibility for
+ applications that expect an 8-bit return type. */
+ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ uint8_t *pucEndOfStack;
+ configSTACK_DEPTH_TYPE uxReturn;
+
+ /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+ the same except for their return type. Using configSTACK_DEPTH_TYPE
+ allows the user to determine the return type. It gets around the
+ problem of the value overflowing on 8-bit types without breaking
+ backward compatibility for applications that expect an 8-bit return
+ type. */
+
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ #if portSTACK_GROWTH < 0
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+ }
+ #else
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+ }
+ #endif
+
+ uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+ return uxReturn;
+ }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ uint8_t *pucEndOfStack;
+ UBaseType_t uxReturn;
+
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ #if portSTACK_GROWTH < 0
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+ }
+ #else
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+ }
+ #endif
+
+ uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+ return uxReturn;
+ }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+ static void prvDeleteTCB( TCB_t *pxTCB )
+ {
+ /* This call is required specifically for the TriCore port. It must be
+ above the vPortFree() calls. The call is also used by ports/demos that
+ want to allocate and clean RAM statically. */
+ portCLEAN_UP_TCB( pxTCB );
+
+ /* Free up the memory allocated by the scheduler for the task. It is up
+ to the task to free any memory allocated at the application level. */
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ _reclaim_reent( &( pxTCB->xNewLib_reent ) );
+ }
+ #endif /* configUSE_NEWLIB_REENTRANT */
+
+ #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+ {
+ /* The task can only have been allocated dynamically - free both
+ the stack and TCB. */
+ vPortFree( pxTCB->pxStack );
+ vPortFree( pxTCB );
+ }
+ #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+ {
+ /* The task could have been allocated statically or dynamically, so
+ check what was statically allocated before trying to free the
+ memory. */
+ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+ {
+ /* Both the stack and TCB were allocated dynamically, so both
+ must be freed. */
+ vPortFree( pxTCB->pxStack );
+ vPortFree( pxTCB );
+ }
+ else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+ {
+ /* Only the stack was statically allocated, so the TCB is the
+ only memory that must be freed. */
+ vPortFree( pxTCB );
+ }
+ else
+ {
+ /* Neither the stack nor the TCB were allocated dynamically, so
+ nothing needs to be freed. */
+ configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ {
+ /* The new current delayed list is empty. Set xNextTaskUnblockTime to
+ the maximum possible value so it is extremely unlikely that the
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+ there is an item in the delayed list. */
+ xNextTaskUnblockTime = portMAX_DELAY;
+ }
+ else
+ {
+ /* The new current delayed list is not empty, get the value of
+ the item at the head of the delayed list. This is the time at
+ which the task at the head of the delayed list should be removed
+ from the Blocked state. */
+ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+ TaskHandle_t xTaskGetCurrentTaskHandle( void )
+ {
+ TaskHandle_t xReturn;
+
+ /* A critical section is not required as this is not called from
+ an interrupt and the current TCB will always be the same for any
+ individual execution thread. */
+ xReturn = pxCurrentTCB;
+
+ return xReturn;
+ }
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+ BaseType_t xTaskGetSchedulerState( void )
+ {
+ BaseType_t xReturn;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ xReturn = taskSCHEDULER_NOT_STARTED;
+ }
+ else
+ {
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ xReturn = taskSCHEDULER_RUNNING;
+ }
+ else
+ {
+ xReturn = taskSCHEDULER_SUSPENDED;
+ }
+ }
+
+ return xReturn;
+ }
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+ {
+ TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+ BaseType_t xReturn = pdFALSE;
+
+ /* If the mutex was given back by an interrupt while the queue was
+ locked then the mutex holder might now be NULL. _RB_ Is this still
+ needed as interrupts can no longer use mutexes? */
+ if( pxMutexHolder != NULL )
+ {
+ /* If the holder of the mutex has a priority below the priority of
+ the task attempting to obtain the mutex then it will temporarily
+ inherit the priority of the task attempting to obtain the mutex. */
+ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+ {
+ /* Adjust the mutex holder state to account for its new
+ priority. Only reset the event list item value if the value is
+ not being used for anything else. */
+ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ {
+ listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* If the task being modified is in the ready state it will need
+ to be moved into a new list. */
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+ {
+ if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Inherit the priority before being moved into the new list. */
+ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+ prvAddTaskToReadyList( pxMutexHolderTCB );
+ }
+ else
+ {
+ /* Just inherit the priority. */
+ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+ }
+
+ traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+ /* Inheritance occurred. */
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+ {
+ /* The base priority of the mutex holder is lower than the
+ priority of the task attempting to take the mutex, but the
+ current priority of the mutex holder is not lower than the
+ priority of the task attempting to take the mutex.
+ Therefore the mutex holder must have already inherited a
+ priority, but inheritance would have occurred if that had
+ not been the case. */
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+ {
+ TCB_t * const pxTCB = pxMutexHolder;
+ BaseType_t xReturn = pdFALSE;
+
+ if( pxMutexHolder != NULL )
+ {
+ /* A task can only have an inherited priority if it holds the mutex.
+ If the mutex is held by a task then it cannot be given from an
+ interrupt, and if a mutex is given by the holding task then it must
+ be the running state task. */
+ configASSERT( pxTCB == pxCurrentTCB );
+ configASSERT( pxTCB->uxMutexesHeld );
+ ( pxTCB->uxMutexesHeld )--;
+
+ /* Has the holder of the mutex inherited the priority of another
+ task? */
+ if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+ {
+ /* Only disinherit if no other mutexes are held. */
+ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+ {
+ /* A task can only have an inherited priority if it holds
+ the mutex. If the mutex is held by a task then it cannot be
+ given from an interrupt, and if a mutex is given by the
+ holding task then it must be the running state task. Remove
+ the holding task from the ready list. */
+ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Disinherit the priority before adding the task into the
+ new ready list. */
+ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+ pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+ /* Reset the event list item value. It cannot be in use for
+ any other purpose if this task is running, and it must be
+ running to give back the mutex. */
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ prvAddTaskToReadyList( pxTCB );
+
+ /* Return true to indicate that a context switch is required.
+ This is only actually required in the corner case whereby
+ multiple mutexes were held and the mutexes were given back
+ in an order different to that in which they were taken.
+ If a context switch did not occur when the first mutex was
+ returned, even if a task was waiting on it, then a context
+ switch should occur when the last mutex is returned whether
+ a task is waiting on it or not. */
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+ {
+ TCB_t * const pxTCB = pxMutexHolder;
+ UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+ const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+ if( pxMutexHolder != NULL )
+ {
+ /* If pxMutexHolder is not NULL then the holder must hold at least
+ one mutex. */
+ configASSERT( pxTCB->uxMutexesHeld );
+
+ /* Determine the priority to which the priority of the task that
+ holds the mutex should be set. This will be the greater of the
+ holding task's base priority and the priority of the highest
+ priority task that is waiting to obtain the mutex. */
+ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+ {
+ uxPriorityToUse = uxHighestPriorityWaitingTask;
+ }
+ else
+ {
+ uxPriorityToUse = pxTCB->uxBasePriority;
+ }
+
+ /* Does the priority need to change? */
+ if( pxTCB->uxPriority != uxPriorityToUse )
+ {
+ /* Only disinherit if no other mutexes are held. This is a
+ simplification in the priority inheritance implementation. If
+ the task that holds the mutex is also holding other mutexes then
+ the other mutexes may have caused the priority inheritance. */
+ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+ {
+ /* If a task has timed out because it already holds the
+ mutex it was trying to obtain then it cannot of inherited
+ its own priority. */
+ configASSERT( pxTCB != pxCurrentTCB );
+
+ /* Disinherit the priority, remembering the previous
+ priority to facilitate determining the subject task's
+ state. */
+ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+ uxPriorityUsedOnEntry = pxTCB->uxPriority;
+ pxTCB->uxPriority = uxPriorityToUse;
+
+ /* Only reset the event list item value if the value is not
+ being used for anything else. */
+ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ {
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* If the running task is not the task that holds the mutex
+ then the task that holds the mutex could be in either the
+ Ready, Blocked or Suspended states. Only remove the task
+ from its current state list if it is in the Ready state as
+ the task's priority is going to change and there is one
+ Ready list per priority. */
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+ {
+ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+ void vTaskEnterCritical( void )
+ {
+ portDISABLE_INTERRUPTS();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ ( pxCurrentTCB->uxCriticalNesting )++;
+
+ /* This is not the interrupt safe version of the enter critical
+ function so assert() if it is being called from an interrupt
+ context. Only API functions that end in "FromISR" can be used in an
+ interrupt. Only assert if the critical nesting count is 1 to
+ protect against recursive calls if the assert function also uses a
+ critical section. */
+ if( pxCurrentTCB->uxCriticalNesting == 1 )
+ {
+ portASSERT_IF_IN_ISR();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+ void vTaskExitCritical( void )
+ {
+ if( xSchedulerRunning != pdFALSE )
+ {
+ if( pxCurrentTCB->uxCriticalNesting > 0U )
+ {
+ ( pxCurrentTCB->uxCriticalNesting )--;
+
+ if( pxCurrentTCB->uxCriticalNesting == 0U )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+ static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+ {
+ size_t x;
+
+ /* Start by copying the entire string. */
+ strcpy( pcBuffer, pcTaskName );
+
+ /* Pad the end of the string with spaces to ensure columns line up when
+ printed out. */
+ for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+ {
+ pcBuffer[ x ] = ' ';
+ }
+
+ /* Terminate. */
+ pcBuffer[ x ] = ( char ) 0x00;
+
+ /* Return the new end of string. */
+ return &( pcBuffer[ x ] );
+ }
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+ void vTaskList( char * pcWriteBuffer )
+ {
+ TaskStatus_t *pxTaskStatusArray;
+ UBaseType_t uxArraySize, x;
+ char cStatus;
+
+ /*
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many
+ * of the demo applications. Do not consider it to be part of the
+ * scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that
+ * displays task names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that
+ * might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms. An alternative, tiny, third party,
+ * and limited functionality implementation of sprintf() is provided in
+ * many of the FreeRTOS/Demo sub-directories in a file called
+ * printf-stdarg.c (note printf-stdarg.c does not provide a full
+ * snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly
+ * through a call to vTaskList().
+ */
+
+
+ /* Make sure the write buffer does not contain a string. */
+ *pcWriteBuffer = ( char ) 0x00;
+
+ /* Take a snapshot of the number of tasks in case it changes while this
+ function is executing. */
+ uxArraySize = uxCurrentNumberOfTasks;
+
+ /* Allocate an array index for each task. NOTE! if
+ configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+ equate to NULL. */
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+ if( pxTaskStatusArray != NULL )
+ {
+ /* Generate the (binary) data. */
+ uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+ /* Create a human readable table from the binary data. */
+ for( x = 0; x < uxArraySize; x++ )
+ {
+ switch( pxTaskStatusArray[ x ].eCurrentState )
+ {
+ case eRunning: cStatus = tskRUNNING_CHAR;
+ break;
+
+ case eReady: cStatus = tskREADY_CHAR;
+ break;
+
+ case eBlocked: cStatus = tskBLOCKED_CHAR;
+ break;
+
+ case eSuspended: cStatus = tskSUSPENDED_CHAR;
+ break;
+
+ case eDeleted: cStatus = tskDELETED_CHAR;
+ break;
+
+ case eInvalid: /* Fall through. */
+ default: /* Should not get here, but it is included
+ to prevent static checking errors. */
+ cStatus = ( char ) 0x00;
+ break;
+ }
+
+ /* Write the task name to the string, padding with spaces so it
+ can be printed in tabular form more easily. */
+ pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+ /* Write the rest of the string. */
+ sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+ pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+ }
+
+ /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION
+ is 0 then vPortFree() will be #defined to nothing. */
+ vPortFree( pxTaskStatusArray );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+ void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ {
+ TaskStatus_t *pxTaskStatusArray;
+ UBaseType_t uxArraySize, x;
+ uint32_t ulTotalTime, ulStatsAsPercentage;
+
+ #if( configUSE_TRACE_FACILITY != 1 )
+ {
+ #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+ }
+ #endif
+
+ /*
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many
+ * of the demo applications. Do not consider it to be part of the
+ * scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+ * of the uxTaskGetSystemState() output into a human readable table that
+ * displays the amount of time each task has spent in the Running state
+ * in both absolute and percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+ * function that might bloat the code size, use a lot of stack, and
+ * provide different results on different platforms. An alternative,
+ * tiny, third party, and limited functionality implementation of
+ * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+ * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+ * a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly
+ * through a call to vTaskGetRunTimeStats().
+ */
+
+ /* Make sure the write buffer does not contain a string. */
+ *pcWriteBuffer = ( char ) 0x00;
+
+ /* Take a snapshot of the number of tasks in case it changes while this
+ function is executing. */
+ uxArraySize = uxCurrentNumberOfTasks;
+
+ /* Allocate an array index for each task. NOTE! If
+ configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+ equate to NULL. */
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+ if( pxTaskStatusArray != NULL )
+ {
+ /* Generate the (binary) data. */
+ uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+ /* For percentage calculations. */
+ ulTotalTime /= 100UL;
+
+ /* Avoid divide by zero errors. */
+ if( ulTotalTime > 0UL )
+ {
+ /* Create a human readable table from the binary data. */
+ for( x = 0; x < uxArraySize; x++ )
+ {
+ /* What percentage of the total run time has the task used?
+ This will always be rounded down to the nearest integer.
+ ulTotalRunTimeDiv100 has already been divided by 100. */
+ ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+ /* Write the task name to the string, padding with
+ spaces so it can be printed in tabular form more
+ easily. */
+ pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+ if( ulStatsAsPercentage > 0UL )
+ {
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+ {
+ sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ }
+ #else
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ printf() library can be used. */
+ sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+ }
+ #endif
+ }
+ else
+ {
+ /* If the percentage is zero here then the task has
+ consumed less than 1% of the total run time. */
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+ {
+ sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
+ #else
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ printf() library can be used. */
+ sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+ }
+ #endif
+ }
+
+ pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION
+ is 0 then vPortFree() will be #defined to nothing. */
+ vPortFree( pxTaskStatusArray );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+ uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+ /* Reset the event list item to its normal value - so it can be used with
+ queues and semaphores. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+ {
+ /* If xSemaphoreCreateMutex() is called before any tasks have been created
+ then pxCurrentTCB will be NULL. */
+ if( pxCurrentTCB != NULL )
+ {
+ ( pxCurrentTCB->uxMutexesHeld )++;
+ }
+
+ return pxCurrentTCB;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+ {
+ uint32_t ulReturn;
+
+ taskENTER_CRITICAL();
+ {
+ /* Only block if the notification count is not already non-zero. */
+ if( pxCurrentTCB->ulNotifiedValue == 0UL )
+ {
+ /* Mark this task as waiting for a notification. */
+ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+ if( xTicksToWait > ( TickType_t ) 0 )
+ {
+ prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+ traceTASK_NOTIFY_TAKE_BLOCK();
+
+ /* All ports are written to allow a yield in a critical
+ section (some will yield immediately, others wait until the
+ critical section exits) - but it is not something that
+ application code should ever do. */
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ taskENTER_CRITICAL();
+ {
+ traceTASK_NOTIFY_TAKE();
+ ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+ if( ulReturn != 0UL )
+ {
+ if( xClearCountOnExit != pdFALSE )
+ {
+ pxCurrentTCB->ulNotifiedValue = 0UL;
+ }
+ else
+ {
+ pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+ }
+ taskEXIT_CRITICAL();
+
+ return ulReturn;
+ }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn;
+
+ taskENTER_CRITICAL();
+ {
+ /* Only block if a notification is not already pending. */
+ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+ {
+ /* Clear bits in the task's notification value as bits may get
+ set by the notifying task or interrupt. This can be used to
+ clear the value to zero. */
+ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+ /* Mark this task as waiting for a notification. */
+ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+ if( xTicksToWait > ( TickType_t ) 0 )
+ {
+ prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+ traceTASK_NOTIFY_WAIT_BLOCK();
+
+ /* All ports are written to allow a yield in a critical
+ section (some will yield immediately, others wait until the
+ critical section exits) - but it is not something that
+ application code should ever do. */
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ taskENTER_CRITICAL();
+ {
+ traceTASK_NOTIFY_WAIT();
+
+ if( pulNotificationValue != NULL )
+ {
+ /* Output the current notification value, which may or may not
+ have changed. */
+ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+ }
+
+ /* If ucNotifyValue is set then either the task never entered the
+ blocked state (because a notification was already pending) or the
+ task unblocked because of a notification. Otherwise the task
+ unblocked because of a timeout. */
+ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+ {
+ /* A notification was not received. */
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ /* A notification was already pending or a notification was
+ received while the task was waiting. */
+ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+ xReturn = pdTRUE;
+ }
+
+ pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+ {
+ TCB_t * pxTCB;
+ BaseType_t xReturn = pdPASS;
+ uint8_t ucOriginalNotifyState;
+
+ configASSERT( xTaskToNotify );
+ pxTCB = xTaskToNotify;
+
+ taskENTER_CRITICAL();
+ {
+ if( pulPreviousNotificationValue != NULL )
+ {
+ *pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+ }
+
+ ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+ pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+ switch( eAction )
+ {
+ case eSetBits :
+ pxTCB->ulNotifiedValue |= ulValue;
+ break;
+
+ case eIncrement :
+ ( pxTCB->ulNotifiedValue )++;
+ break;
+
+ case eSetValueWithOverwrite :
+ pxTCB->ulNotifiedValue = ulValue;
+ break;
+
+ case eSetValueWithoutOverwrite :
+ if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+ {
+ pxTCB->ulNotifiedValue = ulValue;
+ }
+ else
+ {
+ /* The value could not be written to the task. */
+ xReturn = pdFAIL;
+ }
+ break;
+
+ case eNoAction:
+ /* The task is being notified without its notify value being
+ updated. */
+ break;
+
+ default:
+ /* Should not get here if all enums are handled.
+ Artificially force an assert by testing a value the
+ compiler can't assume is const. */
+ configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+ break;
+ }
+
+ traceTASK_NOTIFY();
+
+ /* If the task is in the blocked state specifically to wait for a
+ notification then unblock it now. */
+ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+ {
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+
+ /* The task should not have been on an event list. */
+ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+ #if( configUSE_TICKLESS_IDLE != 0 )
+ {
+ /* If a task is blocked waiting for a notification then
+ xNextTaskUnblockTime might be set to the blocked task's time
+ out time. If the task is unblocked for a reason other than
+ a timeout xNextTaskUnblockTime is normally left unchanged,
+ because it will automatically get reset to a new value when
+ the tick count equals xNextTaskUnblockTime. However if
+ tickless idling is used it might be more important to enter
+ sleep mode at the earliest possible time - so reset
+ xNextTaskUnblockTime here to ensure it is updated at the
+ earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
+ #endif
+
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* The notified task has a priority above the currently
+ executing task so a yield is required. */
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+ {
+ TCB_t * pxTCB;
+ uint8_t ucOriginalNotifyState;
+ BaseType_t xReturn = pdPASS;
+ UBaseType_t uxSavedInterruptStatus;
+
+ configASSERT( xTaskToNotify );
+
+ /* RTOS ports that support interrupt nesting have the concept of a
+ maximum system call (or maximum API call) interrupt priority.
+ Interrupts that are above the maximum system call priority are keep
+ permanently enabled, even when the RTOS kernel is in a critical section,
+ but cannot make any calls to FreeRTOS API functions. If configASSERT()
+ is defined in FreeRTOSConfig.h then
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has
+ been assigned a priority above the configured maximum system call
+ priority. Only FreeRTOS functions that end in FromISR can be called
+ from interrupts that have been assigned a priority at or (logically)
+ below the maximum system call interrupt priority. FreeRTOS maintains a
+ separate interrupt safe API to ensure interrupt entry is as fast and as
+ simple as possible. More information (albeit Cortex-M specific) is
+ provided on the following link:
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ pxTCB = xTaskToNotify;
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( pulPreviousNotificationValue != NULL )
+ {
+ *pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+ }
+
+ ucOriginalNotifyState = pxTCB->ucNotifyState;
+ pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+ switch( eAction )
+ {
+ case eSetBits :
+ pxTCB->ulNotifiedValue |= ulValue;
+ break;
+
+ case eIncrement :
+ ( pxTCB->ulNotifiedValue )++;
+ break;
+
+ case eSetValueWithOverwrite :
+ pxTCB->ulNotifiedValue = ulValue;
+ break;
+
+ case eSetValueWithoutOverwrite :
+ if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+ {
+ pxTCB->ulNotifiedValue = ulValue;
+ }
+ else
+ {
+ /* The value could not be written to the task. */
+ xReturn = pdFAIL;
+ }
+ break;
+
+ case eNoAction :
+ /* The task is being notified without its notify value being
+ updated. */
+ break;
+
+ default:
+ /* Should not get here if all enums are handled.
+ Artificially force an assert by testing a value the
+ compiler can't assume is const. */
+ configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+ break;
+ }
+
+ traceTASK_NOTIFY_FROM_ISR();
+
+ /* If the task is in the blocked state specifically to wait for a
+ notification then unblock it now. */
+ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+ {
+ /* The task should not have been on an event list. */
+ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ /* The delayed and ready lists cannot be accessed, so hold
+ this task pending until the scheduler is resumed. */
+ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+ }
+
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* The notified task has a priority above the currently
+ executing task so a yield is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+
+ /* Mark that a yield is pending in case the user is not
+ using the "xHigherPriorityTaskWoken" parameter to an ISR
+ safe FreeRTOS function. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+ }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+ {
+ TCB_t * pxTCB;
+ uint8_t ucOriginalNotifyState;
+ UBaseType_t uxSavedInterruptStatus;
+
+ configASSERT( xTaskToNotify );
+
+ /* RTOS ports that support interrupt nesting have the concept of a
+ maximum system call (or maximum API call) interrupt priority.
+ Interrupts that are above the maximum system call priority are keep
+ permanently enabled, even when the RTOS kernel is in a critical section,
+ but cannot make any calls to FreeRTOS API functions. If configASSERT()
+ is defined in FreeRTOSConfig.h then
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has
+ been assigned a priority above the configured maximum system call
+ priority. Only FreeRTOS functions that end in FromISR can be called
+ from interrupts that have been assigned a priority at or (logically)
+ below the maximum system call interrupt priority. FreeRTOS maintains a
+ separate interrupt safe API to ensure interrupt entry is as fast and as
+ simple as possible. More information (albeit Cortex-M specific) is
+ provided on the following link:
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ pxTCB = xTaskToNotify;
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ ucOriginalNotifyState = pxTCB->ucNotifyState;
+ pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+ /* 'Giving' is equivalent to incrementing a count in a counting
+ semaphore. */
+ ( pxTCB->ulNotifiedValue )++;
+
+ traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+ /* If the task is in the blocked state specifically to wait for a
+ notification then unblock it now. */
+ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+ {
+ /* The task should not have been on an event list. */
+ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ /* The delayed and ready lists cannot be accessed, so hold
+ this task pending until the scheduler is resumed. */
+ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+ }
+
+ if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* The notified task has a priority above the currently
+ executing task so a yield is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+
+ /* Mark that a yield is pending in case the user is not
+ using the "xHigherPriorityTaskWoken" parameter in an ISR
+ safe FreeRTOS function. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+ }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+ BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ BaseType_t xReturn;
+
+ /* If null is passed in here then it is the calling task that is having
+ its notification state cleared. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ taskENTER_CRITICAL();
+ {
+ if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+ {
+ pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+ TickType_t xTaskGetIdleRunTimeCounter( void )
+ {
+ return xIdleTaskHandle->ulRunTimeCounter;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+ #if( INCLUDE_xTaskAbortDelay == 1 )
+ {
+ /* About to enter a delayed list, so ensure the ucDelayAborted flag is
+ reset to pdFALSE so it can be detected as having been set to pdTRUE
+ when the task leaves the Blocked state. */
+ pxCurrentTCB->ucDelayAborted = pdFALSE;
+ }
+ #endif
+
+ /* Remove the task from the ready list before adding it to the blocked list
+ as the same list item is used for both lists. */
+ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* The current task must be in a ready list, so there is no need to
+ check, and the port reset macro can be called directly. */
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+ {
+ /* Add the task to the suspended task list instead of a delayed task
+ list to ensure it is not woken by a timing event. It will block
+ indefinitely. */
+ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ }
+ else
+ {
+ /* Calculate the time at which the task should be woken if the event
+ does not occur. This may overflow but this doesn't matter, the
+ kernel will manage it correctly. */
+ xTimeToWake = xConstTickCount + xTicksToWait;
+
+ /* The list item will be inserted in wake time order. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+ if( xTimeToWake < xConstTickCount )
+ {
+ /* Wake time has overflowed. Place this item in the overflow
+ list. */
+ vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ }
+ else
+ {
+ /* The wake time has not overflowed, so the current block list
+ is used. */
+ vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+ /* If the task entering the blocked state was placed at the
+ head of the list of blocked tasks then xNextTaskUnblockTime
+ needs to be updated too. */
+ if( xTimeToWake < xNextTaskUnblockTime )
+ {
+ xNextTaskUnblockTime = xTimeToWake;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ }
+ #else /* INCLUDE_vTaskSuspend */
+ {
+ /* Calculate the time at which the task should be woken if the event
+ does not occur. This may overflow but this doesn't matter, the kernel
+ will manage it correctly. */
+ xTimeToWake = xConstTickCount + xTicksToWait;
+
+ /* The list item will be inserted in wake time order. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+ if( xTimeToWake < xConstTickCount )
+ {
+ /* Wake time has overflowed. Place this item in the overflow list. */
+ vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+ }
+ else
+ {
+ /* The wake time has not overflowed, so the current block list is used. */
+ vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+ /* If the task entering the blocked state was placed at the head of the
+ list of blocked tasks then xNextTaskUnblockTime needs to be updated
+ too. */
+ if( xTimeToWake < xNextTaskUnblockTime )
+ {
+ xNextTaskUnblockTime = xTimeToWake;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+ ( void ) xCanBlockIndefinitely;
+ }
+ #endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+ #include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+ #include "freertos_tasks_c_additions.h"
+
+ #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+ static void freertos_tasks_c_additions_init( void )
+ {
+ FREERTOS_TASKS_C_ADDITIONS_INIT();
+ }
+ #endif
+
+#endif
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..ea04327
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -0,0 +1,1102 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+ #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality. This #if is closed at the very bottom
+of this file. If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY ( TickType_t ) 0U
+
+/* The name assigned to the timer service task. This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+ #define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+ const char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */
+ TickType_t xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+ void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */
+ TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */
+ #if( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+ #endif
+ uint8_t ucStatus; /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback. The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+ TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+ Timer_t * pxTimer; /*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+ PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
+ void *pvParameter1; /* << The value that will be used as the callback functions first parameter. */
+ uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+ BaseType_t xMessageID; /*<< The command being sent to the timer service task. */
+ union
+ {
+ TimerParameter_t xTimerParameters;
+
+ /* Don't include xCallbackParameters if it is not going to be used as
+ it makes the structure (and therefore the timer queue) larger. */
+ #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+ CallbackParameters_t xCallbackParameters;
+ #endif /* INCLUDE_xTimerPendFunctionCall */
+ } u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored. Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list. Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1 = { 0 };
+PRIVILEGED_DATA static List_t xActiveTimerList2 = { 0 };
+PRIVILEGED_DATA static List_t *pxCurrentTimerList = NULL;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList = NULL;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ /* If static allocation is supported then the application must provide the
+ following callback function - which enables the application to optionally
+ provide the memory that will be used by the timer task as the task's stack
+ and TCB. */
+ extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon). Timer functionality is controlled by this
+ * task. Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time. Reload the timer if it is an
+ * auto reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed. Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false. If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it. Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const TickType_t xTimerPeriodInTicks,
+ const UBaseType_t uxAutoReload,
+ void * const pvTimerID,
+ TimerCallbackFunction_t pxCallbackFunction,
+ Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+ /* This function is called when the scheduler is started if
+ configUSE_TIMERS is set to 1. Check that the infrastructure used by the
+ timer service task has been created/initialised. If timers have already
+ been created then the initialisation will already have been performed. */
+ prvCheckForValidListAndQueue();
+
+ if( xTimerQueue != NULL )
+ {
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+ StackType_t *pxTimerTaskStackBuffer = NULL;
+ uint32_t ulTimerTaskStackSize;
+
+ vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+ xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+ configTIMER_SERVICE_TASK_NAME,
+ ulTimerTaskStackSize,
+ NULL,
+ ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+ pxTimerTaskStackBuffer,
+ pxTimerTaskTCBBuffer );
+
+ if( xTimerTaskHandle != NULL )
+ {
+ xReturn = pdPASS;
+ }
+ }
+ #else
+ {
+ xReturn = xTaskCreate( prvTimerTask,
+ configTIMER_SERVICE_TASK_NAME,
+ configTIMER_TASK_STACK_DEPTH,
+ NULL,
+ ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+ &xTimerTaskHandle );
+ }
+ #endif /* configSUPPORT_STATIC_ALLOCATION */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ configASSERT( xReturn );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+ TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const TickType_t xTimerPeriodInTicks,
+ const UBaseType_t uxAutoReload,
+ void * const pvTimerID,
+ TimerCallbackFunction_t pxCallbackFunction )
+ {
+ Timer_t *pxNewTimer;
+
+ pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+ if( pxNewTimer != NULL )
+ {
+ /* Status is thus far zero as the timer is not created statically
+ and has not been started. The autoreload bit may get set in
+ prvInitialiseNewTimer. */
+ pxNewTimer->ucStatus = 0x00;
+ prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+ }
+
+ return pxNewTimer;
+ }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+ TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const TickType_t xTimerPeriodInTicks,
+ const UBaseType_t uxAutoReload,
+ void * const pvTimerID,
+ TimerCallbackFunction_t pxCallbackFunction,
+ StaticTimer_t *pxTimerBuffer )
+ {
+ Timer_t *pxNewTimer;
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ /* Sanity check that the size of the structure used to declare a
+ variable of type StaticTimer_t equals the size of the real timer
+ structure. */
+ volatile size_t xSize = sizeof( StaticTimer_t );
+ configASSERT( xSize == sizeof( Timer_t ) );
+ ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+ }
+ #endif /* configASSERT_DEFINED */
+
+ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+ configASSERT( pxTimerBuffer );
+ pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+ if( pxNewTimer != NULL )
+ {
+ /* Timers can be created statically or dynamically so note this
+ timer was created statically in case it is later deleted. The
+ autoreload bit may get set in prvInitialiseNewTimer(). */
+ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+ prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+ }
+
+ return pxNewTimer;
+ }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ const TickType_t xTimerPeriodInTicks,
+ const UBaseType_t uxAutoReload,
+ void * const pvTimerID,
+ TimerCallbackFunction_t pxCallbackFunction,
+ Timer_t *pxNewTimer )
+{
+ /* 0 is not a valid value for xTimerPeriodInTicks. */
+ configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+ if( pxNewTimer != NULL )
+ {
+ /* Ensure the infrastructure used by the timer service task has been
+ created/initialised. */
+ prvCheckForValidListAndQueue();
+
+ /* Initialise the timer structure members using the function
+ parameters. */
+ pxNewTimer->pcTimerName = pcTimerName;
+ pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+ pxNewTimer->pvTimerID = pvTimerID;
+ pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+ vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+ if( uxAutoReload != pdFALSE )
+ {
+ pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+ }
+ traceTIMER_CREATE( pxNewTimer );
+ }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+ configASSERT( xTimer );
+
+ /* Send a message to the timer service task to perform a particular action
+ on a particular timer definition. */
+ if( xTimerQueue != NULL )
+ {
+ /* Send a command to the timer service task to start the xTimer timer. */
+ xMessage.xMessageID = xCommandID;
+ xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+ xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+ if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+ {
+ if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+ {
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+ }
+ else
+ {
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+ }
+ }
+ else
+ {
+ xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+ }
+
+ traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+ /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+ started, then xTimerTaskHandle will be NULL. */
+ configASSERT( ( xTimerTaskHandle != NULL ) );
+ return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+ configASSERT( xTimer );
+ return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer = xTimer;
+
+ configASSERT( xTimer );
+ taskENTER_CRITICAL();
+ {
+ if( uxAutoReload != pdFALSE )
+ {
+ pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+ }
+ else
+ {
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer = xTimer;
+TickType_t xReturn;
+
+ configASSERT( xTimer );
+ xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+ configASSERT( xTimer );
+ return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+ /* Remove the timer from the list of active timers. A check has already
+ been performed to ensure the list is not empty. */
+ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ traceTIMER_EXPIRED( pxTimer );
+
+ /* If the timer is an auto reload timer then calculate the next
+ expiry time and re-insert the timer in the list of active timers. */
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ {
+ /* The timer is inserted into a list using a time relative to anything
+ other than the current time. It will therefore be inserted into the
+ correct list relative to the time this task thinks it is now. */
+ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+ {
+ /* The timer expired before it was added to the active timer
+ list. Reload it now. */
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ configASSERT( xResult );
+ ( void ) xResult;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Call the timer callback. */
+ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+ /* Just to avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ #if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+ {
+ extern void vApplicationDaemonTaskStartupHook( void );
+
+ /* Allow the application writer to execute some code in the context of
+ this task at the point the task starts executing. This is useful if the
+ application includes initialisation code that would benefit from
+ executing after the scheduler has been started. */
+ vApplicationDaemonTaskStartupHook();
+ }
+ #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+ for( ;; )
+ {
+ /* Query the timers list to see if it contains any timers, and if so,
+ obtain the time at which the next timer will expire. */
+ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+ /* If a timer has expired, process it. Otherwise, block this task
+ until either a timer does expire, or a command is received. */
+ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+ /* Empty the command queue. */
+ prvProcessReceivedCommands();
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+ vTaskSuspendAll();
+ {
+ /* Obtain the time now to make an assessment as to whether the timer
+ has expired or not. If obtaining the time causes the lists to switch
+ then don't process this timer as any timers that remained in the list
+ when the lists were switched will have been processed within the
+ prvSampleTimeNow() function. */
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+ if( xTimerListsWereSwitched == pdFALSE )
+ {
+ /* The tick count has not overflowed, has the timer expired? */
+ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+ {
+ ( void ) xTaskResumeAll();
+ prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+ }
+ else
+ {
+ /* The tick count has not overflowed, and the next expire
+ time has not been reached yet. This task should therefore
+ block to wait for the next expire time or a command to be
+ received - whichever comes first. The following line cannot
+ be reached unless xNextExpireTime > xTimeNow, except in the
+ case when the current timer list is empty. */
+ if( xListWasEmpty != pdFALSE )
+ {
+ /* The current timer list is empty - is the overflow list
+ also empty? */
+ xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+ }
+
+ vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ /* Yield to wait for either a command to arrive, or the
+ block time to expire. If a command arrived between the
+ critical section being exited and this yield then the yield
+ will not cause the task to block. */
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ else
+ {
+ ( void ) xTaskResumeAll();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+ /* Timers are listed in expiry time order, with the head of the list
+ referencing the task that will expire first. Obtain the time at which
+ the timer with the nearest expiry time will expire. If there are no
+ active timers then just set the next expire time to 0. That will cause
+ this task to unblock when the tick count overflows, at which point the
+ timer lists will be switched and the next expiry time can be
+ re-assessed. */
+ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+ if( *pxListWasEmpty == pdFALSE )
+ {
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+ }
+ else
+ {
+ /* Ensure the task unblocks when the tick count rolls over. */
+ xNextExpireTime = ( TickType_t ) 0U;
+ }
+
+ return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+ xTimeNow = xTaskGetTickCount();
+
+ if( xTimeNow < xLastTime )
+ {
+ prvSwitchTimerLists();
+ *pxTimerListsWereSwitched = pdTRUE;
+ }
+ else
+ {
+ *pxTimerListsWereSwitched = pdFALSE;
+ }
+
+ xLastTime = xTimeNow;
+
+ return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+ if( xNextExpiryTime <= xTimeNow )
+ {
+ /* Has the expiry time elapsed between the command to start/reset a
+ timer was issued, and the time the command was processed? */
+ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ {
+ /* The time between a command being issued and the command being
+ processed actually exceeds the timers period. */
+ xProcessTimerNow = pdTRUE;
+ }
+ else
+ {
+ vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+ }
+ }
+ else
+ {
+ if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+ {
+ /* If, since the command was issued, the tick count has overflowed
+ but the expiry time has not, then the timer must have already passed
+ its expiry time and should be processed immediately. */
+ xProcessTimerNow = pdTRUE;
+ }
+ else
+ {
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ }
+ }
+
+ return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+ while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+ {
+ #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+ {
+ /* Negative commands are pended function calls rather than timer
+ commands. */
+ if( xMessage.xMessageID < ( BaseType_t ) 0 )
+ {
+ const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+ /* The timer uses the xCallbackParameters member to request a
+ callback be executed. Check the callback is not NULL. */
+ configASSERT( pxCallback );
+
+ /* Call the function. */
+ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* INCLUDE_xTimerPendFunctionCall */
+
+ /* Commands that are positive are timer commands rather than pended
+ function calls. */
+ if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+ {
+ /* The messages uses the xTimerParameters member to work on a
+ software timer. */
+ pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+ {
+ /* The timer is in a list, remove it. */
+ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+ /* In this case the xTimerListsWereSwitched parameter is not used, but
+ it must be present in the function call. prvSampleTimeNow() must be
+ called after the message is received from xTimerQueue so there is no
+ possibility of a higher priority task adding a message to the message
+ queue with a time that is ahead of the timer daemon task (because it
+ pre-empted the timer daemon task after the xTimeNow value was set). */
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+ switch( xMessage.xMessageID )
+ {
+ case tmrCOMMAND_START :
+ case tmrCOMMAND_START_FROM_ISR :
+ case tmrCOMMAND_RESET :
+ case tmrCOMMAND_RESET_FROM_ISR :
+ case tmrCOMMAND_START_DONT_TRACE :
+ /* Start or restart a timer. */
+ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+ if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+ {
+ /* The timer expired before it was added to the active
+ timer list. Process it now. */
+ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ traceTIMER_EXPIRED( pxTimer );
+
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ {
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+ configASSERT( xResult );
+ ( void ) xResult;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ break;
+
+ case tmrCOMMAND_STOP :
+ case tmrCOMMAND_STOP_FROM_ISR :
+ /* The timer has already been removed from the active list. */
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ break;
+
+ case tmrCOMMAND_CHANGE_PERIOD :
+ case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+ pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+ configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+ /* The new period does not really have a reference, and can
+ be longer or shorter than the old one. The command time is
+ therefore set to the current time, and as the period cannot
+ be zero the next expiry time can only be in the future,
+ meaning (unlike for the xTimerStart() case above) there is
+ no fail case that needs to be handled here. */
+ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+ break;
+
+ case tmrCOMMAND_DELETE :
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+ {
+ /* The timer has already been removed from the active list,
+ just free up the memory if the memory was dynamically
+ allocated. */
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+ {
+ vPortFree( pxTimer );
+ }
+ else
+ {
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ }
+ }
+ #else
+ {
+ /* If dynamic allocation is not enabled, the memory
+ could not have been dynamically allocated. So there is
+ no need to free the memory - just mark the timer as
+ "not active". */
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ }
+ #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ break;
+
+ default :
+ /* Don't expect to get here. */
+ break;
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+ /* The tick count has overflowed. The timer lists must be switched.
+ If there are any timers still referenced from the current timer list
+ then they must have expired and should be processed before the lists
+ are switched. */
+ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+ {
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+ /* Remove the timer from the list. */
+ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ traceTIMER_EXPIRED( pxTimer );
+
+ /* Execute its callback, then send a command to restart the timer if
+ it is an auto-reload timer. It cannot be restarted here as the lists
+ have not yet been switched. */
+ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+ {
+ /* Calculate the reload value, and if the reload value results in
+ the timer going into the same timer list then it has already expired
+ and the timer should be re-inserted into the current list so it is
+ processed again within this loop. Otherwise a command should be sent
+ to restart the timer to ensure it is only inserted into a list after
+ the lists have been swapped. */
+ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+ if( xReloadTime > xNextExpireTime )
+ {
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ }
+ else
+ {
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ configASSERT( xResult );
+ ( void ) xResult;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ pxTemp = pxCurrentTimerList;
+ pxCurrentTimerList = pxOverflowTimerList;
+ pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+ /* Check that the list from which active timers are referenced, and the
+ queue used to communicate with the timer service, have been
+ initialised. */
+ taskENTER_CRITICAL();
+ {
+ if( xTimerQueue == NULL )
+ {
+ vListInitialise( &xActiveTimerList1 );
+ vListInitialise( &xActiveTimerList2 );
+ pxCurrentTimerList = &xActiveTimerList1;
+ pxOverflowTimerList = &xActiveTimerList2;
+
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ {
+ /* The timer queue is allocated statically in case
+ configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+ }
+ #else
+ {
+ xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+ }
+ #endif
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+ {
+ if( xTimerQueue != NULL )
+ {
+ vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configQUEUE_REGISTRY_SIZE */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+ configASSERT( xTimer );
+
+ /* Is the timer in the list of active timers? */
+ taskENTER_CRITICAL();
+ {
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+ configASSERT( xTimer );
+
+ taskENTER_CRITICAL();
+ {
+ pvReturn = pxTimer->pvTimerID;
+ }
+ taskEXIT_CRITICAL();
+
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+ configASSERT( xTimer );
+
+ taskENTER_CRITICAL();
+ {
+ pxTimer->pvTimerID = pvNewID;
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+ BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+ {
+ DaemonTaskMessage_t xMessage;
+ BaseType_t xReturn;
+
+ /* Complete the message with the function parameters and post it to the
+ daemon task. */
+ xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+ xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+ xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+ xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+ xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+ tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+ return xReturn;
+ }
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+ {
+ DaemonTaskMessage_t xMessage;
+ BaseType_t xReturn;
+
+ /* This function can only be called after a timer has been created or
+ after the scheduler has been started because, until then, the timer
+ queue does not exist. */
+ configASSERT( xTimerQueue );
+
+ /* Complete the message with the function parameters and post it to the
+ daemon task. */
+ xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+ xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+ xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+ xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+ tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+ return xReturn;
+ }
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+ {
+ return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+ {
+ ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality. If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/device.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/device.c
new file mode 100644
index 0000000..a980787
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/device.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include <metal/errno.h>
+#include <metal/assert.h>
+#include <metal/device.h>
+#include <metal/list.h>
+#include <metal/log.h>
+#include <metal/sys.h>
+#include <metal/utilities.h>
+#include <metal/dma.h>
+#include <metal/cache.h>
+
+int metal_bus_register(struct metal_bus *bus)
+{
+ if (!bus || !bus->name || !strlen(bus->name))
+ return -EINVAL;
+ if (metal_bus_find(bus->name, NULL) == 0)
+ return -EEXIST;
+ metal_list_init(&bus->devices);
+ metal_list_add_tail(&_metal.common.bus_list, &bus->node);
+ metal_log(METAL_LOG_DEBUG, "registered %s bus\n", bus->name);
+ return 0;
+}
+
+int metal_bus_unregister(struct metal_bus *bus)
+{
+ metal_list_del(&bus->node);
+ if (bus->ops.bus_close)
+ bus->ops.bus_close(bus);
+ metal_log(METAL_LOG_DEBUG, "unregistered %s bus\n", bus->name);
+ return 0;
+}
+
+int metal_bus_find(const char *name, struct metal_bus **result)
+{
+ struct metal_list *node;
+ struct metal_bus *bus;
+
+ metal_list_for_each(&_metal.common.bus_list, node) {
+ bus = metal_container_of(node, struct metal_bus, node);
+ if (strcmp(bus->name, name) != 0)
+ continue;
+ if (result)
+ *result = bus;
+ return 0;
+ }
+ return -ENOENT;
+}
+
+int metal_device_open(const char *bus_name, const char *dev_name,
+ struct metal_device **device)
+{
+ struct metal_bus *bus;
+ int error;
+
+ if (!bus_name || !strlen(bus_name) ||
+ !dev_name || !strlen(dev_name) ||
+ !device)
+ return -EINVAL;
+
+ error = metal_bus_find(bus_name, &bus);
+ if (error)
+ return error;
+
+ if (!bus->ops.dev_open)
+ return -ENODEV;
+
+ error = (*bus->ops.dev_open)(bus, dev_name, device);
+ if (error)
+ return error;
+
+ return 0;
+}
+
+void metal_device_close(struct metal_device *device)
+{
+ metal_assert(device && device->bus);
+ if (device->bus->ops.dev_close)
+ device->bus->ops.dev_close(device->bus, device);
+}
+
+int metal_register_generic_device(struct metal_device *device)
+{
+ if (!device->name || !strlen(device->name) ||
+ device->num_regions > METAL_MAX_DEVICE_REGIONS)
+ return -EINVAL;
+
+ device->bus = &metal_generic_bus;
+ metal_list_add_tail(&_metal.common.generic_device_list,
+ &device->node);
+ return 0;
+}
+
+int metal_generic_dev_open(struct metal_bus *bus, const char *dev_name,
+ struct metal_device **device)
+{
+ struct metal_list *node;
+ struct metal_device *dev;
+
+ (void)bus;
+
+ metal_list_for_each(&_metal.common.generic_device_list, node) {
+ dev = metal_container_of(node, struct metal_device, node);
+ if (strcmp(dev->name, dev_name) != 0)
+ continue;
+ *device = dev;
+ return metal_generic_dev_sys_open(dev);
+ }
+
+ return -ENODEV;
+}
+
+int metal_generic_dev_dma_map(struct metal_bus *bus,
+ struct metal_device *device,
+ uint32_t dir,
+ struct metal_sg *sg_in,
+ int nents_in,
+ struct metal_sg *sg_out)
+{
+ (void)bus;
+ (void)device;
+ int i;
+
+ if (sg_out != sg_in)
+ memcpy(sg_out, sg_in, nents_in*(sizeof(struct metal_sg)));
+ for (i = 0; i < nents_in; i++) {
+ if (dir == METAL_DMA_DEV_W) {
+ metal_cache_flush(sg_out[i].virt, sg_out[i].len);
+ }
+ metal_cache_invalidate(sg_out[i].virt, sg_out[i].len);
+ }
+
+ return nents_in;
+}
+
+void metal_generic_dev_dma_unmap(struct metal_bus *bus,
+ struct metal_device *device,
+ uint32_t dir,
+ struct metal_sg *sg,
+ int nents)
+{
+ (void)bus;
+ (void)device;
+ (void)dir;
+ int i;
+
+ for (i = 0; i < nents; i++) {
+ metal_cache_invalidate(sg[i].virt, sg[i].len);
+ }
+}
+
+struct metal_bus metal_weak metal_generic_bus = {
+ .name = "generic",
+ .ops = {
+ .bus_close = NULL,
+ .dev_open = metal_generic_dev_open,
+ .dev_close = NULL,
+ .dev_irq_ack = NULL,
+ .dev_dma_map = metal_generic_dev_dma_map,
+ .dev_dma_unmap = metal_generic_dev_dma_unmap,
+ },
+};
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/alloc.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/alloc.h
new file mode 100644
index 0000000..b82a09a
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/alloc.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file alloc.h
+ * @brief Memory allocation handling primitives for libmetal.
+ */
+
+#ifndef __METAL_ALLOC__H__
+#define __METAL_ALLOC__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup Memory Allocation Interfaces
+ * @{ */
+
+/**
+ * @brief allocate requested memory size
+ * return a pointer to the allocated memory
+ *
+ * @param[in] size size in byte of requested memory
+ * @return memory pointer, or 0 if it failed to allocate
+ */
+static inline void *metal_allocate_memory(unsigned int size);
+
+/**
+ * @brief free the memory previously allocated
+ *
+ * @param[in] ptr pointer to memory
+ */
+static inline void metal_free_memory(void *ptr);
+
+#include <metal/system/generic/alloc.h>
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_ALLOC__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/assert.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/assert.h
new file mode 100644
index 0000000..a2649eb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/assert.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file assert.h
+ * @brief Assertion support.
+ */
+
+#ifndef __METAL_ASSERT__H__
+#define __METAL_ASSERT__H__
+
+#include <metal/system/generic/assert.h>
+
+/**
+ * @brief Assertion macro.
+ * @param cond Condition to test.
+ */
+#define metal_assert(cond) metal_sys_assert(cond)
+
+#endif /* __METAL_ASSERT_H__ */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/atomic.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/atomic.h
new file mode 100644
index 0000000..14f771e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/atomic.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file atomic.h
+ * @brief Atomic primitives for libmetal.
+ */
+
+#ifndef __METAL_ATOMIC__H__
+#define __METAL_ATOMIC__H__
+
+#include <metal/config.h>
+
+#if defined(HAVE_STDATOMIC_H) && !defined (__CC_ARM) && \
+ !defined(__STDC_NO_ATOMICS__) && !defined(__cplusplus)
+
+# include <stdatomic.h>
+
+#ifndef atomic_thread_fence
+#define atomic_thread_fence(order)
+#endif
+
+#elif defined(__GNUC__)
+# include <metal/compiler/gcc/atomic.h>
+#else
+# include <metal/processor/arm/atomic.h>
+#endif
+
+#endif /* __METAL_ATOMIC__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cache.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cache.h
new file mode 100644
index 0000000..54a0155
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cache.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file cache.h
+ * @brief CACHE operation primitives for libmetal.
+ */
+
+#ifndef __METAL_CACHE__H__
+#define __METAL_CACHE__H__
+
+#include <metal/system/generic/cache.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** \defgroup cache CACHE Interfaces
+ * @{ */
+
+/**
+ * @brief flush specified data cache
+ *
+ * @param[in] addr start memory logical address
+ * @param[in] len length of memory
+ * If addr is NULL, and len is 0,
+ * It will flush the whole data cache.
+ */
+static inline void metal_cache_flush(void *addr, unsigned int len)
+{
+ __metal_cache_flush(addr, len);
+}
+
+/**
+ * @brief invalidate specified data cache
+ *
+ * @param[in] addr start memory logical address
+ * @param[in] len length of memory
+ * If addr is NULL, and len is 0,
+ * It will invalidate the whole data cache.
+ */
+static inline void metal_cache_invalidate(void *addr, unsigned int len)
+{
+ __metal_cache_invalidate(addr, len);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_CACHE__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler.h
new file mode 100644
index 0000000..ec4c675
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file compiler.h
+ * @brief Compiler specific primitives for libmetal.
+ */
+
+#ifndef __METAL_COMPILER__H__
+#define __METAL_COMPILER__H__
+
+#if defined(__GNUC__)
+# include <metal/compiler/gcc/compiler.h>
+#elif defined(__ICCARM__)
+# include <metal/compiler/iar/compiler.h>
+#elif defined (__CC_ARM)
+# error "MDK-ARM ARMCC compiler requires the GNU extentions to work correctly"
+#else
+# error "Missing compiler support"
+#endif
+
+#endif /* __METAL_COMPILER__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/atomic.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/atomic.h
new file mode 100644
index 0000000..4470342
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/atomic.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file gcc/atomic.h
+ * @brief GCC specific atomic primitives for libmetal.
+ */
+
+#ifndef __METAL_GCC_ATOMIC__H__
+#define __METAL_GCC_ATOMIC__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef int atomic_flag;
+typedef char atomic_char;
+typedef unsigned char atomic_uchar;
+typedef short atomic_short;
+typedef unsigned short atomic_ushort;
+typedef int atomic_int;
+typedef unsigned int atomic_uint;
+typedef long atomic_long;
+typedef unsigned long atomic_ulong;
+typedef long long atomic_llong;
+typedef unsigned long long atomic_ullong;
+
+#define ATOMIC_FLAG_INIT 0
+#define ATOMIC_VAR_INIT(VAL) (VAL)
+
+typedef enum {
+ memory_order_relaxed,
+ memory_order_consume,
+ memory_order_acquire,
+ memory_order_release,
+ memory_order_acq_rel,
+ memory_order_seq_cst,
+} memory_order;
+
+#define atomic_flag_test_and_set(FLAG) \
+ __sync_lock_test_and_set((FLAG), 1)
+#define atomic_flag_test_and_set_explicit(FLAG, MO) \
+ atomic_flag_test_and_set(FLAG)
+#define atomic_flag_clear(FLAG) \
+ __sync_lock_release((FLAG))
+#define atomic_flag_clear_explicit(FLAG, MO) \
+ atomic_flag_clear(FLAG)
+#define atomic_init(OBJ, VAL) \
+ do { *(OBJ) = (VAL); } while (0)
+#define atomic_is_lock_free(OBJ) \
+ (sizeof(*(OBJ)) <= sizeof(long))
+#define atomic_store(OBJ, VAL) \
+ do { *(OBJ) = (VAL); __sync_synchronize(); } while (0)
+#define atomic_store_explicit(OBJ, VAL, MO) \
+ atomic_store((OBJ), (VAL))
+#define atomic_load(OBJ) \
+ ({ __sync_synchronize(); *(OBJ); })
+#define atomic_load_explicit(OBJ, MO) \
+ atomic_load(OBJ)
+#define atomic_exchange(OBJ, DES) \
+ ({ \
+ typeof(OBJ) obj = (OBJ); \
+ typeof(*obj) des = (DES); \
+ typeof(*obj) expval; \
+ typeof(*obj) oldval = atomic_load(obj); \
+ do { \
+ expval = oldval; \
+ oldval = __sync_val_compare_and_swap( \
+ obj, expval, des); \
+ } while (oldval != expval); \
+ oldval; \
+ })
+#define atomic_exchange_explicit(OBJ, DES, MO) \
+ atomic_exchange((OBJ), (DES))
+#define atomic_compare_exchange_strong(OBJ, EXP, DES) \
+ ({ \
+ typeof(OBJ) obj = (OBJ); \
+ typeof(EXP) exp = (EXP); \
+ typeof(*obj) expval = *exp; \
+ typeof(*obj) oldval = __sync_val_compare_and_swap( \
+ obj, expval, (DES)); \
+ *exp = oldval; \
+ oldval == expval; \
+ })
+#define atomic_compare_exchange_strong_explicit(OBJ, EXP, DES, MO) \
+ atomic_compare_exchange_strong((OBJ), (EXP), (DES))
+#define atomic_compare_exchange_weak(OBJ, EXP, DES) \
+ atomic_compare_exchange_strong((OBJ), (EXP), (DES))
+#define atomic_compare_exchange_weak_explicit(OBJ, EXP, DES, MO) \
+ atomic_compare_exchange_weak((OBJ), (EXP), (DES))
+#define atomic_fetch_add(OBJ, VAL) \
+ __sync_fetch_and_add((OBJ), (VAL))
+#define atomic_fetch_add_explicit(OBJ, VAL, MO) \
+ atomic_fetch_add((OBJ), (VAL))
+#define atomic_fetch_sub(OBJ, VAL) \
+ __sync_fetch_and_sub((OBJ), (VAL))
+#define atomic_fetch_sub_explicit(OBJ, VAL, MO) \
+ atomic_fetch_sub((OBJ), (VAL))
+#define atomic_fetch_or(OBJ, VAL) \
+ __sync_fetch_and_or((OBJ), (VAL))
+#define atomic_fetch_or_explicit(OBJ, VAL, MO) \
+ atomic_fetch_or((OBJ), (VAL))
+#define atomic_fetch_xor(OBJ, VAL) \
+ __sync_fetch_and_xor((OBJ), (VAL))
+#define atomic_fetch_xor_explicit(OBJ, VAL, MO) \
+ atomic_fetch_xor((OBJ), (VAL))
+#define atomic_fetch_and(OBJ, VAL) \
+ __sync_fetch_and_and((OBJ), (VAL))
+#define atomic_fetch_and_explicit(OBJ, VAL, MO) \
+ atomic_fetch_and((OBJ), (VAL))
+#define atomic_thread_fence(MO) \
+ __sync_synchronize()
+#define atomic_signal_fence(MO) \
+ __sync_synchronize()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GCC_ATOMIC__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/compiler.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/compiler.h
new file mode 100644
index 0000000..7295ca8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/gcc/compiler.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file gcc/compiler.h
+ * @brief GCC specific primitives for libmetal.
+ */
+
+#ifndef __METAL_GCC_COMPILER__H__
+#define __METAL_GCC_COMPILER__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define restrict __restrict__
+#define metal_align(n) __attribute__((aligned(n)))
+#define metal_weak __attribute__((weak))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GCC_COMPILER__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/compiler.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/compiler.h
new file mode 100644
index 0000000..ad36bec
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/compiler.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018, ST Microelectronics. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file iar/compiler.h
+ * @brief IAR specific primitives for libmetal.
+ */
+
+#ifndef __METAL_IAR_COMPILER__H__
+#define __METAL_IAR_COMPILER__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define restrict __restrict__
+#define metal_align(n) __attribute__((aligned(n)))
+#define metal_weak __attribute__((weak))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_IAR_COMPILER__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/errno.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/errno.h
new file mode 100644
index 0000000..2450645
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/iar/errno.h
@@ -0,0 +1,118 @@
+/*
+ * * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+ * *
+ * * Copyright (c) 1982, 1986, 1989, 1993
+ * * The Regents of the University of California. All rights reserved.
+ * * Copyright (c) 1982, 1986, 1989, 1993
+ * * The Regents of the University of California. All rights reserved.
+ * * (c) UNIX System Laboratories, Inc.
+ * * All or some portions of this file are derived from material licensed
+ * * to the University of California by American Telephone and Telegraph
+ * * Co. or Unix System Laboratories, Inc. and are reproduced herein with
+ * * the permission of UNIX System Laboratories, Inc.
+ *
+ * * SPDX-License-Identifier: BSD-3-Clause
+ * */
+
+#ifndef __METAL_ERRNO__H__
+#error "Include metal/errno.h instead of metal/iar/errno.h"
+#endif
+
+#ifndef _ERRNO_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define _ERRNO_H_
+
+#define EPERM 1 /* Not owner */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No children */
+#define EAGAIN 11 /* No more processes */
+#define ENOMEM 12 /* Not enough space */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* Too many open files in system */
+#define EMFILE 24 /* File descriptor value too large */
+#define ENOTTY 25 /* Not a character device */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Mathematics argument out of domain of function */
+#define ERANGE 34 /* Result too large */
+#define ENOMSG 35 /* No message of desired type */
+#define EIDRM 36 /* Identifier removed */
+#define EDEADLK 45 /* Deadlock */
+#define ENOLCK 46 /* No lock */
+#define ENOSTR 60 /* Not a stream */
+#define ENODATA 61 /* No data (for no delay io) */
+#define ETIME 62 /* Stream ioctl timeout */
+#define ENOSR 63 /* No stream resources */
+#define ENOLINK 67 /* Virtual circuit is gone */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 74 /* Multihop attempted */
+#define EBADMSG 77 /* Bad message */
+#define EFTYPE 79 /* Inappropriate file type or format */
+#define ENOSYS 88 /* Function not implemented */
+#define ENOTEMPTY 90 /* Directory not empty */
+#define ENAMETOOLONG 91 /* File or path name too long */
+#define ELOOP 92 /* Too many symbolic links */
+#define EOPNOTSUPP 95 /* Operation not supported on socket */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EAFNOSUPPORT 106 /* Address family not supported by protocol family */
+#define EPROTOTYPE 107 /* Protocol wrong type for socket */
+#define ENOTSOCK 108 /* Socket operation on non-socket */
+#define ENOPROTOOPT 109 /* Protocol not available */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EADDRINUSE 112 /* Address already in use */
+#define ECONNABORTED 113 /* Software caused connection abort */
+#define ENETUNREACH 114 /* Network is unreachable */
+#define ENETDOWN 115 /* Network interface is not configured */
+#define ETIMEDOUT 116 /* Connection timed out */
+#define EHOSTDOWN 117 /* Host is down */
+#define EHOSTUNREACH 118 /* Host is unreachable */
+#define EINPROGRESS 119 /* Connection already in progress */
+#define EALREADY 120 /* Socket already connected */
+#define EDESTADDRREQ 121 /* Destination address required */
+#define EMSGSIZE 122 /* Message too long */
+#define EPROTONOSUPPORT 123 /* Unknown protocol */
+#define EADDRNOTAVAIL 125 /* Address not available */
+#define ENETRESET 126 /* Connection aborted by network */
+#define EISCONN 127 /* Socket is already connected */
+#define ENOTCONN 128 /* Socket is not connected */
+#define ETOOMANYREFS 129
+#define EDQUOT 132
+#define ESTALE 133
+#define ENOTSUP 134 /* Not supported */
+#define EILSEQ 138 /* Illegal byte sequence */
+#define EOVERFLOW 139 /* Value too large for defined data type */
+#define ECANCELED 140 /* Operation canceled */
+#define ENOTRECOVERABLE 141 /* State not recoverable */
+#define EOWNERDEAD 142 /* Previous owner died */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+
+#define __ELASTERROR 2000 /* Users can add values starting here */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _ERRNO_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/mdk-arm/errno.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/mdk-arm/errno.h
new file mode 100644
index 0000000..a6d6157
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/compiler/mdk-arm/errno.h
@@ -0,0 +1,137 @@
+/*
+ * * Copyright (c) 2019 STMicroelectronics. All rights reserved.
+ * *
+ * * Copyright (c) 1982, 1986, 1989, 1993
+ * * The Regents of the University of California. All rights reserved.
+ * * Copyright (c) 1982, 1986, 1989, 1993
+ * * The Regents of the University of California. All rights reserved.
+ * * (c) UNIX System Laboratories, Inc.
+ * * All or some portions of this file are derived from material licensed
+ * * to the University of California by American Telephone and Telegraph
+ * * Co. or Unix System Laboratories, Inc. and are reproduced herein with
+ * * the permission of UNIX System Laboratories, Inc.
+ *
+ * * SPDX-License-Identifier: BSD-3-Clause
+ * */
+
+
+#ifndef __METAL_ERRNO__H__
+#error "Include metal/errno.h instead of metal/mdk-arm/errno.h"
+#endif
+
+#ifndef _ERRNO_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define _ERRNO_H_
+
+#define EPERM 1 /* Not owner */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No children */
+#define EAGAIN 11 /* No more processes */
+#ifdef ENOMEM
+#undef ENOMEM
+#endif
+#define ENOMEM 12 /* Not enough space */
+
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#ifdef EINVAL
+#undef EINVAL
+#endif
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* Too many open files in system */
+#define EMFILE 24 /* File descriptor value too large */
+#define ENOTTY 25 /* Not a character device */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#ifdef EDOM
+#undef EDOM
+#endif
+#define EDOM 33 /* Mathematics argument out of domain of function */
+
+#ifdef ERANGE
+#undef ERANGE
+#endif
+#define ERANGE 34 /* Result too large */
+
+#define ENOMSG 35 /* No message of desired type */
+#define EIDRM 36 /* Identifier removed */
+#define EDEADLK 45 /* Deadlock */
+#define ENOLCK 46 /* No lock */
+#define ENOSTR 60 /* Not a stream */
+#define ENODATA 61 /* No data (for no delay io) */
+#define ETIME 62 /* Stream ioctl timeout */
+#define ENOSR 63 /* No stream resources */
+#define ENOLINK 67 /* Virtual circuit is gone */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 74 /* Multihop attempted */
+#define EBADMSG 77 /* Bad message */
+#define EFTYPE 79 /* Inappropriate file type or format */
+#define ENOSYS 88 /* Function not implemented */
+#define ENOTEMPTY 90 /* Directory not empty */
+#define ENAMETOOLONG 91 /* File or path name too long */
+#define ELOOP 92 /* Too many symbolic links */
+#define EOPNOTSUPP 95 /* Operation not supported on socket */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EAFNOSUPPORT 106 /* Address family not supported by protocol family */
+#define EPROTOTYPE 107 /* Protocol wrong type for socket */
+#define ENOTSOCK 108 /* Socket operation on non-socket */
+#define ENOPROTOOPT 109 /* Protocol not available */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EADDRINUSE 112 /* Address already in use */
+#define ECONNABORTED 113 /* Software caused connection abort */
+#define ENETUNREACH 114 /* Network is unreachable */
+#define ENETDOWN 115 /* Network interface is not configured */
+#define ETIMEDOUT 116 /* Connection timed out */
+#define EHOSTDOWN 117 /* Host is down */
+#define EHOSTUNREACH 118 /* Host is unreachable */
+#define EINPROGRESS 119 /* Connection already in progress */
+#define EALREADY 120 /* Socket already connected */
+#define EDESTADDRREQ 121 /* Destination address required */
+#define EMSGSIZE 122 /* Message too long */
+#define EPROTONOSUPPORT 123 /* Unknown protocol */
+#define EADDRNOTAVAIL 125 /* Address not available */
+#define ENETRESET 126 /* Connection aborted by network */
+#define EISCONN 127 /* Socket is already connected */
+#define ENOTCONN 128 /* Socket is not connected */
+#define ETOOMANYREFS 129
+#define EDQUOT 132
+#define ESTALE 133
+#define ENOTSUP 134 /* Not supported */
+#ifdef EILSEQ
+#undef EILSEQ
+#endif
+#define EILSEQ 138 /* Illegal byte sequence */
+#define EOVERFLOW 139 /* Value too large for defined data type */
+#define ECANCELED 140 /* Operation canceled */
+#define ENOTRECOVERABLE 141 /* State not recoverable */
+#define EOWNERDEAD 142 /* Previous owner died */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+
+#define __ELASTERROR 2000 /* Users can add values starting here */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _ERRNO_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/condition.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/condition.h
new file mode 100644
index 0000000..9532936
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/condition.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file condition.h
+ * @brief Condition variable for libmetal.
+ */
+
+#ifndef __METAL_CONDITION__H__
+#define __METAL_CONDITION__H__
+
+#include <metal/mutex.h>
+#include <metal/utilities.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup condition Condition Variable Interfaces
+ * @{ */
+
+/** Opaque libmetal condition variable data structure. */
+struct metal_condition;
+
+/**
+ * @brief Initialize a libmetal condition variable.
+ * @param[in] cv condition variable to initialize.
+ */
+static inline void metal_condition_init(struct metal_condition *cv);
+
+/**
+ * @brief Notify one waiter.
+ * Before calling this function, the caller
+ * should have acquired the mutex.
+ * @param[in] cv condition variable
+ * @return zero on no errors, non-zero on errors
+ * @see metal_condition_wait, metal_condition_broadcast
+ */
+static inline int metal_condition_signal(struct metal_condition *cv);
+
+/**
+ * @brief Notify all waiters.
+ * Before calling this function, the caller
+ * should have acquired the mutex.
+ * @param[in] cv condition variable
+ * @return zero on no errors, non-zero on errors
+ * @see metal_condition_wait, metal_condition_signal
+ */
+static inline int metal_condition_broadcast(struct metal_condition *cv);
+
+/**
+ * @brief Block until the condition variable is notified.
+ * Before calling this function, the caller should
+ * have acquired the mutex.
+ * @param[in] cv condition variable
+ * @param[in] m mutex
+ * @return 0 on success, non-zero on failure.
+ * @see metal_condition_signal
+ */
+int metal_condition_wait(struct metal_condition *cv, metal_mutex_t *m);
+
+#include <metal/system/generic/condition.h>
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_CONDITION__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/config.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/config.h
new file mode 100644
index 0000000..ce08057
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/config.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file config.h
+ * @brief Generated configuration settings for libmetal.
+ */
+
+#ifndef __METAL_CONFIG__H__
+#define __METAL_CONFIG__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Library major version number. */
+#define METAL_VER_MAJOR 0
+
+/** Library minor version number. */
+#define METAL_VER_MINOR 1
+
+/** Library patch level. */
+#define METAL_VER_PATCH 0
+
+/** Library version string. */
+#define METAL_VER "0.1.0"
+
+/** System type (linux, generic, ...). */
+#define METAL_SYSTEM "generic"
+#define METAL_SYSTEM_GENERIC
+
+/** Processor type (arm, x86_64, ...). */
+#define METAL_PROCESSOR "arm"
+#define METAL_PROCESSOR_ARM
+
+/** Machine type (zynq, zynqmp, ...). */
+#define METAL_MACHINE "cortexm"
+#define METAL_MACHINE_CORTEXM
+
+#define HAVE_STDATOMIC_H
+/* #undef HAVE_FUTEX_H */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_CONFIG__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cpu.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cpu.h
new file mode 100644
index 0000000..5537afb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/cpu.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file cpu.h
+ * @brief CPU primitives for libmetal.
+ */
+
+#ifndef __METAL_CPU__H__
+#define __METAL_CPU__H__
+
+# include <metal/processor/arm/cpu.h>
+
+#endif /* __METAL_CPU__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/device.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/device.h
new file mode 100644
index 0000000..c78b50d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/device.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file device.h
+ * @brief Bus abstraction for libmetal.
+ */
+
+#ifndef __METAL_BUS__H__
+#define __METAL_BUS__H__
+
+#include <stdint.h>
+#include <metal/io.h>
+#include <metal/list.h>
+#include <metal/dma.h>
+#include <metal/sys.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup device Bus Abstraction
+ * @{ */
+
+#ifndef METAL_MAX_DEVICE_REGIONS
+#define METAL_MAX_DEVICE_REGIONS 32
+#endif
+
+struct metal_bus;
+struct metal_device;
+
+/** Bus operations. */
+struct metal_bus_ops {
+ void (*bus_close)(struct metal_bus *bus);
+ int (*dev_open)(struct metal_bus *bus,
+ const char *dev_name,
+ struct metal_device **device);
+ void (*dev_close)(struct metal_bus *bus,
+ struct metal_device *device);
+ void (*dev_irq_ack)(struct metal_bus *bus,
+ struct metal_device *device,
+ int irq);
+ int (*dev_dma_map)(struct metal_bus *bus,
+ struct metal_device *device,
+ uint32_t dir,
+ struct metal_sg *sg_in,
+ int nents_in,
+ struct metal_sg *sg_out);
+ void (*dev_dma_unmap)(struct metal_bus *bus,
+ struct metal_device *device,
+ uint32_t dir,
+ struct metal_sg *sg,
+ int nents);
+};
+
+/** Libmetal bus structure. */
+struct metal_bus {
+ const char *name;
+ struct metal_bus_ops ops;
+ struct metal_list devices;
+ struct metal_list node;
+};
+
+/** Libmetal generic bus. */
+extern struct metal_bus metal_generic_bus;
+
+/** Libmetal device structure. */
+struct metal_device {
+ const char *name; /**< Device name */
+ struct metal_bus *bus; /**< Bus that contains device */
+ unsigned num_regions; /**< Number of I/O regions in
+ device */
+ struct metal_io_region regions[METAL_MAX_DEVICE_REGIONS]; /**< Array of
+ I/O regions in device*/
+ struct metal_list node; /**< Node on bus' list of devices */
+ int irq_num; /**< Number of IRQs per device */
+ void *irq_info; /**< IRQ ID */
+};
+
+/**
+ * @brief Register a libmetal bus.
+ * @param[in] bus Pre-initialized bus structure.
+ * @return 0 on success, or -errno on failure.
+ */
+extern int metal_bus_register(struct metal_bus *bus);
+
+/**
+ * @brief Unregister a libmetal bus.
+ * @param[in] bus Pre-registered bus structure.
+ * @return 0 on success, or -errno on failure.
+ */
+extern int metal_bus_unregister(struct metal_bus *bus);
+
+/**
+ * @brief Find a libmetal bus by name.
+ * @param[in] name Bus name.
+ * @param[out] bus Returned bus handle.
+ * @return 0 on success, or -errno on failure.
+ */
+extern int metal_bus_find(const char *name, struct metal_bus **bus);
+
+/**
+ * @brief Statically register a generic libmetal device.
+ *
+ * In non-Linux systems, devices are always required to be statically
+ * registered at application initialization.
+ * In Linux system, devices can be dynamically opened via sysfs or libfdt based
+ * enumeration at runtime.
+ * This interface is used for static registration of devices. Subsequent calls
+ * to metal_device_open() look up in this list of pre-registered devices on the
+ * "generic" bus.
+ * "generic" bus is used on non-Linux system to group the memory mapped devices.
+ *
+ * @param[in] device Generic device.
+ * @return 0 on success, or -errno on failure.
+ */
+extern int metal_register_generic_device(struct metal_device *device);
+
+/**
+ * @brief Open a libmetal device by name.
+ * @param[in] bus_name Bus name.
+ * @param[in] dev_name Device name.
+ * @param[out] device Returned device handle.
+ * @return 0 on success, or -errno on failure.
+ */
+extern int metal_device_open(const char *bus_name, const char *dev_name,
+ struct metal_device **device);
+
+/**
+ * @brief Close a libmetal device.
+ * @param[in] device Device handle.
+ */
+extern void metal_device_close(struct metal_device *device);
+
+/**
+ * @brief Get an I/O region accessor for a device region.
+ *
+ * @param[in] device Device handle.
+ * @param[in] index Region index.
+ * @return I/O accessor handle, or NULL on failure.
+ */
+static inline struct metal_io_region *
+metal_device_io_region(struct metal_device *device, unsigned index)
+{
+ return (index < device->num_regions
+ ? &device->regions[index]
+ : NULL);
+}
+
+/** @} */
+
+#ifdef METAL_INTERNAL
+extern int metal_generic_dev_sys_open(struct metal_device *dev);
+extern int metal_generic_dev_open(struct metal_bus *bus, const char *dev_name,
+ struct metal_device **device);
+extern int metal_generic_dev_dma_map(struct metal_bus *bus,
+ struct metal_device *device,
+ uint32_t dir,
+ struct metal_sg *sg_in,
+ int nents_in,
+ struct metal_sg *sg_out);
+extern void metal_generic_dev_dma_unmap(struct metal_bus *bus,
+ struct metal_device *device,
+ uint32_t dir,
+ struct metal_sg *sg,
+ int nents);
+#endif /* METAL_INTERNAL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_BUS__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/dma.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/dma.h
new file mode 100644
index 0000000..1c8e8b1
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/dma.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file dma.h
+ * @brief DMA primitives for libmetal.
+ */
+
+#ifndef __METAL_DMA__H__
+#define __METAL_DMA__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup dma DMA Interfaces
+ * @{ */
+
+#include <stdint.h>
+#include <metal/sys.h>
+
+#define METAL_DMA_DEV_R 1 /**< DMA direction, device read */
+#define METAL_DMA_DEV_W 2 /**< DMA direction, device write */
+#define METAL_DMA_DEV_WR 3 /**< DMA direction, device read/write */
+
+/**
+ * @brief scatter/gather list element structure
+ */
+struct metal_sg {
+ void *virt; /**< CPU virtual address */
+ struct metal_io_region *io; /**< IO region */
+ int len; /**< length */
+};
+
+struct metal_device;
+
+/**
+ * @brief Map memory for DMA transaction.
+ * After the memory is DMA mapped, the memory should be
+ * accessed by the DMA device but not the CPU.
+ *
+ * @param[in] dev DMA device
+ * @param[in] dir DMA direction
+ * @param[in] sg_in sg list of memory to map
+ * @param[in] nents_in number of sg list entries of memory to map
+ * @param[out] sg_out sg list of mapped memory
+ * @return number of mapped sg entries, -error on failure.
+ */
+int metal_dma_map(struct metal_device *dev,
+ uint32_t dir,
+ struct metal_sg *sg_in,
+ int nents_in,
+ struct metal_sg *sg_out);
+
+/**
+ * @brief Unmap DMA memory
+ * After the memory is DMA unmapped, the memory should
+ * be accessed by the CPU but not the DMA device.
+ *
+ * @param[in] dev DMA device
+ * @param[in] dir DMA direction
+ * @param[in] sg sg list of mapped DMA memory
+ * @param[in] nents number of sg list entries of DMA memory
+ */
+void metal_dma_unmap(struct metal_device *dev,
+ uint32_t dir,
+ struct metal_sg *sg,
+ int nents);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_DMA__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/errno.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/errno.h
new file mode 100644
index 0000000..2f200e8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/errno.h
@@ -0,0 +1,24 @@
+/*
+ * * Copyright (c) 2019 STMicrolectonics , Xilinx Inc. and Contributors. All rights reserved.
+ * *
+ * * SPDX-License-Identifier: BSD-3-Clause
+ * */
+
+/*
+ * * @file metal/errno.h
+ * * @brief error specific primitives for libmetal.
+ * */
+
+#ifndef __METAL_ERRNO__H__
+#define __METAL_ERRNO__H__
+
+#if defined (__CC_ARM)
+# include <metal/compiler/mdk-arm/errno.h>
+#elif defined (__ICCARM__)
+# include <metal/compiler/iar/errno.h>
+#else
+#include <errno.h>
+#endif
+
+#endif /* __METAL_ERRNO__H__ */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/io.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/io.h
new file mode 100644
index 0000000..95512d8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/io.h
@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2015 - 2017, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file io.h
+ * @brief I/O access primitives for libmetal.
+ */
+
+#ifndef __METAL_IO__H__
+#define __METAL_IO__H__
+
+#include <limits.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+#include <metal/assert.h>
+#include <metal/compiler.h>
+#include <metal/atomic.h>
+#include <metal/sys.h>
+#include <metal/cpu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup io IO Interfaces
+ * @{ */
+
+#ifdef __MICROBLAZE__
+#define NO_ATOMIC_64_SUPPORT
+#endif
+
+struct metal_io_region;
+
+/** Generic I/O operations. */
+struct metal_io_ops {
+ uint64_t (*read)(struct metal_io_region *io,
+ unsigned long offset,
+ memory_order order,
+ int width);
+ void (*write)(struct metal_io_region *io,
+ unsigned long offset,
+ uint64_t value,
+ memory_order order,
+ int width);
+ int (*block_read)(struct metal_io_region *io,
+ unsigned long offset,
+ void *restrict dst,
+ memory_order order,
+ int len);
+ int (*block_write)(struct metal_io_region *io,
+ unsigned long offset,
+ const void *restrict src,
+ memory_order order,
+ int len);
+ void (*block_set)(struct metal_io_region *io,
+ unsigned long offset,
+ unsigned char value,
+ memory_order order,
+ int len);
+ void (*close)(struct metal_io_region *io);
+};
+
+/** Libmetal I/O region structure. */
+struct metal_io_region {
+ void *virt; /**< base virtual address */
+ const metal_phys_addr_t *physmap; /**< table of base physical address
+ of each of the pages in the I/O
+ region */
+ size_t size; /**< size of the I/O region */
+ unsigned long page_shift; /**< page shift of I/O region */
+ metal_phys_addr_t page_mask; /**< page mask of I/O region */
+ unsigned int mem_flags; /**< memory attribute of the
+ I/O region */
+ struct metal_io_ops ops; /**< I/O region operations */
+};
+
+/**
+ * @brief Open a libmetal I/O region.
+ *
+ * @param[in, out] io I/O region handle.
+ * @param[in] virt Virtual address of region.
+ * @param[in] physmap Array of physical addresses per page.
+ * @param[in] size Size of region.
+ * @param[in] page_shift Log2 of page size (-1 for single page).
+ * @param[in] mem_flags Memory flags
+ * @param[in] ops ops
+ */
+void
+metal_io_init(struct metal_io_region *io, void *virt,
+ const metal_phys_addr_t *physmap, size_t size,
+ unsigned page_shift, unsigned int mem_flags,
+ const struct metal_io_ops *ops);
+
+/**
+ * @brief Close a libmetal shared memory segment.
+ * @param[in] io I/O region handle.
+ */
+static inline void metal_io_finish(struct metal_io_region *io)
+{
+ if (io->ops.close)
+ (*io->ops.close)(io);
+ memset(io, 0, sizeof(*io));
+}
+
+/**
+ * @brief Get size of I/O region.
+ *
+ * @param[in] io I/O region handle.
+ * @return Size of I/O region.
+ */
+static inline size_t metal_io_region_size(struct metal_io_region *io)
+{
+ return io->size;
+}
+
+/**
+ * @brief Get virtual address for a given offset into the I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] offset Offset into shared memory segment.
+ * @return NULL if offset is out of range, or pointer to offset.
+ */
+static inline void *
+metal_io_virt(struct metal_io_region *io, unsigned long offset)
+{
+ return (io->virt != METAL_BAD_VA && offset <= io->size
+ ? (uint8_t *)io->virt + offset
+ : NULL);
+}
+
+/**
+ * @brief Convert a virtual address to offset within I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] virt Virtual address within segment.
+ * @return METAL_BAD_OFFSET if out of range, or offset.
+ */
+static inline unsigned long
+metal_io_virt_to_offset(struct metal_io_region *io, void *virt)
+{
+ size_t offset = (uint8_t *)virt - (uint8_t *)io->virt;
+ return (offset < io->size ? offset : METAL_BAD_OFFSET);
+}
+
+/**
+ * @brief Get physical address for a given offset into the I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] offset Offset into shared memory segment.
+ * @return METAL_BAD_PHYS if offset is out of range, or physical address
+ * of offset.
+ */
+static inline metal_phys_addr_t
+metal_io_phys(struct metal_io_region *io, unsigned long offset)
+{
+ unsigned long page = (io->page_shift >=
+ sizeof(offset) * CHAR_BIT ?
+ 0 : offset >> io->page_shift);
+ return (io->physmap != NULL && offset <= io->size
+ ? io->physmap[page] + (offset & io->page_mask)
+ : METAL_BAD_PHYS);
+}
+
+/**
+ * @brief Convert a physical address to offset within I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] phys Physical address within segment.
+ * @return METAL_BAD_OFFSET if out of range, or offset.
+ */
+static inline unsigned long
+metal_io_phys_to_offset(struct metal_io_region *io, metal_phys_addr_t phys)
+{
+ unsigned long offset =
+ (io->page_mask == (metal_phys_addr_t)(-1) ?
+ phys - io->physmap[0] : phys & io->page_mask);
+ do {
+ if (metal_io_phys(io, offset) == phys)
+ return offset;
+ offset += io->page_mask + 1;
+ } while (offset < io->size);
+ return METAL_BAD_OFFSET;
+}
+
+/**
+ * @brief Convert a physical address to virtual address.
+ * @param[in] io Shared memory segment handle.
+ * @param[in] phys Physical address within segment.
+ * @return NULL if out of range, or corresponding virtual address.
+ */
+static inline void *
+metal_io_phys_to_virt(struct metal_io_region *io, metal_phys_addr_t phys)
+{
+ return metal_io_virt(io, metal_io_phys_to_offset(io, phys));
+}
+
+/**
+ * @brief Convert a virtual address to physical address.
+ * @param[in] io Shared memory segment handle.
+ * @param[in] virt Virtual address within segment.
+ * @return METAL_BAD_PHYS if out of range, or corresponding
+ * physical address.
+ */
+static inline metal_phys_addr_t
+metal_io_virt_to_phys(struct metal_io_region *io, void *virt)
+{
+ return metal_io_phys(io, metal_io_virt_to_offset(io, virt));
+}
+
+/**
+ * @brief Read a value from an I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] offset Offset into I/O region.
+ * @param[in] order Memory ordering.
+ * @param[in] width Width in bytes of datatype to read. This must be 1, 2,
+ * 4, or 8, and a compile time constant for this function
+ * to inline cleanly.
+ * @return Value.
+ */
+static inline uint64_t
+metal_io_read(struct metal_io_region *io, unsigned long offset,
+ memory_order order, int width)
+{
+ void *ptr = metal_io_virt(io, offset);
+
+ if (io->ops.read)
+ return (*io->ops.read)(io, offset, order, width);
+ else if (ptr && sizeof(atomic_uchar) == width)
+ return atomic_load_explicit((atomic_uchar *)ptr, order);
+ else if (ptr && sizeof(atomic_ushort) == width)
+ return atomic_load_explicit((atomic_ushort *)ptr, order);
+ else if (ptr && sizeof(atomic_uint) == width)
+ return atomic_load_explicit((atomic_uint *)ptr, order);
+ else if (ptr && sizeof(atomic_ulong) == width)
+ return atomic_load_explicit((atomic_ulong *)ptr, order);
+#ifndef NO_ATOMIC_64_SUPPORT
+ else if (ptr && sizeof(atomic_ullong) == width)
+ return atomic_load_explicit((atomic_ullong *)ptr, order);
+#endif
+ metal_assert(0);
+ return 0; /* quiet compiler */
+}
+
+/**
+ * @brief Write a value into an I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] offset Offset into I/O region.
+ * @param[in] value Value to write.
+ * @param[in] order Memory ordering.
+ * @param[in] width Width in bytes of datatype to read. This must be 1, 2,
+ * 4, or 8, and a compile time constant for this function
+ * to inline cleanly.
+ */
+static inline void
+metal_io_write(struct metal_io_region *io, unsigned long offset,
+ uint64_t value, memory_order order, int width)
+{
+ void *ptr = metal_io_virt(io, offset);
+ if (io->ops.write)
+ (*io->ops.write)(io, offset, value, order, width);
+ else if (ptr && sizeof(atomic_uchar) == width)
+ atomic_store_explicit((atomic_uchar *)ptr, value, order);
+ else if (ptr && sizeof(atomic_ushort) == width)
+ atomic_store_explicit((atomic_ushort *)ptr, value, order);
+ else if (ptr && sizeof(atomic_uint) == width)
+ atomic_store_explicit((atomic_uint *)ptr, value, order);
+ else if (ptr && sizeof(atomic_ulong) == width)
+ atomic_store_explicit((atomic_ulong *)ptr, value, order);
+#ifndef NO_ATOMIC_64_SUPPORT
+ else if (ptr && sizeof(atomic_ullong) == width)
+ atomic_store_explicit((atomic_ullong *)ptr, value, order);
+#endif
+ else
+ metal_assert (0);
+}
+
+#define metal_io_read8_explicit(_io, _ofs, _order) \
+ metal_io_read((_io), (_ofs), (_order), 1)
+#define metal_io_read8(_io, _ofs) \
+ metal_io_read((_io), (_ofs), memory_order_seq_cst, 1)
+#define metal_io_write8_explicit(_io, _ofs, _val, _order) \
+ metal_io_write((_io), (_ofs), (_val), (_order), 1)
+#define metal_io_write8(_io, _ofs, _val) \
+ metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 1)
+
+#define metal_io_read16_explicit(_io, _ofs, _order) \
+ metal_io_read((_io), (_ofs), (_order), 2)
+#define metal_io_read16(_io, _ofs) \
+ metal_io_read((_io), (_ofs), memory_order_seq_cst, 2)
+#define metal_io_write16_explicit(_io, _ofs, _val, _order) \
+ metal_io_write((_io), (_ofs), (_val), (_order), 2)
+#define metal_io_write16(_io, _ofs, _val) \
+ metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 2)
+
+#define metal_io_read32_explicit(_io, _ofs, _order) \
+ metal_io_read((_io), (_ofs), (_order), 4)
+#define metal_io_read32(_io, _ofs) \
+ metal_io_read((_io), (_ofs), memory_order_seq_cst, 4)
+#define metal_io_write32_explicit(_io, _ofs, _val, _order) \
+ metal_io_write((_io), (_ofs), (_val), (_order), 4)
+#define metal_io_write32(_io, _ofs, _val) \
+ metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 4)
+
+#define metal_io_read64_explicit(_io, _ofs, _order) \
+ metal_io_read((_io), (_ofs), (_order), 8)
+#define metal_io_read64(_io, _ofs) \
+ metal_io_read((_io), (_ofs), memory_order_seq_cst, 8)
+#define metal_io_write64_explicit(_io, _ofs, _val, _order) \
+ metal_io_write((_io), (_ofs), (_val), (_order), 8)
+#define metal_io_write64(_io, _ofs, _val) \
+ metal_io_write((_io), (_ofs), (_val), memory_order_seq_cst, 8)
+
+/**
+ * @brief Read a block from an I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] offset Offset into I/O region.
+ * @param[in] dst destination to store the read data.
+ * @param[in] len length in bytes to read.
+ * @return On success, number of bytes read. On failure, negative value
+ */
+int metal_io_block_read(struct metal_io_region *io, unsigned long offset,
+ void *restrict dst, int len);
+
+/**
+ * @brief Write a block into an I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] offset Offset into I/O region.
+ * @param[in] src source to write.
+ * @param[in] len length in bytes to write.
+ * @return On success, number of bytes written. On failure, negative value
+ */
+int metal_io_block_write(struct metal_io_region *io, unsigned long offset,
+ const void *restrict src, int len);
+
+/**
+ * @brief fill a block of an I/O region.
+ * @param[in] io I/O region handle.
+ * @param[in] offset Offset into I/O region.
+ * @param[in] value value to fill into the block
+ * @param[in] len length in bytes to fill.
+ * @return On success, number of bytes filled. On failure, negative value
+ */
+int metal_io_block_set(struct metal_io_region *io, unsigned long offset,
+ unsigned char value, int len);
+
+#include <metal/system/generic/io.h>
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_IO__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/irq.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/irq.h
new file mode 100644
index 0000000..9f0344e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/irq.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file irq.h
+ * @brief Interrupt handling primitives for libmetal.
+ */
+
+#ifndef __METAL_IRQ__H__
+#define __METAL_IRQ__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup irq Interrupt Handling Interfaces
+ * @{ */
+
+#include <stdlib.h>
+
+/** IRQ handled status */
+#define METAL_IRQ_NOT_HANDLED 0
+#define METAL_IRQ_HANDLED 1
+
+/**
+ * @brief type of interrupt handler
+ * @param[in] irq interrupt id
+ * @param[in] priv private data
+ * @return irq handled status
+ */
+typedef int (*metal_irq_handler) (int irq, void *priv);
+
+struct metal_device;
+
+/**
+ * @brief Register interrupt handler for driver ID/device.
+ *
+ * @param[in] irq interrupt id
+ * @param[in] irq_handler interrupt handler
+ * @param[in] dev metal device this irq belongs to (can be NULL).
+ * @param[in] drv_id driver id is a unique interrupt handler identifier.
+ * It can also be used for driver data.
+ * @return 0 for success, non-zero on failure
+ */
+int metal_irq_register(int irq,
+ metal_irq_handler irq_handler,
+ struct metal_device *dev,
+ void *drv_id);
+
+/**
+ * @brief Unregister interrupt handler for driver ID and/or device.
+ *
+ * If interrupt handler (hd), driver ID (drv_id) and device (dev)
+ * are NULL, unregister all handlers for this interrupt.
+ *
+ * If interrupt handler (hd), device (dev) or driver ID (drv_id),
+ * are not NULL, unregister handlers matching non NULL criterias.
+ * e.g: when call is made with drv_id and dev non NULL,
+ * all handlers matching both are unregistered.
+ *
+ * If interrupt is not found, or other criterias not matching,
+ * return -ENOENT
+ *
+ * @param[in] irq interrupt id
+ * @param[in] irq_handler interrupt handler
+ * @param[in] dev metal device this irq belongs to
+ * @param[in] drv_id driver id. It can be used for driver data.
+ * @return 0 for success, non-zero on failure
+ */
+int metal_irq_unregister(int irq,
+ metal_irq_handler irq_handler,
+ struct metal_device *dev,
+ void *drv_id);
+
+/**
+ * @brief disable interrupts
+ * @return interrupts state
+ */
+unsigned int metal_irq_save_disable(void);
+
+/**
+ * @brief restore interrupts to their previous state
+ * @param[in] flags previous interrupts state
+ */
+void metal_irq_restore_enable(unsigned int flags);
+
+/**
+ * @brief metal_irq_enable
+ *
+ * Enables the given interrupt
+ *
+ * @param vector - interrupt vector number
+ */
+void metal_irq_enable(unsigned int vector);
+
+/**
+ * @brief metal_irq_disable
+ *
+ * Disables the given interrupt
+ *
+ * @param vector - interrupt vector number
+ */
+void metal_irq_disable(unsigned int vector);
+
+#include <metal/system/generic/irq.h>
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_IRQ__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/list.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/list.h
new file mode 100644
index 0000000..a9395ba
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/list.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file list.h
+ * @brief List primitives for libmetal.
+ */
+
+#ifndef __METAL_LIST__H__
+#define __METAL_LIST__H__
+
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup list List Primitives
+ * @{ */
+
+struct metal_list {
+ struct metal_list *next, *prev;
+};
+
+/*
+ * METAL_INIT_LIST - used for initializing an list elmenet in a static struct
+ * or global
+ */
+#define METAL_INIT_LIST(name) { .next = &name, .prev = &name }
+/*
+ * METAL_DECLARE_LIST - used for defining and initializing a global or
+ * static singleton list
+ */
+#define METAL_DECLARE_LIST(name) \
+ struct metal_list name = METAL_INIT_LIST(name)
+
+static inline void metal_list_init(struct metal_list *list)
+{
+ list->next = list->prev = list;
+}
+
+static inline void metal_list_add_before(struct metal_list *node,
+ struct metal_list *new_node)
+{
+ new_node->prev = node->prev;
+ new_node->next = node;
+ new_node->next->prev = new_node;
+ new_node->prev->next = new_node;
+}
+
+static inline void metal_list_add_after(struct metal_list *node,
+ struct metal_list *new_node)
+{
+ new_node->prev = node;
+ new_node->next = node->next;
+ new_node->next->prev = new_node;
+ new_node->prev->next = new_node;
+}
+
+static inline void metal_list_add_head(struct metal_list *list,
+ struct metal_list *node)
+{
+ metal_list_add_after(list, node);
+}
+
+static inline void metal_list_add_tail(struct metal_list *list,
+ struct metal_list *node)
+{
+ metal_list_add_before(list, node);
+}
+
+static inline int metal_list_is_empty(struct metal_list *list)
+{
+ return list->next == list;
+}
+
+static inline void metal_list_del(struct metal_list *node)
+{
+ node->next->prev = node->prev;
+ node->prev->next = node->next;
+ node->next = node->prev = node;
+}
+
+static inline struct metal_list *metal_list_first(struct metal_list *list)
+{
+ return metal_list_is_empty(list) ? NULL : list->next;
+}
+
+#define metal_list_for_each(list, node) \
+ for ((node) = (list)->next; \
+ (node) != (list); \
+ (node) = (node)->next)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_LIST__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/log.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/log.h
new file mode 100644
index 0000000..d439ef8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/log.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file log.h
+ * @brief Logging support for libmetal.
+ */
+
+#ifndef __METAL_METAL_LOG__H__
+#define __METAL_METAL_LOG__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup logging Library Logging Interfaces
+ * @{ */
+
+/** Log message priority levels for libmetal. */
+enum metal_log_level {
+ METAL_LOG_EMERGENCY, /**< system is unusable. */
+ METAL_LOG_ALERT, /**< action must be taken immediately. */
+ METAL_LOG_CRITICAL, /**< critical conditions. */
+ METAL_LOG_ERROR, /**< error conditions. */
+ METAL_LOG_WARNING, /**< warning conditions. */
+ METAL_LOG_NOTICE, /**< normal but significant condition. */
+ METAL_LOG_INFO, /**< informational messages. */
+ METAL_LOG_DEBUG, /**< debug-level messages. */
+};
+
+/** Log message handler type. */
+typedef void (*metal_log_handler)(enum metal_log_level level,
+ const char *format, ...);
+
+/**
+ * @brief Set libmetal log handler.
+ * @param[in] handler log message handler.
+ * @return 0 on success, or -errno on failure.
+ */
+extern void metal_set_log_handler(metal_log_handler handler);
+
+/**
+ * @brief Get the current libmetal log handler.
+ * @return Current log handler.
+ */
+extern metal_log_handler metal_get_log_handler(void);
+
+/**
+ * @brief Set the level for libmetal logging.
+ * @param[in] level log message level.
+ */
+extern void metal_set_log_level(enum metal_log_level level);
+
+/**
+ * @brief Get the current level for libmetal logging.
+ * @return Current log level.
+ */
+extern enum metal_log_level metal_get_log_level(void);
+
+/**
+ * @brief Default libmetal log handler. This handler prints libmetal log
+ * mesages to stderr.
+ * @param[in] level log message level.
+ * @param[in] format log message format string.
+ * @return 0 on success, or -errno on failure.
+ */
+extern void metal_default_log_handler(enum metal_log_level level,
+ const char *format, ...);
+
+
+/**
+ * Emit a log message if the log level permits.
+ *
+ * @param level Log level.
+ * @param ... Format string and arguments.
+ */
+#define metal_log(level, ...) \
+ ((level <= _metal.common.log_level && _metal.common.log_handler) \
+ ? (void)_metal.common.log_handler(level, __VA_ARGS__) \
+ : (void)0)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <metal/system/generic/log.h>
+
+#endif /* __METAL_METAL_LOG__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/mutex.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/mutex.h
new file mode 100644
index 0000000..c241bd0
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/mutex.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file mutex.h
+ * @brief Mutex primitives for libmetal.
+ */
+
+#ifndef __METAL_MUTEX__H__
+#define __METAL_MUTEX__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup mutex Mutex Interfaces
+ * @{ */
+
+#include <metal/system/generic/mutex.h>
+
+/**
+ * @brief Initialize a libmetal mutex.
+ * @param[in] mutex Mutex to initialize.
+ */
+static inline void metal_mutex_init(metal_mutex_t *mutex)
+{
+ __metal_mutex_init(mutex);
+}
+
+/**
+ * @brief Deinitialize a libmetal mutex.
+ * @param[in] mutex Mutex to deinitialize.
+ */
+static inline void metal_mutex_deinit(metal_mutex_t *mutex)
+{
+ __metal_mutex_deinit(mutex);
+}
+
+/**
+ * @brief Try to acquire a mutex
+ * @param[in] mutex Mutex to mutex.
+ * @return 0 on failure to acquire, non-zero on success.
+ */
+static inline int metal_mutex_try_acquire(metal_mutex_t *mutex)
+{
+ return __metal_mutex_try_acquire(mutex);
+}
+
+/**
+ * @brief Acquire a mutex
+ * @param[in] mutex Mutex to mutex.
+ */
+static inline void metal_mutex_acquire(metal_mutex_t *mutex)
+{
+ __metal_mutex_acquire(mutex);
+}
+
+/**
+ * @brief Release a previously acquired mutex.
+ * @param[in] mutex Mutex to mutex.
+ * @see metal_mutex_try_acquire, metal_mutex_acquire
+ */
+static inline void metal_mutex_release(metal_mutex_t *mutex)
+{
+ __metal_mutex_release(mutex);
+}
+
+/**
+ * @brief Checked if a mutex has been acquired.
+ * @param[in] mutex mutex to check.
+ * @see metal_mutex_try_acquire, metal_mutex_acquire
+ */
+static inline int metal_mutex_is_acquired(metal_mutex_t *mutex)
+{
+ return __metal_mutex_is_acquired(mutex);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_MUTEX__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/atomic.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/atomic.h
new file mode 100644
index 0000000..c5e25cd
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/atomic.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file arm/atomic.h
+ * @brief ARM specific atomic primitives for libmetal.
+ */
+
+#ifndef __METAL_ARM_ATOMIC__H__
+#define __METAL_ARM_ATOMIC__H__
+
+#endif /* __METAL_ARM_ATOMIC__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/cpu.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/cpu.h
new file mode 100644
index 0000000..3e4f848
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/processor/arm/cpu.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file cpu.h
+ * @brief CPU specific primatives
+ */
+
+#ifndef __METAL_ARM_CPU__H__
+#define __METAL_ARM_CPU__H__
+
+#define metal_cpu_yield()
+
+#endif /* __METAL_ARM_CPU__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/shmem.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/shmem.h
new file mode 100644
index 0000000..19f282c
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/shmem.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file shmem.h
+ * @brief Shared memory primitives for libmetal.
+ */
+
+#ifndef __METAL_SHMEM__H__
+#define __METAL_SHMEM__H__
+
+#include <metal/io.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup shmem Shared Memory Interfaces
+ * @{ */
+
+/** Generic shared memory data structure. */
+struct metal_generic_shmem {
+ const char *name;
+ struct metal_io_region io;
+ struct metal_list node;
+};
+
+/**
+ * @brief Open a libmetal shared memory segment.
+ *
+ * Open a shared memory segment.
+ *
+ * @param[in] name Name of segment to open.
+ * @param[in] size Size of segment.
+ * @param[out] io I/O region handle, if successful.
+ * @return 0 on success, or -errno on failure.
+ *
+ * @see metal_shmem_create
+ */
+extern int metal_shmem_open(const char *name, size_t size,
+ struct metal_io_region **io);
+
+/**
+ * @brief Statically register a generic shared memory region.
+ *
+ * Shared memory regions may be statically registered at application
+ * initialization, or may be dynamically opened. This interface is used for
+ * static registration of regions. Subsequent calls to metal_shmem_open() look
+ * up in this list of pre-registered regions.
+ *
+ * @param[in] shmem Generic shmem structure.
+ * @return 0 on success, or -errno on failure.
+ */
+extern int metal_shmem_register_generic(struct metal_generic_shmem *shmem);
+
+#ifdef METAL_INTERNAL
+
+/**
+ * @brief Open a statically registered shmem segment.
+ *
+ * This interface is meant for internal libmetal use within system specific
+ * shmem implementations.
+ *
+ * @param[in] name Name of segment to open.
+ * @param[in] size Size of segment.
+ * @param[out] io I/O region handle, if successful.
+ * @return 0 on success, or -errno on failure.
+ */
+int metal_shmem_open_generic(const char *name, size_t size,
+ struct metal_io_region **result);
+
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_SHMEM__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sleep.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sleep.h
new file mode 100644
index 0000000..0dad401
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sleep.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file sleep.h
+ * @brief Sleep primitives for libmetal.
+ */
+
+#ifndef __METAL_SLEEP__H__
+#define __METAL_SLEEP__H__
+
+#include <metal/system/generic/sleep.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup sleep Sleep Interfaces
+ * @{ */
+
+/**
+ * @brief delay in microseconds
+ * delay the next execution in the calling thread
+ * fo usec microseconds.
+ *
+ * @param[in] usec microsecond intervals
+ * @return 0 on success, non-zero for failures
+ */
+static inline int metal_sleep_usec(unsigned int usec)
+{
+ return __metal_sleep_usec(usec);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_SLEEP__H__ */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/spinlock.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/spinlock.h
new file mode 100644
index 0000000..f6a711e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/spinlock.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file spinlock.h
+ * @brief Spinlock primitives for libmetal.
+ */
+
+#ifndef __METAL_SPINLOCK__H__
+#define __METAL_SPINLOCK__H__
+
+#include <metal/atomic.h>
+#include <metal/cpu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup spinlock Spinlock Interfaces
+ * @{ */
+struct metal_spinlock {
+ union{
+ atomic_int v;
+ atomic_flag w;
+ };
+};
+
+/** Static metal spinlock initialization. */
+#define METAL_SPINLOCK_INIT {ATOMIC_VAR_INIT(0)}
+
+/**
+ * @brief Initialize a libmetal spinlock.
+ * @param[in] slock Spinlock to initialize.
+ */
+static inline void metal_spinlock_init(struct metal_spinlock *slock)
+{
+ atomic_store(&slock->v, 0);
+}
+
+/**
+ * @brief Acquire a spinlock.
+ * @param[in] slock Spinlock to acquire.
+ * @see metal_spinlock_release
+ */
+static inline void metal_spinlock_acquire(struct metal_spinlock *slock)
+{
+ while (atomic_flag_test_and_set(&slock->w)) {
+ metal_cpu_yield();
+ }
+}
+
+/**
+ * @brief Release a previously acquired spinlock.
+ * @param[in] slock Spinlock to release.
+ * @see metal_spinlock_acquire
+ */
+static inline void metal_spinlock_release(struct metal_spinlock *slock)
+{
+ atomic_flag_clear(&slock->w);
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_SPINLOCK__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sys.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sys.h
new file mode 100644
index 0000000..12f7f69
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/sys.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file sys.h
+ * @brief System primitives for libmetal.
+ * @brief Top level include internal to libmetal library code.
+ */
+
+#ifndef __METAL_SYS__H__
+#define __METAL_SYS__H__
+
+#include <stdlib.h>
+
+#include <metal/log.h>
+#include <metal/list.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup system Top Level Interfaces
+ * @{ */
+
+/** Physical address type. */
+typedef unsigned long metal_phys_addr_t;
+
+/** Interrupt request number. */
+typedef int metal_irq_t;
+
+/** Bad offset into shared memory or I/O region. */
+#define METAL_BAD_OFFSET ((unsigned long)-1)
+
+/** Bad physical address value. */
+#define METAL_BAD_PHYS ((metal_phys_addr_t)-1)
+
+/** Bad virtual address value. */
+#define METAL_BAD_VA ((void *)-1)
+
+/** Bad IRQ. */
+#define METAL_BAD_IRQ ((metal_irq_t)-1)
+
+/**
+ * Initialization configuration for libmetal.
+ */
+struct metal_init_params {
+
+ /** log message handler (defaults to stderr). */
+ metal_log_handler log_handler;
+
+ /** default log message level (defaults to emergency). */
+ enum metal_log_level log_level;
+};
+
+/**
+ * System independent runtime state for libmetal. This is part of a system
+ * specific singleton data structure (@see _metal).
+ */
+struct metal_common_state {
+ /** Current log level. */
+ enum metal_log_level log_level;
+
+ /** Current log handler (null for none). */
+ metal_log_handler log_handler;
+
+ /** List of registered buses. */
+ struct metal_list bus_list;
+
+ /** Generic statically defined shared memory segments. */
+ struct metal_list generic_shmem_list;
+
+ /** Generic statically defined devices. */
+ struct metal_list generic_device_list;
+};
+
+struct metal_state;
+
+#include <metal/system/generic/sys.h>
+
+#ifndef METAL_INIT_DEFAULTS
+#define METAL_INIT_DEFAULTS \
+{ \
+ .log_handler = metal_default_log_handler, \
+ .log_level = METAL_LOG_INFO, \
+}
+#endif
+
+/** System specific runtime data. */
+extern struct metal_state _metal;
+
+/**
+ * @brief Initialize libmetal.
+ *
+ * Initialize the libmetal library.
+ *
+ * @param[in] params Initialization params (@see metal_init_params).
+ *
+ * @return 0 on success, or -errno on failure.
+ *
+ * @see metal_finish
+ */
+extern int metal_init(const struct metal_init_params *params);
+
+/**
+ * @brief Shutdown libmetal.
+ *
+ * Shutdown the libmetal library, and release all reserved resources.
+ *
+ * @see metal_init
+ */
+extern void metal_finish(void);
+
+#ifdef METAL_INTERNAL
+
+/**
+ * @brief libmetal system initialization.
+ *
+ * This function initializes libmetal on Linux or Generic platforms. This
+ * involves obtaining necessary pieces of system information (sysfs mount path,
+ * page size, etc.).
+ *
+ * @param[in] params Initialization parameters (@see metal_init_params).
+ * @return 0 on success, or -errno on failure.
+ */
+extern int metal_sys_init(const struct metal_init_params *params);
+
+/**
+ * @brief libmetal system shutdown.
+ *
+ * This function shuts down and releases resources held by libmetal Linux or
+ * Generic platform layers.
+ *
+ * @see metal_sys_init
+ */
+extern void metal_sys_finish(void);
+
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_SYS__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h
new file mode 100644
index 0000000..5338dd7
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/alloc.c
+ * @brief generic libmetal memory allocattion definitions.
+ */
+
+#ifndef __METAL_ALLOC__H__
+#error "Include metal/alloc.h instead of metal/generic/alloc.h"
+#endif
+
+#ifndef __METAL_GENERIC_ALLOC__H__
+#define __METAL_GENERIC_ALLOC__H__
+
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void *metal_allocate_memory(unsigned int size)
+{
+ return (malloc(size));
+}
+
+static inline void metal_free_memory(void *ptr)
+{
+ free(ptr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_ALLOC__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/assert.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/assert.h
new file mode 100644
index 0000000..cd70b00
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/assert.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file assert.h
+ * @brief Generic assertion support.
+ */
+
+#ifndef __METAL_ASSERT__H__
+#error "Include metal/assert.h instead of metal/generic/assert.h"
+#endif
+
+#ifndef __METAL_GENERIC_ASSERT__H__
+#define __METAL_GENERIC_ASSERT__H__
+
+#include <assert.h>
+
+/**
+ * @brief Assertion macro for bare-metal applications.
+ * @param cond Condition to evaluate.
+ */
+#define metal_sys_assert(cond) assert(cond)
+
+#endif /* __METAL_GENERIC_ASSERT__H__ */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cache.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cache.h
new file mode 100644
index 0000000..992750f
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cache.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018, Linaro Limited. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/cache.h
+ * @brief generic cache operation primitives for libmetal.
+ */
+
+#ifndef __METAL_CACHE__H__
+#error "Include metal/cache.h instead of metal/generic/cache.h"
+#endif
+
+#ifndef __METAL_GENERIC_CACHE__H__
+#define __METAL_GENERIC_CACHE__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void metal_machine_cache_flush(void *addr, unsigned int len);
+extern void metal_machine_cache_invalidate(void *addr, unsigned int len);
+
+static inline void __metal_cache_flush(void *addr, unsigned int len)
+{
+ metal_machine_cache_flush(addr, len);
+}
+
+static inline void __metal_cache_invalidate(void *addr, unsigned int len)
+{
+ metal_machine_cache_invalidate(addr, len);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_CACHE__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/condition.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/condition.h
new file mode 100644
index 0000000..c4ce0e2
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/condition.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/condition.h
+ * @brief Generic condition variable primitives for libmetal.
+ */
+
+#ifndef __METAL_CONDITION__H__
+#error "Include metal/condition.h instead of metal/generic/condition.h"
+#endif
+
+#ifndef __METAL_GENERIC_CONDITION__H__
+#define __METAL_GENERIC_CONDITION__H__
+
+#if defined (__CC_ARM)
+#include <stdio.h>
+#endif
+#include <metal/atomic.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <limits.h>
+#include <metal/errno.h>
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct metal_condition {
+ metal_mutex_t *m; /**< mutex.
+ The condition variable is attached to
+ this mutex when it is waiting.
+ It is also used to check correctness
+ in case there are multiple waiters. */
+
+ atomic_int v; /**< condition variable value. */
+};
+
+/** Static metal condition variable initialization. */
+#define METAL_CONDITION_INIT { NULL, ATOMIC_VAR_INIT(0) }
+
+static inline void metal_condition_init(struct metal_condition *cv)
+{
+ cv->m = NULL;
+ atomic_init(&cv->v, 0);
+}
+
+static inline int metal_condition_signal(struct metal_condition *cv)
+{
+ if (!cv)
+ return -EINVAL;
+
+ /** wake up waiters if there are any. */
+ atomic_fetch_add(&cv->v, 1);
+ return 0;
+}
+
+static inline int metal_condition_broadcast(struct metal_condition *cv)
+{
+ return metal_condition_signal(cv);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_CONDITION__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cortexm/sys.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cortexm/sys.h
new file mode 100644
index 0000000..35597d6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/cortexm/sys.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Xilinx nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * @file generic/mp1_m4/sys.h
+ * @brief generic mp1_m4 system primitives for libmetal.
+ */
+
+#ifndef __METAL_GENERIC_SYS__H__
+#error "Include metal/sys.h instead of metal/generic/cortexm/sys.h"
+#endif
+
+#ifndef __METAL_GENERIC_MP1_M4_SYS__H__
+#define __METAL_GENERIC_MP1_M4_SYS__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(MAX_IRQS)
+#define MAX_IRQS 8 /**< maximum number of irqs */
+#endif
+
+static inline void sys_irq_enable(unsigned int vector)
+{
+ (void)vector;
+}
+
+static inline void sys_irq_disable(unsigned int vector)
+{
+ (void)vector;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_MP1_M4_SYS__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/io.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/io.h
new file mode 100644
index 0000000..b154ade
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/io.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/io.h
+ * @brief Generic specific io definitions.
+ */
+
+#ifndef __METAL_IO__H__
+#error "Include metal/io.h instead of metal/generic/io.h"
+#endif
+
+#ifndef __METAL_GENERIC_IO__H__
+#define __METAL_GENERIC_IO__H__
+
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef METAL_INTERNAL
+
+/**
+ * @brief memory mapping for an I/O region
+ */
+void metal_sys_io_mem_map(struct metal_io_region *io);
+
+/**
+ * @brief memory mapping
+ */
+void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
+ size_t size, unsigned int flags);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_IO__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/irq.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/irq.h
new file mode 100644
index 0000000..e201da8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/irq.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/irq.c
+ * @brief Generic libmetal irq definitions.
+ */
+
+#ifndef __METAL_IRQ__H__
+#error "Include metal/irq.h instead of metal/generic/irq.h"
+#endif
+
+#ifndef __METAL_GENERIC_IRQ__H__
+#define __METAL_GENERIC_IRQ__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief default interrupt handler
+ * @param[in] vector interrupt vector
+ */
+void metal_irq_isr(unsigned int vector);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_IRQ__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/log.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/log.h
new file mode 100644
index 0000000..9275040
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/log.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018, Linaro Limited. and Contributors. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Linaro nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * @file generic/log.h
+ * @brief Generic libmetal log handler definition.
+ */
+
+#ifndef __METAL_METAL_LOG__H__
+#error "Include metal/log.h instead of metal/generic/log.h"
+#endif
+
+#ifndef __METAL_GENERIC_LOG__H__
+#define __METAL_GENERIC_LOG__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_LOG__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/mutex.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/mutex.h
new file mode 100644
index 0000000..885cdd4
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/mutex.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/mutex.h
+ * @brief Generic mutex primitives for libmetal.
+ */
+
+#ifndef __METAL_MUTEX__H__
+#error "Include metal/mutex.h instead of metal/generic/mutex.h"
+#endif
+
+#ifndef __METAL_GENERIC_MUTEX__H__
+#define __METAL_GENERIC_MUTEX__H__
+
+#include <metal/atomic.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ union{
+ atomic_int v;
+ atomic_flag w;
+ };
+} metal_mutex_t;
+
+/*
+ * METAL_MUTEX_INIT - used for initializing an mutex elmenet in a static struct
+ * or global
+ */
+#define METAL_MUTEX_INIT(m) { ATOMIC_VAR_INIT(0) }
+/*
+ * METAL_MUTEX_DEFINE - used for defining and initializing a global or
+ * static singleton mutex
+ */
+#define METAL_MUTEX_DEFINE(m) metal_mutex_t m = METAL_MUTEX_INIT(m)
+
+static inline void __metal_mutex_init(metal_mutex_t *mutex)
+{
+ atomic_store(&mutex->v, 0);
+}
+
+static inline void __metal_mutex_deinit(metal_mutex_t *mutex)
+{
+ (void)mutex;
+}
+
+static inline int __metal_mutex_try_acquire(metal_mutex_t *mutex)
+{
+ return 1 - atomic_flag_test_and_set(&mutex->w);
+}
+
+static inline void __metal_mutex_acquire(metal_mutex_t *mutex)
+{
+ while (atomic_flag_test_and_set(&mutex->w)) {
+ ;
+ }
+}
+
+static inline void __metal_mutex_release(metal_mutex_t *mutex)
+{
+ atomic_flag_clear(&mutex->w);
+}
+
+static inline int __metal_mutex_is_acquired(metal_mutex_t *mutex)
+{
+ return atomic_load(&mutex->v);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_MUTEX__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sleep.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sleep.h
new file mode 100644
index 0000000..20ae778
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sleep.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018, Linaro Limited. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/sleep.h
+ * @brief Generic sleep primitives for libmetal.
+ */
+
+#ifndef __METAL_SLEEP__H__
+#error "Include metal/sleep.h instead of metal/generic/sleep.h"
+#endif
+
+#ifndef __METAL_GENERIC_SLEEP__H__
+#define __METAL_GENERIC_SLEEP__H__
+
+#include <metal/utilities.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline int __metal_sleep_usec(unsigned int usec)
+{
+ metal_unused(usec);
+ /* Fix me */
+ return 0;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_SLEEP__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sys.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sys.h
new file mode 100644
index 0000000..707872d
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/system/generic/sys.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/sys.h
+ * @brief Generic system primitives for libmetal.
+ */
+
+#ifndef __METAL_SYS__H__
+#error "Include metal/sys.h instead of metal/generic/sys.h"
+#endif
+
+#ifndef __METAL_GENERIC_SYS__H__
+#define __METAL_GENERIC_SYS__H__
+
+#include <metal/errno.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+
+#include "./cortexm/sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef METAL_MAX_DEVICE_REGIONS
+#define METAL_MAX_DEVICE_REGIONS 1
+#endif
+
+/** Structure of generic libmetal runtime state. */
+struct metal_state {
+
+ /** Common (system independent) data. */
+ struct metal_common_state common;
+};
+
+#ifdef METAL_INTERNAL
+
+/**
+ * @brief restore interrupts to state before disable_global_interrupt()
+ */
+void sys_irq_restore_enable(unsigned int flags);
+
+/**
+ * @brief disable all interrupts
+ */
+unsigned int sys_irq_save_disable(void);
+
+#endif /* METAL_INTERNAL */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_GENERIC_SYS__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/time.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/time.h
new file mode 100644
index 0000000..b05e679
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/time.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file time.h
+ * @brief Time primitives for libmetal.
+ */
+
+#ifndef __METAL_TIME__H__
+#define __METAL_TIME__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup time TIME Interfaces
+ * @{ */
+
+#include <stdint.h>
+#include <metal/sys.h>
+
+/**
+ * @brief get timestamp
+ * This function returns the timestampe as unsigned long long
+ * value.
+ *
+ * @return timestamp
+ */
+unsigned long long metal_get_timestamp(void);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_TIME__H__ */
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/utilities.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/utilities.h
new file mode 100644
index 0000000..95a6670
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/utilities.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file utilities.h
+ * @brief Utility routines for libmetal.
+ */
+
+#ifndef __METAL_UTILITIES__H__
+#define __METAL_UTILITIES__H__
+
+#include <stdint.h>
+#include <metal/assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup utilities Simple Utilities
+ * @{ */
+
+/** Marker for unused function arguments/variables. */
+#define metal_unused(x) do { (x) = (x); } while (0)
+
+/** Figure out number of elements in an array. */
+#define metal_dim(x) (sizeof(x) / sizeof(x[0]))
+
+/** Minimum of two numbers (warning: multiple evaluation!). */
+#define metal_min(x, y) ((x) < (y) ? (x) : (y))
+
+/** Maximum of two numbers (warning: multiple evaluation!). */
+#define metal_max(x, y) ((x) > (y) ? (x) : (y))
+
+/** Sign of a number [-1, 0, or 1] (warning: multiple evaluation!). */
+#define metal_sign(x) ((x) < 0 ? -1 : ((x) > 0 ? 1 : 0))
+
+/** Align 'size' down to a multiple of 'align' (must be a power of two). */
+#define metal_align_down(size, align) \
+ ((size) & ~((align) - 1))
+
+/** Align 'size' up to a multiple of 'align' (must be a power of two). */
+#define metal_align_up(size, align) \
+ metal_align_down((size) + (align) - 1, align)
+
+/** Divide (and round down). */
+#define metal_div_round_down(num, den) \
+ ((num) / (den))
+
+/** Divide (and round up). */
+#define metal_div_round_up(num, den) \
+ metal_div_round_down((num) + (den) - 1, (den))
+
+/** Align 'ptr' down to a multiple of 'align' (must be a power of two). */
+#define metal_ptr_align_down(ptr, align) \
+ (void *)(metal_align_down((uintptr_t)(ptr), (uintptr_t)(align)))
+
+/** Align 'ptr' up to a multiple of 'align' (must be a power of two). */
+#define metal_ptr_align_up(ptr, align) \
+ (void *)(metal_align_up((uintptr_t)(ptr), (uintptr_t)(align)))
+
+/** Compute offset of a field within a structure. */
+#define metal_offset_of(structure, member) \
+ ((uintptr_t) &(((structure *) 0)->member))
+
+/** Compute pointer to a structure given a pointer to one of its fields. */
+#define metal_container_of(ptr, structure, member) \
+ (void *)((uintptr_t)(ptr) - metal_offset_of(structure, member))
+
+#define METAL_BITS_PER_ULONG (8 * sizeof(unsigned long))
+
+#define metal_bit(bit) (1UL << (bit))
+
+#define metal_bitmap_longs(x) metal_div_round_up((x), METAL_BITS_PER_ULONG)
+
+static inline void metal_bitmap_set_bit(unsigned long *bitmap, int bit)
+{
+ bitmap[bit / METAL_BITS_PER_ULONG] |=
+ metal_bit(bit & (METAL_BITS_PER_ULONG - 1));
+}
+
+static inline int metal_bitmap_is_bit_set(unsigned long *bitmap, int bit)
+{
+ return bitmap[bit / METAL_BITS_PER_ULONG] &
+ metal_bit(bit & (METAL_BITS_PER_ULONG - 1));
+}
+
+static inline void metal_bitmap_clear_bit(unsigned long *bitmap, int bit)
+{
+ bitmap[bit / METAL_BITS_PER_ULONG] &=
+ ~metal_bit(bit & (METAL_BITS_PER_ULONG - 1));
+}
+
+static inline int metal_bitmap_is_bit_clear(unsigned long *bitmap, int bit)
+{
+ return !metal_bitmap_is_bit_set(bitmap, bit);
+}
+
+static inline unsigned int
+metal_bitmap_next_set_bit(unsigned long *bitmap, unsigned int start,
+ unsigned int max)
+{
+ unsigned int bit;
+ for (bit = start;
+ bit < max && !metal_bitmap_is_bit_set(bitmap, bit);
+ bit ++)
+ ;
+ return bit;
+}
+
+#define metal_bitmap_for_each_set_bit(bitmap, bit, max) \
+ for ((bit) = metal_bitmap_next_set_bit((bitmap), 0, (max)); \
+ (bit) < (max); \
+ (bit) = metal_bitmap_next_set_bit((bitmap), (bit), (max)))
+
+static inline unsigned int
+metal_bitmap_next_clear_bit(unsigned long *bitmap, unsigned int start,
+ unsigned int max)
+{
+ unsigned int bit;
+ for (bit = start;
+ bit < max && !metal_bitmap_is_bit_clear(bitmap, bit);
+ bit ++)
+ ;
+ return bit;
+}
+
+#define metal_bitmap_for_each_clear_bit(bitmap, bit, max) \
+ for ((bit) = metal_bitmap_next_clear_bit((bitmap), 0, (max)); \
+ (bit) < (max); \
+ (bit) = metal_bitmap_next_clear_bit((bitmap), (bit), (max)))
+
+static inline unsigned long metal_log2(unsigned long in)
+{
+ unsigned long result;
+
+ metal_assert((in & (in - 1)) == 0);
+
+ for (result = 0; (1UL << result) < in; result ++)
+ ;
+ return result;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_UTILITIES__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/version.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/version.h
new file mode 100644
index 0000000..96666b3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/include/metal/version.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file version.h
+ * @brief Library version information for libmetal.
+ */
+
+#ifndef __METAL_VERSION__H__
+#define __METAL_VERSION__H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup versions Library Version Interfaces
+ * @{ */
+
+/**
+ * @brief Library major version number.
+ *
+ * Return the major version number of the library linked into the application.
+ * This is required to match the value of METAL_VER_MAJOR, which is the major
+ * version of the library that the application was compiled against.
+ *
+ * @return Library major version number.
+ * @see METAL_VER_MAJOR
+ */
+extern int metal_ver_major(void);
+
+/**
+ * @brief Library minor version number.
+ *
+ * Return the minor version number of the library linked into the application.
+ * This could differ from the value of METAL_VER_MINOR, which is the minor
+ * version of the library that the application was compiled against.
+ *
+ * @return Library minor version number.
+ * @see METAL_VER_MINOR
+ */
+extern int metal_ver_minor(void);
+
+/**
+ * @brief Library patch level.
+ *
+ * Return the patch level of the library linked into the application. This
+ * could differ from the value of METAL_VER_PATCH, which is the patch level of
+ * the library that the application was compiled against.
+ *
+ * @return Library patch level.
+ * @see METAL_VER_PATCH
+ */
+extern int metal_ver_patch(void);
+
+/**
+ * @brief Library version string.
+ *
+ * Return the version string of the library linked into the application. This
+ * could differ from the value of METAL_VER, which is the version string of
+ * the library that the application was compiled against.
+ *
+ * @return Library version string.
+ * @see METAL_VER
+ */
+extern const char *metal_ver(void);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __METAL_VERSION__H__ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/init.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/init.c
new file mode 100644
index 0000000..33e5124
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/init.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include <metal/sys.h>
+
+int metal_init(const struct metal_init_params *params)
+{
+ int error = 0;
+
+ memset(&_metal, 0, sizeof(_metal));
+
+ _metal.common.log_handler = params->log_handler;
+ _metal.common.log_level = params->log_level;
+
+ metal_list_init(&_metal.common.bus_list);
+ metal_list_init(&_metal.common.generic_shmem_list);
+ metal_list_init(&_metal.common.generic_device_list);
+
+ error = metal_sys_init(params);
+ if (error)
+ return error;
+
+ return error;
+}
+
+void metal_finish(void)
+{
+ metal_sys_finish();
+ memset(&_metal, 0, sizeof(_metal));
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/io.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/io.c
new file mode 100644
index 0000000..eb5375b
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/io.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <metal/errno.h>
+#include <limits.h>
+#include <metal/io.h>
+#include <metal/sys.h>
+
+void metal_io_init(struct metal_io_region *io, void *virt,
+ const metal_phys_addr_t *physmap, size_t size,
+ unsigned page_shift, unsigned int mem_flags,
+ const struct metal_io_ops *ops)
+{
+ const struct metal_io_ops nops = {NULL, NULL, NULL, NULL, NULL, NULL};
+
+ io->virt = virt;
+ io->physmap = physmap;
+ io->size = size;
+ io->page_shift = page_shift;
+ if (page_shift >= sizeof(io->page_mask) * CHAR_BIT)
+ /* avoid overflow */
+ io->page_mask = -1UL;
+ else
+ io->page_mask = (1UL << page_shift) - 1UL;
+ io->mem_flags = mem_flags;
+ io->ops = ops ? *ops : nops;
+ metal_sys_io_mem_map(io);
+}
+
+int metal_io_block_read(struct metal_io_region *io, unsigned long offset,
+ void *restrict dst, int len)
+{
+ unsigned char *ptr = metal_io_virt(io, offset);
+ unsigned char *dest = dst;
+ int retlen;
+
+ if (offset > io->size)
+ return -ERANGE;
+ if ((offset + len) > io->size)
+ len = io->size - offset;
+ retlen = len;
+ if (io->ops.block_read) {
+ retlen = (*io->ops.block_read)(
+ io, offset, dst, memory_order_seq_cst, len);
+ } else {
+ atomic_thread_fence(memory_order_seq_cst);
+ while ( len && (
+ ((uintptr_t)dest % sizeof(int)) ||
+ ((uintptr_t)ptr % sizeof(int)))) {
+ *(unsigned char *)dest =
+ *(const unsigned char *)ptr;
+ dest++;
+ ptr++;
+ len--;
+ }
+ for (; len >= (int)sizeof(int); dest += sizeof(int),
+ ptr += sizeof(int),
+ len -= sizeof(int))
+ *(unsigned int *)dest = *(const unsigned int *)ptr;
+ for (; len != 0; dest++, ptr++, len--)
+ *(unsigned char *)dest =
+ *(const unsigned char *)ptr;
+ }
+ return retlen;
+}
+
+int metal_io_block_write(struct metal_io_region *io, unsigned long offset,
+ const void *restrict src, int len)
+{
+ unsigned char *ptr = metal_io_virt(io, offset);
+ const unsigned char *source = src;
+ int retlen;
+
+ if (offset > io->size)
+ return -ERANGE;
+ if ((offset + len) > io->size)
+ len = io->size - offset;
+ retlen = len;
+ if (io->ops.block_write) {
+ retlen = (*io->ops.block_write)(
+ io, offset, src, memory_order_seq_cst, len);
+ } else {
+ while ( len && (
+ ((uintptr_t)ptr % sizeof(int)) ||
+ ((uintptr_t)source % sizeof(int)))) {
+ *(unsigned char *)ptr =
+ *(const unsigned char *)source;
+ ptr++;
+ source++;
+ len--;
+ }
+ for (; len >= (int)sizeof(int); ptr += sizeof(int),
+ source += sizeof(int),
+ len -= sizeof(int))
+ *(unsigned int *)ptr = *(const unsigned int *)source;
+ for (; len != 0; ptr++, source++, len--)
+ *(unsigned char *)ptr =
+ *(const unsigned char *)source;
+ atomic_thread_fence(memory_order_seq_cst);
+ }
+ return retlen;
+}
+
+int metal_io_block_set(struct metal_io_region *io, unsigned long offset,
+ unsigned char value, int len)
+{
+ unsigned char *ptr = metal_io_virt(io, offset);
+ int retlen = len;
+
+ if (offset > io->size)
+ return -ERANGE;
+ if ((offset + len) > io->size)
+ len = io->size - offset;
+ retlen = len;
+ if (io->ops.block_set) {
+ (*io->ops.block_set)(
+ io, offset, value, memory_order_seq_cst, len);
+ } else {
+ unsigned int cint = value;
+ unsigned int i;
+
+ for (i = 1; i < sizeof(int); i++)
+ cint |= ((unsigned int)value << (8 * i));
+
+ for (; len && ((uintptr_t)ptr % sizeof(int)); ptr++, len--)
+ *(unsigned char *)ptr = (unsigned char) value;
+ for (; len >= (int)sizeof(int); ptr += sizeof(int),
+ len -= sizeof(int))
+ *(unsigned int *)ptr = cint;
+ for (; len != 0; ptr++, len--)
+ *(unsigned char *)ptr = (unsigned char) value;
+ atomic_thread_fence(memory_order_seq_cst);
+ }
+ return retlen;
+}
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/log.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/log.c
new file mode 100644
index 0000000..1549ff9
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/log.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <stdio.h>
+
+#include <metal/log.h>
+#include <metal/sys.h>
+
+void metal_default_log_handler(enum metal_log_level level,
+ const char *format, ...)
+{
+#ifdef DEFAULT_LOGGER_ON
+ char msg[1024];
+ va_list args;
+ static const char *level_strs[] = {
+ "metal: emergency: ",
+ "metal: alert: ",
+ "metal: critical: ",
+ "metal: error: ",
+ "metal: warning: ",
+ "metal: notice: ",
+ "metal: info: ",
+ "metal: debug: ",
+ };
+
+ va_start(args, format);
+ vsnprintf(msg, sizeof(msg), format, args);
+ va_end(args);
+
+ if (level <= METAL_LOG_EMERGENCY || level > METAL_LOG_DEBUG)
+ level = METAL_LOG_EMERGENCY;
+
+ fprintf(stderr, "%s%s", level_strs[level], msg);
+#else
+ (void)level;
+ (void)format;
+#endif
+}
+
+void metal_set_log_handler(metal_log_handler handler)
+{
+ _metal.common.log_handler = handler;
+}
+
+metal_log_handler metal_get_log_handler(void)
+{
+ return _metal.common.log_handler;
+}
+
+void metal_set_log_level(enum metal_log_level level)
+{
+ _metal.common.log_level = level;
+}
+
+enum metal_log_level metal_get_log_level(void)
+{
+ return _metal.common.log_level;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/shmem.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/shmem.c
new file mode 100644
index 0000000..c364785
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/shmem.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/shmem.c
+ * @brief Generic libmetal shared memory handling.
+ */
+
+#include <metal/errno.h>
+#include <metal/assert.h>
+#include <metal/shmem.h>
+#include <metal/sys.h>
+#include <metal/utilities.h>
+
+int metal_shmem_register_generic(struct metal_generic_shmem *shmem)
+{
+ /* Make sure that we can be found. */
+ metal_assert(shmem->name && strlen(shmem->name) != 0);
+
+ /* Statically registered shmem regions cannot have a destructor. */
+ metal_assert(!shmem->io.ops.close);
+
+ metal_list_add_tail(&_metal.common.generic_shmem_list,
+ &shmem->node);
+ return 0;
+}
+
+int metal_shmem_open_generic(const char *name, size_t size,
+ struct metal_io_region **result)
+{
+ struct metal_generic_shmem *shmem;
+ struct metal_list *node;
+
+ metal_list_for_each(&_metal.common.generic_shmem_list, node) {
+ shmem = metal_container_of(node, struct metal_generic_shmem, node);
+ if (strcmp(shmem->name, name) != 0)
+ continue;
+ if (size > metal_io_region_size(&shmem->io))
+ continue;
+ *result = &shmem->io;
+ return 0;
+ }
+
+ return -ENOENT;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/condition.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/condition.c
new file mode 100644
index 0000000..d58cc16
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/condition.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/condition.c
+ * @brief Generic libmetal condition variable handling.
+ */
+
+#include <metal/condition.h>
+#include <metal/irq.h>
+
+extern void metal_generic_default_poll(void);
+
+int metal_condition_wait(struct metal_condition *cv,
+ metal_mutex_t *m)
+{
+ metal_mutex_t *tmpm = 0;
+ int v;
+ unsigned int flags;
+
+ /* Check if the mutex has been acquired */
+ if (!cv || !m || !metal_mutex_is_acquired(m))
+ return -EINVAL;
+
+ if (!atomic_compare_exchange_strong(&cv->m->v, &tmpm->v, m->v)) {
+ if (m != tmpm)
+ return -EINVAL;
+ }
+
+ v = atomic_load(&cv->v);
+
+ /* Release the mutex first. */
+ metal_mutex_release(m);
+ do {
+ flags = metal_irq_save_disable();
+ if (atomic_load(&cv->v) != v) {
+ metal_irq_restore_enable(flags);
+ break;
+ }
+ metal_generic_default_poll();
+ metal_irq_restore_enable(flags);
+ } while(1);
+ /* Acquire the mutex again. */
+ metal_mutex_acquire(m);
+ return 0;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c
new file mode 100644
index 0000000..3bbd74e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/cortexm/sys.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Xilinx nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * @file generic/sys.c
+ * @brief machine specific system primitives implementation.
+ */
+
+
+#include "metal/io.h"
+#include "metal/sys.h"
+
+void sys_irq_restore_enable(unsigned int flags)
+{
+}
+
+unsigned int sys_irq_save_disable(void)
+{
+ return 0;
+}
+
+void metal_machine_cache_flush(void *addr, unsigned int len)
+{
+ (void)addr;
+ (void)len;
+}
+
+void metal_machine_cache_invalidate(void *addr, unsigned int len)
+{
+ (void)addr;
+ (void)len;
+}
+
+/**
+ * @brief poll function until some event happens
+ */
+void __attribute__((weak)) metal_generic_default_poll(void)
+{
+}
+
+void *metal_machine_io_mem_map(void *va, metal_phys_addr_t pa,
+ size_t size, unsigned int flags)
+{
+ (void)va;
+ (void)pa;
+ (void)size;
+ (void)flags;
+
+ return va;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_device.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_device.c
new file mode 100644
index 0000000..f339bba
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_device.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/device.c
+ * @brief Generic libmetal device operations.
+ */
+
+#include <metal/device.h>
+#include <metal/io.h>
+#include <metal/sys.h>
+#include <metal/utilities.h>
+
+int metal_generic_dev_sys_open(struct metal_device *dev)
+{
+ struct metal_io_region *io;
+ unsigned i;
+
+ /* map I/O memory regions */
+ for (i = 0; i < dev->num_regions; i++) {
+ io = &dev->regions[i];
+ if (!io->size)
+ break;
+ metal_sys_io_mem_map(io);
+ }
+
+ return 0;
+}
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_init.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_init.c
new file mode 100644
index 0000000..54df335
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_init.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/init.c
+ * @brief Generic libmetal initialization.
+ */
+
+#include <metal/sys.h>
+#include <metal/utilities.h>
+#include <metal/device.h>
+
+struct metal_state _metal;
+
+int metal_sys_init(const struct metal_init_params *params)
+{
+ metal_unused(params);
+ metal_bus_register(&metal_generic_bus);
+ return 0;
+}
+
+void metal_sys_finish(void)
+{
+ metal_bus_unregister(&metal_generic_bus);
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_io.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_io.c
new file mode 100644
index 0000000..e680c79
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_io.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/io.c
+ * @brief Generic libmetal io operations
+ */
+
+#include <metal/io.h>
+
+void metal_sys_io_mem_map(struct metal_io_region *io)
+{
+ unsigned long p;
+ size_t psize;
+ size_t *va;
+
+ va = (size_t *)io->virt;
+ psize = io->size;
+ if (psize) {
+ if (psize >> io->page_shift)
+ psize = (size_t)1 << io->page_shift;
+ for (p = 0; p <= (io->size >> io->page_shift); p++) {
+ metal_machine_io_mem_map(va, io->physmap[p],
+ psize, io->mem_flags);
+ va += psize;
+ }
+ }
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_shmem.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_shmem.c
new file mode 100644
index 0000000..7fa30a8
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/generic_shmem.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/shmem.c
+ * @brief Generic libmetal shared memory handling.
+ */
+
+#include <metal/shmem.h>
+
+int metal_shmem_open(const char *name, size_t size,
+ struct metal_io_region **io)
+{
+ return metal_shmem_open_generic(name, size, io);
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/time.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/time.c
new file mode 100644
index 0000000..e52f89a
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/libmetal/lib/system/generic/time.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016, Xilinx Inc. and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * @file generic/time.c
+ * @brief Generic libmetal time handling.
+ */
+
+#include <metal/time.h>
+
+unsigned long long metal_get_timestamp(void)
+{
+ /* TODO: Implement timestamp for generic system */
+ return 0;
+}
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/compiler.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/compiler.h
new file mode 100644
index 0000000..4253efc
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/compiler.h
@@ -0,0 +1,71 @@
+#ifndef _COMPILER_H_
+#define _COMPILER_H_
+
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**************************************************************************
+ * FILE NAME
+ *
+ * compiler.h
+ *
+ * DESCRIPTION
+ *
+ * This file defines compiler-specific macros.
+ *
+ ***************************************************************************/
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* IAR ARM build tools */
+#if defined(__ICCARM__)
+
+#ifndef OPENAMP_PACKED_BEGIN
+#define OPENAMP_PACKED_BEGIN __packed
+#endif
+
+#ifndef OPENAMP_PACKED_END
+#define OPENAMP_PACKED_END
+#endif
+
+/* GNUC */
+#elif defined(__GNUC__)
+
+#ifndef OPENAMP_PACKED_BEGIN
+#define OPENAMP_PACKED_BEGIN
+#endif
+
+#ifndef OPENAMP_PACKED_END
+#define OPENAMP_PACKED_END __attribute__((__packed__))
+#endif
+
+/* ARM GCC */
+#elif defined(__CC_ARM)
+
+#ifndef OPENAMP_PACKED_BEGIN
+#define OPENAMP_PACKED_BEGIN _Pragma("pack(1U)")
+#endif
+
+#ifndef OPENAMP_PACKED_END
+#define OPENAMP_PACKED_END _Pragma("pack()")
+#endif
+
+#else
+/*
+ * There is no default definition here to avoid wrong structures packing in case
+ * of not supported compiler
+ */
+#error Please implement the structure packing macros for your compiler here!
+#endif
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* _COMPILER_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/elf_loader.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/elf_loader.h
new file mode 100644
index 0000000..acf3d29
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/elf_loader.h
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ELF_LOADER_H_
+#define ELF_LOADER_H_
+
+#include <openamp/remoteproc.h>
+#include <openamp/remoteproc_loader.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* ELF32 base types - 32-bit. */
+typedef uint32_t Elf32_Addr;
+typedef uint16_t Elf32_Half;
+typedef uint32_t Elf32_Off;
+typedef int32_t Elf32_Sword;
+typedef uint32_t Elf32_Word;
+
+/* ELF64 base types - 64-bit. */
+typedef uint64_t Elf64_Addr;
+typedef uint16_t Elf64_Half;
+typedef uint64_t Elf64_Off;
+typedef int32_t Elf64_Sword;
+typedef uint32_t Elf64_Word;
+typedef uint64_t Elf64_Xword;
+typedef int64_t Elf64_Sxword;
+
+/* Size of ELF identifier field in the ELF file header. */
+#define EI_NIDENT 16
+
+/* ELF32 file header */
+typedef struct {
+ unsigned char e_ident[EI_NIDENT];
+ Elf32_Half e_type;
+ Elf32_Half e_machine;
+ Elf32_Word e_version;
+ Elf32_Addr e_entry;
+ Elf32_Off e_phoff;
+ Elf32_Off e_shoff;
+ Elf32_Word e_flags;
+ Elf32_Half e_ehsize;
+ Elf32_Half e_phentsize;
+ Elf32_Half e_phnum;
+ Elf32_Half e_shentsize;
+ Elf32_Half e_shnum;
+ Elf32_Half e_shstrndx;
+} Elf32_Ehdr;
+
+/* ELF64 file header */
+typedef struct {
+ unsigned char e_ident[EI_NIDENT];
+ Elf64_Half e_type;
+ Elf64_Half e_machine;
+ Elf64_Word e_version;
+ Elf64_Addr e_entry;
+ Elf64_Off e_phoff;
+ Elf64_Off e_shoff;
+ Elf64_Word e_flags;
+ Elf64_Half e_ehsize;
+ Elf64_Half e_phentsize;
+ Elf64_Half e_phnum;
+ Elf64_Half e_shentsize;
+ Elf64_Half e_shnum;
+ Elf64_Half e_shstrndx;
+} Elf64_Ehdr;
+
+/* e_ident */
+#define ET_NONE 0
+#define ET_REL 1 /* Re-locatable file */
+#define ET_EXEC 2 /* Executable file */
+#define ET_DYN 3 /* Shared object file */
+#define ET_CORE 4 /* Core file */
+#define ET_LOOS 0xfe00 /* Operating system-specific */
+#define ET_HIOS 0xfeff /* Operating system-specific */
+#define ET_LOPROC 0xff00 /* remote_proc-specific */
+#define ET_HIPROC 0xffff /* remote_proc-specific */
+
+/* e_machine */
+#define EM_ARM 40 /* ARM/Thumb Architecture */
+
+/* e_version */
+#define EV_CURRENT 1 /* Current version */
+
+/* e_ident[] Identification Indexes */
+#define EI_MAG0 0 /* File identification */
+#define EI_MAG1 1 /* File identification */
+#define EI_MAG2 2 /* File identification */
+#define EI_MAG3 3 /* File identification */
+#define EI_CLASS 4 /* File class */
+#define EI_DATA 5 /* Data encoding */
+#define EI_VERSION 6 /* File version */
+#define EI_OSABI 7 /* Operating system/ABI identification */
+#define EI_ABIVERSION 8 /* ABI version */
+#define EI_PAD 9 /* Start of padding bytes */
+#define EI_NIDENT 16 /* Size of e_ident[] */
+
+/*
+ * EI_MAG0 to EI_MAG3 - A file's first 4 bytes hold amagic number, identifying
+ * the file as an ELF object file
+ */
+#define ELFMAG0 0x7f /* e_ident[EI_MAG0] */
+#define ELFMAG1 'E' /* e_ident[EI_MAG1] */
+#define ELFMAG2 'L' /* e_ident[EI_MAG2] */
+#define ELFMAG3 'F' /* e_ident[EI_MAG3] */
+#define ELFMAG "\177ELF"
+#define SELFMAG 4
+
+/*
+ * EI_CLASS - The next byte, e_ident[EI_CLASS], identifies the file's class, or
+ * capacity.
+ */
+#define ELFCLASSNONE 0 /* Invalid class */
+#define ELFCLASS32 1 /* 32-bit objects */
+#define ELFCLASS64 2 /* 64-bit objects */
+
+/*
+ * EI_DATA - Byte e_ident[EI_DATA] specifies the data encoding of the
+ * remote_proc-specific data in the object file. The following encodings are
+ * currently defined.
+ */
+#define ELFDATANONE 0 /* Invalid data encoding */
+#define ELFDATA2LSB 1 /* See Data encodings, below */
+#define ELFDATA2MSB 2 /* See Data encodings, below */
+
+/* EI_OSABI - We do not define an OS specific ABI */
+#define ELFOSABI_NONE 0
+
+/* ELF32 program header */
+typedef struct elf32_phdr{
+ Elf32_Word p_type;
+ Elf32_Off p_offset;
+ Elf32_Addr p_vaddr;
+ Elf32_Addr p_paddr;
+ Elf32_Word p_filesz;
+ Elf32_Word p_memsz;
+ Elf32_Word p_flags;
+ Elf32_Word p_align;
+} Elf32_Phdr;
+
+/* ELF64 program header */
+typedef struct elf64_phdr {
+ Elf64_Word p_type;
+ Elf64_Word p_flags;
+ Elf64_Off p_offset;
+ Elf64_Addr p_vaddr;
+ Elf64_Addr p_paddr;
+ Elf64_Xword p_filesz;
+ Elf64_Xword p_memsz;
+ Elf64_Xword p_align;
+} Elf64_Phdr;
+
+/* segment types */
+#define PT_NULL 0
+#define PT_LOAD 1
+#define PT_DYNAMIC 2
+#define PT_INTERP 3
+#define PT_NOTE 4
+#define PT_SHLIB 5
+#define PT_PHDR 6
+#define PT_TLS 7 /* Thread local storage segment */
+#define PT_LOOS 0x60000000 /* OS-specific */
+#define PT_HIOS 0x6fffffff /* OS-specific */
+#define PT_LOPROC 0x70000000
+#define PT_HIPROC 0x7fffffff
+
+/* ELF32 section header. */
+typedef struct {
+ Elf32_Word sh_name;
+ Elf32_Word sh_type;
+ Elf32_Word sh_flags;
+ Elf32_Addr sh_addr;
+ Elf32_Off sh_offset;
+ Elf32_Word sh_size;
+ Elf32_Word sh_link;
+ Elf32_Word sh_info;
+ Elf32_Word sh_addralign;
+ Elf32_Word sh_entsize;
+} Elf32_Shdr;
+
+/* ELF64 section header. */
+typedef struct {
+ Elf64_Word sh_name;
+ Elf64_Word sh_type;
+ Elf64_Xword sh_flags;
+ Elf64_Addr sh_addr;
+ Elf64_Off sh_offset;
+ Elf64_Xword sh_size;
+ Elf64_Word sh_link;
+ Elf64_Word sh_info;
+ Elf64_Xword sh_addralign;
+ Elf64_Xword sh_entsize;
+} Elf64_Shdr;
+
+/* sh_type */
+#define SHT_NULL 0
+#define SHT_PROGBITS 1
+#define SHT_SYMTAB 2
+#define SHT_STRTAB 3
+#define SHT_RELA 4
+#define SHT_HASH 5
+#define SHT_DYNAMIC 6
+#define SHT_NOTE 7
+#define SHT_NOBITS 8
+#define SHT_REL 9
+#define SHT_SHLIB 10
+#define SHT_DYNSYM 11
+#define SHT_INIT_ARRAY 14
+#define SHT_FINI_ARRAY 15
+#define SHT_PREINIT_ARRAY 16
+#define SHT_GROUP 17
+#define SHT_SYMTAB_SHNDX 18
+#define SHT_LOOS 0x60000000
+#define SHT_HIOS 0x6fffffff
+#define SHT_LOPROC 0x70000000
+#define SHT_HIPROC 0x7fffffff
+#define SHT_LOUSER 0x80000000
+#define SHT_HIUSER 0xffffffff
+
+/* sh_flags */
+#define SHF_WRITE 0x1
+#define SHF_ALLOC 0x2
+#define SHF_EXECINSTR 0x4
+#define SHF_MASKPROC 0xf0000000
+
+/* Relocation entry (without addend) */
+typedef struct {
+ Elf32_Addr r_offset;
+ Elf32_Word r_info;
+
+} Elf32_Rel;
+
+typedef struct {
+ Elf64_Addr r_offset;
+ Elf64_Xword r_info;
+
+} Elf64_Rel;
+
+/* Relocation entry with addend */
+typedef struct {
+ Elf32_Addr r_offset;
+ Elf32_Word r_info;
+ Elf32_Sword r_addend;
+
+} Elf32_Rela;
+
+typedef struct elf64_rela {
+ Elf64_Addr r_offset;
+ Elf64_Xword r_info;
+ Elf64_Sxword r_addend;
+} Elf64_Rela;
+
+/* Macros to extract information from 'r_info' field of relocation entries */
+#define ELF32_R_SYM(i) ((i) >> 8)
+#define ELF32_R_TYPE(i) ((unsigned char)(i))
+#define ELF64_R_SYM(i) ((i) >> 32)
+#define ELF64_R_TYPE(i) ((i) & 0xffffffff)
+
+/* Symbol table entry */
+typedef struct {
+ Elf32_Word st_name;
+ Elf32_Addr st_value;
+ Elf32_Word st_size;
+ unsigned char st_info;
+ unsigned char st_other;
+ Elf32_Half st_shndx;
+
+} Elf32_Sym;
+
+typedef struct elf64_sym {
+ Elf64_Word st_name;
+ unsigned char st_info;
+ unsigned char st_other;
+ Elf64_Half st_shndx;
+ Elf64_Addr st_value;
+ Elf64_Xword st_size;
+} Elf64_Sym;
+
+/* ARM specific dynamic relocation codes */
+#define R_ARM_GLOB_DAT 21 /* 0x15 */
+#define R_ARM_JUMP_SLOT 22 /* 0x16 */
+#define R_ARM_RELATIVE 23 /* 0x17 */
+#define R_ARM_ABS32 2 /* 0x02 */
+
+/* ELF decoding information */
+struct elf32_info {
+ Elf32_Ehdr ehdr;
+ unsigned int load_state;
+ Elf32_Phdr *phdrs;
+ Elf32_Shdr *shdrs;
+ void *shstrtab;
+};
+
+struct elf64_info {
+ Elf64_Ehdr ehdr;
+ unsigned int load_state;
+ Elf64_Phdr *phdrs;
+ Elf64_Shdr *shdrs;
+ void *shstrtab;
+};
+
+#define ELF_STATE_INIT 0x0UL
+#define ELF_STATE_WAIT_FOR_PHDRS 0x100UL
+#define ELF_STATE_WAIT_FOR_SHDRS 0x200UL
+#define ELF_STATE_WAIT_FOR_SHSTRTAB 0x400UL
+#define ELF_STATE_HDRS_COMPLETE 0x800UL
+#define ELF_STATE_MASK 0xFF00UL
+#define ELF_NEXT_SEGMENT_MASK 0x00FFUL
+
+extern struct loader_ops elf_ops;
+
+/**
+ * elf_identify - check if it is an ELF file
+ *
+ * It will check if the input image header is an ELF header.
+ *
+ * @img_data: firmware private data which will be passed to user defined loader
+ * operations
+ * @len: firmware header length
+ *
+ * return 0 for success or negative value for failure.
+ */
+int elf_identify(const void *img_data, size_t len);
+
+/**
+ * elf_load_header - Load ELF headers
+ *
+ * It will get the ELF header, the program header, and the section header.
+ *
+ * @img_data: image data
+ * @offset: input image data offset to the start of image file
+ * @len: input image data length
+ * @img_info: pointer to store image information data
+ * @last_load_state: last state return by this function
+ * @noffset: pointer to next offset required by loading ELF header
+ * @nlen: pointer to next data length required by loading ELF header
+ *
+ * return ELF loading header state, or negative value for failure
+ */
+int elf_load_header(const void *img_data, size_t offset, size_t len,
+ void **img_info, int last_load_state,
+ size_t *noffset, size_t *nlen);
+
+/**
+ * elf_load - load ELF data
+ *
+ * It will parse the ELF image and return the target device address,
+ * offset to the start of the ELF image of the data to load and the
+ * length of the data to load.
+ *
+ * @rproc: pointer to remoteproc instance
+ * @img_data: image data which will passed to the function.
+ * it can be NULL, if image data doesn't need to be handled
+ * by the load function. E.g. binary data which was
+ * loaded to the target memory.
+ * @offset: last loaded image data offset to the start of image file
+ * @len: last loaded image data length
+ * @img_info: pointer to store image information data
+ * @last_load_state: the returned state of the last function call.
+ * @da: target device address, if the data to load is not for target memory
+ * the da will be set to ANY.
+ * @noffset: pointer to next offset required by loading ELF header
+ * @nlen: pointer to next data length required by loading ELF header
+ * @padding: value to pad it is possible that a size of a segment in memory
+ * is larger than what it is in the ELF image. e.g. a segment
+ * can have stack section .bss. It doesn't need to copy image file
+ * space, in this case, it will be packed with 0.
+ * @nmemsize: pointer to next data target memory size. The size of a segment
+ * in the target memory can be larger than the its size in the
+ * image file.
+ *
+ * return 0 for success, otherwise negative value for failure
+ */
+int elf_load(struct remoteproc *rproc, const void *img_data,
+ size_t offset, size_t len,
+ void **img_info, int last_load_state,
+ metal_phys_addr_t *da,
+ size_t *noffset, size_t *nlen,
+ unsigned char *padding, size_t *nmemsize);
+
+/**
+ * elf_release - Release ELF image information
+ *
+ * It will release ELF image information data.
+ *
+ * @img_info: pointer to ELF image information
+ */
+void elf_release(void *img_info);
+
+/**
+ * elf_get_entry - Get entry point
+ *
+ * It will return entry point specified in the ELF file.
+ *
+ * @img_info: pointer to ELF image information
+ *
+ * return entry address
+ */
+metal_phys_addr_t elf_get_entry(void *img_info);
+
+/**
+ * elf_locate_rsc_table - locate the resource table information
+ *
+ * It will return the length of the resource table, and the device address of
+ * the resource table.
+ *
+ * @img_info: pointer to ELF image information
+ * @da: pointer to the device address
+ * @offset: pointer to the offset to in the ELF image of the resource
+ * table section.
+ * @size: pointer to the size of the resource table section.
+ *
+ * return 0 if successfully locate the resource table, negative value for
+ * failure.
+ */
+int elf_locate_rsc_table(void *img_info, metal_phys_addr_t *da,
+ size_t *offset, size_t *size);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* ELF_LOADER_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/open_amp.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/open_amp.h
new file mode 100644
index 0000000..603ecdd
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/open_amp.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef OPEN_AMP_H_
+#define OPEN_AMP_H_
+
+#include <openamp/rpmsg.h>
+#include <openamp/rpmsg_virtio.h>
+#include <openamp/remoteproc.h>
+#include <openamp/remoteproc_virtio.h>
+
+
+#endif /* OPEN_AMP_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc.h
new file mode 100644
index 0000000..6b2495c
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc.h
@@ -0,0 +1,871 @@
+/*
+ * Remoteproc Framework
+ *
+ * Copyright(c) 2018 Xilinx Ltd.
+ * Copyright(c) 2011 Texas Instruments, Inc.
+ * Copyright(c) 2011 Google, Inc.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REMOTEPROC_H
+#define REMOTEPROC_H
+
+#include <metal/io.h>
+#include <metal/mutex.h>
+#include <openamp/compiler.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+#define RSC_NOTIFY_ID_ANY 0xFFFFFFFFUL
+
+/**
+ * struct resource_table - firmware resource table header
+ * @ver: version number
+ * @num: number of resource entries
+ * @reserved: reserved (must be zero)
+ * @offset: array of offsets pointing at the various resource entries
+ *
+ * A resource table is essentially a list of system resources required
+ * by the remote remote_proc. It may also include configuration entries.
+ * If needed, the remote remote_proc firmware should contain this table
+ * as a dedicated ".resource_table" ELF section.
+ *
+ * Some resources entries are mere announcements, where the host is informed
+ * of specific remoteproc configuration. Other entries require the host to
+ * do something (e.g. allocate a system resource). Sometimes a negotiation
+ * is expected, where the firmware requests a resource, and once allocated,
+ * the host should provide back its details (e.g. address of an allocated
+ * memory region).
+ *
+ * The header of the resource table, as expressed by this structure,
+ * contains a version number (should we need to change this format in the
+ * future), the number of available resource entries, and their offsets
+ * in the table.
+ *
+ * Immediately following this header are the resource entries themselves,
+ * each of which begins with a resource entry header (as described below).
+ */
+OPENAMP_PACKED_BEGIN
+struct resource_table {
+ uint32_t ver;
+ uint32_t num;
+ uint32_t reserved[2];
+ uint32_t offset[0];
+} OPENAMP_PACKED_END;
+
+/**
+ * struct fw_rsc_hdr - firmware resource entry header
+ * @type: resource type
+ * @data: resource data
+ *
+ * Every resource entry begins with a 'struct fw_rsc_hdr' header providing
+ * its @type. The content of the entry itself will immediately follow
+ * this header, and it should be parsed according to the resource type.
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_hdr {
+ uint32_t type;
+ uint8_t data[0];
+} OPENAMP_PACKED_END;
+
+/**
+ * enum fw_resource_type - types of resource entries
+ *
+ * @RSC_CARVEOUT: request for allocation of a physically contiguous
+ * memory region.
+ * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
+ * @RSC_TRACE: announces the availability of a trace buffer into which
+ * the remote remote_proc will be writing logs.
+ * @RSC_VDEV: declare support for a virtio device, and serve as its
+ * virtio header.
+ * @RSC_VENDOR_START: start of the vendor specific resource types range
+ * @RSC_VENDOR_END : end of the vendor specific resource types range
+ * @RSC_LAST: just keep this one at the end
+ *
+ * For more details regarding a specific resource type, please see its
+ * dedicated structure below.
+ *
+ * Please note that these values are used as indices to the rproc_handle_rsc
+ * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to
+ * check the validity of an index before the lookup table is accessed, so
+ * please update it as needed.
+ */
+enum fw_resource_type {
+ RSC_CARVEOUT = 0,
+ RSC_DEVMEM = 1,
+ RSC_TRACE = 2,
+ RSC_VDEV = 3,
+ RSC_RPROC_MEM = 4,
+ RSC_FW_CHKSUM = 5,
+ RSC_LAST = 6,
+ RSC_VENDOR_START = 128,
+ RSC_VENDOR_END = 512,
+};
+
+#define FW_RSC_ADDR_ANY (0xFFFFFFFFFFFFFFFF)
+#define FW_RSC_U32_ADDR_ANY (0xFFFFFFFF)
+
+/**
+ * struct fw_rsc_carveout - physically contiguous memory request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested memory region
+ *
+ * This resource entry requests the host to allocate a physically contiguous
+ * memory region.
+ *
+ * These request entries should precede other firmware resource entries,
+ * as other entries might request placing other data objects inside
+ * these memory regions (e.g. data/code segments, trace resource entries, ...).
+ *
+ * Allocating memory this way helps utilizing the reserved physical memory
+ * (e.g. CMA) more efficiently, and also minimizes the number of TLB entries
+ * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
+ * pressure is important; it may have a substantial impact on performance.
+ *
+ * If the firmware is compiled with static addresses, then @da should specify
+ * the expected device address of this memory region. If @da is set to
+ * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then
+ * overwrite @da with the dynamically allocated address.
+ *
+ * We will always use @da to negotiate the device addresses, even if it
+ * isn't using an iommu. In that case, though, it will obviously contain
+ * physical addresses.
+ *
+ * Some remote remote_procs needs to know the allocated physical address
+ * even if they do use an iommu. This is needed, e.g., if they control
+ * hardware accelerators which access the physical memory directly (this
+ * is the case with OMAP4 for instance). In that case, the host will
+ * overwrite @pa with the dynamically allocated physical address.
+ * Generally we don't want to expose physical addresses if we don't have to
+ * (remote remote_procs are generally _not_ trusted), so we might want to
+ * change this to happen _only_ when explicitly required by the hardware.
+ *
+ * @flags is used to provide IOMMU protection flags, and @name should
+ * (optionally) contain a human readable name of this carveout region
+ * (mainly for debugging purposes).
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_carveout {
+ uint32_t type;
+ uint32_t da;
+ uint32_t pa;
+ uint32_t len;
+ uint32_t flags;
+ uint32_t reserved;
+ uint8_t name[32];
+} OPENAMP_PACKED_END;
+
+/**
+ * struct fw_rsc_devmem - iommu mapping request
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @flags: iommu protection flags
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the requested region to be mapped
+ *
+ * This resource entry requests the host to iommu map a physically contiguous
+ * memory region. This is needed in case the remote remote_proc requires
+ * access to certain memory-based peripherals; _never_ use it to access
+ * regular memory.
+ *
+ * This is obviously only needed if the remote remote_proc is accessing memory
+ * via an iommu.
+ *
+ * @da should specify the required device address, @pa should specify
+ * the physical address we want to map, @len should specify the size of
+ * the mapping and @flags is the IOMMU protection flags. As always, @name may
+ * (optionally) contain a human readable name of this mapping (mainly for
+ * debugging purposes).
+ *
+ * Note: at this point we just "trust" those devmem entries to contain valid
+ * physical addresses, but this isn't safe and will be changed: eventually we
+ * want remoteproc implementations to provide us ranges of physical addresses
+ * the firmware is allowed to request, and not allow firmwares to request
+ * access to physical addresses that are outside those ranges.
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_devmem {
+ uint32_t type;
+ uint32_t da;
+ uint32_t pa;
+ uint32_t len;
+ uint32_t flags;
+ uint32_t reserved;
+ uint8_t name[32];
+} OPENAMP_PACKED_END;
+
+/**
+ * struct fw_rsc_trace - trace buffer declaration
+ * @da: device address
+ * @len: length (in bytes)
+ * @reserved: reserved (must be zero)
+ * @name: human-readable name of the trace buffer
+ *
+ * This resource entry provides the host information about a trace buffer
+ * into which the remote remote_proc will write log messages.
+ *
+ * @da specifies the device address of the buffer, @len specifies
+ * its size, and @name may contain a human readable name of the trace buffer.
+ *
+ * After booting the remote remote_proc, the trace buffers are exposed to the
+ * user via debugfs entries (called trace0, trace1, etc..).
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_trace {
+ uint32_t type;
+ uint32_t da;
+ uint32_t len;
+ uint32_t reserved;
+ uint8_t name[32];
+} OPENAMP_PACKED_END;
+
+/**
+ * struct fw_rsc_vdev_vring - vring descriptor entry
+ * @da: device address
+ * @align: the alignment between the consumer and producer parts of the vring
+ * @num: num of buffers supported by this vring (must be power of two)
+ * @notifyid is a unique rproc-wide notify index for this vring. This notify
+ * index is used when kicking a remote remote_proc, to let it know that this
+ * vring is triggered.
+ * @reserved: reserved (must be zero)
+ *
+ * This descriptor is not a resource entry by itself; it is part of the
+ * vdev resource type (see below).
+ *
+ * Note that @da should either contain the device address where
+ * the remote remote_proc is expecting the vring, or indicate that
+ * dynamically allocation of the vring's device address is supported.
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_vdev_vring {
+ uint32_t da;
+ uint32_t align;
+ uint32_t num;
+ uint32_t notifyid;
+ uint32_t reserved;
+} OPENAMP_PACKED_END;
+
+/**
+ * struct fw_rsc_vdev - virtio device header
+ * @id: virtio device id (as in virtio_ids.h)
+ * @notifyid is a unique rproc-wide notify index for this vdev. This notify
+ * index is used when kicking a remote remote_proc, to let it know that the
+ * status/features of this vdev have changes.
+ * @dfeatures specifies the virtio device features supported by the firmware
+ * @gfeatures is a place holder used by the host to write back the
+ * negotiated features that are supported by both sides.
+ * @config_len is the size of the virtio config space of this vdev. The config
+ * space lies in the resource table immediate after this vdev header.
+ * @status is a place holder where the host will indicate its virtio progress.
+ * @num_of_vrings indicates how many vrings are described in this vdev header
+ * @reserved: reserved (must be zero)
+ * @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'.
+ *
+ * This resource is a virtio device header: it provides information about
+ * the vdev, and is then used by the host and its peer remote remote_procs
+ * to negotiate and share certain virtio properties.
+ *
+ * By providing this resource entry, the firmware essentially asks remoteproc
+ * to statically allocate a vdev upon registration of the rproc (dynamic vdev
+ * allocation is not yet supported).
+ *
+ * Note: unlike virtualization systems, the term 'host' here means
+ * the Linux side which is running remoteproc to control the remote
+ * remote_procs. We use the name 'gfeatures' to comply with virtio's terms,
+ * though there isn't really any virtualized guest OS here: it's the host
+ * which is responsible for negotiating the final features.
+ * Yeah, it's a bit confusing.
+ *
+ * Note: immediately following this structure is the virtio config space for
+ * this vdev (which is specific to the vdev; for more info, read the virtio
+ * spec). the size of the config space is specified by @config_len.
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_vdev {
+ uint32_t type;
+ uint32_t id;
+ uint32_t notifyid;
+ uint32_t dfeatures;
+ uint32_t gfeatures;
+ uint32_t config_len;
+ uint8_t status;
+ uint8_t num_of_vrings;
+ uint8_t reserved[2];
+ struct fw_rsc_vdev_vring vring[0];
+} OPENAMP_PACKED_END;
+
+/**
+ * struct fw_rsc_vendor - remote processor vendor specific resource
+ * @len: length of the resource
+ *
+ * This resource entry tells the host the vendor specific resource
+ * required by the remote.
+ *
+ * These request entries should precede other shared resource entries
+ * such as vdevs, vrings.
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_vendor {
+ uint32_t type;
+ uint32_t len;
+} OPENAMP_PACKED_END;
+
+/**
+ * struct fw_rsc_rproc_mem - remote processor memory
+ * @da: device address
+ * @pa: physical address
+ * @len: length (in bytes)
+ * @reserved: reserved (must be zero)
+ *
+ * This resource entry tells the host to the remote processor
+ * memory that the host can be used as shared memory.
+ *
+ * These request entries should precede other shared resource entries
+ * such as vdevs, vrings.
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_rproc_mem {
+ uint32_t type;
+ uint32_t da;
+ uint32_t pa;
+ uint32_t len;
+ uint32_t reserved;
+} OPENAMP_PACKED_END;
+
+/*
+ * struct fw_rsc_fw_chksum - firmware checksum
+ * @algo: algorithm to generate the cheksum
+ * @chksum: checksum of the firmware loadable sections.
+ *
+ * This resource entry provides checksum for the firmware loadable sections.
+ * It is used to check if the remote already runs with the expected firmware to
+ * decide if it needs to start the remote if the remote is already running.
+ */
+OPENAMP_PACKED_BEGIN
+struct fw_rsc_fw_chksum {
+ uint32_t type;
+ uint8_t algo[16];
+ uint8_t chksum[64];
+} OPENAMP_PACKED_END;
+
+struct loader_ops;
+struct image_store_ops;
+struct remoteproc_ops;
+
+/**
+ * struct remoteproc_mem
+ *
+ * This structure presents the memory used by the remote processor
+ *
+ * @da: device memory
+ * @pa: physical memory
+ * @size: size of the memory
+ * @io: pointer to the I/O region
+ * @node: list node
+ */
+struct remoteproc_mem {
+ metal_phys_addr_t da;
+ metal_phys_addr_t pa;
+ size_t size;
+ char name[32];
+ struct metal_io_region *io;
+ struct metal_list node;
+};
+
+/**
+ * struct remoteproc
+ *
+ * This structure is maintained by the remoteproc to represent the remote
+ * processor instance. This structure acts as a prime parameter to use
+ * the remoteproc APIs.
+ *
+ * @bootadd: boot address
+ * @loader: executable loader
+ * @lock: mutext lock
+ * @ops: remoteproc operations
+ * @rsc_table: pointer to resource table
+ * @rsc_len: length of resource table
+ * @rsc_io: metal I/O region of resource table
+ * @mems: remoteproc memories
+ * @vdevs: remoteproc virtio devices
+ * @bitmap: bitmap for notify IDs for remoteproc subdevices
+ * @state: remote processor state
+ * @priv: private data
+ */
+struct remoteproc {
+ metal_mutex_t lock;
+ void *rsc_table;
+ size_t rsc_len;
+ struct metal_io_region *rsc_io;
+ struct metal_list mems;
+ struct metal_list vdevs;
+ unsigned long bitmap;
+ struct remoteproc_ops *ops;
+ metal_phys_addr_t bootaddr;
+ struct loader_ops *loader;
+ unsigned int state;
+ void *priv;
+};
+
+/**
+ * struct remoteproc_ops
+ *
+ * remoteproc operations needs to be implemented by each remoteproc driver
+ *
+ * @init: initialize the remoteproc instance
+ * @remove: remove the remoteproc instance
+ * @mmap: memory mapped the mempory with physical address or destination
+ * address as input.
+ * @handle_rsc: handle the vendor specific resource
+ * @config: configure the remoteproc to make it ready to load and run
+ * executable
+ * @start: kick the remoteproc to run application
+ * @stop: stop the remoteproc from running application, the resource such as
+ * memory may not be off.
+ * @shutdown: shutdown the remoteproc and release its resources.
+ * @notify: notify the remote
+ */
+struct remoteproc_ops {
+ struct remoteproc *(*init)(struct remoteproc *rproc,
+ struct remoteproc_ops *ops, void *arg);
+ void (*remove)(struct remoteproc *rproc);
+ void *(*mmap)(struct remoteproc *rproc,
+ metal_phys_addr_t *pa, metal_phys_addr_t *da,
+ size_t size, unsigned int attribute,
+ struct metal_io_region **io);
+ int (*handle_rsc)(struct remoteproc *rproc, void *rsc, size_t len);
+ int (*config)(struct remoteproc *rproc, void *data);
+ int (*start)(struct remoteproc *rproc);
+ int (*stop)(struct remoteproc *rproc);
+ int (*shutdown)(struct remoteproc *rproc);
+ int (*notify)(struct remoteproc *rproc, uint32_t id);
+};
+
+/* Remoteproc error codes */
+#define RPROC_EBASE 0
+#define RPROC_ENOMEM (RPROC_EBASE + 1)
+#define RPROC_EINVAL (RPROC_EBASE + 2)
+#define RPROC_ENODEV (RPROC_EBASE + 3)
+#define RPROC_EAGAIN (RPROC_EBASE + 4)
+#define RPROC_ERR_RSC_TAB_TRUNC (RPROC_EBASE + 5)
+#define RPROC_ERR_RSC_TAB_VER (RPROC_EBASE + 6)
+#define RPROC_ERR_RSC_TAB_RSVD (RPROC_EBASE + 7)
+#define RPROC_ERR_RSC_TAB_VDEV_NRINGS (RPROC_EBASE + 9)
+#define RPROC_ERR_RSC_TAB_NP (RPROC_EBASE + 10)
+#define RPROC_ERR_RSC_TAB_NS (RPROC_EBASE + 11)
+#define RPROC_ERR_LOADER_STATE (RPROC_EBASE + 12)
+#define RPROC_EMAX (RPROC_EBASE + 16)
+#define RPROC_EPTR (void *)(-1)
+#define RPROC_EOF (void *)(-1)
+
+static inline long RPROC_PTR_ERR(const void *ptr)
+{
+ return (long)ptr;
+}
+
+static inline int RPROC_IS_ERR(const void *ptr)
+{
+ if ((unsigned long)ptr >= (unsigned long)(-RPROC_EMAX))
+ return 1;
+ else
+ return 0;
+}
+
+static inline void *RPROC_ERR_PTR(long error)
+{
+ return (void *)error;
+}
+
+/**
+ * enum rproc_state - remote processor states
+ * @RPROC_OFFLINE: remote is offline
+ * @RPROC_READY: remote is ready to start
+ * @RPROC_RUNNING: remote is up and running
+ * @RPROC_SUSPENDED: remote is suspended
+ * @RPROC_ERROR: remote has error; need to recover
+ * @RPROC_STOPPED: remote is stopped
+ * @RPROC_LAST: just keep this one at the end
+ */
+enum remoteproc_state {
+ RPROC_OFFLINE = 0,
+ RPROC_CONFIGURED = 1,
+ RPROC_READY = 2,
+ RPROC_RUNNING = 3,
+ RPROC_SUSPENDED = 4,
+ RPROC_ERROR = 5,
+ RPROC_STOPPED = 6,
+ RPROC_LAST = 7,
+};
+
+/**
+ * remoteproc_init
+ *
+ * Initializes remoteproc resource.
+ *
+ * @rproc - pointer to remoteproc instance
+ * @ops - pointer to remoteproc operations
+ * @priv - pointer to private data
+ *
+ * @returns created remoteproc pointer
+ */
+struct remoteproc *remoteproc_init(struct remoteproc *rproc,
+ struct remoteproc_ops *ops, void *priv);
+
+/**
+ * remoteproc_remove
+ *
+ * Remove remoteproc resource
+ *
+ * @rproc - pointer to remoteproc instance
+ *
+ * returns 0 for success, negative value for failure
+ */
+int remoteproc_remove(struct remoteproc *rproc);
+
+/**
+ * remoteproc_init_mem
+ *
+ * Initialize remoteproc memory
+ *
+ * @mem - pointer to remoteproc memory
+ * @char - memory name
+ * @pa - physcial address
+ * @da - device address
+ * @size - memory size
+ * @io - pointer to the I/O region
+ */
+static inline void
+remoteproc_init_mem(struct remoteproc_mem *mem, const char *name,
+ metal_phys_addr_t pa, metal_phys_addr_t da,
+ size_t size, struct metal_io_region *io)
+{
+ if (!mem)
+ return;
+ if (name)
+ strncpy(mem->name, name, sizeof(mem->name));
+ else
+ mem->name[0] = 0;
+ mem->pa = pa;
+ mem->da = da;
+ mem->io = io;
+ mem->size = size;
+}
+
+/**
+ * remoteproc_add_mem
+ *
+ * Add remoteproc memory
+ *
+ * @rproc - pointer to remoteproc
+ * @mem - pointer to remoteproc memory
+ */
+static inline void
+remoteproc_add_mem(struct remoteproc *rproc, struct remoteproc_mem *mem)
+{
+ if (!rproc || !mem)
+ return;
+ metal_list_add_tail(&rproc->mems, &mem->node);
+}
+
+/**
+ * remoteproc_get_io_with_name
+ *
+ * get remoteproc memory I/O region with name
+ *
+ * @rproc - pointer to the remote processor
+ * @name - name of the shared memory
+ * @io - pointer to the pointer of the I/O region
+ *
+ * returns metal I/O region pointer, NULL for failure
+ */
+struct metal_io_region *
+remoteproc_get_io_with_name(struct remoteproc *rproc,
+ const char *name);
+
+/**
+ * remoteproc_get_io_with_pa
+ *
+ * get remoteproc memory I/O region with physical address
+ *
+ * @rproc - pointer to the remote processor
+ * @pa - physical address
+ *
+ * returns metal I/O region pointer, NULL for failure
+ */
+struct metal_io_region *
+remoteproc_get_io_with_pa(struct remoteproc *rproc,
+ metal_phys_addr_t pa);
+
+/**
+ * remoteproc_get_io_with_da
+ *
+ * get remoteproc memory I/O region with device address
+ *
+ * @rproc - pointer to the remote processor
+ * @da - device address
+ * @offset - I/O region offset of the device address
+ *
+ * returns metal I/O region pointer, NULL for failure
+ */
+struct metal_io_region *
+remoteproc_get_io_with_da(struct remoteproc *rproc,
+ metal_phys_addr_t da,
+ unsigned long *offset);
+
+/**
+ * remoteproc_get_io_with_va
+ *
+ * get remoteproc memory I/O region with virtual address
+ *
+ * @rproc - pointer to the remote processor
+ * @va - virtual address
+ *
+ * returns metal I/O region pointer, NULL for failure
+ */
+struct metal_io_region *
+remoteproc_get_io_with_va(struct remoteproc *rproc,
+ void *va);
+
+/**
+ * remoteproc_mmap
+ *
+ * remoteproc mmap memory
+ *
+ * @rproc - pointer to the remote processor
+ * @pa - physical address pointer
+ * @da - device address pointer
+ * @size - size of the memory
+ * @attribute - memory attribute
+ * @io - pointer to the I/O region
+ *
+ * returns pointer to the memory
+ */
+void *remoteproc_mmap(struct remoteproc *rproc,
+ metal_phys_addr_t *pa, metal_phys_addr_t *da,
+ size_t size, unsigned int attribute,
+ struct metal_io_region **io);
+
+/**
+ * remoteproc_parse_rsc_table
+ *
+ * Parse resource table of remoteproc
+ *
+ * @rproc - pointer to remoteproc instance
+ * @rsc_table - pointer to resource table
+ * @rsc_size - resource table size
+ *
+ * returns 0 for success and negative value for errors
+ */
+int remoteproc_parse_rsc_table(struct remoteproc *rproc,
+ struct resource_table *rsc_table,
+ size_t rsc_size);
+
+/**
+ * remoteproc_set_rsc_table
+ *
+ * Parse and set resource table of remoteproc
+ *
+ * @rproc - pointer to remoteproc instance
+ * @rsc_table - pointer to resource table
+ * @rsc_size - resource table size
+ *
+ * returns 0 for success and negative value for errors
+ */
+int remoteproc_set_rsc_table(struct remoteproc *rproc,
+ struct resource_table *rsc_table,
+ size_t rsc_size);
+
+/**
+ * remoteproc_config
+ *
+ * This function configures the remote processor to get it
+ * ready to load and run executable.
+ *
+ * @rproc - pointer to remoteproc instance to start
+ * @data - configuration data
+ *
+ * returns 0 for success and negative value for errors
+ */
+int remoteproc_config(struct remoteproc *rproc, void *data);
+
+/**
+ * remoteproc_start
+ *
+ * This function starts the remote processor.
+ * It assumes the firmware is already loaded,
+ *
+ * @rproc - pointer to remoteproc instance to start
+ *
+ * returns 0 for success and negative value for errors
+ */
+int remoteproc_start(struct remoteproc *rproc);
+
+/**
+ * remoteproc_stop
+ *
+ * This function stops the remote processor but it
+ * will not release its resource.
+ *
+ * @rproc - pointer to remoteproc instance
+ *
+ * returns 0 for success and negative value for errors
+ */
+int remoteproc_stop(struct remoteproc *rproc);
+
+/**
+ * remoteproc_shutdown
+ *
+ * This function shutdown the remote processor and
+ * release its resources.
+ *
+ * @rproc - pointer to remoteproc instance
+ *
+ * returns 0 for success and negative value for errors
+ */
+int remoteproc_shutdown(struct remoteproc *rproc);
+
+/**
+ * remoteproc_load
+ *
+ * load executable, it expects the user application defines how to
+ * open the executable file and how to get data from the executable file
+ * and how to load data to the target memory.
+ *
+ * @rproc: pointer to the remoteproc instance
+ * @path: optional path to the image file
+ * @store: pointer to user defined image store argument
+ * @store_ops: pointer to image store operations
+ * @image_info: pointer to memory which stores image information used
+ * by remoteproc loader
+ *
+ * return 0 for success and negative value for failure
+ */
+int remoteproc_load(struct remoteproc *rproc, const char *path,
+ void *store, struct image_store_ops *store_ops,
+ void **img_info);
+
+/**
+ * remoteproc_load_noblock
+ *
+ * load executable, it expects the caller has loaded image data to local
+ * memory and passed to the this function. If the function needs more
+ * image data it will return the next expected image data offset and
+ * the next expected image data length. If the function requires the
+ * caller to download image data to the target memory, it will also
+ * return the target physical address besides the offset and length.
+ * This function can be used to load firmware in stream mode. In this
+ * mode, you cannot do seek to the executable file. If the executable
+ * is ELF, it cannot get the resource table section before it loads
+ * the full ELF file. Furthermore, application usually don't store
+ * the data which is loaded to local memory in streaming mode, and
+ * thus, in this mode, it will load the binrary to the target memory
+ * before it gets the resource table. And thus, when calling this funciton
+ * don't put the target exectuable memory in the resource table, as
+ * this function will parse the resource table after it loads the binary
+ * to target memory.
+ *
+ * @rproc: pointer to the remoteproc instance
+ * @img_data: pointer to image data for remoteproc loader to parse
+ * @offset: image data offset to the beginning of the image file
+ * @len: image data length
+ * @image_info: pointer to memory which stores image information used
+ * by remoteproc loader
+ * @pa: pointer to the target memory physical address. If the next expected
+ * data doesn't need to load to the target memory, the function will
+ * set it to ANY.
+ * @io: pointer to the target memory physical address. If the next expected
+ * data doesn't need to load to the target memory, the function will
+ * set it to ANY.
+ * @noffset: pointer to the next image data offset to the beginning of
+ * the image file needs to load to local or to the target
+ * memory.
+ * @nlen: pointer to the next image data length needs to load to local
+ * or to the target memory.
+ * @nmlen: pointer to the memory size. It is only used when the next
+ * expected data is going to be loaded to the target memory. E.g.
+ * in ELF, it is possible that loadable segment in memory is
+ * larger that the segment data in the ELF file. In this case,
+ * application will need to pad the rest of the memory with
+ * padding.
+ * @padding: pointer to the padding value. It is only used when the next
+ * expected data is going to be loaded to the target memory.
+ * and the target memory size is larger than the segment data in
+ * the executable file.
+ *
+ * return 0 for success and negative value for failure
+ */
+int remoteproc_load_noblock(struct remoteproc *rproc,
+ const void *img_data, size_t offset, size_t len,
+ void **img_info,
+ metal_phys_addr_t *pa, struct metal_io_region **io,
+ size_t *noffset, size_t *nlen,
+ size_t *nmlen, unsigned char *padding);
+
+/**
+ * remoteproc_allocate_id
+ *
+ * allocate notifyid for resource
+ *
+ * @rproc - pointer to the remoteproc instance
+ * @start - start of the id range
+ * @end - end of the id range
+ *
+ * return allocated notify id
+ */
+unsigned int remoteproc_allocate_id(struct remoteproc *rproc,
+ unsigned int start,
+ unsigned int end);
+
+/* remoteproc_create_virtio
+ *
+ * create virtio device, it returns pointer to the created virtio device.
+ *
+ * @rproc: pointer to the remoteproc instance
+ * @vdev_id: virtio device ID
+ * @role: virtio device role
+ * @rst_cb: virtio device reset callback
+ *
+ * return pointer to the created virtio device, NULL for failure.
+ */
+struct virtio_device *
+remoteproc_create_virtio(struct remoteproc *rproc,
+ int vdev_id, unsigned int role,
+ void (*rst_cb)(struct virtio_device *vdev));
+
+/* remoteproc_remove_virtio
+ *
+ * Remove virtio device
+ *
+ * @rproc: pointer to the remoteproc instance
+ * @vdev: pointer to the virtio device
+ *
+ */
+void remoteproc_remove_virtio(struct remoteproc *rproc,
+ struct virtio_device *vdev);
+
+/* remoteproc_get_notification
+ *
+ * remoteproc is got notified, it will check its subdevices
+ * for the notification
+ *
+ * @rproc - pointer to the remoteproc instance
+ * @notifyid - notificatin id
+ *
+ * return 0 for succeed, negative value for failure
+ */
+int remoteproc_get_notification(struct remoteproc *rproc,
+ uint32_t notifyid);
+#if defined __cplusplus
+}
+#endif
+
+#endif /* REMOTEPROC_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_loader.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_loader.h
new file mode 100644
index 0000000..dce3dbb
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_loader.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**************************************************************************
+ * FILE NAME
+ *
+ * remoteproc_loader.h
+ *
+ * COMPONENT
+ *
+ * OpenAMP stack.
+ *
+ * DESCRIPTION
+ *
+ * This file provides definitions for remoteproc loader
+ *
+ *
+ **************************************************************************/
+#ifndef REMOTEPROC_LOADER_H_
+#define REMOTEPROC_LOADER_H_
+
+#include <metal/io.h>
+#include <metal/list.h>
+#include <metal/sys.h>
+#include <openamp/remoteproc.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* Loader feature macros */
+#define SUPPORT_SEEK 1UL
+
+/* Remoteproc loader any address */
+#define RPROC_LOAD_ANYADDR ((metal_phys_addr_t)-1)
+
+/* Remoteproc loader Exectuable Image Parsing States */
+/* Remoteproc loader parser intial state */
+#define RPROC_LOADER_NOT_READY 0x0UL
+/* Remoteproc loader ready to load, even it can be not finish parsing */
+#define RPROC_LOADER_READY_TO_LOAD 0x10000UL
+/* Remoteproc loader post data load */
+#define RPROC_LOADER_POST_DATA_LOAD 0x20000UL
+/* Remoteproc loader finished loading */
+#define RPROC_LOADER_LOAD_COMPLETE 0x40000UL
+/* Remoteproc loader state mask */
+#define RPROC_LOADER_MASK 0x00FF0000UL
+/* Remoteproc loader private mask */
+#define RPROC_LOADER_PRIVATE_MASK 0x0000FFFFUL
+/* Remoteproc loader reserved mask */
+#define RPROC_LOADER_RESERVED_MASK 0x0F000000UL
+
+/**
+ * struct image_store_ops - user defined image store operations
+ * @open: user defined callback to open the "firmware" to prepare loading
+ * @close: user defined callback to close the "firmware" to clean up
+ * after loading
+ * @load: user defined callback to load the firmware contents to target
+ * memory or local memory
+ * @features: loader supported features. e.g. seek
+ */
+struct image_store_ops {
+ int (*open)(void *store, const char *path, const void **img_data);
+ void (*close)(void *store);
+ int (*load)(void *store, size_t offset, size_t size,
+ const void **data,
+ metal_phys_addr_t pa,
+ struct metal_io_region *io, char is_blocking);
+ unsigned int features;
+};
+
+/**
+ * struct loader_ops - loader oeprations
+ * @load_header: define how to get the executable headers
+ * @load_data: define how to load the target data
+ * @locate_rsc_table: define how to get the resource table target address,
+ * offset to the ELF image file and size of the resource
+ * table.
+ * @release: define how to release the loader
+ * @get_entry: get entry address
+ * @get_load_state: get load state from the image information
+ */
+struct loader_ops {
+ int (*load_header)(const void *img_data, size_t offset, size_t len,
+ void **img_info, int last_state,
+ size_t *noffset, size_t *nlen);
+ int (*load_data)(struct remoteproc *rproc,
+ const void *img_data, size_t offset, size_t len,
+ void **img_info, int last_load_state,
+ metal_phys_addr_t *da,
+ size_t *noffset, size_t *nlen,
+ unsigned char *padding, size_t *nmemsize);
+ int (*locate_rsc_table)(void *img_info, metal_phys_addr_t *da,
+ size_t *offset, size_t *size);
+ void (*release)(void *img_info);
+ metal_phys_addr_t (*get_entry)(void *img_info);
+ int (*get_load_state)(void *img_info);
+};
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* REMOTEPROC_LOADER_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_virtio.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_virtio.h
new file mode 100644
index 0000000..fc1627e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/remoteproc_virtio.h
@@ -0,0 +1,150 @@
+/*
+ * Remoteproc Virtio Framework
+ *
+ * Copyright(c) 2018 Xilinx Ltd.
+ * Copyright(c) 2011 Texas Instruments, Inc.
+ * Copyright(c) 2011 Google, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name Texas Instruments nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef REMOTEPROC_VIRTIO_H
+#define REMOTEPROC_VIRTIO_H
+
+#include <metal/io.h>
+#include <metal/list.h>
+#include <openamp/virtio.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* define vdev notification funciton user should implement */
+typedef int (*rpvdev_notify_func)(void *priv, uint32_t id);
+
+/**
+ * struct remoteproc_virtio
+ * @priv pointer to private data
+ * @notifyid notification id
+ * @vdev_rsc address of vdev resource
+ * @vdev_rsc_io metal I/O region of vdev_info, can be NULL
+ * @notify notification function
+ * @vdev virtio device
+ * @node list node
+ */
+struct remoteproc_virtio {
+ void *priv;
+ uint32_t notify_id;
+ void *vdev_rsc;
+ struct metal_io_region *vdev_rsc_io;
+ rpvdev_notify_func notify;
+ struct virtio_device vdev;
+ struct metal_list node;
+};
+
+/**
+ * rproc_virtio_create_vdev
+ *
+ * Create rproc virtio vdev
+ *
+ * @role: 0 - virtio master, 1 - virtio slave
+ * @notifyid: virtio device notification id
+ * @rsc: pointer to the virtio device resource
+ * @rsc_io: pointer to the virtio device resource I/O region
+ * @priv: pointer to the private data
+ * @notify: vdev and virtqueue notification function
+ * @rst_cb: reset virtio device callback
+ *
+ * return pointer to the created virtio device for success,
+ * NULL for failure.
+ */
+struct virtio_device *
+rproc_virtio_create_vdev(unsigned int role, unsigned int notifyid,
+ void *rsc, struct metal_io_region *rsc_io,
+ void *priv,
+ rpvdev_notify_func notify,
+ virtio_dev_reset_cb rst_cb);
+
+/**
+ * rproc_virtio_remove_vdev
+ *
+ * Create rproc virtio vdev
+ *
+ * @vdev - pointer to the virtio device
+ */
+void rproc_virtio_remove_vdev(struct virtio_device *vdev);
+
+/**
+ * rproc_virtio_create_vring
+ *
+ * Create rproc virtio vring
+ *
+ * @vdev: pointer to the virtio device
+ * @index: vring index in the virtio device
+ * @notifyid: remoteproc vring notification id
+ * @va: vring virtual address
+ * @io: pointer to vring I/O region
+ * @num_desc: number of descriptors
+ * @align: vring alignment
+ *
+ * return 0 for success, negative value for failure.
+ */
+int rproc_virtio_init_vring(struct virtio_device *vdev, unsigned int index,
+ unsigned int notifyid, void *va,
+ struct metal_io_region *io,
+ unsigned int num_descs, unsigned int align);
+
+/**
+ * rproc_virtio_notified
+ *
+ * remoteproc virtio is got notified
+ *
+ * @vdev - pointer to the virtio device
+ * @notifyid - notify id
+ *
+ * return 0 for successful, negative value for failure
+ */
+int rproc_virtio_notified(struct virtio_device *vdev, uint32_t notifyid);
+
+/**
+ * rproc_virtio_wait_remote_ready
+ *
+ * Blocking function, waiting for the remote core is ready to start
+ * communications.
+ *
+ * @vdev - pointer to the virtio device
+ *
+ * return true when remote processor is ready.
+ */
+void rproc_virtio_wait_remote_ready(struct virtio_device *vdev);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* REMOTEPROC_VIRTIO_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg.h
new file mode 100644
index 0000000..6f24243
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg.h
@@ -0,0 +1,358 @@
+/*
+ * Remote processor messaging
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011 Google, Inc.
+ * All rights reserved.
+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RPMSG_H_
+#define _RPMSG_H_
+
+#include <openamp/compiler.h>
+#include <metal/mutex.h>
+#include <metal/list.h>
+#include <metal/utilities.h>
+#include <string.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* Configurable parameters */
+#define RPMSG_NAME_SIZE (32)
+#define RPMSG_ADDR_BMP_SIZE (128)
+
+#define RPMSG_NS_EPT_ADDR (0x35)
+#define RPMSG_ADDR_ANY 0xFFFFFFFF
+
+/* Error macros. */
+#define RPMSG_SUCCESS 0
+#define RPMSG_ERROR_BASE -2000
+#define RPMSG_ERR_NO_MEM (RPMSG_ERROR_BASE - 1)
+#define RPMSG_ERR_NO_BUFF (RPMSG_ERROR_BASE - 2)
+#define RPMSG_ERR_PARAM (RPMSG_ERROR_BASE - 3)
+#define RPMSG_ERR_DEV_STATE (RPMSG_ERROR_BASE - 4)
+#define RPMSG_ERR_BUFF_SIZE (RPMSG_ERROR_BASE - 5)
+#define RPMSG_ERR_INIT (RPMSG_ERROR_BASE - 6)
+#define RPMSG_ERR_ADDR (RPMSG_ERROR_BASE - 7)
+
+struct rpmsg_endpoint;
+struct rpmsg_device;
+
+typedef int (*rpmsg_ept_cb)(struct rpmsg_endpoint *ept, void *data,
+ size_t len, uint32_t src, void *priv);
+typedef void (*rpmsg_ns_unbind_cb)(struct rpmsg_endpoint *ept);
+typedef void (*rpmsg_ns_bind_cb)(struct rpmsg_device *rdev,
+ const char *name, uint32_t dest);
+
+/**
+ * struct rpmsg_endpoint - binds a local rpmsg address to its user
+ * @name:name of the service supported
+ * @rdev: pointer to the rpmsg device
+ * @addr: local address of the endpoint
+ * @dest_addr: address of the default remote endpoint binded.
+ * @cb: user rx callback, return value of this callback is reserved
+ * for future use, for now, only allow RPMSG_SUCCESS as return value.
+ * @ns_unbind_cb: end point service service unbind callback, called when remote
+ * ept is destroyed.
+ * @node: end point node.
+ * @addr: local rpmsg address
+ * @priv: private data for the driver's use
+ *
+ * In essence, an rpmsg endpoint represents a listener on the rpmsg bus, as
+ * it binds an rpmsg address with an rx callback handler.
+ */
+struct rpmsg_endpoint {
+ char name[RPMSG_NAME_SIZE];
+ struct rpmsg_device *rdev;
+ uint32_t addr;
+ uint32_t dest_addr;
+ rpmsg_ept_cb cb;
+ rpmsg_ns_unbind_cb ns_unbind_cb;
+ struct metal_list node;
+ void *priv;
+};
+
+/**
+ * struct rpmsg_device_ops - RPMsg device operations
+ * @send_offchannel_raw: send RPMsg data
+ */
+struct rpmsg_device_ops {
+ int (*send_offchannel_raw)(struct rpmsg_device *rdev,
+ uint32_t src, uint32_t dst,
+ const void *data, int size, int wait);
+};
+
+/**
+ * struct rpmsg_device - representation of a RPMsg device
+ * @endpoints: list of endpoints
+ * @ns_ept: name service endpoint
+ * @bitmap: table endpoin address allocation.
+ * @lock: mutex lock for rpmsg management
+ * @ns_bind_cb: callback handler for name service announcement without local
+ * endpoints waiting to bind.
+ * @ops: RPMsg device operations
+ */
+struct rpmsg_device {
+ struct metal_list endpoints;
+ struct rpmsg_endpoint ns_ept;
+ unsigned long bitmap[metal_bitmap_longs(RPMSG_ADDR_BMP_SIZE)];
+ metal_mutex_t lock;
+ rpmsg_ns_bind_cb ns_bind_cb;
+ struct rpmsg_device_ops ops;
+};
+
+/**
+ * rpmsg_send_offchannel_raw() - send a message across to the remote processor,
+ * specifying source and destination address.
+ * @ept: the rpmsg endpoint
+ * @data: payload of the message
+ * @len: length of the payload
+ *
+ * This function sends @data of length @len to the remote @dst address from
+ * the source @src address.
+ * The message will be sent to the remote processor which the channel belongs
+ * to.
+ * In case there are no TX buffers available, the function will block until
+ * one becomes available, or a timeout of 15 seconds elapses. When the latter
+ * happens, -ERESTARTSYS is returned.
+ *
+ * Returns number of bytes it has sent or negative error value on failure.
+ */
+int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src,
+ uint32_t dst, const void *data, int size,
+ int wait);
+
+/**
+ * rpmsg_send() - send a message across to the remote processor
+ * @ept: the rpmsg endpoint
+ * @data: payload of the message
+ * @len: length of the payload
+ *
+ * This function sends @data of length @len based on the @ept.
+ * The message will be sent to the remote processor which the channel belongs
+ * to, using @ept's source and destination addresses.
+ * In case there are no TX buffers available, the function will block until
+ * one becomes available, or a timeout of 15 seconds elapses. When the latter
+ * happens, -ERESTARTSYS is returned.
+ *
+ * Returns number of bytes it has sent or negative error value on failure.
+ */
+static inline int rpmsg_send(struct rpmsg_endpoint *ept, const void *data,
+ int len)
+{
+ if (ept->dest_addr == RPMSG_ADDR_ANY)
+ return RPMSG_ERR_ADDR;
+ return rpmsg_send_offchannel_raw(ept, ept->addr, ept->dest_addr, data,
+ len, true);
+}
+
+/**
+ * rpmsg_sendto() - send a message across to the remote processor, specify dst
+ * @ept: the rpmsg endpoint
+ * @data: payload of message
+ * @len: length of payload
+ * @dst: destination address
+ *
+ * This function sends @data of length @len to the remote @dst address.
+ * The message will be sent to the remote processor which the @ept
+ * channel belongs to, using @ept's source address.
+ * In case there are no TX buffers available, the function will block until
+ * one becomes available, or a timeout of 15 seconds elapses. When the latter
+ * happens, -ERESTARTSYS is returned.
+ *
+ * Returns number of bytes it has sent or negative error value on failure.
+ */
+static inline int rpmsg_sendto(struct rpmsg_endpoint *ept, const void *data,
+ int len, uint32_t dst)
+{
+ return rpmsg_send_offchannel_raw(ept, ept->addr, dst, data, len, true);
+}
+
+/**
+ * rpmsg_send_offchannel() - send a message using explicit src/dst addresses
+ * @ept: the rpmsg endpoint
+ * @src: source address
+ * @dst: destination address
+ * @data: payload of message
+ * @len: length of payload
+ *
+ * This function sends @data of length @len to the remote @dst address,
+ * and uses @src as the source address.
+ * The message will be sent to the remote processor which the @ept
+ * channel belongs to.
+ * In case there are no TX buffers available, the function will block until
+ * one becomes available, or a timeout of 15 seconds elapses. When the latter
+ * happens, -ERESTARTSYS is returned.
+ *
+ * Returns number of bytes it has sent or negative error value on failure.
+ */
+static inline int rpmsg_send_offchannel(struct rpmsg_endpoint *ept,
+ uint32_t src, uint32_t dst,
+ const void *data, int len)
+{
+ return rpmsg_send_offchannel_raw(ept, src, dst, data, len, true);
+}
+
+/**
+ * rpmsg_trysend() - send a message across to the remote processor
+ * @ept: the rpmsg endpoint
+ * @data: payload of message
+ * @len: length of payload
+ *
+ * This function sends @data of length @len on the @ept channel.
+ * The message will be sent to the remote processor which the @ept
+ * channel belongs to, using @ept's source and destination addresses.
+ * In case there are no TX buffers available, the function will immediately
+ * return -ENOMEM without waiting until one becomes available.
+ *
+ * Returns number of bytes it has sent or negative error value on failure.
+ */
+static inline int rpmsg_trysend(struct rpmsg_endpoint *ept, const void *data,
+ int len)
+{
+ if (ept->dest_addr == RPMSG_ADDR_ANY)
+ return RPMSG_ERR_ADDR;
+ return rpmsg_send_offchannel_raw(ept, ept->addr, ept->dest_addr, data,
+ len, false);
+}
+
+/**
+ * rpmsg_trysendto() - send a message across to the remote processor,
+ * specify dst
+ * @ept: the rpmsg endpoint
+ * @data: payload of message
+ * @len: length of payload
+ * @dst: destination address
+ *
+ * This function sends @data of length @len to the remote @dst address.
+ * The message will be sent to the remote processor which the @ept
+ * channel belongs to, using @ept's source address.
+ * In case there are no TX buffers available, the function will immediately
+ * return -ENOMEM without waiting until one becomes available.
+ *
+ * Returns number of bytes it has sent or negative error value on failure.
+ */
+static inline int rpmsg_trysendto(struct rpmsg_endpoint *ept, const void *data,
+ int len, uint32_t dst)
+{
+ return rpmsg_send_offchannel_raw(ept, ept->addr, dst, data, len, false);
+}
+
+/**
+ * rpmsg_trysend_offchannel() - send a message using explicit src/dst addresses
+ * @ept: the rpmsg endpoint
+ * @src: source address
+ * @dst: destination address
+ * @data: payload of message
+ * @len: length of payload
+ *
+ * This function sends @data of length @len to the remote @dst address,
+ * and uses @src as the source address.
+ * The message will be sent to the remote processor which the @ept
+ * channel belongs to.
+ * In case there are no TX buffers available, the function will immediately
+ * return -ENOMEM without waiting until one becomes available.
+ *
+ * Returns number of bytes it has sent or negative error value on failure.
+ */
+static inline int rpmsg_trysend_offchannel(struct rpmsg_endpoint *ept,
+ uint32_t src, uint32_t dst,
+ const void *data, int len)
+{
+ return rpmsg_send_offchannel_raw(ept, src, dst, data, len, false);
+}
+
+/**
+ * rpmsg_init_ept - initialize rpmsg endpoint
+ *
+ * Initialize an RPMsg endpoint with a name, source address,
+ * remoteproc address, endpoitn callback, and destroy endpoint callback.
+ *
+ * @ept: pointer to rpmsg endpoint
+ * @name: service name associated to the endpoint
+ * @src: local address of the endpoint
+ * @dest: target address of the endpoint
+ * @cb: endpoint callback
+ * @ns_unbind_cb: end point service unbind callback, called when remote ept is
+ * destroyed.
+ */
+static inline void rpmsg_init_ept(struct rpmsg_endpoint *ept,
+ const char *name,
+ uint32_t src, uint32_t dest,
+ rpmsg_ept_cb cb,
+ rpmsg_ns_unbind_cb ns_unbind_cb)
+{
+ strncpy(ept->name, name, sizeof(ept->name));
+ ept->addr = src;
+ ept->dest_addr = dest;
+ ept->cb = cb;
+ ept->ns_unbind_cb = ns_unbind_cb;
+}
+
+/**
+ * rpmsg_create_ept - create rpmsg endpoint and register it to rpmsg device
+ *
+ * Create a RPMsg endpoint, initialize it with a name, source address,
+ * remoteproc address, endpoitn callback, and destroy endpoint callback,
+ * and register it to the RPMsg device.
+ *
+ * @ept: pointer to rpmsg endpoint
+ * @name: service name associated to the endpoint
+ * @src: local address of the endpoint
+ * @dest: target address of the endpoint
+ * @cb: endpoint callback
+ * @ns_unbind_cb: end point service unbind callback, called when remote ept is
+ * destroyed.
+ *
+ * In essence, an rpmsg endpoint represents a listener on the rpmsg bus, as
+ * it binds an rpmsg address with an rx callback handler.
+ *
+ * Rpmsg client should create an endpoint to discuss with remote. rpmsg client
+ * provide at least a channel name, a callback for message notification and by
+ * default endpoint source address should be set to RPMSG_ADDR_ANY.
+ *
+ * As an option Some rpmsg clients can specify an endpoint with a specific
+ * source address.
+ */
+
+int rpmsg_create_ept(struct rpmsg_endpoint *ept, struct rpmsg_device *rdev,
+ const char *name, uint32_t src, uint32_t dest,
+ rpmsg_ept_cb cb, rpmsg_ns_unbind_cb ns_unbind_cb);
+
+/**
+ * rpmsg_destroy_ept - destroy rpmsg endpoint and unregister it from rpmsg
+ * device
+ *
+ * @ept: pointer to the rpmsg endpoint
+ *
+ * It unregisters the rpmsg endpoint from the rpmsg device and calls the
+ * destroy endpoint callback if it is provided.
+ */
+void rpmsg_destroy_ept(struct rpmsg_endpoint *ept);
+
+/**
+ * is_rpmsg_ept_ready - check if the rpmsg endpoint ready to send
+ *
+ * @ept: pointer to rpmsg endpoint
+ *
+ * Returns 1 if the rpmsg endpoint has both local addr and destination
+ * addr set, 0 otherwise
+ */
+static inline unsigned int is_rpmsg_ept_ready(struct rpmsg_endpoint *ept)
+{
+ return (ept->dest_addr != RPMSG_ADDR_ANY &&
+ ept->addr != RPMSG_ADDR_ANY);
+}
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* _RPMSG_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_retarget.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_retarget.h
new file mode 100644
index 0000000..0df3a79
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_retarget.h
@@ -0,0 +1,119 @@
+#ifndef RPMSG_RETARGET_H
+#define RPMSG_RETARGET_H
+
+#include <metal/mutex.h>
+#include <openamp/open_amp.h>
+#include <stdint.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* File Operations System call definitions */
+#define OPEN_SYSCALL_ID 0x1UL
+#define CLOSE_SYSCALL_ID 0x2UL
+#define WRITE_SYSCALL_ID 0x3UL
+#define READ_SYSCALL_ID 0x4UL
+#define ACK_STATUS_ID 0x5UL
+
+#define TERM_SYSCALL_ID 0x6UL
+
+#define DEFAULT_PROXY_ENDPOINT 0xFFUL
+
+struct rpmsg_rpc_data;
+
+typedef int (*rpmsg_rpc_poll)(void *arg);
+typedef void (*rpmsg_rpc_shutdown_cb)(struct rpmsg_rpc_data *rpc);
+
+struct rpmsg_rpc_syscall_header {
+ int32_t int_field1;
+ int32_t int_field2;
+ uint32_t data_len;
+};
+
+struct rpmsg_rpc_syscall {
+ uint32_t id;
+ struct rpmsg_rpc_syscall_header args;
+};
+
+struct rpmsg_rpc_data {
+ struct rpmsg_endpoint ept;
+ int ept_destroyed;
+ atomic_int nacked;
+ void *respbuf;
+ size_t respbuf_len;
+ rpmsg_rpc_poll poll;
+ void *poll_arg;
+ rpmsg_rpc_shutdown_cb shutdown_cb;
+ metal_mutex_t lock;
+ struct metal_spinlock buflock;
+};
+
+/**
+ * rpmsg_rpc_init - initialize RPMsg remote procedure call
+ *
+ * This function is to intialize the remote procedure call
+ * global data. RPMsg RPC will send request to remote and
+ * wait for callback.
+ *
+ * @rpc: pointer to the global remote procedure call data
+ * @rdev: pointer to the rpmsg device
+ * @ept_name: name of the endpoint used by RPC
+ * @ept_addr: address of the endpoint used by RPC
+ * @ept_raddr: remote address of the endpoint used by RPC
+ * @poll_arg: pointer to poll function argument
+ * @poll: poll function
+ * @shutdown_cb: shutdown callback function
+ *
+ * return 0 for success, and negative value for failure.
+ */
+int rpmsg_rpc_init(struct rpmsg_rpc_data *rpc,
+ struct rpmsg_device *rdev,
+ const char *ept_name, uint32_t ept_addr,
+ uint32_t ept_raddr,
+ void *poll_arg, rpmsg_rpc_poll poll,
+ rpmsg_rpc_shutdown_cb shutdown_cb);
+
+/**
+ * rpmsg_rpc_release - release RPMsg remote procedure call
+ *
+ * This function is to release remoteproc procedure call
+ * global data.
+ *
+ * @rpc: pointer to the globacl remote procedure call
+ */
+void rpmsg_rpc_release(struct rpmsg_rpc_data *rpc);
+
+/**
+ * rpmsg_rpc_send - Request RPMsg RPC call
+ *
+ * This function sends RPC request it will return with the length
+ * of data and the response buffer.
+ *
+ * @rpc: pointer to remoteproc procedure call data struct
+ * @req: pointer to request buffer
+ * @len: length of the request data
+ * @resp: pointer to where store the response buffer
+ * @resp_len: length of the response buffer
+ *
+ * return length of the received response, negative value for failure.
+ */
+int rpmsg_rpc_send(struct rpmsg_rpc_data *rpc,
+ void *req, size_t len,
+ void *resp, size_t resp_len);
+
+/**
+ * rpmsg_set_default_rpc - set default RPMsg RPC data
+ *
+ * The default RPC data is used to redirect standard C file operations
+ * to RPMsg channels.
+ *
+ * @rpc: pointer to remoteproc procedure call data struct
+ */
+void rpmsg_set_default_rpc(struct rpmsg_rpc_data *rpc);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* RPMSG_RETARGET_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_virtio.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_virtio.h
new file mode 100644
index 0000000..ea0a255
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rpmsg_virtio.h
@@ -0,0 +1,190 @@
+/*
+ * rpmsg based on virtio
+ *
+ * Copyright (C) 2018 Linaro, Inc.
+ *
+ * All rights reserved.
+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RPMSG_VIRTIO_H_
+#define _RPMSG_VIRTIO_H_
+
+#include <metal/io.h>
+#include <metal/mutex.h>
+#include <openamp/rpmsg.h>
+#include <openamp/virtio.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* Configurable parameters */
+#ifndef RPMSG_BUFFER_SIZE
+#define RPMSG_BUFFER_SIZE (512)
+#endif
+
+/* The feature bitmap for virtio rpmsg */
+#define VIRTIO_RPMSG_F_NS 0 /* RP supports name service notifications */
+
+struct rpmsg_virtio_shm_pool;
+/**
+ * struct rpmsg_virtio_shm_pool - shared memory pool used for rpmsg buffers
+ * @get_buffer: function to get buffer from the pool
+ * @base: base address of the memory pool
+ * @avail: available memory size
+ * @size: total pool size
+ */
+struct rpmsg_virtio_shm_pool {
+ void *base;
+ size_t avail;
+ size_t size;
+};
+
+/**
+ * struct rpmsg_virtio_device - representation of a rpmsg device based on virtio
+ * @rdev: rpmsg device, first property in the struct
+ * @vdev: pointer to the virtio device
+ * @rvq: pointer to receive virtqueue
+ * @svq: pointer to send virtqueue
+ * @shbuf_io: pointer to the shared buffer I/O region
+ * @shpool: pointer to the shared buffers pool
+ * @endpoints: list of endpoints.
+ */
+struct rpmsg_virtio_device {
+ struct rpmsg_device rdev;
+ struct virtio_device *vdev;
+ struct virtqueue *rvq;
+ struct virtqueue *svq;
+ struct metal_io_region *shbuf_io;
+ struct rpmsg_virtio_shm_pool *shpool;
+};
+
+#define RPMSG_REMOTE VIRTIO_DEV_SLAVE
+#define RPMSG_MASTER VIRTIO_DEV_MASTER
+static inline unsigned int
+ rpmsg_virtio_get_role(struct rpmsg_virtio_device *rvdev)
+{
+ return rvdev->vdev->role;
+}
+
+static inline void rpmsg_virtio_set_status(struct rpmsg_virtio_device *rvdev,
+ uint8_t status)
+{
+ rvdev->vdev->func->set_status(rvdev->vdev, status);
+}
+
+static inline uint8_t rpmsg_virtio_get_status(struct rpmsg_virtio_device *rvdev)
+{
+ return rvdev->vdev->func->get_status(rvdev->vdev);
+}
+
+static inline uint32_t
+ rpmsg_virtio_get_features(struct rpmsg_virtio_device *rvdev)
+{
+ return rvdev->vdev->func->get_features(rvdev->vdev);
+}
+
+static inline int
+ rpmsg_virtio_create_virtqueues(struct rpmsg_virtio_device *rvdev,
+ int flags, unsigned int nvqs,
+ const char *names[],
+ vq_callback * callbacks[])
+{
+ return virtio_create_virtqueues(rvdev->vdev, flags, nvqs, names,
+ callbacks);
+}
+
+/**
+ * rpmsg_virtio_get_buffer_size - get rpmsg virtio buffer size
+ *
+ * @rdev - pointer to the rpmsg device
+ *
+ * @return - next available buffer size for text, negative value for failure
+ */
+int rpmsg_virtio_get_buffer_size(struct rpmsg_device *rdev);
+
+/**
+ * rpmsg_init_vdev - initialize rpmsg virtio device
+ * Master side:
+ * Initialize RPMsg virtio queues and shared buffers, the address of shm can be
+ * ANY. In this case, function will get shared memory from system shared memory
+ * pools. If the vdev has RPMsg name service feature, this API will create an
+ * name service endpoint.
+ *
+ * Slave side:
+ * This API will not return until the driver ready is set by the master side.
+ *
+ * @param rvdev - pointer to the rpmsg virtio device
+ * @param vdev - pointer to the virtio device
+ * @param ns_bind_cb - callback handler for name service announcement without
+ * local endpoints waiting to bind.
+ * @param shm_io - pointer to the share memory I/O region.
+ * @param shpool - pointer to shared memory pool. rpmsg_virtio_init_shm_pool has
+ * to be called first to fill this structure.
+ *
+ * @return - status of function execution
+ */
+int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev,
+ struct virtio_device *vdev,
+ rpmsg_ns_bind_cb ns_bind_cb,
+ struct metal_io_region *shm_io,
+ struct rpmsg_virtio_shm_pool *shpool);
+
+/**
+ * rpmsg_deinit_vdev - deinitialize rpmsg virtio device
+ *
+ * @param rvdev - pointer to the rpmsg virtio device
+ */
+void rpmsg_deinit_vdev(struct rpmsg_virtio_device *rvdev);
+
+/**
+ * rpmsg_virtio_init_shm_pool - initialize default shared buffers pool
+ *
+ * RPMsg virtio has default shared buffers pool implementation.
+ * The memory assigned to this pool will be dedicated to the RPMsg
+ * virtio. This function has to be called before calling rpmsg_init_vdev,
+ * to initialize the rpmsg_virtio_shm_pool structure.
+ *
+ * @param shpool - pointer to the shared buffers pool structure
+ * @param shbuf - pointer to the beginning of shared buffers
+ * @param size - shared buffers total size
+ */
+void rpmsg_virtio_init_shm_pool(struct rpmsg_virtio_shm_pool *shpool,
+ void *shbuf, size_t size);
+
+/**
+ * rpmsg_virtio_get_rpmsg_device - get RPMsg device from RPMsg virtio device
+ *
+ * @param rvdev - pointer to RPMsg virtio device
+ * @return - RPMsg device pointed by RPMsg virtio device
+ */
+static inline struct rpmsg_device *
+rpmsg_virtio_get_rpmsg_device(struct rpmsg_virtio_device *rvdev)
+{
+ return &rvdev->rdev;
+}
+
+/**
+ * rpmsg_virtio_shm_pool_get_buffer - get buffer in the shared memory pool
+ *
+ * RPMsg virtio has default shared buffers pool implementation.
+ * The memory assigned to this pool will be dedicated to the RPMsg
+ * virtio. If you prefer to have other shared buffers allocation,
+ * you can implement your rpmsg_virtio_shm_pool_get_buffer function.
+ *
+ * @param shpool - pointer to the shared buffers pool
+ * @param size - shared buffers total size
+ * @return - buffer pointer if free buffer is available, NULL otherwise.
+ */
+metal_weak void *
+rpmsg_virtio_shm_pool_get_buffer(struct rpmsg_virtio_shm_pool *shpool,
+ size_t size);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* _RPMSG_VIRTIO_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rsc_table_parser.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rsc_table_parser.h
new file mode 100644
index 0000000..6802d03
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/rsc_table_parser.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RSC_TABLE_PARSER_H
+#define RSC_TABLE_PARSER_H
+
+#include <openamp/remoteproc.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+#define RSC_TAB_SUPPORTED_VERSION 1
+#define RSC_TAB_HEADER_SIZE 12
+#define RSC_TAB_MAX_VRINGS 2
+
+/* Standard control request handling. */
+typedef int (*rsc_handler) (struct remoteproc *rproc, void *rsc);
+
+/**
+ * handle_rsc_table
+ *
+ * This function parses resource table.
+ *
+ * @param rproc - pointer to remote remoteproc
+ * @param rsc_table - resource table to parse
+ * @param size - size of rsc table
+ * @param io - pointer to the resource table I/O region
+ * It can be NULL if the resource table
+ * is in the local memory.
+ *
+ * @returns - execution status
+ *
+ */
+int handle_rsc_table(struct remoteproc *rproc,
+ struct resource_table *rsc_table, int len,
+ struct metal_io_region *io);
+int handle_carve_out_rsc(struct remoteproc *rproc, void *rsc);
+int handle_trace_rsc(struct remoteproc *rproc, void *rsc);
+int handle_vdev_rsc(struct remoteproc *rproc, void *rsc);
+int handle_vendor_rsc(struct remoteproc *rproc, void *rsc);
+
+/**
+ * find_rsc
+ *
+ * find out location of a resource type in the resource table.
+ *
+ * @rsc_table - pointer to the resource table
+ * @rsc_type - type of the resource
+ * @index - index of the resource of the specified type
+ *
+ * return the offset to the resource on success, or 0 on failure
+ */
+size_t find_rsc(void *rsc_table, unsigned int rsc_type, unsigned int index);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* RSC_TABLE_PARSER_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio.h
new file mode 100644
index 0000000..51a4740
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio.h
@@ -0,0 +1,176 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _VIRTIO_H_
+#define _VIRTIO_H_
+
+#include <openamp/virtqueue.h>
+#include <metal/spinlock.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* TODO: define this as compiler flags */
+#ifndef VIRTIO_MAX_NUM_VRINGS
+#define VIRTIO_MAX_NUM_VRINGS 2
+#endif
+
+/* VirtIO device IDs. */
+#define VIRTIO_ID_NETWORK 0x01UL
+#define VIRTIO_ID_BLOCK 0x02UL
+#define VIRTIO_ID_CONSOLE 0x03UL
+#define VIRTIO_ID_ENTROPY 0x04UL
+#define VIRTIO_ID_BALLOON 0x05UL
+#define VIRTIO_ID_IOMEMORY 0x06UL
+#define VIRTIO_ID_RPMSG 0x07UL /* remote processor messaging */
+#define VIRTIO_ID_SCSI 0x08UL
+#define VIRTIO_ID_9P 0x09UL
+#define VIRTIO_DEV_ANY_ID (-1)UL
+
+/* Status byte for guest to report progress. */
+#define VIRTIO_CONFIG_STATUS_ACK 0x01
+#define VIRTIO_CONFIG_STATUS_DRIVER 0x02
+#define VIRTIO_CONFIG_STATUS_DRIVER_OK 0x04
+#define VIRTIO_CONFIG_STATUS_NEEDS_RESET 0x40
+#define VIRTIO_CONFIG_STATUS_FAILED 0x80
+
+/* Virtio device role */
+#define VIRTIO_DEV_MASTER 0UL
+#define VIRTIO_DEV_SLAVE 1UL
+
+struct virtio_device_id {
+ uint32_t device;
+ uint32_t vendor;
+};
+
+/*
+ * Generate interrupt when the virtqueue ring is
+ * completely used, even if we've suppressed them.
+ */
+#define VIRTIO_F_NOTIFY_ON_EMPTY (1 << 24)
+
+/*
+ * The guest should never negotiate this feature; it
+ * is used to detect faulty drivers.
+ */
+#define VIRTIO_F_BAD_FEATURE (1 << 30)
+
+/*
+ * Some VirtIO feature bits (currently bits 28 through 31) are
+ * reserved for the transport being used (eg. virtio_ring), the
+ * rest are per-device feature bits.
+ */
+#define VIRTIO_TRANSPORT_F_START 28
+#define VIRTIO_TRANSPORT_F_END 32
+
+typedef void (*virtio_dev_reset_cb)(struct virtio_device *vdev);
+
+struct virtio_dispatch;
+
+struct virtio_feature_desc {
+ uint32_t vfd_val;
+ const char *vfd_str;
+};
+
+/**
+ * struct proc_shm
+ *
+ * This structure is maintained by hardware interface layer for
+ * shared memory information. The shared memory provides buffers
+ * for use by the vring to exchange messages between the cores.
+ *
+ */
+struct virtio_buffer_info {
+ /* Start address of shared memory used for buffers. */
+ void *vaddr;
+ /* Start physical address of shared memory used for buffers. */
+ metal_phys_addr_t paddr;
+ /* sharmed memory I/O region */
+ struct metal_io_region *io;
+ /* Size of shared memory. */
+ unsigned long size;
+};
+
+/**
+ * struct remoteproc_vring - remoteproc vring structure
+ * @vq virtio queue
+ * @va logical address
+ * @notifyid vring notify id
+ * @num_descs number of descriptors
+ * @align vring alignment
+ * @io metal I/O region of the vring memory, can be NULL
+ */
+struct virtio_vring_info {
+ struct virtqueue *vq;
+ struct vring_alloc_info info;
+ uint32_t notifyid;
+ struct metal_io_region *io;
+};
+
+/*
+ * Structure definition for virtio devices for use by the
+ * applications/drivers
+ */
+
+struct virtio_device {
+ uint32_t index; /**< unique position on the virtio bus */
+ struct virtio_device_id id; /**< the device type identification
+ * (used to match it with a driver
+ */
+ uint64_t features; /**< the features supported by both ends. */
+ unsigned int role; /**< if it is virtio backend or front end. */
+ virtio_dev_reset_cb reset_cb; /**< user registered device callback */
+ const struct virtio_dispatch *func; /**< Virtio dispatch table */
+ void *priv; /**< TODO: remove pointer to virtio_device private data */
+ unsigned int vrings_num; /**< number of vrings */
+ struct virtio_vring_info *vrings_info;
+};
+
+/*
+ * Helper functions.
+ */
+const char *virtio_dev_name(uint16_t devid);
+void virtio_describe(struct virtio_device *dev, const char *msg,
+ uint32_t features,
+ struct virtio_feature_desc *feature_desc);
+
+/*
+ * Functions for virtio device configuration as defined in Rusty Russell's
+ * paper.
+ * Drivers are expected to implement these functions in their respective codes.
+ */
+
+struct virtio_dispatch {
+ uint8_t (*get_status)(struct virtio_device *dev);
+ void (*set_status)(struct virtio_device *dev, uint8_t status);
+ uint32_t (*get_features)(struct virtio_device *dev);
+ void (*set_features)(struct virtio_device *dev, uint32_t feature);
+ uint32_t (*negotiate_features)(struct virtio_device *dev,
+ uint32_t features);
+
+ /*
+ * Read/write a variable amount from the device specific (ie, network)
+ * configuration region. This region is encoded in the same endian as
+ * the guest.
+ */
+ void (*read_config)(struct virtio_device *dev, uint32_t offset,
+ void *dst, int length);
+ void (*write_config)(struct virtio_device *dev, uint32_t offset,
+ void *src, int length);
+ void (*reset_device)(struct virtio_device *dev);
+ void (*notify)(struct virtqueue *vq);
+};
+
+int virtio_create_virtqueues(struct virtio_device *vdev, unsigned int flags,
+ unsigned int nvqs, const char *names[],
+ vq_callback *callbacks[]);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* _VIRTIO_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio_ring.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio_ring.h
new file mode 100644
index 0000000..3f348e3
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtio_ring.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright Rusty Russell IBM Corporation 2007.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * $FreeBSD$
+ */
+
+#ifndef VIRTIO_RING_H
+#define VIRTIO_RING_H
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+/* This marks a buffer as continuing via the next field. */
+#define VRING_DESC_F_NEXT 1
+/* This marks a buffer as write-only (otherwise read-only). */
+#define VRING_DESC_F_WRITE 2
+/* This means the buffer contains a list of buffer descriptors. */
+#define VRING_DESC_F_INDIRECT 4
+
+/* The Host uses this in used->flags to advise the Guest: don't kick me
+ * when you add a buffer. It's unreliable, so it's simply an
+ * optimization. Guest will still kick if it's out of buffers.
+ */
+#define VRING_USED_F_NO_NOTIFY 1
+/* The Guest uses this in avail->flags to advise the Host: don't
+ * interrupt me when you consume a buffer. It's unreliable, so it's
+ * simply an optimization.
+ */
+#define VRING_AVAIL_F_NO_INTERRUPT 1
+
+/* VirtIO ring descriptors: 16 bytes.
+ * These can chain together via "next".
+ */
+struct vring_desc {
+ /* Address (guest-physical). */
+ uint64_t addr;
+ /* Length. */
+ uint32_t len;
+ /* The flags as indicated above. */
+ uint16_t flags;
+ /* We chain unused descriptors via this, too. */
+ uint16_t next;
+};
+
+struct vring_avail {
+ uint16_t flags;
+ uint16_t idx;
+ uint16_t ring[0];
+};
+
+/* uint32_t is used here for ids for padding reasons. */
+struct vring_used_elem {
+ /* Index of start of used descriptor chain. */
+ uint32_t id;
+ /* Total length of the descriptor chain which was written to. */
+ uint32_t len;
+};
+
+struct vring_used {
+ uint16_t flags;
+ uint16_t idx;
+ struct vring_used_elem ring[0];
+};
+
+struct vring {
+ unsigned int num;
+
+ struct vring_desc *desc;
+ struct vring_avail *avail;
+ struct vring_used *used;
+};
+
+/* The standard layout for the ring is a continuous chunk of memory which
+ * looks like this. We assume num is a power of 2.
+ *
+ * struct vring {
+ * // The actual descriptors (16 bytes each)
+ * struct vring_desc desc[num];
+ *
+ * // A ring of available descriptor heads with free-running index.
+ * __u16 avail_flags;
+ * __u16 avail_idx;
+ * __u16 available[num];
+ * __u16 used_event_idx;
+ *
+ * // Padding to the next align boundary.
+ * char pad[];
+ *
+ * // A ring of used descriptor heads with free-running index.
+ * __u16 used_flags;
+ * __u16 used_idx;
+ * struct vring_used_elem used[num];
+ * __u16 avail_event_idx;
+ * };
+ *
+ * NOTE: for VirtIO PCI, align is 4096.
+ */
+
+/*
+ * We publish the used event index at the end of the available ring, and vice
+ * versa. They are at the end for backwards compatibility.
+ */
+#define vring_used_event(vr) ((vr)->avail->ring[(vr)->num])
+#define vring_avail_event(vr) ((vr)->used->ring[(vr)->num].id & 0xFFFF)
+
+static inline int vring_size(unsigned int num, unsigned long align)
+{
+ int size;
+
+ size = num * sizeof(struct vring_desc);
+ size += sizeof(struct vring_avail) + (num * sizeof(uint16_t)) +
+ sizeof(uint16_t);
+ size = (size + align - 1) & ~(align - 1);
+ size += sizeof(struct vring_used) +
+ (num * sizeof(struct vring_used_elem)) + sizeof(uint16_t);
+
+ return size;
+}
+
+static inline void
+vring_init(struct vring *vr, unsigned int num, uint8_t *p, unsigned long align)
+{
+ vr->num = num;
+ vr->desc = (struct vring_desc *)p;
+ vr->avail = (struct vring_avail *)(p + num * sizeof(struct vring_desc));
+ vr->used = (struct vring_used *)
+ (((unsigned long)&vr->avail->ring[num] + sizeof(uint16_t) +
+ align - 1) & ~(align - 1));
+}
+
+/*
+ * The following is used with VIRTIO_RING_F_EVENT_IDX.
+ *
+ * Assuming a given event_idx value from the other size, if we have
+ * just incremented index from old to new_idx, should we trigger an
+ * event?
+ */
+static inline int
+vring_need_event(uint16_t event_idx, uint16_t new_idx, uint16_t old)
+{
+ return (uint16_t)(new_idx - event_idx - 1) <
+ (uint16_t)(new_idx - old);
+}
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* VIRTIO_RING_H */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtqueue.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtqueue.h
new file mode 100644
index 0000000..11aabf9
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/include/openamp/virtqueue.h
@@ -0,0 +1,236 @@
+#ifndef VIRTQUEUE_H_
+#define VIRTQUEUE_H_
+
+/*-
+ * Copyright (c) 2011, Bryan Venteicher <bryanv@FreeBSD.org>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * $FreeBSD$
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+typedef uint8_t boolean;
+
+#include <openamp/virtio_ring.h>
+#include <metal/alloc.h>
+#include <metal/io.h>
+
+/*Error Codes*/
+#define VQ_ERROR_BASE -3000
+#define ERROR_VRING_FULL (VQ_ERROR_BASE - 1)
+#define ERROR_INVLD_DESC_IDX (VQ_ERROR_BASE - 2)
+#define ERROR_EMPTY_RING (VQ_ERROR_BASE - 3)
+#define ERROR_NO_MEM (VQ_ERROR_BASE - 4)
+#define ERROR_VRING_MAX_DESC (VQ_ERROR_BASE - 5)
+#define ERROR_VRING_ALIGN (VQ_ERROR_BASE - 6)
+#define ERROR_VRING_NO_BUFF (VQ_ERROR_BASE - 7)
+#define ERROR_VQUEUE_INVLD_PARAM (VQ_ERROR_BASE - 8)
+
+#define VQUEUE_SUCCESS 0
+
+/* The maximum virtqueue size is 2^15. Use that value as the end of
+ * descriptor chain terminator since it will never be a valid index
+ * in the descriptor table. This is used to verify we are correctly
+ * handling vq_free_cnt.
+ */
+#define VQ_RING_DESC_CHAIN_END 32768
+#define VIRTQUEUE_FLAG_INDIRECT 0x0001
+#define VIRTQUEUE_FLAG_EVENT_IDX 0x0002
+#define VIRTQUEUE_MAX_NAME_SZ 32
+
+/* Support for indirect buffer descriptors. */
+#define VIRTIO_RING_F_INDIRECT_DESC (1 << 28)
+
+/* Support to suppress interrupt until specific index is reached. */
+#define VIRTIO_RING_F_EVENT_IDX (1 << 29)
+
+struct virtqueue_buf {
+ void *buf;
+ int len;
+};
+
+struct virtqueue {
+ struct virtio_device *vq_dev;
+ const char *vq_name;
+ uint16_t vq_queue_index;
+ uint16_t vq_nentries;
+ uint32_t vq_flags;
+ void (*callback)(struct virtqueue *vq);
+ void (*notify)(struct virtqueue *vq);
+ struct vring vq_ring;
+ uint16_t vq_free_cnt;
+ uint16_t vq_queued_cnt;
+ void *shm_io; /* opaque pointer to data needed to allow v2p & p2v */
+
+ /*
+ * Head of the free chain in the descriptor table. If
+ * there are no free descriptors, this will be set to
+ * VQ_RING_DESC_CHAIN_END.
+ */
+ uint16_t vq_desc_head_idx;
+
+ /*
+ * Last consumed descriptor in the used table,
+ * trails vq_ring.used->idx.
+ */
+ uint16_t vq_used_cons_idx;
+
+ /*
+ * Last consumed descriptor in the available table -
+ * used by the consumer side.
+ */
+ uint16_t vq_available_idx;
+
+#ifdef VQUEUE_DEBUG
+ boolean vq_inuse;
+#endif
+
+ /*
+ * Used by the host side during callback. Cookie
+ * holds the address of buffer received from other side.
+ * Other fields in this structure are not used currently.
+ */
+
+ struct vq_desc_extra {
+ void *cookie;
+ uint16_t ndescs;
+ } vq_descx[0];
+};
+
+/* struct to hold vring specific information */
+struct vring_alloc_info {
+ void *vaddr;
+ uint32_t align;
+ uint16_t num_descs;
+ uint16_t pad;
+};
+
+typedef void vq_callback(struct virtqueue *);
+typedef void vq_notify(struct virtqueue *);
+
+#ifdef VQUEUE_DEBUG
+#include <metal/log.h>
+#include <metal/assert.h>
+
+#define VQASSERT(_vq, _exp, _msg) \
+ do { \
+ if (!(_exp)) { \
+ metal_log(METAL_LOG_EMERGENCY, \
+ "%s: %s - _msg", __func__, (_vq)->vq_name); \
+ metal_assert(_exp); \
+ } \
+ } while (0)
+
+#define VQ_RING_ASSERT_VALID_IDX(_vq, _idx) \
+ VQASSERT((_vq), (_idx) < (_vq)->vq_nentries, "invalid ring index")
+
+#define VQ_RING_ASSERT_CHAIN_TERM(_vq) \
+ VQASSERT((_vq), (_vq)->vq_desc_head_idx == \
+ VQ_RING_DESC_CHAIN_END, \
+ "full ring terminated incorrectly: invalid head")
+
+#define VQ_PARAM_CHK(condition, status_var, status_err) \
+ do { \
+ if (((status_var) == 0) && (condition)) { \
+ status_var = status_err; \
+ } \
+ } while (0)
+
+#define VQUEUE_BUSY(vq) \
+ do { \
+ if (!(vq)->vq_inuse) \
+ (vq)->vq_inuse = true; \
+ else \
+ VQASSERT(vq, !(vq)->vq_inuse,\
+ "VirtQueue already in use") \
+ } while (0)
+
+#define VQUEUE_IDLE(vq) ((vq)->vq_inuse = false)
+
+#else
+
+#define KASSERT(cond, str)
+#define VQASSERT(_vq, _exp, _msg)
+#define VQ_RING_ASSERT_VALID_IDX(_vq, _idx)
+#define VQ_RING_ASSERT_CHAIN_TERM(_vq)
+#define VQ_PARAM_CHK(condition, status_var, status_err)
+#define VQUEUE_BUSY(vq)
+#define VQUEUE_IDLE(vq)
+
+#endif
+
+int virtqueue_create(struct virtio_device *device, unsigned short id,
+ const char *name, struct vring_alloc_info *ring,
+ void (*callback)(struct virtqueue *vq),
+ void (*notify)(struct virtqueue *vq),
+ struct virtqueue *v_queue);
+
+/*
+ * virtqueue_set_shmem_io
+ *
+ * set virtqueue shared memory I/O region
+ *
+ * @vq - virt queue
+ * @io - pointer to the shared memory I/O region
+ */
+static inline void virtqueue_set_shmem_io(struct virtqueue *vq,
+ struct metal_io_region *io)
+{
+ vq->shm_io = io;
+}
+
+int virtqueue_add_buffer(struct virtqueue *vq, struct virtqueue_buf *buf_list,
+ int readable, int writable, void *cookie);
+
+void *virtqueue_get_buffer(struct virtqueue *vq, uint32_t *len, uint16_t *idx);
+
+void *virtqueue_get_available_buffer(struct virtqueue *vq, uint16_t *avail_idx,
+ uint32_t *len);
+
+int virtqueue_add_consumed_buffer(struct virtqueue *vq, uint16_t head_idx,
+ uint32_t len);
+
+void virtqueue_disable_cb(struct virtqueue *vq);
+
+int virtqueue_enable_cb(struct virtqueue *vq);
+
+void virtqueue_kick(struct virtqueue *vq);
+
+static inline struct virtqueue *virtqueue_allocate(unsigned int num_desc_extra)
+{
+ struct virtqueue *vqs;
+ uint32_t vq_size = sizeof(struct virtqueue) +
+ num_desc_extra * sizeof(struct vq_desc_extra);
+
+ vqs = (struct virtqueue *)metal_allocate_memory(vq_size);
+
+ if (vqs) {
+ memset(vqs, 0x00, vq_size);
+ }
+
+ return vqs;
+}
+
+void virtqueue_free(struct virtqueue *vq);
+
+void virtqueue_dump(struct virtqueue *vq);
+
+void virtqueue_notification(struct virtqueue *vq);
+
+uint32_t virtqueue_get_desc_size(struct virtqueue *vq);
+
+uint32_t virtqueue_get_buffer_length(struct virtqueue *vq, uint16_t idx);
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* VIRTQUEUE_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/remoteproc/remoteproc_virtio.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/remoteproc/remoteproc_virtio.c
new file mode 100644
index 0000000..011a5ed
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/remoteproc/remoteproc_virtio.c
@@ -0,0 +1,330 @@
+/*
+ * Remoteproc Virtio Framework Implementation
+ *
+ * Copyright(c) 2018 Xilinx Ltd.
+ * Copyright(c) 2011 Texas Instruments, Inc.
+ * Copyright(c) 2011 Google, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name Texas Instruments nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <openamp/remoteproc.h>
+#include <openamp/remoteproc_virtio.h>
+#include <openamp/virtqueue.h>
+#include <metal/utilities.h>
+#include <metal/alloc.h>
+
+static void rproc_virtio_virtqueue_notify(struct virtqueue *vq)
+{
+ struct remoteproc_virtio *rpvdev;
+ struct virtio_vring_info *vring_info;
+ struct virtio_device *vdev;
+ unsigned int vq_id = vq->vq_queue_index;
+
+ vdev = vq->vq_dev;
+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev);
+ metal_assert(vq_id <= vdev->vrings_num);
+ vring_info = &vdev->vrings_info[vq_id];
+ rpvdev->notify(rpvdev->priv, vring_info->notifyid);
+}
+
+static unsigned char rproc_virtio_get_status(struct virtio_device *vdev)
+{
+ struct remoteproc_virtio *rpvdev;
+ struct fw_rsc_vdev *vdev_rsc;
+ struct metal_io_region *io;
+ char status;
+
+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev);
+ vdev_rsc = rpvdev->vdev_rsc;
+ io = rpvdev->vdev_rsc_io;
+ status = metal_io_read8(io,
+ metal_io_virt_to_offset(io, &vdev_rsc->status));
+ return status;
+}
+
+#ifndef VIRTIO_SLAVE_ONLY
+static void rproc_virtio_set_status(struct virtio_device *vdev,
+ unsigned char status)
+{
+ struct remoteproc_virtio *rpvdev;
+ struct fw_rsc_vdev *vdev_rsc;
+ struct metal_io_region *io;
+
+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev);
+ vdev_rsc = rpvdev->vdev_rsc;
+ io = rpvdev->vdev_rsc_io;
+ metal_io_write8(io,
+ metal_io_virt_to_offset(io, &vdev_rsc->status),
+ status);
+ rpvdev->notify(rpvdev->priv, vdev->index);
+}
+#endif
+
+static uint32_t rproc_virtio_get_features(struct virtio_device *vdev)
+{
+ struct remoteproc_virtio *rpvdev;
+ struct fw_rsc_vdev *vdev_rsc;
+ struct metal_io_region *io;
+ uint32_t features;
+
+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev);
+ vdev_rsc = rpvdev->vdev_rsc;
+ io = rpvdev->vdev_rsc_io;
+ /* TODO: shall we get features based on the role ? */
+ features = metal_io_read32(io,
+ metal_io_virt_to_offset(io, &vdev_rsc->dfeatures));
+
+ return features;
+}
+
+#ifndef VIRTIO_SLAVE_ONLY
+static void rproc_virtio_set_features(struct virtio_device *vdev,
+ uint32_t features)
+{
+ struct remoteproc_virtio *rpvdev;
+ struct fw_rsc_vdev *vdev_rsc;
+ struct metal_io_region *io;
+
+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev);
+ vdev_rsc = rpvdev->vdev_rsc;
+ io = rpvdev->vdev_rsc_io;
+ /* TODO: shall we set features based on the role ? */
+ metal_io_write32(io,
+ metal_io_virt_to_offset(io, &vdev_rsc->dfeatures),
+ features);
+ rpvdev->notify(rpvdev->priv, vdev->index);
+}
+#endif
+
+static uint32_t rproc_virtio_negotiate_features(struct virtio_device *vdev,
+ uint32_t features)
+{
+ (void)vdev;
+ (void)features;
+
+ return 0;
+}
+
+static void rproc_virtio_read_config(struct virtio_device *vdev,
+ uint32_t offset, void *dst, int length)
+{
+ (void)vdev;
+ (void)offset;
+ (void)dst;
+ (void)length;
+}
+
+#ifndef VIRTIO_SLAVE_ONLY
+static void rproc_virtio_write_config(struct virtio_device *vdev,
+ uint32_t offset, void *src, int length)
+{
+ (void)vdev;
+ (void)offset;
+ (void)src;
+ (void)length;
+}
+
+static void rproc_virtio_reset_device(struct virtio_device *vdev)
+{
+ if (vdev->role == VIRTIO_DEV_MASTER)
+ rproc_virtio_set_status(vdev,
+ VIRTIO_CONFIG_STATUS_NEEDS_RESET);
+}
+#endif
+
+const struct virtio_dispatch remoteproc_virtio_dispatch_funcs = {
+ .get_status = rproc_virtio_get_status,
+ .get_features = rproc_virtio_get_features,
+ .read_config = rproc_virtio_read_config,
+ .notify = rproc_virtio_virtqueue_notify,
+ .negotiate_features = rproc_virtio_negotiate_features,
+#ifndef VIRTIO_SLAVE_ONLY
+ /*
+ * We suppose here that the vdev is in a shared memory so that can
+ * be access only by one core: the master. In this case salve core has
+ * only read access right.
+ */
+ .set_status = rproc_virtio_set_status,
+ .set_features = rproc_virtio_set_features,
+ .write_config = rproc_virtio_write_config,
+ .reset_device = rproc_virtio_reset_device,
+#endif
+};
+
+struct virtio_device *
+rproc_virtio_create_vdev(unsigned int role, unsigned int notifyid,
+ void *rsc, struct metal_io_region *rsc_io,
+ void *priv,
+ rpvdev_notify_func notify,
+ virtio_dev_reset_cb rst_cb)
+{
+ struct remoteproc_virtio *rpvdev;
+ struct virtio_vring_info *vrings_info;
+ struct fw_rsc_vdev *vdev_rsc = rsc;
+ struct virtio_device *vdev;
+ unsigned int num_vrings = vdev_rsc->num_of_vrings;
+ unsigned int i;
+
+ rpvdev = metal_allocate_memory(sizeof(*rpvdev));
+ if (!rpvdev)
+ return NULL;
+ vrings_info = metal_allocate_memory(sizeof(*vrings_info) * num_vrings);
+ if (!vrings_info)
+ goto err0;
+ memset(rpvdev, 0, sizeof(*rpvdev));
+ memset(vrings_info, 0, sizeof(*vrings_info));
+ vdev = &rpvdev->vdev;
+
+ for (i = 0; i < num_vrings; i++) {
+ struct virtqueue *vq;
+ struct fw_rsc_vdev_vring *vring_rsc;
+ unsigned int num_extra_desc = 0;
+
+ vring_rsc = &vdev_rsc->vring[i];
+ if (role == VIRTIO_DEV_MASTER) {
+ num_extra_desc = vring_rsc->num;
+ }
+ vq = virtqueue_allocate(num_extra_desc);
+ if (!vq)
+ goto err1;
+ vrings_info[i].vq = vq;
+ }
+
+ /* FIXME commended as seems not nedded, already stored in vdev */
+ //rpvdev->notifyid = notifyid;
+ rpvdev->notify = notify;
+ rpvdev->priv = priv;
+ vdev->vrings_info = vrings_info;
+ /* Assuming the shared memory has been mapped and registered if
+ * necessary
+ */
+ rpvdev->vdev_rsc = vdev_rsc;
+ rpvdev->vdev_rsc_io = rsc_io;
+
+ vdev->index = notifyid;
+ vdev->role = role;
+ vdev->reset_cb = rst_cb;
+ vdev->vrings_num = num_vrings;
+ vdev->func = &remoteproc_virtio_dispatch_funcs;
+ /* TODO: Shall we set features here ? */
+
+ return &rpvdev->vdev;
+
+err1:
+ for (i = 0; i < num_vrings; i++) {
+ if (vrings_info[i].vq)
+ metal_free_memory(vrings_info[i].vq);
+ }
+ metal_free_memory(vrings_info);
+err0:
+ metal_free_memory(rpvdev);
+ return NULL;
+}
+
+void rproc_virtio_remove_vdev(struct virtio_device *vdev)
+{
+ struct remoteproc_virtio *rpvdev;
+ unsigned int i;
+
+ if (!vdev)
+ return;
+ rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev);
+ for (i = 0; i < vdev->vrings_num; i++) {
+ struct virtqueue *vq;
+
+ vq = vdev->vrings_info[i].vq;
+ if (vq)
+ metal_free_memory(vq);
+ }
+ metal_free_memory(vdev->vrings_info);
+ metal_free_memory(rpvdev);
+}
+
+int rproc_virtio_init_vring(struct virtio_device *vdev, unsigned int index,
+ unsigned int notifyid, void *va,
+ struct metal_io_region *io,
+ unsigned int num_descs, unsigned int align)
+{
+ struct virtio_vring_info *vring_info;
+ unsigned int num_vrings;
+
+ num_vrings = vdev->vrings_num;
+ if (index >= num_vrings)
+ return -RPROC_EINVAL;
+ vring_info = &vdev->vrings_info[index];
+ vring_info->io = io;
+ vring_info->notifyid = notifyid;
+ vring_info->info.vaddr = va;
+ vring_info->info.num_descs = num_descs;
+ vring_info->info.align = align;
+
+ return 0;
+}
+
+int rproc_virtio_notified(struct virtio_device *vdev, uint32_t notifyid)
+{
+ unsigned int num_vrings, i;
+ struct virtio_vring_info *vring_info;
+ struct virtqueue *vq;
+
+ if (!vdev)
+ return -EINVAL;
+ /* We do nothing for vdev notification in this implementation */
+ if (vdev->index == notifyid)
+ return 0;
+ num_vrings = vdev->vrings_num;
+ for (i = 0; i < num_vrings; i++) {
+ vring_info = &vdev->vrings_info[i];
+ if (vring_info->notifyid == notifyid ||
+ notifyid == RSC_NOTIFY_ID_ANY) {
+ vq = vring_info->vq;
+ virtqueue_notification(vq);
+ }
+ }
+ return 0;
+}
+
+void rproc_virtio_wait_remote_ready(struct virtio_device *vdev)
+{
+ uint8_t status;
+
+ /*
+ * No status available for slave. As Master has not to wait
+ * slave action, we can return. Behavior should be updated
+ * in future if a slave status is added.
+ */
+ if (vdev->role == VIRTIO_DEV_MASTER)
+ return;
+
+ while (1) {
+ status = rproc_virtio_get_status(vdev);
+ if (status & VIRTIO_CONFIG_STATUS_DRIVER_OK)
+ return;
+ }
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/CMakeLists.txt b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/CMakeLists.txt
new file mode 100644
index 0000000..1e3d7ae
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/CMakeLists.txt
@@ -0,0 +1,2 @@
+collect (PROJECT_LIB_SOURCES rpmsg.c)
+collect (PROJECT_LIB_SOURCES rpmsg_virtio.c)
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg.c
new file mode 100644
index 0000000..5542c2e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (c) 2018 Linaro, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <openamp/rpmsg.h>
+#include <metal/alloc.h>
+
+#include "rpmsg_internal.h"
+
+/**
+ * rpmsg_get_address
+ *
+ * This function provides unique 32 bit address.
+ *
+ * @param bitmap - bit map for addresses
+ * @param size - size of bitmap
+ *
+ * return - a unique address
+ */
+static uint32_t rpmsg_get_address(unsigned long *bitmap, int size)
+{
+ unsigned int addr = RPMSG_ADDR_ANY;
+ unsigned int nextbit;
+
+ nextbit = metal_bitmap_next_clear_bit(bitmap, 0, size);
+ if (nextbit < (uint32_t)size) {
+ addr = nextbit;
+ metal_bitmap_set_bit(bitmap, nextbit);
+ }
+
+ return addr;
+}
+
+/**
+ * rpmsg_release_address
+ *
+ * Frees the given address.
+ *
+ * @param bitmap - bit map for addresses
+ * @param size - size of bitmap
+ * @param addr - address to free
+ */
+static void rpmsg_release_address(unsigned long *bitmap, int size,
+ int addr)
+{
+ if (addr < size)
+ metal_bitmap_clear_bit(bitmap, addr);
+}
+
+/**
+ * rpmsg_is_address_set
+ *
+ * Checks whether address is used or free.
+ *
+ * @param bitmap - bit map for addresses
+ * @param size - size of bitmap
+ * @param addr - address to free
+ *
+ * return - TRUE/FALSE
+ */
+static int rpmsg_is_address_set(unsigned long *bitmap, int size, int addr)
+{
+ if (addr < size)
+ return metal_bitmap_is_bit_set(bitmap, addr);
+ else
+ return RPMSG_ERR_PARAM;
+}
+
+/**
+ * rpmsg_set_address
+ *
+ * Marks the address as consumed.
+ *
+ * @param bitmap - bit map for addresses
+ * @param size - size of bitmap
+ * @param addr - address to free
+ *
+ * return - none
+ */
+static int rpmsg_set_address(unsigned long *bitmap, int size, int addr)
+{
+ if (addr < size) {
+ metal_bitmap_set_bit(bitmap, addr);
+ return RPMSG_SUCCESS;
+ } else {
+ return RPMSG_ERR_PARAM;
+ }
+}
+
+/**
+ * This function sends rpmsg "message" to remote device.
+ *
+ * @param ept - pointer to end point
+ * @param src - source address of channel
+ * @param dst - destination address of channel
+ * @param data - data to transmit
+ * @param size - size of data
+ * @param wait - boolean, wait or not for buffer to become
+ * available
+ *
+ * @return - size of data sent or negative value for failure.
+ *
+ */
+int rpmsg_send_offchannel_raw(struct rpmsg_endpoint *ept, uint32_t src,
+ uint32_t dst, const void *data, int size,
+ int wait)
+{
+ struct rpmsg_device *rdev;
+
+ if (!ept || !ept->rdev || !data || dst == RPMSG_ADDR_ANY)
+ return RPMSG_ERR_PARAM;
+
+ rdev = ept->rdev;
+
+ if (rdev->ops.send_offchannel_raw)
+ return rdev->ops.send_offchannel_raw(rdev, src, dst, data,
+ size, wait);
+
+ return RPMSG_ERR_PARAM;
+}
+
+int rpmsg_send_ns_message(struct rpmsg_endpoint *ept, unsigned long flags)
+{
+ struct rpmsg_ns_msg ns_msg;
+ int ret;
+
+ ns_msg.flags = flags;
+ ns_msg.addr = ept->addr;
+ strncpy(ns_msg.name, ept->name, sizeof(ns_msg.name));
+ ret = rpmsg_send_offchannel_raw(ept, ept->addr,
+ RPMSG_NS_EPT_ADDR,
+ &ns_msg, sizeof(ns_msg), true);
+ if (ret < 0)
+ return ret;
+ else
+ return RPMSG_SUCCESS;
+}
+
+struct rpmsg_endpoint *rpmsg_get_endpoint(struct rpmsg_device *rdev,
+ const char *name, uint32_t addr,
+ uint32_t dest_addr)
+{
+ struct metal_list *node;
+ struct rpmsg_endpoint *ept;
+
+ metal_list_for_each(&rdev->endpoints, node) {
+ int name_match = 0;
+
+ ept = metal_container_of(node, struct rpmsg_endpoint, node);
+ /* try to get by local address only */
+ if (addr != RPMSG_ADDR_ANY && ept->addr == addr)
+ return ept;
+ /* try to find match on local end remote address */
+ if (addr == ept->addr && dest_addr == ept->dest_addr)
+ return ept;
+ /* else use name service and destination address */
+ if (name)
+ name_match = !strncmp(ept->name, name,
+ sizeof(ept->name));
+ if (!name || !name_match)
+ continue;
+ /* destination address is known, equal to ept remote address*/
+ if (dest_addr != RPMSG_ADDR_ANY && ept->dest_addr == dest_addr)
+ return ept;
+ /* ept is registered but not associated to remote ept*/
+ if (addr == RPMSG_ADDR_ANY && ept->dest_addr == RPMSG_ADDR_ANY)
+ return ept;
+ }
+ return NULL;
+}
+
+static void rpmsg_unregister_endpoint(struct rpmsg_endpoint *ept)
+{
+ struct rpmsg_device *rdev;
+
+ if (!ept)
+ return;
+
+ rdev = ept->rdev;
+
+ if (ept->addr != RPMSG_ADDR_ANY)
+ rpmsg_release_address(rdev->bitmap, RPMSG_ADDR_BMP_SIZE,
+ ept->addr);
+ metal_list_del(&ept->node);
+}
+
+int rpmsg_register_endpoint(struct rpmsg_device *rdev,
+ struct rpmsg_endpoint *ept)
+{
+ ept->rdev = rdev;
+
+ metal_list_add_tail(&rdev->endpoints, &ept->node);
+ return RPMSG_SUCCESS;
+}
+
+int rpmsg_create_ept(struct rpmsg_endpoint *ept, struct rpmsg_device *rdev,
+ const char *name, uint32_t src, uint32_t dest,
+ rpmsg_ept_cb cb, rpmsg_ns_unbind_cb unbind_cb)
+{
+ int status;
+ uint32_t addr = src;
+
+ if (!ept)
+ return RPMSG_ERR_PARAM;
+
+ metal_mutex_acquire(&rdev->lock);
+ if (src != RPMSG_ADDR_ANY) {
+ status = rpmsg_is_address_set(rdev->bitmap,
+ RPMSG_ADDR_BMP_SIZE, src);
+ if (!status) {
+ /* Mark the address as used in the address bitmap. */
+ rpmsg_set_address(rdev->bitmap, RPMSG_ADDR_BMP_SIZE,
+ src);
+ } else if (status > 0) {
+ status = RPMSG_SUCCESS;
+ goto ret_status;
+ } else {
+ goto ret_status;
+ }
+ } else {
+ addr = rpmsg_get_address(rdev->bitmap, RPMSG_ADDR_BMP_SIZE);
+ }
+
+ rpmsg_init_ept(ept, name, addr, dest, cb, unbind_cb);
+
+ status = rpmsg_register_endpoint(rdev, ept);
+ if (status < 0)
+ rpmsg_release_address(rdev->bitmap, RPMSG_ADDR_BMP_SIZE, addr);
+
+ if (!status && ept->dest_addr == RPMSG_ADDR_ANY) {
+ /* Send NS announcement to remote processor */
+ metal_mutex_release(&rdev->lock);
+ status = rpmsg_send_ns_message(ept, RPMSG_NS_CREATE);
+ metal_mutex_acquire(&rdev->lock);
+ if (status)
+ rpmsg_unregister_endpoint(ept);
+ }
+
+ret_status:
+ metal_mutex_release(&rdev->lock);
+ return status;
+}
+
+/**
+ * rpmsg_destroy_ept
+ *
+ * This function deletes rpmsg endpoint and performs cleanup.
+ *
+ * @param ept - pointer to endpoint to destroy
+ *
+ */
+void rpmsg_destroy_ept(struct rpmsg_endpoint *ept)
+{
+ struct rpmsg_device *rdev;
+
+ if (!ept)
+ return;
+
+ rdev = ept->rdev;
+ if (ept->addr != RPMSG_NS_EPT_ADDR)
+ (void)rpmsg_send_ns_message(ept, RPMSG_NS_DESTROY);
+ metal_mutex_acquire(&rdev->lock);
+ rpmsg_unregister_endpoint(ept);
+ metal_mutex_release(&rdev->lock);
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_internal.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_internal.h
new file mode 100644
index 0000000..535a835
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_internal.h
@@ -0,0 +1,105 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _RPMSG_INTERNAL_H_
+#define _RPMSG_INTERNAL_H_
+
+#include <stdint.h>
+#include <openamp/rpmsg.h>
+
+#if defined __cplusplus
+extern "C" {
+#endif
+
+#ifdef RPMSG_DEBUG
+#define RPMSG_ASSERT(_exp, _msg) do { \
+ if (!(_exp)) { \
+ openamp_print("FATAL: %s - _msg", __func__); \
+ while (1) { \
+ ; \
+ } \
+ } \
+ } while (0)
+#else
+#define RPMSG_ASSERT(_exp, _msg) do { \
+ if (!(_exp)) \
+ while (1) { \
+ ; \
+ } \
+ } while (0)
+#endif
+
+#define RPMSG_LOCATE_DATA(p) ((unsigned char *)(p) + sizeof(struct rpmsg_hdr))
+/**
+ * enum rpmsg_ns_flags - dynamic name service announcement flags
+ *
+ * @RPMSG_NS_CREATE: a new remote service was just created
+ * @RPMSG_NS_DESTROY: a known remote service was just destroyed
+ * @RPMSG_NS_CREATE_WITH_ACK: a new remote service was just created waiting
+ * acknowledgment.
+ */
+enum rpmsg_ns_flags {
+ RPMSG_NS_CREATE = 0,
+ RPMSG_NS_DESTROY = 1,
+};
+
+/**
+ * struct rpmsg_hdr - common header for all rpmsg messages
+ * @src: source address
+ * @dst: destination address
+ * @reserved: reserved for future use
+ * @len: length of payload (in bytes)
+ * @flags: message flags
+ *
+ * Every message sent(/received) on the rpmsg bus begins with this header.
+ */
+OPENAMP_PACKED_BEGIN
+struct rpmsg_hdr {
+ uint32_t src;
+ uint32_t dst;
+ uint32_t reserved;
+ uint16_t len;
+ uint16_t flags;
+} OPENAMP_PACKED_END;
+
+/**
+ * struct rpmsg_ns_msg - dynamic name service announcement message
+ * @name: name of remote service that is published
+ * @addr: address of remote service that is published
+ * @flags: indicates whether service is created or destroyed
+ *
+ * This message is sent across to publish a new service, or announce
+ * about its removal. When we receive these messages, an appropriate
+ * rpmsg channel (i.e device) is created/destroyed. In turn, the ->probe()
+ * or ->remove() handler of the appropriate rpmsg driver will be invoked
+ * (if/as-soon-as one is registered).
+ */
+OPENAMP_PACKED_BEGIN
+struct rpmsg_ns_msg {
+ char name[RPMSG_NAME_SIZE];
+ uint32_t addr;
+ uint32_t flags;
+} OPENAMP_PACKED_END;
+
+int rpmsg_send_ns_message(struct rpmsg_endpoint *ept, unsigned long flags);
+
+struct rpmsg_endpoint *rpmsg_get_endpoint(struct rpmsg_device *rvdev,
+ const char *name, uint32_t addr,
+ uint32_t dest_addr);
+int rpmsg_register_endpoint(struct rpmsg_device *rdev,
+ struct rpmsg_endpoint *ept);
+
+static inline struct rpmsg_endpoint *
+rpmsg_get_ept_from_addr(struct rpmsg_device *rdev, uint32_t addr)
+{
+ return rpmsg_get_endpoint(rdev, NULL, addr, RPMSG_ADDR_ANY);
+}
+
+#if defined __cplusplus
+}
+#endif
+
+#endif /* _RPMSG_INTERNAL_H_ */
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c
new file mode 100644
index 0000000..9c72fd9
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/rpmsg/rpmsg_virtio.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (c) 2018 Linaro, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <metal/alloc.h>
+#include <metal/cache.h>
+#include <metal/sleep.h>
+#include <metal/utilities.h>
+#include <openamp/rpmsg_virtio.h>
+#include <openamp/virtqueue.h>
+
+#include "rpmsg_internal.h"
+
+#define RPMSG_NUM_VRINGS (2)
+
+/* Total tick count for 15secs - 1msec tick. */
+#define RPMSG_TICK_COUNT 15000
+
+/* Time to wait - In multiple of 10 msecs. */
+#define RPMSG_TICKS_PER_INTERVAL 10
+
+#define WORD_SIZE sizeof(unsigned long)
+#define WORD_ALIGN(a) ((((a) & (WORD_SIZE - 1)) != 0) ? \
+ (((a) & (~(WORD_SIZE - 1))) + WORD_SIZE) : (a))
+
+#ifndef VIRTIO_SLAVE_ONLY
+metal_weak void *
+rpmsg_virtio_shm_pool_get_buffer(struct rpmsg_virtio_shm_pool *shpool,
+ size_t size)
+{
+ void *buffer;
+
+ if (shpool->avail < size)
+ return NULL;
+ buffer = (void *)((char *)shpool->base + shpool->size - shpool->avail);
+ shpool->avail -= size;
+
+ return buffer;
+}
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+void rpmsg_virtio_init_shm_pool(struct rpmsg_virtio_shm_pool *shpool,
+ void *shb, size_t size)
+{
+ if (!shpool)
+ return;
+ shpool->base = shb;
+ shpool->size = WORD_ALIGN(size);
+ shpool->avail = WORD_ALIGN(size);
+}
+
+/**
+ * rpmsg_virtio_return_buffer
+ *
+ * Places the used buffer back on the virtqueue.
+ *
+ * @param rvdev - pointer to remote core
+ * @param buffer - buffer pointer
+ * @param len - buffer length
+ * @param idx - buffer index
+ *
+ */
+static void rpmsg_virtio_return_buffer(struct rpmsg_virtio_device *rvdev,
+ void *buffer, unsigned long len,
+ unsigned short idx)
+{
+ unsigned int role = rpmsg_virtio_get_role(rvdev);
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER) {
+ struct virtqueue_buf vqbuf;
+
+ (void)idx;
+ /* Initialize buffer node */
+ vqbuf.buf = buffer;
+ vqbuf.len = len;
+ virtqueue_add_buffer(rvdev->rvq, &vqbuf, 0, 1, buffer);
+ }
+#endif /*VIRTIO_SLAVE_ONLY*/
+
+#ifndef VIRTIO_MASTER_ONLY
+ if (role == RPMSG_REMOTE) {
+ (void)buffer;
+ virtqueue_add_consumed_buffer(rvdev->rvq, idx, len);
+ }
+#endif /*VIRTIO_MASTER_ONLY*/
+}
+
+/**
+ * rpmsg_virtio_enqueue_buffer
+ *
+ * Places buffer on the virtqueue for consumption by the other side.
+ *
+ * @param rvdev - pointer to rpmsg virtio
+ * @param buffer - buffer pointer
+ * @param len - buffer length
+ * @param idx - buffer index
+ *
+ * @return - status of function execution
+ */
+static int rpmsg_virtio_enqueue_buffer(struct rpmsg_virtio_device *rvdev,
+ void *buffer, unsigned long len,
+ unsigned short idx)
+{
+ unsigned int role = rpmsg_virtio_get_role(rvdev);
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER) {
+ struct virtqueue_buf vqbuf;
+ (void)idx;
+
+ /* Initialize buffer node */
+ vqbuf.buf = buffer;
+ vqbuf.len = len;
+ return virtqueue_add_buffer(rvdev->svq, &vqbuf, 0, 1, buffer);
+ }
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+#ifndef VIRTIO_MASTER_ONLY
+ if (role == RPMSG_REMOTE) {
+ (void)buffer;
+ return virtqueue_add_consumed_buffer(rvdev->svq, idx, len);
+ }
+#endif /*!VIRTIO_MASTER_ONLY*/
+ return 0;
+}
+
+/**
+ * rpmsg_virtio_get_tx_buffer
+ *
+ * Provides buffer to transmit messages.
+ *
+ * @param rvdev - pointer to rpmsg device
+ * @param len - length of returned buffer
+ * @param idx - buffer index
+ *
+ * return - pointer to buffer.
+ */
+static void *rpmsg_virtio_get_tx_buffer(struct rpmsg_virtio_device *rvdev,
+ unsigned long *len,
+ unsigned short *idx)
+{
+ unsigned int role = rpmsg_virtio_get_role(rvdev);
+ void *data = NULL;
+
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER) {
+ data = virtqueue_get_buffer(rvdev->svq, (uint32_t *)len, idx);
+ if (data == NULL) {
+ data = rpmsg_virtio_shm_pool_get_buffer(rvdev->shpool,
+ RPMSG_BUFFER_SIZE);
+ *len = RPMSG_BUFFER_SIZE;
+ }
+ }
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+#ifndef VIRTIO_MASTER_ONLY
+ if (role == RPMSG_REMOTE) {
+ data = virtqueue_get_available_buffer(rvdev->svq, idx,
+ (uint32_t *)len);
+ }
+#endif /*!VIRTIO_MASTER_ONLY*/
+
+ return data;
+}
+
+/**
+ * rpmsg_virtio_get_rx_buffer
+ *
+ * Retrieves the received buffer from the virtqueue.
+ *
+ * @param rvdev - pointer to rpmsg device
+ * @param len - size of received buffer
+ * @param idx - index of buffer
+ *
+ * @return - pointer to received buffer
+ *
+ */
+static void *rpmsg_virtio_get_rx_buffer(struct rpmsg_virtio_device *rvdev,
+ unsigned long *len,
+ unsigned short *idx)
+{
+ unsigned int role = rpmsg_virtio_get_role(rvdev);
+ void *data = NULL;
+
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER) {
+ data = virtqueue_get_buffer(rvdev->rvq, (uint32_t *)len, idx);
+ }
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+#ifndef VIRTIO_MASTER_ONLY
+ if (role == RPMSG_REMOTE) {
+ data =
+ virtqueue_get_available_buffer(rvdev->rvq, idx,
+ (uint32_t *)len);
+ }
+#endif /*!VIRTIO_MASTER_ONLY*/
+
+ if (data) {
+ /* FIX ME: library should not worry about if it needs
+ * to flush/invalidate cache, it is shared memory.
+ * The shared memory should be mapped properly before
+ * using it.
+ */
+ metal_cache_invalidate(data, (unsigned int)(*len));
+ }
+
+ return data;
+}
+
+#ifndef VIRTIO_MASTER_ONLY
+/**
+ * check if the remote is ready to start RPMsg communication
+ */
+static int rpmsg_virtio_wait_remote_ready(struct rpmsg_virtio_device *rvdev)
+{
+ uint8_t status;
+
+ while (1) {
+ status = rpmsg_virtio_get_status(rvdev);
+ /* Busy wait until the remote is ready */
+ if (status & VIRTIO_CONFIG_STATUS_NEEDS_RESET) {
+ rpmsg_virtio_set_status(rvdev, 0);
+ /* TODO notify remote processor */
+ } else if (status & VIRTIO_CONFIG_STATUS_DRIVER_OK) {
+ return true;
+ }
+ /* TODO: clarify metal_cpu_yield usage*/
+ metal_cpu_yield();
+ }
+
+ return false;
+}
+#endif /*!VIRTIO_MASTER_ONLY*/
+
+/**
+ * _rpmsg_virtio_get_buffer_size
+ *
+ * Returns buffer size available for sending messages.
+ *
+ * @param channel - pointer to rpmsg channel
+ *
+ * @return - buffer size
+ *
+ */
+static int _rpmsg_virtio_get_buffer_size(struct rpmsg_virtio_device *rvdev)
+{
+ unsigned int role = rpmsg_virtio_get_role(rvdev);
+ int length = 0;
+
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER) {
+ /*
+ * If device role is Remote then buffers are provided by us
+ * (RPMSG Master), so just provide the macro.
+ */
+ length = RPMSG_BUFFER_SIZE - sizeof(struct rpmsg_hdr);
+ }
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+#ifndef VIRTIO_MASTER_ONLY
+ if (role == RPMSG_REMOTE) {
+ /*
+ * If other core is Master then buffers are provided by it,
+ * so get the buffer size from the virtqueue.
+ */
+ length =
+ (int)virtqueue_get_desc_size(rvdev->svq) -
+ sizeof(struct rpmsg_hdr);
+ }
+#endif /*!VIRTIO_MASTER_ONLY*/
+
+ return length;
+}
+
+/**
+ * This function sends rpmsg "message" to remote device.
+ *
+ * @param rdev - pointer to rpmsg device
+ * @param src - source address of channel
+ * @param dst - destination address of channel
+ * @param data - data to transmit
+ * @param size - size of data
+ * @param wait - boolean, wait or not for buffer to become
+ * available
+ *
+ * @return - size of data sent or negative value for failure.
+ *
+ */
+static int rpmsg_virtio_send_offchannel_raw(struct rpmsg_device *rdev,
+ uint32_t src, uint32_t dst,
+ const void *data,
+ int size, int wait)
+{
+ struct rpmsg_virtio_device *rvdev;
+ struct rpmsg_hdr rp_hdr;
+ void *buffer = NULL;
+ unsigned short idx;
+ int tick_count = 0;
+ unsigned long buff_len;
+ int status;
+ struct metal_io_region *io;
+
+ /* Get the associated remote device for channel. */
+ rvdev = metal_container_of(rdev, struct rpmsg_virtio_device, rdev);
+
+ status = rpmsg_virtio_get_status(rvdev);
+ /* Validate device state */
+ if (!(status & VIRTIO_CONFIG_STATUS_DRIVER_OK)) {
+ return RPMSG_ERR_DEV_STATE;
+ }
+
+ if (wait)
+ tick_count = RPMSG_TICK_COUNT / RPMSG_TICKS_PER_INTERVAL;
+ else
+ tick_count = 0;
+
+ while (1) {
+ int avail_size;
+
+ /* Lock the device to enable exclusive access to virtqueues */
+ metal_mutex_acquire(&rdev->lock);
+ avail_size = _rpmsg_virtio_get_buffer_size(rvdev);
+ if (size <= avail_size)
+ buffer = rpmsg_virtio_get_tx_buffer(rvdev, &buff_len,
+ &idx);
+ metal_mutex_release(&rdev->lock);
+ if (buffer || !tick_count)
+ break;
+ if (avail_size != 0)
+ return RPMSG_ERR_BUFF_SIZE;
+ metal_sleep_usec(RPMSG_TICKS_PER_INTERVAL);
+ tick_count--;
+ }
+ if (!buffer)
+ return RPMSG_ERR_NO_BUFF;
+
+ /* Initialize RPMSG header. */
+ rp_hdr.dst = dst;
+ rp_hdr.src = src;
+ rp_hdr.len = size;
+ rp_hdr.reserved = 0;
+
+ /* Copy data to rpmsg buffer. */
+ io = rvdev->shbuf_io;
+ status = metal_io_block_write(io, metal_io_virt_to_offset(io, buffer),
+ &rp_hdr, sizeof(rp_hdr));
+ RPMSG_ASSERT(status == sizeof(rp_hdr), "failed to write header\n");
+
+ status = metal_io_block_write(io,
+ metal_io_virt_to_offset(io,
+ RPMSG_LOCATE_DATA(buffer)),
+ data, size);
+ RPMSG_ASSERT(status == size, "failed to write buffer\n");
+ metal_mutex_acquire(&rdev->lock);
+
+ /* Enqueue buffer on virtqueue. */
+ status = rpmsg_virtio_enqueue_buffer(rvdev, buffer, buff_len, idx);
+ RPMSG_ASSERT(status == VQUEUE_SUCCESS, "failed to enqueue buffer\n");
+ /* Let the other side know that there is a job to process. */
+ virtqueue_kick(rvdev->svq);
+
+ metal_mutex_release(&rdev->lock);
+
+ return size;
+}
+
+/**
+ * rpmsg_virtio_tx_callback
+ *
+ * Tx callback function.
+ *
+ * @param vq - pointer to virtqueue on which Tx is has been
+ * completed.
+ *
+ */
+static void rpmsg_virtio_tx_callback(struct virtqueue *vq)
+{
+ (void)vq;
+}
+
+/**
+ * rpmsg_virtio_rx_callback
+ *
+ * Rx callback function.
+ *
+ * @param vq - pointer to virtqueue on which messages is received
+ *
+ */
+static void rpmsg_virtio_rx_callback(struct virtqueue *vq)
+{
+ struct virtio_device *vdev = vq->vq_dev;
+ struct rpmsg_virtio_device *rvdev = vdev->priv;
+ struct rpmsg_device *rdev = &rvdev->rdev;
+ struct rpmsg_endpoint *ept;
+ struct rpmsg_hdr *rp_hdr;
+ unsigned long len;
+ unsigned short idx;
+ int status;
+
+ metal_mutex_acquire(&rdev->lock);
+
+ /* Process the received data from remote node */
+ rp_hdr = (struct rpmsg_hdr *)rpmsg_virtio_get_rx_buffer(rvdev,
+ &len, &idx);
+
+ metal_mutex_release(&rdev->lock);
+
+ while (rp_hdr) {
+ /* Get the channel node from the remote device channels list. */
+ metal_mutex_acquire(&rdev->lock);
+ ept = rpmsg_get_ept_from_addr(rdev, rp_hdr->dst);
+ metal_mutex_release(&rdev->lock);
+
+ if (!ept)
+ /* Fatal error no endpoint for the given dst addr. */
+ return;
+
+ if (ept->dest_addr == RPMSG_ADDR_ANY) {
+ /*
+ * First message received from the remote side,
+ * update channel destination address
+ */
+ ept->dest_addr = rp_hdr->src;
+ }
+ status = ept->cb(ept, (void *)RPMSG_LOCATE_DATA(rp_hdr),
+ rp_hdr->len, rp_hdr->src/*ept->addr*/, ept->priv);
+
+ RPMSG_ASSERT(status == RPMSG_SUCCESS,
+ "unexpected callback status\n");
+ metal_mutex_acquire(&rdev->lock);
+
+ /* Return used buffers. */
+ rpmsg_virtio_return_buffer(rvdev, rp_hdr, len, idx);
+
+ rp_hdr = (struct rpmsg_hdr *)
+ rpmsg_virtio_get_rx_buffer(rvdev, &len, &idx);
+ metal_mutex_release(&rdev->lock);
+ }
+}
+
+/**
+ * rpmsg_virtio_ns_callback
+ *
+ * This callback handles name service announcement from the remote device
+ * and creates/deletes rpmsg channels.
+ *
+ * @param server_chnl - pointer to server channel control block.
+ * @param data - pointer to received messages
+ * @param len - length of received data
+ * @param priv - any private data
+ * @param src - source address
+ *
+ * @return - rpmag endpoint callback handled
+ */
+
+#if defined (__GNUC__) && ! defined (__CC_ARM)
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+#elif defined (__CC_ARM)
+#pragma push
+#pragma O0
+#endif
+static int rpmsg_virtio_ns_callback(struct rpmsg_endpoint *ept, void *data,
+ size_t len, uint32_t src, void *priv)
+{
+ struct rpmsg_device *rdev = ept->rdev;
+ struct rpmsg_virtio_device *rvdev = (struct rpmsg_virtio_device *)rdev;
+ struct metal_io_region *io = rvdev->shbuf_io;
+ struct rpmsg_endpoint *_ept;
+ struct rpmsg_ns_msg *ns_msg;
+ uint32_t dest;
+ char name[RPMSG_NAME_SIZE];
+
+ (void)priv;
+ (void)src;
+
+ ns_msg = (struct rpmsg_ns_msg *)data;
+ if (len != sizeof(*ns_msg))
+ /* Returns as the message is corrupted */
+ return RPMSG_SUCCESS;
+ metal_io_block_read(io,
+ metal_io_virt_to_offset(io, ns_msg->name),
+ &name, sizeof(name));
+ dest = ns_msg->addr;
+
+ /* check if a Ept has been locally registered */
+ metal_mutex_acquire(&rdev->lock);
+ _ept = rpmsg_get_endpoint(rdev, name, RPMSG_ADDR_ANY, dest);
+
+ if (ns_msg->flags & RPMSG_NS_DESTROY) {
+ if (_ept)
+ _ept->dest_addr = RPMSG_ADDR_ANY;
+ metal_mutex_release(&rdev->lock);
+ if (_ept && _ept->ns_unbind_cb)
+ _ept->ns_unbind_cb(ept);
+ } else {
+ if (!_ept) {
+ /*
+ * send callback to application, that can
+ * - create the associated endpoints.
+ * - store information for future use.
+ * - just ignore the request as service not supported.
+ */
+ metal_mutex_release(&rdev->lock);
+ if (rdev->ns_bind_cb)
+ rdev->ns_bind_cb(rdev, name, dest);
+ } else {
+ _ept->dest_addr = dest;
+ metal_mutex_release(&rdev->lock);
+ }
+ }
+
+ return RPMSG_SUCCESS;
+}
+#if defined (__GNUC__) && ! defined (__CC_ARM)
+#pragma GCC pop_options
+#elif defined (__CC_ARM)
+#pragma pop
+#endif
+
+int rpmsg_virtio_get_buffer_size(struct rpmsg_device *rdev)
+{
+ int size;
+ struct rpmsg_virtio_device *rvdev;
+
+ if (!rdev)
+ return RPMSG_ERR_PARAM;
+ metal_mutex_acquire(&rdev->lock);
+ rvdev = (struct rpmsg_virtio_device *)rdev;
+ size = _rpmsg_virtio_get_buffer_size(rvdev);
+ metal_mutex_release(&rdev->lock);
+ return size;
+}
+
+int rpmsg_init_vdev(struct rpmsg_virtio_device *rvdev,
+ struct virtio_device *vdev,
+ rpmsg_ns_bind_cb ns_bind_cb,
+ struct metal_io_region *shm_io,
+ struct rpmsg_virtio_shm_pool *shpool)
+{
+ struct rpmsg_device *rdev;
+ const char *vq_names[RPMSG_NUM_VRINGS];
+ typedef void (*vqcallback)(struct virtqueue *vq);
+ vqcallback callback[RPMSG_NUM_VRINGS];
+ unsigned long dev_features;
+ int status;
+ unsigned int i, role;
+
+ rdev = &rvdev->rdev;
+ memset(rdev, 0, sizeof(*rdev));
+ metal_mutex_init(&rdev->lock);
+ rvdev->vdev = vdev;
+ rdev->ns_bind_cb = ns_bind_cb;
+ vdev->priv = rvdev;
+ rdev->ops.send_offchannel_raw = rpmsg_virtio_send_offchannel_raw;
+ role = rpmsg_virtio_get_role(rvdev);
+
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER) {
+ /*
+ * Since device is RPMSG Remote so we need to manage the
+ * shared buffers. Create shared memory pool to handle buffers.
+ */
+ if (!shpool)
+ return RPMSG_ERR_PARAM;
+ if (!shpool->size)
+ return RPMSG_ERR_NO_BUFF;
+ rvdev->shpool = shpool;
+
+ vq_names[0] = "rx_vq";
+ vq_names[1] = "tx_vq";
+ callback[0] = rpmsg_virtio_rx_callback;
+ callback[1] = rpmsg_virtio_tx_callback;
+ rvdev->rvq = vdev->vrings_info[0].vq;
+ rvdev->svq = vdev->vrings_info[1].vq;
+ }
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+#ifndef VIRTIO_MASTER_ONLY
+ (void)shpool;
+ if (role == RPMSG_REMOTE) {
+ vq_names[0] = "tx_vq";
+ vq_names[1] = "rx_vq";
+ callback[0] = rpmsg_virtio_tx_callback;
+ callback[1] = rpmsg_virtio_rx_callback;
+ rvdev->rvq = vdev->vrings_info[1].vq;
+ rvdev->svq = vdev->vrings_info[0].vq;
+ }
+#endif /*!VIRTIO_MASTER_ONLY*/
+ rvdev->shbuf_io = shm_io;
+
+#ifndef VIRTIO_MASTER_ONLY
+ if (role == RPMSG_REMOTE) {
+ /* wait synchro with the master */
+ rpmsg_virtio_wait_remote_ready(rvdev);
+ }
+#endif /*!VIRTIO_MASTER_ONLY*/
+
+ /* Create virtqueues for remote device */
+ status = rpmsg_virtio_create_virtqueues(rvdev, 0, RPMSG_NUM_VRINGS,
+ vq_names, callback);
+ if (status != RPMSG_SUCCESS)
+ return status;
+
+ /* TODO: can have a virtio function to set the shared memory I/O */
+ for (i = 0; i < RPMSG_NUM_VRINGS; i++) {
+ struct virtqueue *vq;
+
+ vq = vdev->vrings_info[i].vq;
+ vq->shm_io = shm_io;
+ }
+
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER) {
+ struct virtqueue_buf vqbuf;
+ unsigned int idx;
+ void *buffer;
+
+ vqbuf.len = RPMSG_BUFFER_SIZE;
+ for (idx = 0; idx < rvdev->rvq->vq_nentries; idx++) {
+ /* Initialize TX virtqueue buffers for remote device */
+ buffer = rpmsg_virtio_shm_pool_get_buffer(shpool,
+ RPMSG_BUFFER_SIZE);
+
+ if (!buffer) {
+ return RPMSG_ERR_NO_BUFF;
+ }
+
+ vqbuf.buf = buffer;
+
+ metal_io_block_set(shm_io,
+ metal_io_virt_to_offset(shm_io,
+ buffer),
+ 0x00, RPMSG_BUFFER_SIZE);
+ status =
+ virtqueue_add_buffer(rvdev->rvq, &vqbuf, 0, 1,
+ buffer);
+
+ if (status != RPMSG_SUCCESS) {
+ return status;
+ }
+ }
+ }
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+ /* Initialize channels and endpoints list */
+ metal_list_init(&rdev->endpoints);
+
+ dev_features = rpmsg_virtio_get_features(rvdev);
+
+ /*
+ * Create name service announcement endpoint if device supports name
+ * service announcement feature.
+ */
+ if ((dev_features & (1 << VIRTIO_RPMSG_F_NS))) {
+ rpmsg_init_ept(&rdev->ns_ept, "NS",
+ RPMSG_NS_EPT_ADDR, RPMSG_NS_EPT_ADDR,
+ rpmsg_virtio_ns_callback, NULL);
+ (void)rpmsg_register_endpoint(rdev, &rdev->ns_ept);
+ }
+
+#ifndef VIRTIO_SLAVE_ONLY
+ if (role == RPMSG_MASTER)
+ rpmsg_virtio_set_status(rvdev, VIRTIO_CONFIG_STATUS_DRIVER_OK);
+#endif /*!VIRTIO_SLAVE_ONLY*/
+
+ return status;
+}
+
+void rpmsg_deinit_vdev(struct rpmsg_virtio_device *rvdev)
+{
+ struct metal_list *node;
+ struct rpmsg_device *rdev;
+ struct rpmsg_endpoint *ept;
+
+ rdev = &rvdev->rdev;
+ while (!metal_list_is_empty(&rdev->endpoints)) {
+ node = rdev->endpoints.next;
+ ept = metal_container_of(node, struct rpmsg_endpoint, node);
+ rpmsg_destroy_ept(ept);
+ }
+
+ rvdev->rvq = 0;
+ rvdev->svq = 0;
+
+ metal_mutex_deinit(&rdev->lock);
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtio.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtio.c
new file mode 100644
index 0000000..ee327d2
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtio.c
@@ -0,0 +1,121 @@
+/*-
+ * Copyright (c) 2011, Bryan Venteicher <bryanv@FreeBSD.org>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#include <openamp/virtio.h>
+
+static const char *virtio_feature_name(unsigned long feature,
+ const struct virtio_feature_desc *);
+
+//TODO : This structure may change depending on the types of devices we support.
+static const struct virtio_ident {
+ unsigned short devid;
+ const char *name;
+} virtio_ident_table[] = {
+ {
+ VIRTIO_ID_NETWORK, "Network"}, {
+ VIRTIO_ID_BLOCK, "Block"}, {
+ VIRTIO_ID_CONSOLE, "Console"}, {
+ VIRTIO_ID_ENTROPY, "Entropy"}, {
+ VIRTIO_ID_BALLOON, "Balloon"}, {
+ VIRTIO_ID_IOMEMORY, "IOMemory"}, {
+ VIRTIO_ID_SCSI, "SCSI"}, {
+ VIRTIO_ID_9P, "9P Transport"}, {
+ 0, NULL}
+};
+
+/* Device independent features. */
+static const struct virtio_feature_desc virtio_common_feature_desc[] = {
+ {VIRTIO_F_NOTIFY_ON_EMPTY, "NotifyOnEmpty"},
+ {VIRTIO_RING_F_INDIRECT_DESC, "RingIndirect"},
+ {VIRTIO_RING_F_EVENT_IDX, "EventIdx"},
+ {VIRTIO_F_BAD_FEATURE, "BadFeature"},
+
+ {0, NULL}
+};
+
+const char *virtio_dev_name(unsigned short devid)
+{
+ const struct virtio_ident *ident;
+
+ for (ident = virtio_ident_table; ident->name != NULL; ident++) {
+ if (ident->devid == devid)
+ return (ident->name);
+ }
+
+ return (NULL);
+}
+
+static const char *virtio_feature_name(unsigned long val,
+ const struct virtio_feature_desc *desc)
+{
+ int i, j;
+ const struct virtio_feature_desc *descs[2] = { desc,
+ virtio_common_feature_desc
+ };
+
+ for (i = 0; i < 2; i++) {
+ if (!descs[i])
+ continue;
+
+ for (j = 0; descs[i][j].vfd_val != 0; j++) {
+ if (val == descs[i][j].vfd_val)
+ return (descs[i][j].vfd_str);
+ }
+ }
+
+ return (NULL);
+}
+
+void virtio_describe(struct virtio_device *dev, const char *msg,
+ uint32_t features, struct virtio_feature_desc *desc)
+{
+ (void)dev;
+ (void)msg;
+ (void)features;
+
+ // TODO: Not used currently - keeping it for future use
+ virtio_feature_name(0, desc);
+}
+
+int virtio_create_virtqueues(struct virtio_device *vdev, unsigned int flags,
+ unsigned int nvqs, const char *names[],
+ vq_callback *callbacks[])
+{
+ struct virtio_vring_info *vring_info;
+ struct vring_alloc_info *vring_alloc;
+ unsigned int num_vrings, i;
+ int ret;
+ (void)flags;
+
+ num_vrings = vdev->vrings_num;
+ if (nvqs > num_vrings)
+ return -ERROR_VQUEUE_INVLD_PARAM;
+ /* Initialize virtqueue for each vring */
+ for (i = 0; i < nvqs; i++) {
+ vring_info = &vdev->vrings_info[i];
+
+ vring_alloc = &vring_info->info;
+#ifndef VIRTIO_SLAVE_ONLY
+ if (vdev->role == VIRTIO_DEV_MASTER) {
+ size_t offset;
+ struct metal_io_region *io = vring_info->io;
+
+ offset = metal_io_virt_to_offset(io,
+ vring_alloc->vaddr);
+ metal_io_block_set(io, offset, 0,
+ vring_size(vring_alloc->num_descs,
+ vring_alloc->align));
+ }
+#endif
+ ret = virtqueue_create(vdev, i, names[i], vring_alloc,
+ callbacks[i], vdev->func->notify,
+ vring_info->vq);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtqueue.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtqueue.c
new file mode 100644
index 0000000..1f46552
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/open-amp/lib/virtio/virtqueue.c
@@ -0,0 +1,618 @@
+/*-
+ * Copyright (c) 2011, Bryan Venteicher <bryanv@FreeBSD.org>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#include <string.h>
+#include <openamp/virtqueue.h>
+#include <metal/atomic.h>
+#include <metal/log.h>
+#include <metal/alloc.h>
+
+/* Prototype for internal functions. */
+static void vq_ring_init(struct virtqueue *, void *, int);
+static void vq_ring_update_avail(struct virtqueue *, uint16_t);
+static uint16_t vq_ring_add_buffer(struct virtqueue *, struct vring_desc *,
+ uint16_t, struct virtqueue_buf *, int, int);
+static int vq_ring_enable_interrupt(struct virtqueue *, uint16_t);
+static void vq_ring_free_chain(struct virtqueue *, uint16_t);
+static int vq_ring_must_notify_host(struct virtqueue *vq);
+static void vq_ring_notify_host(struct virtqueue *vq);
+static int virtqueue_nused(struct virtqueue *vq);
+
+/* Default implementation of P2V based on libmetal */
+static inline void *virtqueue_phys_to_virt(struct virtqueue *vq,
+ metal_phys_addr_t phys)
+{
+ struct metal_io_region *io = vq->shm_io;
+
+ return metal_io_phys_to_virt(io, phys);
+}
+
+/* Default implementation of V2P based on libmetal */
+static inline metal_phys_addr_t virtqueue_virt_to_phys(struct virtqueue *vq,
+ void *buf)
+{
+ struct metal_io_region *io = vq->shm_io;
+
+ return metal_io_virt_to_phys(io, buf);
+}
+
+/**
+ * virtqueue_create - Creates new VirtIO queue
+ *
+ * @param device - Pointer to VirtIO device
+ * @param id - VirtIO queue ID , must be unique
+ * @param name - Name of VirtIO queue
+ * @param ring - Pointer to vring_alloc_info control block
+ * @param callback - Pointer to callback function, invoked
+ * when message is available on VirtIO queue
+ * @param notify - Pointer to notify function, used to notify
+ * other side that there is job available for it
+ * @param vq - Created VirtIO queue.
+ *
+ * @return - Function status
+ */
+int virtqueue_create(struct virtio_device *virt_dev, unsigned short id,
+ const char *name, struct vring_alloc_info *ring,
+ void (*callback)(struct virtqueue *vq),
+ void (*notify)(struct virtqueue *vq),
+ struct virtqueue *vq)
+{
+ int status = VQUEUE_SUCCESS;
+
+ VQ_PARAM_CHK(ring == NULL, status, ERROR_VQUEUE_INVLD_PARAM);
+ VQ_PARAM_CHK(ring->num_descs == 0, status, ERROR_VQUEUE_INVLD_PARAM);
+ VQ_PARAM_CHK(ring->num_descs & (ring->num_descs - 1), status,
+ ERROR_VRING_ALIGN);
+ VQ_PARAM_CHK(vq == NULL, status, ERROR_NO_MEM);
+
+ if (status == VQUEUE_SUCCESS) {
+ vq->vq_dev = virt_dev;
+ vq->vq_name = name;
+ vq->vq_queue_index = id;
+ vq->vq_nentries = ring->num_descs;
+ vq->vq_free_cnt = vq->vq_nentries;
+ vq->callback = callback;
+ vq->notify = notify;
+
+ /* Initialize vring control block in virtqueue. */
+ vq_ring_init(vq, (void *)ring->vaddr, ring->align);
+
+ /* Disable callbacks - will be enabled by the application
+ * once initialization is completed.
+ */
+ virtqueue_disable_cb(vq);
+ }
+
+ return (status);
+}
+
+/**
+ * virtqueue_add_buffer() - Enqueues new buffer in vring for consumption
+ * by other side. Readable buffers are always
+ * inserted before writable buffers
+ *
+ * @param vq - Pointer to VirtIO queue control block.
+ * @param buf_list - Pointer to a list of virtqueue buffers.
+ * @param readable - Number of readable buffers
+ * @param writable - Number of writable buffers
+ * @param cookie - Pointer to hold call back data
+ *
+ * @return - Function status
+ */
+int virtqueue_add_buffer(struct virtqueue *vq, struct virtqueue_buf *buf_list,
+ int readable, int writable, void *cookie)
+{
+ struct vq_desc_extra *dxp = NULL;
+ int status = VQUEUE_SUCCESS;
+ uint16_t head_idx;
+ uint16_t idx;
+ int needed;
+
+ needed = readable + writable;
+
+ VQ_PARAM_CHK(vq == NULL, status, ERROR_VQUEUE_INVLD_PARAM);
+ VQ_PARAM_CHK(needed < 1, status, ERROR_VQUEUE_INVLD_PARAM);
+ VQ_PARAM_CHK(vq->vq_free_cnt == 0, status, ERROR_VRING_FULL);
+
+ VQUEUE_BUSY(vq);
+
+ if (status == VQUEUE_SUCCESS) {
+ VQASSERT(vq, cookie != NULL, "enqueuing with no cookie");
+
+ head_idx = vq->vq_desc_head_idx;
+ VQ_RING_ASSERT_VALID_IDX(vq, head_idx);
+ dxp = &vq->vq_descx[head_idx];
+
+ VQASSERT(vq, dxp->cookie == NULL,
+ "cookie already exists for index");
+
+ dxp->cookie = cookie;
+ dxp->ndescs = needed;
+
+ /* Enqueue buffer onto the ring. */
+ idx = vq_ring_add_buffer(vq, vq->vq_ring.desc, head_idx,
+ buf_list, readable, writable);
+
+ vq->vq_desc_head_idx = idx;
+ vq->vq_free_cnt -= needed;
+
+ if (vq->vq_free_cnt == 0) {
+ VQ_RING_ASSERT_CHAIN_TERM(vq);
+ } else {
+ VQ_RING_ASSERT_VALID_IDX(vq, idx);
+ }
+
+ /*
+ * Update vring_avail control block fields so that other
+ * side can get buffer using it.
+ */
+ vq_ring_update_avail(vq, head_idx);
+ }
+
+ VQUEUE_IDLE(vq);
+
+ return status;
+}
+
+/**
+ * virtqueue_get_buffer - Returns used buffers from VirtIO queue
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ * @param len - Length of conumed buffer
+ * @param idx - index of the buffer
+ *
+ * @return - Pointer to used buffer
+ */
+void *virtqueue_get_buffer(struct virtqueue *vq, uint32_t *len, uint16_t *idx)
+{
+ struct vring_used_elem *uep;
+ void *cookie;
+ uint16_t used_idx, desc_idx;
+
+ if (!vq || vq->vq_used_cons_idx == vq->vq_ring.used->idx)
+ return (NULL);
+
+ VQUEUE_BUSY(vq);
+
+ used_idx = vq->vq_used_cons_idx++ & (vq->vq_nentries - 1);
+ uep = &vq->vq_ring.used->ring[used_idx];
+
+ atomic_thread_fence(memory_order_seq_cst);
+
+ desc_idx = (uint16_t)uep->id;
+ if (len)
+ *len = uep->len;
+
+ vq_ring_free_chain(vq, desc_idx);
+
+ cookie = vq->vq_descx[desc_idx].cookie;
+ vq->vq_descx[desc_idx].cookie = NULL;
+
+ if (idx)
+ *idx = used_idx;
+ VQUEUE_IDLE(vq);
+
+ return cookie;
+}
+
+uint32_t virtqueue_get_buffer_length(struct virtqueue *vq, uint16_t idx)
+{
+ return vq->vq_ring.desc[idx].len;
+}
+
+/**
+ * virtqueue_free - Frees VirtIO queue resources
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ *
+ */
+void virtqueue_free(struct virtqueue *vq)
+{
+ if (vq) {
+ if (vq->vq_free_cnt != vq->vq_nentries) {
+ metal_log(METAL_LOG_WARNING,
+ "%s: freeing non-empty virtqueue\r\n",
+ vq->vq_name);
+ }
+
+ metal_free_memory(vq);
+ }
+}
+
+/**
+ * virtqueue_get_available_buffer - Returns buffer available for use in the
+ * VirtIO queue
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ * @param avail_idx - Pointer to index used in vring desc table
+ * @param len - Length of buffer
+ *
+ * @return - Pointer to available buffer
+ */
+void *virtqueue_get_available_buffer(struct virtqueue *vq, uint16_t *avail_idx,
+ uint32_t *len)
+{
+ uint16_t head_idx = 0;
+ void *buffer;
+
+ atomic_thread_fence(memory_order_seq_cst);
+ if (vq->vq_available_idx == vq->vq_ring.avail->idx) {
+ return NULL;
+ }
+
+ VQUEUE_BUSY(vq);
+
+ head_idx = vq->vq_available_idx++ & (vq->vq_nentries - 1);
+ *avail_idx = vq->vq_ring.avail->ring[head_idx];
+
+ buffer = virtqueue_phys_to_virt(vq, vq->vq_ring.desc[*avail_idx].addr);
+ *len = vq->vq_ring.desc[*avail_idx].len;
+
+ VQUEUE_IDLE(vq);
+
+ return buffer;
+}
+
+/**
+ * virtqueue_add_consumed_buffer - Returns consumed buffer back to VirtIO queue
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ * @param head_idx - Index of vring desc containing used buffer
+ * @param len - Length of buffer
+ *
+ * @return - Function status
+ */
+int virtqueue_add_consumed_buffer(struct virtqueue *vq, uint16_t head_idx,
+ uint32_t len)
+{
+ struct vring_used_elem *used_desc = NULL;
+ uint16_t used_idx;
+
+ if (head_idx > vq->vq_nentries) {
+ return ERROR_VRING_NO_BUFF;
+ }
+
+ VQUEUE_BUSY(vq);
+
+ used_idx = vq->vq_ring.used->idx & (vq->vq_nentries - 1);
+ used_desc = &vq->vq_ring.used->ring[used_idx];
+ used_desc->id = head_idx;
+ used_desc->len = len;
+
+ atomic_thread_fence(memory_order_seq_cst);
+
+ vq->vq_ring.used->idx++;
+
+ VQUEUE_IDLE(vq);
+
+ return VQUEUE_SUCCESS;
+}
+
+/**
+ * virtqueue_enable_cb - Enables callback generation
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ *
+ * @return - Function status
+ */
+int virtqueue_enable_cb(struct virtqueue *vq)
+{
+ return vq_ring_enable_interrupt(vq, 0);
+}
+
+/**
+ * virtqueue_enable_cb - Disables callback generation
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ *
+ */
+void virtqueue_disable_cb(struct virtqueue *vq)
+{
+ VQUEUE_BUSY(vq);
+
+ if (vq->vq_flags & VIRTQUEUE_FLAG_EVENT_IDX) {
+ vring_used_event(&vq->vq_ring) =
+ vq->vq_used_cons_idx - vq->vq_nentries - 1;
+ } else {
+ vq->vq_ring.avail->flags |= VRING_AVAIL_F_NO_INTERRUPT;
+ }
+
+ VQUEUE_IDLE(vq);
+}
+
+/**
+ * virtqueue_kick - Notifies other side that there is buffer available for it.
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ */
+void virtqueue_kick(struct virtqueue *vq)
+{
+ VQUEUE_BUSY(vq);
+
+ /* Ensure updated avail->idx is visible to host. */
+ atomic_thread_fence(memory_order_seq_cst);
+
+ if (vq_ring_must_notify_host(vq))
+ vq_ring_notify_host(vq);
+
+ vq->vq_queued_cnt = 0;
+
+ VQUEUE_IDLE(vq);
+}
+
+/**
+ * virtqueue_dump Dumps important virtqueue fields , use for debugging purposes
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ */
+void virtqueue_dump(struct virtqueue *vq)
+{
+ if (!vq)
+ return;
+
+ metal_log(METAL_LOG_DEBUG,
+ "VQ: %s - size=%d; free=%d; used=%d; queued=%d; "
+ "desc_head_idx=%d; avail.idx=%d; used_cons_idx=%d; "
+ "used.idx=%d; avail.flags=0x%x; used.flags=0x%x\r\n",
+ vq->vq_name, vq->vq_nentries, vq->vq_free_cnt,
+ virtqueue_nused(vq), vq->vq_queued_cnt, vq->vq_desc_head_idx,
+ vq->vq_ring.avail->idx, vq->vq_used_cons_idx,
+ vq->vq_ring.used->idx, vq->vq_ring.avail->flags,
+ vq->vq_ring.used->flags);
+}
+
+/**
+ * virtqueue_get_desc_size - Returns vring descriptor size
+ *
+ * @param vq - Pointer to VirtIO queue control block
+ *
+ * @return - Descriptor length
+ */
+uint32_t virtqueue_get_desc_size(struct virtqueue *vq)
+{
+ uint16_t head_idx = 0;
+ uint16_t avail_idx = 0;
+ uint32_t len = 0;
+
+ if (vq->vq_available_idx == vq->vq_ring.avail->idx) {
+ return 0;
+ }
+
+ VQUEUE_BUSY(vq);
+
+ head_idx = vq->vq_available_idx & (vq->vq_nentries - 1);
+ avail_idx = vq->vq_ring.avail->ring[head_idx];
+ len = vq->vq_ring.desc[avail_idx].len;
+
+ VQUEUE_IDLE(vq);
+
+ return len;
+}
+
+/**************************************************************************
+ * Helper Functions *
+ **************************************************************************/
+
+/**
+ *
+ * vq_ring_add_buffer
+ *
+ */
+static uint16_t vq_ring_add_buffer(struct virtqueue *vq,
+ struct vring_desc *desc, uint16_t head_idx,
+ struct virtqueue_buf *buf_list, int readable,
+ int writable)
+{
+ struct vring_desc *dp;
+ int i, needed;
+ uint16_t idx;
+
+ (void)vq;
+
+ needed = readable + writable;
+
+ for (i = 0, idx = head_idx; i < needed; i++, idx = dp->next) {
+ VQASSERT(vq, idx != VQ_RING_DESC_CHAIN_END,
+ "premature end of free desc chain");
+
+ dp = &desc[idx];
+ dp->addr = virtqueue_virt_to_phys(vq, buf_list[i].buf);
+ dp->len = buf_list[i].len;
+ dp->flags = 0;
+
+ if (i < needed - 1)
+ dp->flags |= VRING_DESC_F_NEXT;
+
+ /*
+ * Readable buffers are inserted into vring before the
+ * writable buffers.
+ */
+ if (i >= readable)
+ dp->flags |= VRING_DESC_F_WRITE;
+ }
+
+ return (idx);
+}
+
+/**
+ *
+ * vq_ring_free_chain
+ *
+ */
+static void vq_ring_free_chain(struct virtqueue *vq, uint16_t desc_idx)
+{
+ struct vring_desc *dp;
+ struct vq_desc_extra *dxp;
+
+ VQ_RING_ASSERT_VALID_IDX(vq, desc_idx);
+ dp = &vq->vq_ring.desc[desc_idx];
+ dxp = &vq->vq_descx[desc_idx];
+
+ if (vq->vq_free_cnt == 0) {
+ VQ_RING_ASSERT_CHAIN_TERM(vq);
+ }
+
+ vq->vq_free_cnt += dxp->ndescs;
+ dxp->ndescs--;
+
+ if ((dp->flags & VRING_DESC_F_INDIRECT) == 0) {
+ while (dp->flags & VRING_DESC_F_NEXT) {
+ VQ_RING_ASSERT_VALID_IDX(vq, dp->next);
+ dp = &vq->vq_ring.desc[dp->next];
+ dxp->ndescs--;
+ }
+ }
+
+ VQASSERT(vq, (dxp->ndescs == 0),
+ "failed to free entire desc chain, remaining");
+
+ /*
+ * We must append the existing free chain, if any, to the end of
+ * newly freed chain. If the virtqueue was completely used, then
+ * head would be VQ_RING_DESC_CHAIN_END (ASSERTed above).
+ */
+ dp->next = vq->vq_desc_head_idx;
+ vq->vq_desc_head_idx = desc_idx;
+}
+
+/**
+ *
+ * vq_ring_init
+ *
+ */
+static void vq_ring_init(struct virtqueue *vq, void *ring_mem, int alignment)
+{
+ struct vring *vr;
+ int i, size;
+
+ size = vq->vq_nentries;
+ vr = &vq->vq_ring;
+
+ vring_init(vr, size, (unsigned char *)ring_mem, alignment);
+
+ for (i = 0; i < size - 1; i++)
+ vr->desc[i].next = i + 1;
+ vr->desc[i].next = VQ_RING_DESC_CHAIN_END;
+}
+
+/**
+ *
+ * vq_ring_update_avail
+ *
+ */
+static void vq_ring_update_avail(struct virtqueue *vq, uint16_t desc_idx)
+{
+ uint16_t avail_idx;
+
+ /*
+ * Place the head of the descriptor chain into the next slot and make
+ * it usable to the host. The chain is made available now rather than
+ * deferring to virtqueue_notify() in the hopes that if the host is
+ * currently running on another CPU, we can keep it processing the new
+ * descriptor.
+ */
+ avail_idx = vq->vq_ring.avail->idx & (vq->vq_nentries - 1);
+ vq->vq_ring.avail->ring[avail_idx] = desc_idx;
+
+ atomic_thread_fence(memory_order_seq_cst);
+
+ vq->vq_ring.avail->idx++;
+
+ /* Keep pending count until virtqueue_notify(). */
+ vq->vq_queued_cnt++;
+}
+
+/**
+ *
+ * vq_ring_enable_interrupt
+ *
+ */
+static int vq_ring_enable_interrupt(struct virtqueue *vq, uint16_t ndesc)
+{
+ /*
+ * Enable interrupts, making sure we get the latest index of
+ * what's already been consumed.
+ */
+ if (vq->vq_flags & VIRTQUEUE_FLAG_EVENT_IDX) {
+ vring_used_event(&vq->vq_ring) = vq->vq_used_cons_idx + ndesc;
+ } else {
+ vq->vq_ring.avail->flags &= ~VRING_AVAIL_F_NO_INTERRUPT;
+ }
+
+ atomic_thread_fence(memory_order_seq_cst);
+
+ /*
+ * Enough items may have already been consumed to meet our threshold
+ * since we last checked. Let our caller know so it processes the new
+ * entries.
+ */
+ if (virtqueue_nused(vq) > ndesc) {
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ *
+ * virtqueue_interrupt
+ *
+ */
+void virtqueue_notification(struct virtqueue *vq)
+{
+ atomic_thread_fence(memory_order_seq_cst);
+ if (vq->callback)
+ vq->callback(vq);
+}
+
+/**
+ *
+ * vq_ring_must_notify_host
+ *
+ */
+static int vq_ring_must_notify_host(struct virtqueue *vq)
+{
+ uint16_t new_idx, prev_idx, event_idx;
+
+ if (vq->vq_flags & VIRTQUEUE_FLAG_EVENT_IDX) {
+ new_idx = vq->vq_ring.avail->idx;
+ prev_idx = new_idx - vq->vq_queued_cnt;
+ event_idx = vring_avail_event(&vq->vq_ring);
+
+ return (vring_need_event(event_idx, new_idx, prev_idx) != 0);
+ }
+
+ return ((vq->vq_ring.used->flags & VRING_USED_F_NO_NOTIFY) == 0);
+}
+
+/**
+ *
+ * vq_ring_notify_host
+ *
+ */
+static void vq_ring_notify_host(struct virtqueue *vq)
+{
+ if (vq->notify)
+ vq->notify(vq);
+}
+
+/**
+ *
+ * virtqueue_nused
+ *
+ */
+static int virtqueue_nused(struct virtqueue *vq)
+{
+ uint16_t used_idx, nused;
+
+ used_idx = vq->vq_ring.used->idx;
+
+ nused = (uint16_t)(used_idx - vq->vq_used_cons_idx);
+ VQASSERT(vq, nused <= vq->vq_nentries, "used more than available");
+
+ return nused;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.c b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.c
new file mode 100644
index 0000000..dd16a0f
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.c
@@ -0,0 +1,128 @@
+/**
+ ******************************************************************************
+ * @file virt_uart.c
+ * @author MCD Application Team
+ * @brief UART HAL module driver.
+ * This file provides firmware functions to manage an rpmsg endpoint
+ * from user application
+ *
+ *
+ @verbatim
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ The VIRTUAL UART driver can be used as follows:
+ (#) Initialize the Virtual UART by calling the VIRT_UART_Init() API.
+ (++) create an endpoint. listener on the OpenAMP-rpmsg channel is now enabled.
+ Receive data is now possible if user registers a callback to this VIRTUAL UART instance
+ by calling in providing a callback function when a message is received from
+ remote processor (VIRT_UART_read_cb)
+ OpenAMP MW deals with memory allocation/free and signal events
+ (#) Transmit data on the created rpmsg channel by calling the VIRT_UART_Transmit()
+ (#) Receive data in calling VIRT_UART_RegisterCallback to register user callback
+
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "virt_uart.h"
+#include "metal/utilities.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* this string will be sent to remote processor */
+#define RPMSG_SERVICE_NAME "rpmsg-tty-channel"
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+static int VIRT_UART_read_cb(struct rpmsg_endpoint *ept, void *data,
+ size_t len, uint32_t src, void *priv)
+{
+ VIRT_UART_HandleTypeDef *huart = metal_container_of(ept, VIRT_UART_HandleTypeDef, ept);
+ (void)src;
+
+ huart->pRxBuffPtr = data;
+ huart->RxXferSize = len;
+ if (huart->RxCpltCallback != NULL) {
+ huart->RxCpltCallback(huart);
+ }
+
+ return 0;
+}
+
+VIRT_UART_StatusTypeDef VIRT_UART_Init(VIRT_UART_HandleTypeDef *huart)
+{
+
+ int status;
+
+ /* Create a endpoint for rmpsg communication */
+
+ status = OPENAMP_create_endpoint(&huart->ept, RPMSG_SERVICE_NAME, RPMSG_ADDR_ANY,
+ VIRT_UART_read_cb, NULL);
+
+ if(status < 0) {
+ return VIRT_UART_ERROR;
+ }
+
+ return VIRT_UART_OK;
+}
+
+VIRT_UART_StatusTypeDef VIRT_UART_DeInit (VIRT_UART_HandleTypeDef *huart)
+{
+ OPENAMP_destroy_ept(&huart->ept);
+
+ return VIRT_UART_OK;
+}
+
+VIRT_UART_StatusTypeDef VIRT_UART_RegisterCallback(VIRT_UART_HandleTypeDef *huart,
+ VIRT_UART_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(VIRT_UART_HandleTypeDef *_huart))
+{
+ VIRT_UART_StatusTypeDef status = VIRT_UART_OK;
+
+ switch (CallbackID)
+ {
+ case VIRT_UART_RXCPLT_CB_ID :
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = VIRT_UART_ERROR;
+ break;
+ }
+ return status;
+
+ return VIRT_UART_OK;
+}
+
+VIRT_UART_StatusTypeDef VIRT_UART_Transmit(VIRT_UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ int res;
+
+ if (Size > (RPMSG_BUFFER_SIZE-16))
+ return VIRT_UART_ERROR;
+
+ res = OPENAMP_send(&huart->ept, pData, Size);
+ if (res <0) {
+ return VIRT_UART_ERROR;
+ }
+
+ return VIRT_UART_OK;
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.h b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.h
new file mode 100644
index 0000000..d810908
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/Middlewares/Third_Party/OpenAMP/virtual_driver/virt_uart.h
@@ -0,0 +1,76 @@
+/**
+ ******************************************************************************
+ * @file virt_uart.h
+ * @author MCD Application Team
+ * @brief Header file of UART VIRT module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __VIRT_UART_H
+#define __VIRT_UART_H
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "openamp.h"
+
+/* Exported structures --------------------------------------------------------*/
+typedef struct __VIRT_UART_HandleTypeDef
+{
+ struct rpmsg_endpoint ept; /*!< rpmsg endpoint */
+ struct rpmsg_virtio_device *rvdev; /*< pointer to the rpmsg virtio device */
+ uint8_t *pRxBuffPtr; /*!< Pointer to VIRTUAL UART Rx transfer Buffer */
+ uint16_t RxXferSize; /*!< VIRTUAL UART Rx Transfer size */
+ void (* RxCpltCallback)( struct __VIRT_UART_HandleTypeDef * hppp); /*!< RX CPLT callback */
+}VIRT_UART_HandleTypeDef;
+
+
+typedef enum
+{
+ VIRT_UART_OK = 0x00U,
+ VIRT_UART_ERROR = 0x01U,
+ VIRT_UART_BUSY = 0x02U,
+ VIRT_UART_TIMEOUT = 0x03U
+} VIRT_UART_StatusTypeDef;
+
+
+typedef enum
+{
+ VIRT_UART_RXCPLT_CB_ID = 0x00U, /*!< PPP event 1 callback ID */
+}VIRT_UART_CallbackIDTypeDef;
+
+
+/* Exported functions --------------------------------------------------------*/
+/* Initialization and de-initialization functions ****************************/
+VIRT_UART_StatusTypeDef VIRT_UART_Init(VIRT_UART_HandleTypeDef *huart);
+VIRT_UART_StatusTypeDef VIRT_UART_DeInit (VIRT_UART_HandleTypeDef *huart);
+VIRT_UART_StatusTypeDef VIRT_UART_RegisterCallback(VIRT_UART_HandleTypeDef *huart,
+ VIRT_UART_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(VIRT_UART_HandleTypeDef *_huart));
+
+/* IO operation functions *****************************************************/
+VIRT_UART_StatusTypeDef VIRT_UART_Transmit(VIRT_UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __VIRT_UART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/txt2-M4-rt-core/cubemx/txt/startup/startup_stm32mp15xx.s b/txt2-M4-rt-core/cubemx/txt/startup/startup_stm32mp15xx.s
new file mode 100644
index 0000000..de977d6
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/startup/startup_stm32mp15xx.s
@@ -0,0 +1,792 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32mp15xx.s
+ * @author MCD Application Team
+ * @brief STM32MP15xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+ .section .startup_copro_fw.Reset_Handler,"ax"
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * _sidata: End of code section, i.e., begin of data sections to copy from.
+ * _sdata/_edata: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+
+ bl SystemInit
+ // ldr r0, =SystemInit
+ // blx r0
+/* Call static constructors */
+ bl __libc_init_array
+ // ldr r0, =__libc_init_array
+ // blx r0
+/* Call the application's entry point.*/
+ bl main
+ //ldr r0, =main
+ //blx r0
+
+LoopForever:
+ b LoopForever
+
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack // Top of Stack
+ .word Reset_Handler // Reset Handler
+ .word NMI_Handler // NMI Handler
+ .word HardFault_Handler // Hard Fault Handler
+ .word MemManage_Handler // MPU Fault Handler
+ .word BusFault_Handler // Bus Fault Handler
+ .word UsageFault_Handler // Usage Fault Handler
+ .word 0 // Reserved
+ .word 0 // Reserved
+ .word 0 // Reserved
+ .word 0 // Reserved
+ .word SVC_Handler // SVCall Handler
+ .word DebugMon_Handler // Debug Monitor Handler
+ .word 0 // Reserved
+ .word PendSV_Handler // PendSV Handler
+ .word SysTick_Handler // SysTick Handler
+
+ // External Interrupts
+ .word WWDG1_IRQHandler // Window WatchDog 1
+ .word PVD_AVD_IRQHandler // PVD and AVD through EXTI Line detection
+ .word TAMP_IRQHandler // Tamper and TimeStamps through the EXTI line
+ .word RTC_WKUP_ALARM_IRQHandler // RTC Wakeup and Alarm through the EXTI line
+ .word RESERVED4_IRQHandler // Reserved
+ .word RCC_IRQHandler // RCC
+ .word EXTI0_IRQHandler // EXTI Line0
+ .word EXTI1_IRQHandler // EXTI Line1
+ .word EXTI2_IRQHandler // EXTI Line2
+ .word EXTI3_IRQHandler // EXTI Line3
+ .word EXTI4_IRQHandler // EXTI Line4
+ .word DMA1_Stream0_IRQHandler // DMA1 Stream 0
+ .word DMA1_Stream1_IRQHandler // DMA1 Stream 1
+ .word DMA1_Stream2_IRQHandler // DMA1 Stream 2
+ .word DMA1_Stream3_IRQHandler // DMA1 Stream 3
+ .word DMA1_Stream4_IRQHandler // DMA1 Stream 4
+ .word DMA1_Stream5_IRQHandler // DMA1 Stream 5
+ .word DMA1_Stream6_IRQHandler // DMA1 Stream 6
+ .word ADC1_IRQHandler // ADC1
+ .word FDCAN1_IT0_IRQHandler // FDCAN1 Interrupt line 0
+ .word FDCAN2_IT0_IRQHandler // FDCAN2 Interrupt line 0
+ .word FDCAN1_IT1_IRQHandler // FDCAN1 Interrupt line 1
+ .word FDCAN2_IT1_IRQHandler // FDCAN2 Interrupt line 1
+ .word EXTI5_IRQHandler // External Line5 interrupts through AIEC
+ .word TIM1_BRK_IRQHandler // TIM1 Break interrupt
+ .word TIM1_UP_IRQHandler // TIM1 Update Interrupt
+ .word TIM1_TRG_COM_IRQHandler // TIM1 Trigger and Commutation Interrupt
+ .word TIM1_CC_IRQHandler // TIM1 Capture Compare
+ .word TIM2_IRQHandler // TIM2
+ .word TIM3_IRQHandler // TIM3
+ .word TIM4_IRQHandler // TIM4
+ .word I2C1_EV_IRQHandler // I2C1 Event
+ .word I2C1_ER_IRQHandler // I2C1 Error
+ .word I2C2_EV_IRQHandler // I2C2 Event
+ .word I2C2_ER_IRQHandler // I2C2 Error
+ .word SPI1_IRQHandler // SPI1
+ .word SPI2_IRQHandler // SPI2
+ .word USART1_IRQHandler // USART1
+ .word USART2_IRQHandler // USART2
+ .word USART3_IRQHandler // USART3
+ .word EXTI10_IRQHandler // External Line10 interrupts through AIEC
+ .word RTC_TIMESTAMP_IRQHandler // RTC TimeStamp through EXTI Line
+ .word EXTI11_IRQHandler // External Line11 interrupts through AIEC
+ .word TIM8_BRK_IRQHandler // TIM8 Break Interrupt
+ .word TIM8_UP_IRQHandler // TIM8 Update Interrupt
+ .word TIM8_TRG_COM_IRQHandler // TIM8 Trigger and Commutation Interrupt
+ .word TIM8_CC_IRQHandler // TIM8 Capture Compare Interrupt
+ .word DMA1_Stream7_IRQHandler // DMA1 Stream7
+ .word FMC_IRQHandler // FMC
+ .word SDMMC1_IRQHandler // SDMMC1
+ .word TIM5_IRQHandler // TIM5
+ .word SPI3_IRQHandler // SPI3
+ .word UART4_IRQHandler // UART4
+ .word UART5_IRQHandler // UART5
+ .word TIM6_IRQHandler // TIM6
+ .word TIM7_IRQHandler // TIM7
+ .word DMA2_Stream0_IRQHandler // DMA2 Stream 0
+ .word DMA2_Stream1_IRQHandler // DMA2 Stream 1
+ .word DMA2_Stream2_IRQHandler // DMA2 Stream 2
+ .word DMA2_Stream3_IRQHandler // DMA2 Stream 3
+ .word DMA2_Stream4_IRQHandler // DMA2 Stream 4
+ .word ETH1_IRQHandler // Ethernet
+ .word ETH1_WKUP_IRQHandler // Ethernet Wakeup through EXTI line
+ .word FDCAN_CAL_IRQHandler // FDCAN Calibration
+ .word EXTI6_IRQHandler // EXTI Line6 interrupts through AIEC
+ .word EXTI7_IRQHandler // EXTI Line7 interrupts through AIEC
+ .word EXTI8_IRQHandler // EXTI Line8 interrupts through AIEC
+ .word EXTI9_IRQHandler // EXTI Line9 interrupts through AIEC
+ .word DMA2_Stream5_IRQHandler // DMA2 Stream 5
+ .word DMA2_Stream6_IRQHandler // DMA2 Stream 6
+ .word DMA2_Stream7_IRQHandler // DMA2 Stream 7
+ .word USART6_IRQHandler // USART6
+ .word I2C3_EV_IRQHandler // I2C3 event
+ .word I2C3_ER_IRQHandler // I2C3 error
+ .word USBH_OHCI_IRQHandler // USB Host OHCI
+ .word USBH_EHCI_IRQHandler // USB Host EHCI
+ .word EXTI12_IRQHandler // EXTI Line12 interrupts through AIEC
+ .word EXTI13_IRQHandler // EXTI Line13 interrupts through AIEC
+ .word DCMI_IRQHandler // DCMI
+ .word CRYP1_IRQHandler // Crypto1 global interrupt
+ .word HASH1_IRQHandler // Crypto Hash1 interrupt
+ .word FPU_IRQHandler // FPU
+ .word UART7_IRQHandler // UART7
+ .word UART8_IRQHandler // UART8
+ .word SPI4_IRQHandler // SPI4
+ .word SPI5_IRQHandler // SPI5
+ .word SPI6_IRQHandler // SPI6
+ .word SAI1_IRQHandler // SAI1
+ .word LTDC_IRQHandler // LTDC
+ .word LTDC_ER_IRQHandler // LTDC error
+ .word ADC2_IRQHandler // ADC2
+ .word SAI2_IRQHandler // SAI2
+ .word QUADSPI_IRQHandler // QUADSPI
+ .word LPTIM1_IRQHandler // LPTIM1 global interrupt
+ .word CEC_IRQHandler // HDMI_CEC
+ .word I2C4_EV_IRQHandler // I2C4 Event
+ .word I2C4_ER_IRQHandler // I2C4 Error
+ .word SPDIF_RX_IRQHandler // SPDIF_RX
+ .word OTG_IRQHandler // USB On The Go HS global interrupt
+ .word RESERVED99_IRQHandler // Reserved
+ .word IPCC_RX0_IRQHandler // Mailbox RX0 Free interrupt
+ .word IPCC_TX0_IRQHandler // Mailbox TX0 Free interrupt
+ .word DMAMUX1_OVR_IRQHandler // DMAMUX1 Overrun interrupt
+ .word IPCC_RX1_IRQHandler // Mailbox RX1 Free interrupt
+ .word IPCC_TX1_IRQHandler // Mailbox TX1 Free interrupt
+ .word CRYP2_IRQHandler // Crypto2 global interrupt
+ .word HASH2_IRQHandler // Crypto Hash2 interrupt
+ .word I2C5_EV_IRQHandler // I2C5 Event Interrupt
+ .word I2C5_ER_IRQHandler // I2C5 Error Interrupt
+ .word GPU_IRQHandler // GPU Global Interrupt
+ .word DFSDM1_FLT0_IRQHandler // DFSDM Filter0 Interrupt
+ .word DFSDM1_FLT1_IRQHandler // DFSDM Filter1 Interrupt
+ .word DFSDM1_FLT2_IRQHandler // DFSDM Filter2 Interrupt
+ .word DFSDM1_FLT3_IRQHandler // DFSDM Filter3 Interrupt
+ .word SAI3_IRQHandler // SAI3 global Interrupt
+ .word DFSDM1_FLT4_IRQHandler // DFSDM Filter4 Interrupt
+ .word TIM15_IRQHandler // TIM15 global Interrupt
+ .word TIM16_IRQHandler // TIM16 global Interrupt
+ .word TIM17_IRQHandler // TIM17 global Interrupt
+ .word TIM12_IRQHandler // TIM12 global Interrupt
+ .word MDIOS_IRQHandler // MDIOS global Interrupt
+ .word EXTI14_IRQHandler // EXTI Line14 interrupts through AIEC
+ .word MDMA_IRQHandler // MDMA global Interrupt
+ .word DSI_IRQHandler // DSI global Interrupt
+ .word SDMMC2_IRQHandler // SDMMC2 global Interrupt
+ .word HSEM_IT2_IRQHandler // HSEM global Interrupt
+ .word DFSDM1_FLT5_IRQHandler // DFSDM Filter5 Interrupt
+ .word EXTI15_IRQHandler // EXTI Line15 interrupts through AIEC
+ .word nCTIIRQ1_IRQHandler // Cortex-M4 CTI interrupt 1
+ .word nCTIIRQ2_IRQHandler // Cortex-M4 CTI interrupt 2
+ .word TIM13_IRQHandler // TIM13 global interrupt
+ .word TIM14_IRQHandler // TIM14 global interrupt
+ .word DAC_IRQHandler // DAC1 and DAC2 underrun error interrupts
+ .word RNG1_IRQHandler // RNG1 interrupt
+ .word RNG2_IRQHandler // RNG2 interrupt
+ .word I2C6_EV_IRQHandler // I2C6 Event Interrupt
+ .word I2C6_ER_IRQHandler // I2C6 Error Interrupt
+ .word SDMMC3_IRQHandler // SDMMC3 global Interrupt
+ .word LPTIM2_IRQHandler // LPTIM2 global interrupt
+ .word LPTIM3_IRQHandler // LPTIM3 global interrupt
+ .word LPTIM4_IRQHandler // LPTIM4 global interrupt
+ .word LPTIM5_IRQHandler // LPTIM5 global interrupt
+ .word ETH1_LPI_IRQHandler // ETH1_LPI interrupt
+ .word RESERVED143_IRQHandler // Reserved
+ .word MPU_SEV_IRQHandler // MPU Send Event through AIEC
+ .word RCC_WAKEUP_IRQHandler // RCC Wake up interrupt
+ .word SAI4_IRQHandler // SAI4 global interrupt
+ .word DTS_IRQHandler // Temperature sensor interrupt
+ .word RESERVED148_IRQHandler // Reserved
+ .word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak RESERVED4_IRQHandler
+ .thumb_set RESERVED4_IRQHandler,Default_Handler
+
+ .weak RESERVED99_IRQHandler
+ .thumb_set RESERVED99_IRQHandler,Default_Handler
+
+ .weak ETH1_LPI_IRQHandler
+ .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+ .weak RESERVED143_IRQHandler
+ .thumb_set RESERVED143_IRQHandler,Default_Handler
+
+ .weak WWDG1_IRQHandler
+ .thumb_set WWDG1_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_IRQHandler
+ .thumb_set TAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_ALARM_IRQHandler
+ .thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak ADC2_IRQHandler
+ .thumb_set ADC2_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak EXTI5_IRQHandler
+ .thumb_set EXTI5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI10_IRQHandler
+ .thumb_set EXTI10_IRQHandler,Default_Handler
+
+ .weak RTC_TIMESTAMP_IRQHandler
+ .thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
+
+ .weak EXTI11_IRQHandler
+ .thumb_set EXTI11_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH1_IRQHandler
+ .thumb_set ETH1_IRQHandler,Default_Handler
+
+ .weak ETH1_WKUP_IRQHandler
+ .thumb_set ETH1_WKUP_IRQHandler,Default_Handler
+
+ .weak ETH1_LPI_IRQHandler
+ .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+ .weak EXTI6_IRQHandler
+ .thumb_set EXTI6_IRQHandler,Default_Handler
+
+ .weak EXTI7_IRQHandler
+ .thumb_set EXTI7_IRQHandler,Default_Handler
+
+ .weak EXTI8_IRQHandler
+ .thumb_set EXTI8_IRQHandler,Default_Handler
+
+ .weak EXTI9_IRQHandler
+ .thumb_set EXTI9_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak USBH_OHCI_IRQHandler
+ .thumb_set USBH_OHCI_IRQHandler,Default_Handler
+
+ .weak USBH_EHCI_IRQHandler
+ .thumb_set USBH_EHCI_IRQHandler,Default_Handler
+
+ .weak EXTI12_IRQHandler
+ .thumb_set EXTI12_IRQHandler,Default_Handler
+
+ .weak EXTI13_IRQHandler
+ .thumb_set EXTI13_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak CRYP1_IRQHandler
+ .thumb_set CRYP1_IRQHandler,Default_Handler
+
+ .weak HASH1_IRQHandler
+ .thumb_set HASH1_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_IRQHandler
+ .thumb_set OTG_IRQHandler,Default_Handler
+
+ .weak IPCC_RX0_IRQHandler
+ .thumb_set IPCC_RX0_IRQHandler,Default_Handler
+
+ .weak IPCC_TX0_IRQHandler
+ .thumb_set IPCC_TX0_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak IPCC_RX1_IRQHandler
+ .thumb_set IPCC_RX1_IRQHandler,Default_Handler
+
+ .weak IPCC_TX1_IRQHandler
+ .thumb_set IPCC_TX1_IRQHandler,Default_Handler
+
+ .weak CRYP2_IRQHandler
+ .thumb_set CRYP2_IRQHandler,Default_Handler
+
+ .weak HASH2_IRQHandler
+ .thumb_set HASH2_IRQHandler,Default_Handler
+
+ .weak I2C5_EV_IRQHandler
+ .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+ .weak I2C5_ER_IRQHandler
+ .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+ .weak GPU_IRQHandler
+ .thumb_set GPU_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak TIM12_IRQHandler
+ .thumb_set TIM12_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak EXTI14_IRQHandler
+ .thumb_set EXTI14_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak DSI_IRQHandler
+ .thumb_set DSI_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM_IT2_IRQHandler
+ .thumb_set HSEM_IT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak EXTI15_IRQHandler
+ .thumb_set EXTI15_IRQHandler,Default_Handler
+
+ .weak nCTIIRQ1_IRQHandler
+ .thumb_set nCTIIRQ1_IRQHandler,Default_Handler
+
+ .weak nCTIIRQ2_IRQHandler
+ .thumb_set nCTIIRQ2_IRQHandler,Default_Handler
+
+ .weak TIM13_IRQHandler
+ .thumb_set TIM13_IRQHandler,Default_Handler
+
+ .weak TIM14_IRQHandler
+ .thumb_set TIM14_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak RNG1_IRQHandler
+ .thumb_set RNG1_IRQHandler,Default_Handler
+
+ .weak RNG2_IRQHandler
+ .thumb_set RNG2_IRQHandler,Default_Handler
+
+ .weak I2C6_EV_IRQHandler
+ .thumb_set I2C6_EV_IRQHandler,Default_Handler
+
+ .weak I2C6_ER_IRQHandler
+ .thumb_set I2C6_ER_IRQHandler,Default_Handler
+
+ .weak SDMMC3_IRQHandler
+ .thumb_set SDMMC3_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak MPU_SEV_IRQHandler
+ .thumb_set MPU_SEV_IRQHandler,Default_Handler
+
+ .weak RCC_WAKEUP_IRQHandler
+ .thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak RESERVED148_IRQHandler
+ .thumb_set RESERVED148_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/txt2-M4-rt-core/cubemx/txt/stm32mp15xx_m4.ld b/txt2-M4-rt-core/cubemx/txt/stm32mp15xx_m4.ld
new file mode 100644
index 0000000..34d63f4
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/stm32mp15xx_m4.ld
@@ -0,0 +1,202 @@
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld
+**
+** Abstract : Linker script for STM32MP1 series
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed “as is,†without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>© Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the License; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+** opensource.org/licenses/BSD-3-Clause
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x10040000; /* end of RAM */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000298
+ m_text (RX) : ORIGIN = 0x10000000, LENGTH = 0x00020000
+ m_data (RW) : ORIGIN = 0x10020000, LENGTH = 0x00020000
+ m_ipc_shm (RW) : ORIGIN = 0x10040000, LENGTH = 0x00008000
+}
+
+ /* Symbols needed for OpenAMP to enable rpmsg */
+__OPENAMP_region_start__ = ORIGIN(m_ipc_shm);
+__OPENAMP_region_end__ = ORIGIN(m_ipc_shm)+LENGTH(m_ipc_shm);
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into ROM memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+
+ /* The program code and other data into ROM memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } > m_text
+
+ /* Constant data into ROM memory*/
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } > m_text
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } > m_text
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } > m_text
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } > m_text
+
+ /* Used by the startup to initialize data */
+ __DATA_ROM = .;
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections */
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (_edata - _sdata);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ .resource_table :
+ {
+ . = ALIGN(4);
+ KEEP (*(.resource_table*))
+ . = ALIGN(4);
+ } > m_data
+
+
+ /* Uninitialized data section into RAM memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } > m_data
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } > m_data
+
+
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+}
diff --git a/txt2-M4-rt-core/cubemx/txt/txt2.ioc b/txt2-M4-rt-core/cubemx/txt/txt2.ioc
new file mode 100644
index 0000000..0bc785e
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/txt2.ioc
@@ -0,0 +1,1399 @@
+#MicroXplorer Configuration settings - do not modify
+PF7.GPIOParameters=GPIO_Label,GPIO_Speed_Medium_Default
+PD7.Mode=SD_4_bits_Wide_bus
+RCC.HSIDivClkFreq_Value=64000000
+DDR_DQ13.Mode=DDR3
+VP_TIM5_VS_ClockSourceINT.Mode=Internal
+PB13.GPIOParameters=GPIO_PuPd,GPIO_Label
+PD12.GPIO_Label=TOUCH_SCL
+PC7.GPIOParameters=GPIO_Label
+PC10.GPIO_PuPd=GPIO_PULLUP
+DDR_ATO.GPIOParameters=GPIO_Label
+TIM4.Channel-Input_Capture3_from_TI3=TIM_CHANNEL_3
+VP_DDR_DDR3.Signal=DDR_DDR3
+PE11.GPIOParameters=GPIO_Label
+DDR_CKE.GPIOParameters=GPIO_Label
+PG8.Signal=S_TIM2_CH1
+FDCAN1.RxBuffersNbr=2
+DDR_CASN.Mode=DDR3
+RCC.RTCFreq_Value=32768
+RCC.PLLDSIFreq_Value=480000000
+PE10.GPIO_PuPd=GPIO_PULLDOWN
+PD2.GPIOParameters=GPIO_PuPd,GPIO_Label
+PG14.GPIOParameters=GPIO_Label
+RCC.SPI23Freq_Value=50000000
+RCC.I2C12Freq_Value=64000000
+PA2.GPIOParameters=GPIO_Label
+DDR_DQS0P.Mode=DDR3
+RCC.UART78CLockSelection=RCC_UART78CLKSOURCE_PCLK1
+DDR.tRC=50.625
+DDR_DQ3.GPIOParameters=GPIO_Label
+RCC.PLL3Source=RCC_PLL3SOURCE_HSE
+RCC.LPTIM1Freq_Value=100000000
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
+DDR_A10.GPIOParameters=GPIO_Label
+PG15.GPIO_Label=WIFI
+DDR_DTO1.Mode=DDR3
+PF7.Signal=QUADSPI_BK1_IO2
+PD7.GPIO_PuPd=GPIO_PULLUP
+GIC.IPCC_RX0_IRQn=true\:false\:High level
+RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_PER
+SPI1.Direction=SPI_DIRECTION_2LINES_TXONLY
+SPI3.VirtualNSS=VM_NSSHARD
+DDR.tRP=13.125
+NVIC.IPCC_RX1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true
+RCC.PLL4FRACV=0
+PB6.Signal=QUADSPI_BK1_NCS
+PC7.Signal=S_TIM8_CH2
+SPI1.CalculateBaudRate=60.0 MBits/s
+PD0.Signal=SDMMC3_CMD
+PE1.Signal=GPIO_Input
+FREERTOS.configMINIMAL_STACK_SIZE=512
+PE14.Locked=true
+DDR.t_ras_max=0
+USB_DM1.Mode=Enable
+SPI3.MasterReceiverAutoSusp=SPI_MASTER_RX_AUTOSUSP_ENABLE
+DDR.tRCD=13.125
+ProjectManager.ProjectBuild=false
+DDR_DQ1.GPIOParameters=GPIO_Label
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+DDR_A12.GPIOParameters=GPIO_Label
+PA0.Locked=true
+PB3.Mode=mmc_4_bits_Wide_bus
+PA8.Locked=true
+DDR_BA0.Mode=DDR3
+DDR_DTO0.GPIOParameters=GPIO_Label
+RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
+RCC.APB5DIVClockFreq_Value=66000000
+PD1.GPIO_Label=WIFI
+VP_BSEC_VS_BSEC.Mode=BSEC_Activate
+PB12.GPIO_Label=AUDIO
+PG14.Mode=Half_duplex(single_wire_mode)
+ProjectManager.FirmwarePackage=STM32Cube FW_MP1 V1.2.0
+DDR_A6.Mode=DDR3
+DDR_DTO1.GPIO_Label=DDR Memory
+RCC.AXIDIVFreq_Value=264000000
+ProjectManager.BackupPrevious=false
+DDR_A10.Signal=DDR_A10
+RCC.FMCFreq_Value=264000000
+SH.S_TIM12_CH1.0=TIM12_CH1,Input_Capture1_from_TI1
+PC4.GPIO_Label=AIO_IN
+PG12.GPIOParameters=GPIO_Label
+PE9.Signal=GPIO_Input
+GIC.DTS_IRQn=true\:false\:High level
+VP_VREFBUF_VS_VREFBUF.Signal=VREFBUF_VS_VREFBUF
+PE9.Locked=true
+FDCAN1.TransmitPause=DISABLE
+DDR_A7.Mode=DDR3
+PB1.GPIO_Label=COUNTER_2
+PF7.GPIO_Speed_Medium_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE4.GPIO_Label=CAN_STANDBY
+GIC.USBH_OHCI_IRQn=true\:false\:High level
+PC9.Mode=SD_4_bits_Wide_bus
+DDR.t_xp=10
+DDR_DQM1.GPIOParameters=GPIO_Label
+VP_ETZPC_VS_ETZPC.Signal=ETZPC_VS_ETZPC
+I2S2.IPParameters=Instance,VirtualMode,FullDuplexMode,RealAudioFreq,ErrorAudioFreq
+PA8.Signal=GPIO_Output
+DDR_A3.GPIO_Label=DDR Memory
+PE1.Locked=true
+RCC.SPI1CLockSelection=RCC_SPI1CLKSOURCE_PLL3_Q
+DDR_CASN.GPIOParameters=GPIO_Label
+ProjectManager.HalAssertFull=false
+PB2.GPIO_PuPd=GPIO_PULLUP
+RCC.DIVP2Freq_Value=264000000
+DDR_A10.GPIO_Label=DDR Memory
+PA0.Signal=GPIO_Input
+DDR_A9.GPIOParameters=GPIO_Label
+DDR_CASN.GPIO_Label=DDR Memory
+SH.ADCx_INP4.ConfNb=1
+Mcu.Package=TFBGA257
+PB9.Signal=I2C1_SDA
+TIM2.Prescaler=Prescaler
+PB1.Signal=S_TIM3_CH4
+RCC.LPTIM23Freq_Value=100000000
+SPI3.Mode=SPI_MODE_MASTER
+JTMS-SWDIO.Mode=JTAG_5_pins
+PD12.Signal=I2C1_SCL
+RCC.PLL3FRACV=0
+DDR_CKE.GPIO_Label=DDR Memory
+DDR_A1.Signal=DDR_A1
+DDR_A6.Signal=DDR_A6
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+DDR_A9.Signal=DDR_A9
+PA10.Signal=USB_OTG_HS_ID
+FREERTOS.FootprintOK=true
+PE12.GPIO_Label=AUDIO_NRESET
+TIM7.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+Mcu.Context4=CortexM4
+PC11.Mode=SD_4_bits_Wide_bus
+Mcu.Context2=CortexA7S
+Mcu.Context3=CortexA7NS
+Mcu.Context0=BootROM
+RCC.AXICLKSource=RCC_AXISSOURCE_PLL2
+Mcu.Context1=BootLoader
+DDR.t_xs_x32=5
+RCC.DSI_VALUE=60000000
+FREERTOS.configGENERATE_RUN_TIME_STATS=1
+PF10.Mode=Single Bank 1
+PE6.Locked=true
+DDR_A5.GPIOParameters=GPIO_Label
+PF6.GPIO_Speed_Medium_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE6.GPIO_PuPd=GPIO_PULLUP
+DDR.wr2rd=14
+PA4.GPIO_Label=USB_OC
+USB_DP1.GPIO_Label=USB Host
+DDR_BA0.GPIO_Label=DDR Memory
+PD15.Signal=GPIO_Output
+RCC.STGENCLockSelection=RCC_STGENCLKSOURCE_HSE
+RCC.VCO3OutputFreq_Value=600000000
+DDR_DQS1N.Signal=DDR_DQS1N
+PG12.Signal=GPIO_Output
+PA5.Mode=TX_Only_Simplex_Unidirect_Master
+DDR_DQ14.GPIOParameters=GPIO_Label
+PA6.GPIOParameters=GPIO_Label
+USART6.FIFOMode=FIFOMODE_ENABLE
+Mcu.Pin80=PG14
+PD6.GPIOParameters=GPIO_Label
+Mcu.Pin81=PG13
+ProjectManager.ProjectFileName=txt2.ioc
+FREERTOS.Tasks01=ftserver,8,2048,appmain,As weak,NULL,Static,ftserverBuffer,ftserverControlBlock;hwloop,8,1024,ftopThread,As external,NULL,Static,hwloopBuffer,hwloopControlBlock;NotificationThr,8,1024,sendThread,As external,NULL,Static,NotificationThrBuffer,NotificationThrControlBlock;RTExtEngine,8,512,HWFDCAN_thread,As external,NULL,Static,RTExtEngineBuffer,RTExtEngineControlBlock;MotorTask,16,512,MotorTaskStart,As external,NULL,Static,MotorTaskBuffer,MotorTaskControlBlock
+DDR_A0.Mode=DDR3
+Mcu.Pin79=DDR_BA1
+Mcu.PinsNb=181
+Mcu.Pin73=DDR_A14
+Mcu.Pin74=DDR_A11
+Mcu.Pin71=PA3
+Mcu.Pin72=PA0
+Mcu.Pin77=PC3
+PC13.Locked=true
+RCC.DDRPHYFreq_Value=528000000
+DDR_A14.GPIOParameters=GPIO_Label
+Mcu.Pin78=DDR_CKE
+ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
+Mcu.Pin75=PE2
+PC13.Signal=GPIO_Output
+Mcu.Pin76=PC2
+PB6.GPIO_PuPd=GPIO_PULLUP
+FDCAN1.ProtocolException=ENABLE
+PD3.Signal=I2S2_CK
+DDR_DTO0.Mode=DDR3
+Mcu.Pin70=DDR_A1
+DDR.t_rp=3
+PC2.Signal=I2S2_SDI
+RCC.AXICLKFreq_VALUE=264000000
+Mcu.Pin68=DDR_A10
+Mcu.Pin69=DDR_A12
+PB14.Locked=true
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+GIC.I2C4_EV_IRQn=true\:false\:High level
+PD6.Mode=Full_Duplex_Master
+RCC.SPI45CLockSelection=RCC_SPI45CLKSOURCE_PCLK2
+Mcu.Pin62=DDR_WEN
+PG14.Locked=true
+Mcu.Pin63=DDR_CASN
+Mcu.Pin60=PH1-OSC_OUT
+Mcu.Pin61=DDR_CSN
+Mcu.Pin66=PA13
+Mcu.Pin67=DDR_CLKP
+Mcu.Pin64=DDR_CLKN
+Mcu.Pin65=PA14
+DDR.ADDRMAP5=0x06060606
+DDR.ADDRMAP6=0x0F060606
+DDR.t_ras_min=3
+DDR_A3.Signal=DDR_A3
+DDR_DQ11.Signal=DDR_DQ11
+DDR.ADDRMAP3=0x1F000000
+DDR_DQ6.Mode=DDR3
+PF8.GPIO_Label=NOR Flash
+DDR_DQS1N.Mode=DDR3
+DDR.ADDRMAP1=0x00070707
+PC3.GPIOParameters=GPIO_Label
+PD10.Signal=SPI3_MISO
+DDR_WEN.Mode=DDR3
+PB8.GPIO_Label=COUNTER_3
+PA15.Locked=true
+RCC.Tim1OutputFreq_Value=200000000
+PA8.GPIO_Label=TOUCH_WAKE
+Mcu.Pin59=DDR_ODT
+Mcu.Pin57=PH0-OSC_IN
+DDR.MR2.RTT=1
+Mcu.Pin58=DDR_BA2
+VP_OPENAMP_VS_OPENAMP.Signal=OPENAMP_VS_OPENAMP
+GIC.HASH1_IRQn=true\:false\:High level
+Mcu.Pin51=DDR_A2
+VP_CRYP1_VS_CRYP.Mode=CRYP_Activate
+RCC.USART6Freq_Value=100000000
+Mcu.Pin52=DDR_A3
+DDR.SPEED_BIN_GRADE=SPEED BIN GRADE CONFIG1
+Mcu.Pin50=PC15-OSC32_OUT
+RCC.PLLDSIVCOFreq_Value=960000000
+Mcu.Pin55=DDR_A0
+Mcu.Pin56=DDR_BA0
+DDR.MR2.CWL=0
+Mcu.Pin53=PC14-OSC32_IN
+Mcu.Pin54=PC13
+PE8.GPIO_Label=DISP_CS
+DDR_BA1.GPIOParameters=GPIO_Label
+PB11.GPIOParameters=GPIO_Label
+DDR.tfaw=8
+DDR_A14.GPIO_Label=DDR Memory
+Mcu.Pin48=DDR_A13
+Mcu.Pin49=DDR_A9
+Mcu.Pin46=DDR_DQ5
+Mcu.Pin47=PE13
+DDR_VREF.GPIOParameters=GPIO_Label
+PG6.GPIOParameters=GPIO_PuPd,GPIO_Label
+PB14.Signal=S_TIM12_CH1
+Mcu.Pin40=DDR_DQ2
+PA5.Signal=SPI1_SCK
+Mcu.Pin41=DDR_DQ6
+PE13.GPIOParameters=GPIO_PuPd,GPIO_Label
+JTDO-TRACESWO.GPIO_Label=JTAG Debug
+Mcu.Pin44=PE15
+PC12.Mode=SD_4_bits_Wide_bus
+Mcu.Pin45=DDR_DQ4
+Mcu.Pin42=PG12
+Mcu.Pin43=PE11
+PE1.GPIO_Label=PWR_DC
+SH.S_TIM15_CH1.ConfNb=1
+DDR_DQS1P.Signal=DDR_DQS1P
+DDR_ZQ.GPIO_Label=DDR Memory
+PD1.Mode=SD_4_bits_Wide_bus
+DDR_DQ5.Signal=DDR_DQ5
+PB13.GPIO_PuPd=GPIO_PULLUP
+FDCAN1.AutoRetransmission=DISABLE
+DDR_BA1.Mode=DDR3
+PE14.Signal=GPIO_Output
+PE6.Mode=mmc_4_bits_Wide_bus
+Mcu.Pin37=JTMS-SWDIO
+PB4.GPIO_Label=EMMC
+DDR_DQS1P.Mode=DDR3
+Mcu.Pin38=DDR_RESETN
+PB15.GPIO_Label=AUDIO
+Mcu.Pin35=PC7
+Mcu.Pin36=PC11
+RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_ACLK
+SPI1.Mode=SPI_MODE_MASTER
+Mcu.Pin39=DDR_DQM0
+PG7.GPIO_Label=IOMUX_DO
+SPI3.MasterKeepIOState=SPI_MASTER_KEEP_IO_STATE_ENABLE
+Mcu.Pin30=PD0
+PA1.GPIO_Label=SERVO_PWM2
+DDR_ATO.GPIO_Label=DDR Memory
+DDR_A14.Mode=4Gb_16bits
+PC9.GPIO_PuPd=GPIO_PULLUP
+Mcu.Pin33=PB15
+Mcu.Pin34=PB9
+PE3.GPIO_PuPd=GPIO_PULLUP
+Mcu.Pin31=PA9
+DDR_DQ7.GPIOParameters=GPIO_Label
+Mcu.Pin32=PB3
+DDR.tdllsrst=8
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+RCC.SAI4Freq_Value=50000000
+DDR_A11.GPIO_Label=DDR Memory
+SH.S_TIM2_CH3.ConfNb=1
+TIM3.Channel-Input_Capture4_from_TI4=TIM_CHANNEL_4
+PC10.GPIOParameters=GPIO_PuPd,GPIO_Label
+RCC.DACCLKFreq_VALUE=32000
+PH1-OSC_OUT.GPIO_Label=OSC System
+DDR_DQS0P.GPIO_Label=DDR Memory
+JTDO-TRACESWO.Mode=JTAG_5_pins
+TIM2.Period=SERVO_PERIOD
+PC9.GPIOParameters=GPIO_PuPd,GPIO_Label
+PF9.GPIOParameters=GPIO_Label,GPIO_Speed_Medium_Default
+Mcu.Pin26=PE12
+Mcu.Pin27=PE0
+Mcu.Pin24=DDR_DQS0N
+DDR_DQ11.GPIO_Label=DDR Memory
+Mcu.Pin25=DDR_DQS0P
+ADC1.ExternalTrigConv=ADC_EXTERNALTRIG_T6_TRGO
+DDR.trtp=4
+PC7.GPIO_Label=BACKLIGHT
+Mcu.Pin28=PD4
+DDR_DQ0.Signal=DDR_DQ0
+PC8.Mode=SD_4_bits_Wide_bus
+Mcu.Pin29=PD5
+PC8.GPIO_PuPd=GPIO_PULLUP
+PD14.GPIOParameters=GPIO_Label
+TIM12.Channel-Input_Capture1_from_TI1=TIM_CHANNEL_1
+Mcu.Pin22=DDR_DQ3
+DDR_A0.GPIOParameters=GPIO_Label
+Mcu.Pin23=DDR_DQ7
+Mcu.Pin20=NJTRST
+ADC1.master=1
+PA3.Locked=true
+Mcu.Pin21=JTDI
+DDR_A5.Mode=DDR3
+PD10.Locked=true
+PA10.Locked=true
+PA5.GPIO_Label=DISP_SCK
+NVIC.ForceEnableDMAVector=true
+JTMS-SWDIO.GPIOParameters=GPIO_Label
+DDR.addrmap_col_b10=31
+DDR.addrmap_col_b11=31
+PA14.GPIOParameters=GPIO_Label
+VP_MDMA_VS_MDMA_A7NS_8.Signal=MDMA_VS_MDMA_A7NS_8
+RCC.SAI3Freq_Value=50000000
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PE5.GPIO_Label=COUNTER_1
+PC12.GPIO_Label=SDCARD
+DDR_DQM1.GPIO_Label=DDR Memory
+PD15.Locked=true
+DDR_ATO.Mode=DDR3
+ProjectManager.HeapSize=0x200
+Mcu.Pin15=PB4
+PA0.GPIOParameters=GPIO_Label
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+Mcu.Pin16=PE5
+Mcu.Pin13=PA15
+PD0.GPIO_PuPd=GPIO_PULLUP
+Mcu.Pin14=PG6
+Mcu.Pin19=PC10
+PF10.GPIOParameters=GPIO_Label,GPIO_Speed_High_ByDefault
+RCC.STGENFreq_Value=24000000
+Mcu.Pin17=PA8
+RCC.RNG2Freq_Value=4000000
+Mcu.Pin18=PC9
+DDR_A7.GPIOParameters=GPIO_Label
+USART6.VirtualMode-Half_duplex(single_wire_mode)=VM_ASYNC
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+DDR.t_rc=6
+Mcu.Pin11=PE6
+Mcu.Pin12=PD7
+PD0.GPIOParameters=GPIO_PuPd,GPIO_Label
+Mcu.Pin10=PG15
+DDR_VREF.Signal=DDR_VREF
+PE3.Signal=SDMMC2_CK
+DDR_DQ15.GPIO_Label=DDR Memory
+RCC.PLL4PDSIFreq_Value=50000000
+DDR_DQ8.Mode=DDR3
+DDR_VREF.GPIO_Label=DDR Memory
+PD2.Signal=SDMMC1_CMD
+VP_DMA_VS_DMA1_A7NS.Signal=DMA_VS_DMA1_A7NS
+TIM12.IPParameters=Channel-Input_Capture1_from_TI1
+RCC.APB4DIV=RCC_APB4_DIV2
+Mcu.Family=STM32MP1
+ProjectManager.MainLocation=Src
+TIM6.IPParametersWithoutCheck=Prescaler,Period
+DDR.DFITMG0=0x02050105
+DDR_A1.Mode=DDR3
+DDR_CLKP.Mode=DDR3
+GIC.I2C2_ER_IRQn=true\:false\:High level
+PG9.GPIOParameters=GPIO_Label
+VP_TIM6_VS_OPM.Mode=OPM_bit
+Mcu.Pin150=PA4
+Mcu.Pin151=PB13
+ProjectManager.KeepUserCode=true
+ADC1.Overrun=ADC_OVR_DATA_OVERWRITTEN
+RCC.SPI1Freq_Value=120000000
+FDCAN1.ExtFiltersNbr=2
+Mcu.Pin156=VP_CRYP1_VS_CRYP
+Mcu.Pin157=VP_DDR_DDR3
+RCC.PLL4Source=RCC_PLL4SOURCE_HSE
+Mcu.Pin158=VP_DDR_DDR_16_bits
+Mcu.Pin159=VP_DDR_DDR3_16_4Gb
+PE11.GPIO_Label=AUDIO_GPIN
+Mcu.Pin152=PE9
+Mcu.Pin153=PF10
+Mcu.Pin154=VP_BSEC_VS_BSEC
+Mcu.Pin155=VP_CRC1_VS_CRC
+PC5.Locked=true
+DDR_A1.GPIOParameters=GPIO_Label
+PB6.GPIO_Speed_Medium_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PA0.GPIO_Label=SERVO_OC
+PA12.GPIOParameters=GPIO_Label
+PA9.GPIOParameters=GPIO_Label
+RCC.PLL2FRACV=0
+PA11.GPIOParameters=GPIO_Label
+PD0.GPIO_Label=WIFI
+DDR_ODT.GPIOParameters=GPIO_Label
+PA11.Mode=FDCANFD
+PH0-OSC_IN.GPIOParameters=GPIO_Label
+PD6.Locked=true
+RCC.VCO2OutputFreq_Value=1056000000
+Mcu.Pin160=VP_DTS_VS_DTS
+Mcu.Pin161=VP_ETZPC_VS_ETZPC
+Mcu.Pin162=VP_FREERTOS_VS_CMSIS_V2
+TIM2.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
+PB13.GPIO_Label=BUTTON_IN
+DDR_DQ1.Mode=DDR3
+PB15.Signal=I2S2_SDO
+Mcu.Pin167=VP_OPENAMP_VS_OPENAMP
+Mcu.Pin168=VP_RNG1_VS_RNG
+Mcu.Pin169=VP_RTC_VS_RTC_Activate
+Mcu.Pin163=VP_GPU_VS_GPU
+PG15.Signal=SDMMC3_CK
+PG11.Signal=UART4_TX
+Mcu.Pin164=VP_HASH1_VS_HASH
+RCC.APB2DIV=RCC_APB2_DIV2
+DDR_ZQ.Mode=DDR3
+Mcu.Pin165=VP_HSEM_VS_HSEM
+PB5.GPIOParameters=GPIO_Label
+DDR_DQ11.Mode=DDR3
+Mcu.Pin166=VP_IPCC_VS_IPCC
+DDR_A4.Signal=DDR_A4
+DDR_DQ12.Signal=DDR_DQ12
+Mcu.Pin138=PD6
+Mcu.Pin139=PE14
+USB_DM1.GPIOParameters=GPIO_Label
+PD13.Signal=I2C4_SDA
+Mcu.IP4=DDR
+Mcu.IP5=DEBUG
+DDR_A2.GPIO_Label=DDR Memory
+VP_MDMA_VS_MDMA_A7NS_8.Mode=8\:8
+Mcu.IP2=CRC1
+RCC.SDMMC3Freq_Value=200000000
+Mcu.IP3=CRYP1
+PA15.GPIO_Label=MOTOR_NSS
+PC11.GPIO_PuPd=GPIO_PULLUP
+Mcu.IP0=ADC1
+Mcu.IP1=BSEC
+PE4.GPIOParameters=GPIO_Label
+DDR_A2.GPIOParameters=GPIO_Label
+RCC.DIVP3Freq_Value=200000000
+DDR_WEN.GPIOParameters=GPIO_Label
+Mcu.Pin134=PB14
+DDR.addrmap_row_b1=6
+NJTRST.GPIO_Label=JTAG Debug
+Mcu.Pin135=PD2
+DDR_DTO0.GPIO_Label=DDR Memory
+Mcu.Pin136=DDR_ZQ
+Mcu.Pin137=DDR_A7
+Mcu.Pin130=DDR_DQ11
+Mcu.Pin131=PE1
+DDR.t_cksrx=5
+Mcu.Pin132=PD10
+DDR_RESETN.GPIOParameters=GPIO_Label
+Mcu.Pin133=PE3
+ADC1.Resolution=ADC_RESOLUTION_12B
+DDR.addrmap_row_b0=6
+ProjectManager.PreviousToolchain=SW4STM32
+DDR.t_cksre=5
+GIC.SPI2_IRQn=true\:false\:High level
+PG15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_MEDIUM
+DDR.write_latency=5
+PG8.GPIOParameters=GPIO_Label
+Mcu.Pin149=PA5
+RCC.AHB1234Freq_Value=200000000
+PA8.GPIOParameters=GPIO_Label
+FDCAN1.RxFifo1ElmtSize=FDCAN_DATA_BYTES_64
+TIM7.Period=MuxerDelay
+FDCAN1.FrameFormat=FDCAN_FRAME_FD_BRS
+FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,FootprintOK,configTIMER_TASK_STACK_DEPTH,configMINIMAL_STACK_SIZE,configGENERATE_RUN_TIME_STATS,configUSE_IDLE_HOOK
+JTDO-TRACESWO.Signal=DEBUG_JTDO-SWO
+DDR.trrd=4
+NJTRST.GPIOParameters=GPIO_Label
+PD5.Mode=SD_4_bits_Wide_bus
+Mcu.Pin140=PC12
+TIM8.IPParameters=Channel-PWM Generation2 CH2
+DDR_DQ4.GPIO_Label=DDR Memory
+Mcu.Pin145=PD14
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_4
+Mcu.Pin146=DDR_RASN
+RCC.DIVR3Freq_Value=50000000
+RCC.HSE_VALUE=24000000
+Mcu.Pin147=DDR_ATO
+Mcu.Pin148=DDR_A6
+Mcu.Pin141=PD15
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+DDR_A13.GPIO_Label=DDR Memory
+Mcu.Pin142=DDR_DTO1
+PA4.GPIO_PuPd=GPIO_PULLUP
+Mcu.Pin143=DDR_A5
+Mcu.Pin144=DDR_DTO0
+JTCK-SWCLK.GPIO_Label=JTAG Debug
+Mcu.IP10=GIC
+Mcu.IP12=HASH1
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:false\:true
+PE13.GPIO_PuPd=GPIO_PULLUP
+Mcu.IP11=GPU
+DDR_DQ7.Signal=DDR_DQ7
+DDR_DQ4.Signal=DDR_DQ4
+Mcu.IP18=IPCC
+Mcu.IP17=I2S2
+Mcu.IP19=NVIC
+RCC.USART35CLockSelection=RCC_UART35CLKSOURCE_PCLK1
+PB3.GPIO_PuPd=GPIO_PULLUP
+Mcu.IP14=I2C1
+RCC.DIVP1Freq_Value=648000000
+PF9.Mode=Single Bank 1
+FDCAN1.StdFiltersNbr=3
+Mcu.IP13=HSEM
+DDR_A12.Signal=DDR_A12
+Mcu.IP16=I2C4
+Mcu.IP15=I2C2
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+DDR_CSN.Mode=DDR3
+PE8.Locked=true
+PC11.GPIO_Label=SDCARD
+PB5.Mode=TX_Only_Simplex_Unidirect_Master
+PE3.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label
+VP_BSEC_VS_BSEC.Signal=BSEC_VS_BSEC
+DDR_DQ10.GPIOParameters=GPIO_Label
+PB7.Signal=SDMMC2_D1
+PE3.Locked=true
+VP_HASH1_VS_HASH.Signal=HASH1_VS_HASH
+Mcu.IP21=QUADSPI
+Mcu.IP20=OPENAMP
+Mcu.IP23=RNG1
+DDR_DQ1.GPIO_Label=DDR Memory
+DDR_A8.Mode=DDR3
+Mcu.IP22=RCC
+TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+RCC.USBPHYCLKSource=RCC_USBPHYCLKSOURCE_HSE
+Mcu.IP29=SPI3
+Mcu.IP28=SPI1
+Mcu.IP25=SDMMC1
+Mcu.IP24=RTC
+TIM7.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
+PB6.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Speed_Medium_Default
+Mcu.IP27=SDMMC3
+Mcu.IP26=SDMMC2
+PB0.Locked=true
+VP_CRC1_VS_CRC.Mode=CRC_Activate
+PA13.GPIOParameters=GPIO_Label
+DDR.wr2pre=12
+PB7.GPIO_Label=EMMC
+PH1-OSC_OUT.Mode=HSE-External-Oscillator
+DDR.read_latency=6
+PD13.GPIO_Label=I2C4_BUS_EXT
+PA6.Signal=GPIO_Output
+PB12.Mode=Full_Duplex_Master
+Mcu.IP32=TIM2
+Mcu.IP31=TAMP
+DDR_A5.GPIO_Label=DDR Memory
+Mcu.IP34=TIM4
+PG11.Locked=true
+Mcu.IP33=TIM3
+DDR.t_rfc_nom_x1_x32=3
+Mcu.IP30=SYS
+GIC.SPI1_IRQn=true\:false\:High level
+PD5.GPIO_Label=WIFI
+VP_VREFBUF_VS_VREFBUF.Mode=VREFBUF_Activate
+Mcu.IP39=TIM12
+FDCAN1.RxFifo0ElmtsNbr=16
+ProjectManager.ToolChainLocation=
+DDR_A12.Mode=4Gb_16bits
+VP_RNG1_VS_RNG.Signal=RNG1_VS_RNG
+Mcu.IP36=TIM6
+RCC.DSIFreq_Value=60000000
+Mcu.IP35=TIM5
+Mcu.IP38=TIM8
+PA15.Signal=SPI3_NSS
+Mcu.IP37=TIM7
+PF8.Signal=QUADSPI_BK1_IO0
+Mcu.Pin170=VP_SYS_VS_Systick
+Mcu.Pin171=VP_TAMP_VS_TAMP_Activate
+RCC.DIVR1Freq_Value=324000000
+Mcu.Pin172=VP_TIM5_VS_ClockSourceINT
+Mcu.Pin173=VP_TIM6_VS_ClockSourceINT
+NVIC.SPI3_IRQn=true\:5\:0\:true\:false\:false\:true\:true\:false
+JTDI.Signal=DEBUG_JTDI
+Mcu.Pin95=PG10
+Mcu.Pin178=VP_DMA_VS_DMA1_A7NS
+Mcu.Pin96=PF6
+Mcu.Pin179=VP_DMA_VS_DMA2_M4
+Mcu.Pin93=PB10
+Mcu.Pin94=PG11
+Mcu.Pin99=PD12
+Mcu.Pin174=VP_TIM6_VS_OPM
+PB5.GPIO_Label=DISP_MOSI
+Mcu.Pin175=VP_TIM7_VS_ClockSourceINT
+Mcu.Pin97=PE8
+Mcu.Pin176=VP_TIM7_VS_OPM
+Mcu.Pin98=PD13
+Mcu.Pin177=VP_VREFBUF_VS_VREFBUF
+Mcu.IP43=USBH_HS1
+Mcu.IP42=USART6
+Mcu.IP44=VREFBUF
+Mcu.Pin91=PB11
+Mcu.Pin92=PC0
+PG11.GPIO_Label=Console UART
+Mcu.IP41=UART4
+PD3.GPIO_Label=AUDIO
+Mcu.Pin90=PB0
+PC5.Signal=GPIO_Input
+Mcu.IP40=TIM15
+PE7.Signal=GPIO_Input
+DDR_CKE.Signal=DDR_CKE
+PD6.Signal=SPI3_MOSI
+DDR_BA0.Signal=DDR_BA0
+PE2.GPIO_Label=I2C4_BUS_EXT
+PE12.Locked=true
+Mcu.Pin180=VP_MDMA_VS_MDMA_A7NS_8
+RCC.PLL1UserDefinedConfig=true
+Mcu.Pin84=PA1
+DDR_A7.GPIO_Label=DDR Memory
+Mcu.Pin85=PA2
+PB4.Signal=SDMMC2_D3
+Mcu.Pin82=DDR_A4
+Mcu.Pin83=DDR_DQ8
+PA3.Signal=GPIO_Output
+Mcu.Pin88=DDR_DQ10
+NVIC.FDCAN1_IT0_IRQn=true\:5\:0\:false\:false\:false\:true\:true\:false
+Mcu.Pin89=PB1
+Mcu.Pin86=DDR_A8
+Mcu.Pin87=DDR_DQ13
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
+DDR.tdinit1=7
+DDR.tdinit0=12500
+DDR_DQS1N.GPIO_Label=DDR Memory
+DDR.tdinit2=5000
+DDR.tcke=4
+RCC.I2C35Freq_Value=100000000
+SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1
+PB8.GPIOParameters=GPIO_Label
+PG7.Locked=true
+PD15.GPIO_Label=RESET_OUT
+PG7.Signal=GPIO_Output
+DDR_DQ11.GPIOParameters=GPIO_Label
+PE14.GPIOParameters=GPIO_Label
+RCC.MPUCLKSource=RCC_MPUSOURCE_PLL1
+PC9.GPIO_Label=SDCARD
+DDR_CLKP.Signal=DDR_CLKP
+DDR_CLKP.GPIO_Label=DDR Memory
+PC11.Signal=SDMMC1_D3
+RCC.PUBLFreq_Value=528000000
+RCC.USBOHSFreq_Value=48000000
+PC8.Signal=SDMMC1_D0
+DDR_DTO0.Signal=DDR_DTO0
+TIM6.Prescaler=PrescalerI18
+PC10.Mode=SD_4_bits_Wide_bus
+VP_IPCC_VS_IPCC.Signal=IPCC_VS_IPCC
+VP_TIM6_VS_ClockSourceINT.Mode=Enable_Timer
+ProjectManager.DefaultFWLocation=true
+PC2.Mode=Full_Duplex_Master
+PE14.GPIO_Label=MOTOR_NSLEEP
+VP_CRC1_VS_CRC.Signal=CRC1_VS_CRC
+PB12.Locked=true
+VP_DDR_DDR3.Mode=DDR3
+ProjectManager.DeletePrevious=true
+DDR_DQ14.Mode=DDR3
+PB10.Locked=true
+DDR.MR0.WR=1
+DDR_DQ4.Mode=DDR3
+DDR_DQ5.GPIOParameters=GPIO_Label
+PA12.GPIO_Label=CAN
+PinOutPanel.CurrentBGAView=Top
+RCC.FamilyName=M
+VP_TIM6_VS_OPM.Signal=TIM6_VS_OPM
+DDR_DQ10.GPIO_Label=DDR Memory
+DDR_DQ0.Mode=DDR3
+PB9.GPIOParameters=GPIO_Label
+PE15.GPIOParameters=GPIO_PuPd,GPIO_Label
+PG8.GPIO_Label=SERVO_PWM1
+PA13.Signal=GPIO_Output
+FREERTOS.configUSE_IDLE_HOOK=1
+PD4.GPIO_PuPd=GPIO_PULLUP
+TIM6.IPParameters=Prescaler,AutoReloadPreload,Period,TIM_MasterOutputTrigger
+PF6.Signal=QUADSPI_BK1_IO3
+PB10.GPIO_Label=I2C2_BUS_INTERN
+RCC.VCO1OutputFreq_Value=1296000000
+RCC.SPI6CLockSelection=RCC_SPI6CLKSOURCE_PCLK5
+PB7.GPIOParameters=GPIO_PuPd,GPIO_Label
+SH.S_TIM4_CH3.0=TIM4_CH3,Input_Capture3_from_TI3
+PB9.Mode=I2C
+DDR_DQM0.Signal=DDR_DQM0
+PC5.GPIOParameters=GPIO_Label
+JTCK-SWCLK.Signal=DEBUG_JTCK-SWCLK
+RCC.LPTIM1CLockSelection=RCC_LPTIM1CLKSOURCE_PCLK1
+PE2.GPIOParameters=GPIO_Label
+PG10.GPIOParameters=GPIO_Label
+PE0.Locked=true
+PF9.GPIO_Label=NOR Flash
+PD10.GPIO_Label=MOTOR_MISO
+CortexA7S.IPs=BSEC\:I,ETZPC\:I,PWR\:I,RCC,RNG1\:I,RTC\:I,GIC\:I,DDR,HSEM,IWDG2\:I,TAMP,MDMA_A7S\:I
+TIM15.IPParameters=Channel-Input_Capture1_from_TI1
+DDR_BA2.Signal=DDR_BA2
+PA1.Signal=S_TIM2_CH2
+PG15.Mode=SD_4_bits_Wide_bus
+SH.S_TIM4_CH3.ConfNb=1
+PD2.Mode=SD_4_bits_Wide_bus
+DDR_A4.GPIOParameters=GPIO_Label
+TIM7.Prescaler=PrescalerI18
+board=custom
+SPI3.CLKPhase=SPI_PHASE_2EDGE
+DDR_ODT.GPIO_Label=DDR Memory
+DDR_A3.GPIOParameters=GPIO_Label
+PB15.Mode=Full_Duplex_Master
+DDR_DQ2.Signal=DDR_DQ2
+DDR_CSN.GPIOParameters=GPIO_Label
+DDR_DQ13.GPIOParameters=GPIO_Label
+MxCube.Version=5.6.1
+SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3
+RCC.FDCANFreq_Value=24000000
+DDR_BA2.Mode=DDR3
+RCC.PLL12Source=RCC_PLL12SOURCE_HSE
+VP_GPU_VS_GPU.Mode=GPU_Activate
+RCC.ADCFreq_Value=24000000
+PD4.GPIOParameters=GPIO_PuPd,GPIO_Label
+VP_SYS_VS_Systick.Mode=SysTick
+TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
+RCC.DIVR4Freq_Value=50000000
+TIM6.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
+RCC.MCUCLKFreq_VALUE=200000000
+PD5.GPIO_PuPd=GPIO_PULLUP
+RCC.CSI_VALUE=4000000
+PE5.Locked=true
+RCC.LPTIM45Freq_Value=100000000
+ADC1.NbrOfConversion=1
+RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHB1234Freq_Value,APB1DIV,APB1Freq_Value,APB2DIV,APB2Freq_Value,APB3DIV,APB3Freq_Value,APB4DIV,APB4Freq_Value,APB5DIV,APB5DIVClockFreq_Value,AXICLKFreq_VALUE,AXICLKSource,AXIDIVFreq_Value,CECFreq_Value,CKPERCLKFreq_VALUE,CKPERCLKSource,CSI_VALUE,CortexFreq_Value,DACCLKFreq_VALUE,DDRCFreq_Value,DDRPERFMFreq_Value,DDRPHYFreq_Value,DFSDFAFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVM4,DIVN1,DIVN2,DIVN3,DIVN4,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3,DIVP3Freq_Value,DIVP4,DIVP4Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVQ4,DIVQ4Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,DIVR4,DIVR4Freq_Value,DSIFreq_Value,DSIPixelFreq_Value,DSITXEscFreq_Value,DSI_VALUE,ETHFreq_Value,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HSE_VALUE,HSIDivClkFreq_Value,HSI_VALUE,Hclk5DIVFreq_Value,Hclk6DIVFreq_Value,I2C12CLockSelection,I2C12Freq_Value,I2C35CLockSelection,I2C35Freq_Value,I2C46CLockSelection,I2C46Freq_Value,LPTIM1CLockSelection,LPTIM1Freq_Value,LPTIM23CLockSelection,LPTIM23Freq_Value,LPTIM45CLockSelection,LPTIM45Freq_Value,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,MCUCLKFreq_VALUE,MCUCLKSource,MCUClockFreq_Value,MCUDIVCLKFreq_Value,MPUCLKFreq_VALUE,MPUCLKSource,PLL12Source,PLL1UserDefinedConfig,PLL2FRACV,PLL3FRACV,PLL3Source,PLL4FRACV,PLL4PDSIFreq_Value,PLL4Source,PLLDSIFreq_Value,PLLDSIVCOFreq_Value,PUBLFreq_Value,QSPICLockSelection,QSPIFreq_Value,RNG1Freq_Value,RNG2Freq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SAI3Freq_Value,SAI4Freq_Value,SDMMC12CLockSelection,SDMMC12Freq_Value,SDMMC3Freq_Value,SPDIFRXFreq_Value,SPI1CLockSelection,SPI1Freq_Value,SPI23Freq_Value,SPI45CLockSelection,SPI45Freq_Value,SPI6CLockSelection,SPI6Freq_Value,STGENCLockSelection,STGENFreq_Value,Tim1OutputFreq_Value,Tim2OutputFreq_Value,UART78CLockSelection,UART78Freq_Value,USART1CLockSelection,USART1Freq_Value,USART24CLockSelection,USART24Freq_Value,USART35CLockSelection,USART35Freq_Value,USART6Freq_Value,USBOCLKSource,USBOHSFreq_Value,USBPHYCLKSource,USBPHYFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCO4OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInput4Freq_Value
+ProjectManager.AskForMigrate=true
+PE0.Signal=SPI3_SCK
+DDR_A14.Signal=DDR_A14
+PE7.GPIO_Label=DISP_MESH
+PE12.Signal=GPIO_Output
+DDR_DQ4.GPIOParameters=GPIO_Label
+DDR_DQ7.GPIO_Label=DDR Memory
+PB2.Locked=true
+Mcu.IP8=FDCAN1
+Mcu.IP9=FREERTOS
+Mcu.IP6=DTS
+Mcu.IP7=ETZPC
+ProjectManager.CoupleFile=false
+GIC.I2C2_EV_IRQn=true\:false\:High level
+DDR_DQ7.Mode=DDR3
+I2S2.ErrorAudioFreq=1.72 %
+KeepUserPlacement=false
+TIM5.Prescaler=2000
+PH1-OSC_OUT.GPIOParameters=GPIO_Label
+PA13.Locked=true
+PB2.Mode=Asynchronous
+RCC.QSPICLockSelection=RCC_QSPICLKSOURCE_ACLK
+DDR_A4.Mode=DDR3
+PE15.GPIO_PuPd=GPIO_PULLUP
+PB2.GPIO_Label=Console UART
+RCC.Hclk6DIVFreq_Value=264000000
+PC6.GPIOParameters=GPIO_Label
+RCC.I2C35CLockSelection=RCC_I2C35CLKSOURCE_PCLK1
+RCC.HSI_VALUE=64000000
+SH.S_TIM3_CH4.ConfNb=1
+DDR_DQ13.GPIO_Label=DDR Memory
+DDR_DQ12.GPIOParameters=GPIO_Label
+TIM5.Period=0xffffffff
+DDR.CL=7
+VP_DDR_DDR3_16_4Gb.Mode=4Gb_16bits
+DDR_A11.GPIOParameters=GPIO_Label
+DDR.IPParameters=DDR_Frequency,CL,addrmap_col_b9,addrmap_col_b10,addrmap_col_b11,addrmap_bank_b0,addrmap_bank_b1,addrmap_bank_b2,addrmap_row_b0,addrmap_row_b1,addrmap_row_b2_10,addrmap_row_b11,addrmap_row_b12,addrmap_row_b13,addrmap_row_b14,addrmap_row_b15,MSTR,RFSHTMG,DRAMTMG0,DRAMTMG1,DRAMTMG2,DRAMTMG4,SCHED,ADDRMAP1,ADDRMAP3,ADDRMAP5,ADDRMAP6,PTR0,PTR1,PTR2,DTPR0,DTPR1,MR0,MR2,SPEED_BIN_GRADE,tRCD,tRP,tRC,wr2pre,t_faw,t_ras_max,t_ras_min,t_xp,t_rd2pre,t_rp,t_rc,write_latency,read_latency,wr2rd,t_rcd,t_rrd,t_cksrx,t_cksre,t_ckesr,t_cke,t_xs_dll_x32,t_xs_x32,t_rfc_nom_x1_x32,t_rfc_min,dfi_t_rddata_en,dfi_tphy_wrlat,tdlllock,tdllsrst,tdinit1,tdinit0,tdinit2,tccd,trc,trrd,tras,trcd,trp,twtr,trtp,tmrd,trfc,tmod,tfaw,tdllk,tcke,txp,txs,MR0.WR,MR0.CL,MR2.RTT,MR2.CWL,data_bus_width,TEMPERATURE_OVER_85C,tREFI,DFITMG0
+I2S2.RealAudioFreq=16.276 KHz
+DDR.trfc=7
+FDCAN1.TxFifoQueueElmtsNbr=0
+SH.S_TIM8_CH2.ConfNb=1
+PB12.Signal=I2S2_WS
+DDR_DQ14.Signal=DDR_DQ14
+DDR_RASN.GPIOParameters=GPIO_Label
+PG11.GPIOParameters=GPIO_PuPd,GPIO_Label
+PE1.GPIOParameters=GPIO_PuPd,GPIO_Label
+GIC.SDMMC3_IRQn=true\:false\:High level
+PA3.GPIO_Label=PWR_BUCK_EN
+CortexM4.IPs=IPCC,HSEM,ETZPC,FREERTOS\:I,PWR,RCC,SYS\:I,DMA,NVIC\:I,TIM2\:I,TIM3\:I,DEBUG\:I,FDCAN1\:I,SPI3\:I,ADC1\:I,ADC2\:I,OPENAMP\:I,USART6\:I,TIM6\:I,TIM7\:I,TIM15\:I,TIM12\:I,TIM4\:I,TIM5\:I,DMA2\:I
+PA6.Locked=true
+DDR_A8.GPIOParameters=GPIO_Label
+PE3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_MEDIUM
+RCC.USART1Freq_Value=66000000
+PH0-OSC_IN.Signal=RCC_OSC_IN
+SPI3.Direction=SPI_DIRECTION_2LINES
+DDR_DQ3.Mode=DDR3
+DDR.tccd=0
+SPI3.VirtualType=VM_MASTER
+DDR_A12.GPIO_Label=DDR Memory
+DDR_DQ2.GPIOParameters=GPIO_Label
+SPI1.VirtualType=VM_MASTER
+PB10.Mode=I2C
+DDR_A1.GPIO_Label=DDR Memory
+VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT
+GIC.QUADSPI_IRQn=true\:false\:High level
+PC12.Signal=SDMMC1_CK
+PB14.GPIO_Label=COUNTER_4
+PG6.GPIO_Label=EMMC
+PA14.GPIO_Label=LED_GREEN
+DDR.RFSHTMG=0x0040008A
+PD3.GPIOParameters=GPIO_Label
+RCC.VCOInput4Freq_Value=4000000
+DDR.t_rcd=3
+PC6.GPIO_Label=AUDIO
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+PC3.Locked=true
+DDR_ODT.Signal=DDR_ODT
+PA3.GPIOParameters=GPIO_Label
+DDR.PTR0=0x0022A41B
+PA6.GPIO_Label=DISP_A0
+PB6.GPIO_Label=NOR Flash
+DDR.PTR1=0x047C0740
+DDR_RESETN.Mode=DDR3
+RCC.USBOCLKSource=RCC_USBOCLKSOURCE_PHY
+DDR_DTO1.GPIOParameters=GPIO_Label
+DDR.DDR_Frequency=528.0
+PB13.Signal=GPIO_Input
+PG6.Mode=mmc_4_bits_Wide_bus
+PG13.Signal=GPIO_Output
+PD6.GPIO_Label=MOTOR_MOSI
+PC15-OSC32_OUT.GPIO_Label=OSC RTC
+PinOutPanel.RotationAngle=0
+PE6.GPIO_Label=EMMC
+PF6.GPIO_Label=NOR Flash
+RCC.MCO1PinFreq_Value=64000000
+DDR.trc=6
+NVIC.ADC1_IRQn=true\:5\:0\:true\:false\:false\:true\:true\:false
+DDR.PTR2=0x042D9C80
+PD15.GPIOParameters=GPIO_Label
+DDR_A3.Mode=DDR3
+DDR.trcd=3
+TIM2.Pulse-PWM\ Generation3\ CH3=SERVO_MID_PULSE
+RCC.LPTIM45CLockSelection=RCC_LPTIM45CLKSOURCE_PCLK3
+DDR.trp=3
+JTDI.GPIO_Label=JTAG Debug
+DDR_A11.Mode=DDR3
+PE2.Mode=I2C
+TIM2.IPParameters=Period,AutoReloadPreload,Prescaler,Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Pulse-PWM Generation1 CH1,Pulse-PWM Generation2 CH2,Pulse-PWM Generation3 CH3
+PD4.Signal=SDMMC3_D1
+PB6.Mode=Single Bank 1
+RCC.DIVQ3Freq_Value=120000000
+PC3.Signal=GPIO_Input
+RCC.SAI2Freq_Value=50000000
+DDR_DQ5.GPIO_Label=DDR Memory
+GIC.GPU_IRQn=true\:false\:High level
+PE5.Signal=S_TIM15_CH1
+PE10.Locked=true
+DDR_CASN.Signal=DDR_CASN
+DDR_DQ15.GPIOParameters=GPIO_Label
+DDR.tras=3
+SH.ADCx_INP4.0=ADC1_INP4,IN4-Single-Ended
+PF10.GPIO_Label=NOR/NAND Flash
+PB13.Locked=true
+DDR.t_rd2pre=4
+GIC.I2C4_ER_IRQn=true\:false\:High level
+PG13.Locked=true
+DDR_ODT.Mode=DDR3
+PB2.Signal=UART4_RX
+PA4.Locked=true
+RCC.DIVM3=2
+RCC.DIVM2=3
+PD1.GPIOParameters=GPIO_PuPd,GPIO_Label
+RCC.DIVM1=3
+DDR_DQ6.Signal=DDR_DQ6
+DDR_DQ1.Signal=DDR_DQ1
+RCC.DIVM4=6
+RCC.I2C12CLockSelection=RCC_I2C12CLKSOURCE_HSI
+MxDb.Version=DB.5.0.60
+PE15.Locked=true
+PB0.GPIOParameters=GPIO_Label
+PE0.GPIOParameters=GPIO_Label
+PG6.GPIO_PuPd=GPIO_PULLUP
+PA1.GPIOParameters=GPIO_Label
+FDCAN1.RxBufferSize=FDCAN_DATA_BYTES_64
+BootLoader.IPs=RCC,DDR,USB_OTG_HS,SDMMC1,QUADSPI,UART4
+DDR_BA2.GPIOParameters=GPIO_Label
+PE2.Signal=I2C4_SCL
+PF8.Mode=Single Bank 1
+DDR.tmrd=0
+NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
+PD3.Mode=Full_Duplex_Master
+RCC.DIVR2Freq_Value=528000000
+PE10.Signal=GPIO_Output
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_32CYCLES_5
+FDCAN1.TxBuffersNbr=20
+RCC.MCO2PinFreq_Value=648000000
+PC8.GPIOParameters=GPIO_PuPd,GPIO_Label
+PF8.GPIOParameters=GPIO_Label,GPIO_Speed_Medium_Default
+DDR_RASN.Signal=DDR_RASN
+DDR_DQ10.Signal=DDR_DQ10
+PG13.GPIOParameters=GPIO_Label
+DDR_CLKN.Mode=DDR3
+PE10.GPIOParameters=GPIO_PuPd,GPIO_Label
+PD5.GPIOParameters=GPIO_PuPd,GPIO_Label
+PA14.Locked=true
+DDR_A13.GPIOParameters=GPIO_Label
+VP_DTS_VS_DTS.Signal=DTS_VS_DTS
+DDR_BA2.GPIO_Label=DDR Memory
+DDR.MSTR=0x00041401
+RCC.DFSDMFreq_Value=200000000
+PA5.GPIOParameters=GPIO_Label
+PB14.GPIOParameters=GPIO_Label
+TIM2.Pulse-PWM\ Generation2\ CH2=SERVO_MID_PULSE
+VP_HSEM_VS_HSEM.Mode=HSEM_Activate
+PD4.Mode=SD_4_bits_Wide_bus
+RCC.APB4Freq_Value=132000000
+RCC.CECFreq_Value=32768
+DDR.DTPR0=0x36D477D0
+DDR.DTPR1=0x098A00D8
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+DDR_DQM1.Mode=DDR3
+TIM2.IPParametersWithoutCheck=Pulse-PWM Generation1 CH1,Pulse-PWM Generation2 CH2,Pulse-PWM Generation3 CH3,Prescaler,Period
+PB10.GPIOParameters=GPIO_Label
+PC12.GPIO_PuPd=GPIO_PULLUP
+PC15-OSC32_OUT.GPIOParameters=GPIO_Label
+DDR.t_rfc_min=7
+PE10.GPIO_Label=CAN_TERM
+ProjectManager.CustomerFirmwarePackage=
+PC4.GPIOParameters=GPIO_Label
+DDR_ZQ.Signal=DDR_ZQ
+DDR_DQ9.Signal=DDR_DQ9
+BootROM.IPs=RCC,SDMMC1,UART4
+PB7.GPIO_PuPd=GPIO_PULLUP
+RCC.DIVQ4=10
+DDR.tmod=0
+RCC.DIVQ3=5
+CortexA7NS.IPs=IWDG2,BSEC,DDR\:I,ETZPC,HSEM\:I,IPCC\:I,PWR,RCC\:I,RTC,TAMP\:I,DMA\:I,GIC,SDMMC1\:I,SDMMC2\:I,VREFBUF\:I,I2S2\:I,SPI2\:I,SPI1\:I,I2S1\:I,I2C1\:I,I2C2\:I,UART4\:I,I2C4\:I,SDMMC3\:I,DTS\:I,USBH_HS1\:I,USB_OTG_HS\:I,QUADSPI\:I,TIM8\:I,RNG1,CRC1\:I,HASH1\:I,CRYP1\:I,GPU\:I,DMA1\:I,MDMA_A7NS\:I
+DDR_A4.GPIO_Label=DDR Memory
+ADC1.Rank-0\#ChannelRegularConversion=1
+TIM5.IPParameters=Prescaler,AutoReloadPreload,Period
+DDR_DQ2.GPIO_Label=DDR Memory
+PA15.GPIOParameters=GPIO_Label
+RCC.CKPERCLKSource=RCC_CKPERCLKSOURCE_HSE
+RCC.USART35Freq_Value=100000000
+PD2.GPIO_PuPd=GPIO_PULLUP
+RCC.UART78Freq_Value=100000000
+VP_DMA_VS_DMA2_M4.Mode=CortexM4
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,Resolution,NbrOfConversion,ClockPrescaler,ExternalTrigConv,DiscontinuousConvMode,Overrun,master
+DDR_CSN.Signal=DDR_CSN
+PG9.Locked=true
+PG9.Signal=GPIO_Output
+PA9.GPIO_Label=ENC2_A
+DDR_CLKN.Signal=DDR_CLKN
+RCC.DIVP4=10
+RCC.DIVP3=3
+PC6.Signal=I2S2_MCK
+JTCK-SWCLK.GPIOParameters=GPIO_Label
+PB11.GPIO_Label=I2C2_BUS_INTERN
+PD7.Signal=SDMMC3_D3
+DDR_DQ6.GPIOParameters=GPIO_Label
+PD13.GPIOParameters=GPIO_Label
+PD1.Signal=SDMMC3_D0
+PA11.GPIO_Label=CAN
+PE1.GPIO_PuPd=GPIO_PULLUP
+DDR_RESETN.GPIO_Label=DDR Memory
+FDCAN1.RxFifo0ElmtSize=FDCAN_DATA_BYTES_64
+VP_DTS_VS_DTS.Mode=DTS_Activate
+PD1.GPIO_PuPd=GPIO_PULLUP
+PC0.Signal=GPIO_Output
+DDR_DQM0.Mode=DDR3
+PC11.GPIOParameters=GPIO_PuPd,GPIO_Label
+RCC.QSPIFreq_Value=264000000
+PG13.GPIO_Label=AIO_PRESCALE
+SH.S_TIM8_CH2.0=TIM8_CH2,PWM Generation2 CH2
+PG10.Signal=GPIO_Output
+GIC.SDMMC2_IRQn=true\:false\:High level
+PG10.Locked=true
+VP_TIM6_VS_ClockSourceINT.Signal=TIM6_VS_ClockSourceINT
+DDR_DQS0N.Signal=DDR_DQS0N
+DDR_A7.Signal=DDR_A7
+DDR_DQ10.Mode=DDR3
+PB11.Mode=I2C
+TIM4.IPParameters=Channel-Input_Capture3_from_TI3
+PC6.Mode=Master_Clock_Activated
+DDR.t_cke=3
+RCC.APB5DIV=RCC_APB5_DIV4
+PC6.Locked=true
+RCC.DIVN4=125
+PA9.Signal=GPIO_Input
+I2S2.VirtualMode=I2S_MODE_MASTER
+RCC.DIVN3=50
+SH.S_TIM2_CH2.ConfNb=1
+RCC.DIVN2=66
+RCC.DIVN1=81
+DDR_A6.GPIOParameters=GPIO_Label
+PB4.GPIO_PuPd=GPIO_PULLUP
+RCC.SDMMC12Freq_Value=50000000
+PE9.GPIO_Label=TOUCH_INT
+PB10.Signal=I2C2_SCL
+RCC.RNG1Freq_Value=4000000
+ProjectManager.LastFirmware=true
+SH.S_TIM15_CH1.0=TIM15_CH1,Input_Capture1_from_TI1
+Mcu.Pin116=PB2
+Mcu.Pin117=USB_DP1
+Mcu.Pin118=PA12
+Mcu.Pin119=DDR_DQ15
+SH.S_TIM12_CH1.ConfNb=1
+DDR_A11.Signal=DDR_A11
+PE15.Signal=GPIO_Input
+DDR_DQS1P.GPIOParameters=GPIO_Label
+DDR.tdllk=512
+PE8.Signal=GPIO_Output
+DDR.data_bus_width=1
+PC2.GPIOParameters=GPIO_Label
+Mcu.Pin112=PF8
+Mcu.Pin113=PF9
+Mcu.Pin114=PG7
+Mcu.Pin115=PE10
+TIM3.IPParameters=Channel-Input_Capture4_from_TI4
+Mcu.Pin110=PG8
+DDR.tdlllock=128
+RCC.APB3DIV=RCC_APB3_DIV2
+Mcu.Pin111=PE7
+PA9.Locked=true
+RCC.CKPERCLKFreq_VALUE=24000000
+Mcu.Pin127=USB_DM1
+Mcu.Pin128=DDR_VREF
+Mcu.Pin129=DDR_DQ12
+PE7.Locked=true
+PG14.GPIO_Label=IOMUX_DI
+ProjectManager.FreePins=false
+VP_DMA_VS_DMA1_A7NS.Mode=CortexA7NS
+VP_RNG1_VS_RNG.Mode=RNG_Activate
+ProjectManager.UnderRoot=true
+PE13.Locked=true
+I2S2.FullDuplexMode=I2S_MODE_MASTER_FD
+DDR_WEN.GPIO_Label=DDR Memory
+PC12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_MEDIUM
+Mcu.Pin123=PA6
+Mcu.Pin124=PF7
+Mcu.Pin125=PG9
+PA4.Signal=GPIO_Input
+Mcu.Pin126=PB6
+PB5.Signal=SPI1_MOSI
+PG15.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label
+Mcu.Pin120=DDR_DQM1
+Mcu.Pin121=DDR_DQS1P
+TIM7.IPParametersWithoutCheck=Prescaler,Period
+PE13.GPIO_Label=PWR_BUCK_ALERT
+PD12.Mode=I2C
+Mcu.Pin122=PA7
+PF10.GPIO_Speed_High_ByDefault=GPIO_SPEED_FREQ_VERY_HIGH
+RCC.USART1CLockSelection=RCC_USART1CLKSOURCE_PCLK5
+DDR_A8.GPIO_Label=DDR Memory
+JTMS-SWDIO.GPIO_Label=JTAG Debug
+ProjectManager.CompilerOptimize=6
+PG11.Mode=Asynchronous
+DDR_A2.Signal=DDR_A2
+PA11.Signal=FDCAN1_RX
+PF8.Locked=true
+GIC.RCC_IRQn=true\:false\:High level
+PF6.Mode=Single Bank 1
+ProjectManager.ComputerToolchain=false
+DDR_DQ9.GPIO_Label=DDR Memory
+PF9.Signal=QUADSPI_BK1_IO1
+RCC.LTDCFreq_Value=50000000
+Mcu.Pin109=PB5
+TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
+PC3.GPIO_Label=PWR_HOLD
+Mcu.Pin105=PC5
+Mcu.Pin106=PC4
+DDR_DQ0.GPIOParameters=GPIO_Label
+Mcu.Pin107=PB12
+Mcu.Pin108=PB8
+DDR_DQ15.Mode=DDR3
+PE12.GPIOParameters=GPIO_Label
+RCC.DIVR4=10
+RCC.DIVR3=12
+RCC.DIVR2=1
+PB0.Signal=GPIO_Input
+Mcu.ContextNb=5
+PA7.GPIOParameters=GPIO_Label
+PC0.Locked=true
+DDR_BA0.GPIOParameters=GPIO_Label
+PB12.GPIOParameters=GPIO_Label
+PD7.GPIOParameters=GPIO_PuPd,GPIO_Label
+PG15.GPIO_PuPd=GPIO_PULLUP
+PG10.GPIO_Label=IOMUX_C
+PG7.GPIOParameters=GPIO_Label
+PD2.GPIO_Label=SDCARD
+Mcu.Pin101=PA10
+Mcu.Pin102=DDR_DQ14
+DDR_ZQ.GPIOParameters=GPIO_Label
+RCC.DIVP4Freq_Value=50000000
+Mcu.Pin103=DDR_DQS1N
+Mcu.Pin104=DDR_DQ9
+Mcu.Pin100=PA11
+DDR_BA1.GPIO_Label=DDR Memory
+RCC.DIVQ2Freq_Value=264000000
+RCC.I2C46CLockSelection=RCC_I2C46CLKSOURCE_HSI
+VP_DMA_VS_DMA2_M4.Signal=DMA_VS_DMA2_M4
+TIM15.Channel-Input_Capture1_from_TI1=TIM_CHANNEL_1
+DDR_DQS1N.GPIOParameters=GPIO_Label
+RCC.SAI1Freq_Value=50000000
+RCC.CortexFreq_Value=200000000
+PG6.Signal=SDMMC2_CMD
+JTDO-TRACESWO.GPIOParameters=GPIO_Label
+VP_TIM7_VS_OPM.Mode=OPM_bit
+Mcu.UserName=STM32MP157CADx
+DDR.addrmap_col_b9=31
+DDR.dfi_t_rddata_en=4
+NJTRST.Signal=DEBUG_JTRST
+PC10.Signal=SDMMC1_D2
+DDR_DQM1.Signal=DDR_DQM1
+DDR.addrmap_row_b2_10=6
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-true-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_ETZPC_Init-ETZPC-false-HAL-true,5-MX_FDCAN1_Init-FDCAN1-false-HAL-true,6-MX_IPCC_Init-IPCC-false-HAL-true,7-MX_SPI3_Init-SPI3-false-HAL-true,8-MX_TIM2_Init-TIM2-false-HAL-true,9-MX_TIM6_Init-TIM6-false-HAL-true,10-MX_TIM7_Init-TIM7-false-HAL-true,11-MX_USART6_UART_Init-USART6-false-HAL-true,12-MX_OPENAMP_Init-OPENAMP-false-HAL-false,13-MX_TIM15_Init-TIM15-false-HAL-true,14-MX_TIM12_Init-TIM12-false-HAL-true,15-MX_TIM3_Init-TIM3-false-HAL-true,16-MX_TIM4_Init-TIM4-false-HAL-true,17-MX_TIM5_Init-TIM5-false-HAL-true
+PC0.GPIOParameters=GPIO_Label
+PC0.GPIO_Label=SERVO_EN
+DDR_DQ12.GPIO_Label=DDR Memory
+PB0.GPIO_Label=ENC1_A
+DDR_BA1.Signal=DDR_BA1
+PC13.GPIO_Label=TEST_TP1
+PB11.Signal=I2C2_SDA
+VP_HASH1_VS_HASH.Mode=HASH_Activate
+RCC.USBPHYFreq_Value=24000000
+USART6.Mode=MODE_RX
+PE5.GPIOParameters=GPIO_Label
+ProjectManager.StackSize=0x400
+VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
+RCC.VCOInput3Freq_Value=12000000
+USB_DP1.GPIOParameters=GPIO_Label
+DDR_DQ6.GPIO_Label=DDR Memory
+VP_TIM7_VS_ClockSourceINT.Mode=Enable_Timer
+DDR_A8.Signal=DDR_A8
+DDR_A0.Signal=DDR_A0
+PB4.GPIOParameters=GPIO_PuPd,GPIO_Label
+PA12.Locked=true
+PA12.Signal=FDCAN1_TX
+DDR_DQ8.GPIOParameters=GPIO_Label
+Mcu.UserConstants=
+Mcu.ThirdPartyNb=0
+GIC.SDMMC1_IRQn=true\:false\:High level
+PG11.GPIO_PuPd=GPIO_PULLUP
+GIC.PMUIRQ0_IRQn=true\:false\:High level
+Mcu.IPNb=45
+DDR.TEMPERATURE_OVER_85C=true
+GIC.RTC_WKUP_ALARM_IRQn=true\:false\:High level
+RCC.SPDIFRXFreq_Value=50000000
+DDR_DQS0N.Mode=DDR3
+PD10.Mode=Full_Duplex_Master
+Mcu.Pin6=JTDO-TRACESWO
+Mcu.Pin7=JTCK-SWCLK
+Mcu.Pin8=DDR_DQ0
+Mcu.Pin9=DDR_DQ1
+DDR_A0.GPIO_Label=DDR Memory
+PH0-OSC_IN.Mode=HSE-External-Oscillator
+DDR_CLKN.GPIO_Label=DDR Memory
+Mcu.Pin0=PD1
+PH0-OSC_IN.GPIO_Label=OSC System
+SPI3.DataSize=SPI_DATASIZE_16BIT
+Mcu.Pin1=PB7
+GPIO.groupedBy=Group By Peripherals
+Mcu.Pin2=PC6
+Mcu.Pin3=PD3
+Mcu.Pin4=PC8
+PD10.GPIOParameters=GPIO_Label
+Mcu.Pin5=PE4
+DDR.t_rrd=4
+VP_DDR_DDR_16_bits.Signal=DDR_DDR_16_bits
+PA15.Mode=NSS_Signal_Hard_Output
+FDCAN1.Mode=FDCAN_MODE_BUS_MONITORING
+DDR.MR0.CL=2
+DDR_DQ14.GPIO_Label=DDR Memory
+RCC.MCUClockFreq_Value=200000000
+VP_TIM7_VS_ClockSourceINT.Signal=TIM7_VS_ClockSourceINT
+PB4.Mode=mmc_4_bits_Wide_bus
+PE13.Signal=GPIO_Input
+PF7.GPIO_Label=NOR Flash
+NJTRST.Mode=JTAG_5_pins
+RCC.Hclk5DIVFreq_Value=264000000
+DDR_A9.GPIO_Label=DDR Memory
+DDR_DQM0.GPIO_Label=DDR Memory
+File.Version=6
+DDR.dfi_tphy_wrlat=4
+USB_DM1.Signal=USBH_HS1_DM
+PB3.GPIOParameters=GPIO_PuPd,GPIO_Label
+RCC.USART24Freq_Value=100000000
+SH.S_TIM2_CH1.ConfNb=1
+TIM6.Period=MuxerDelay
+DDR_CKE.Mode=DDR3
+PE4.Signal=GPIO_Output
+PE6.GPIOParameters=GPIO_PuPd,GPIO_Label
+DDR_RESETN.Signal=DDR_RESETN
+USB_DP1.Signal=USBH_HS1_DP
+JTCK-SWCLK.Mode=JTAG_5_pins
+FREERTOS.configTOTAL_HEAP_SIZE=10240
+PC14-OSC32_IN.GPIOParameters=GPIO_Label
+RCC.ETHFreq_Value=50000000
+ProjectManager.ProjectName=txt2
+PD7.GPIO_Label=WIFI
+RCC.APB3Freq_Value=100000000
+DDR_A13.Mode=4Gb_16bits
+PF9.GPIO_Speed_Medium_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PA7.Locked=true
+RCC.DDRPERFMFreq_Value=528000000
+DDR_CSN.GPIO_Label=DDR Memory
+DDR.t_ckesr=2
+DDR_DQS0P.Signal=DDR_DQS0P
+VP_TAMP_VS_TAMP_Activate.Signal=TAMP_VS_TAMP_Activate
+DDR.MR0=0x00000830
+PA2.GPIO_Label=SERVO_PWM3
+PD14.Locked=true
+RCC.LSI_VALUE=32000
+RCC.DIVQ4Freq_Value=50000000
+TIM8.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
+DDR_RASN.GPIO_Label=DDR Memory
+PE0.GPIO_Label=MOTOR_SCK
+DDR_DQ5.Mode=DDR3
+DDR_DQS1P.GPIO_Label=DDR Memory
+NVIC.IPCC_TX1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true
+RCC.DDRCFreq_Value=528000000
+VP_OPENAMP_VS_OPENAMP.Mode=OpenAmp_Activated
+DDR.MR2=0x00000248
+RCC.APB1DIV=RCC_APB1_DIV2
+ProjectManager.DeviceTreeLocation=/home/ioblakov/txt2-rt-core/txt2-M4-rt-core/cubemx/txt2/CA7/DeviceTree/
+JTMS-SWDIO.Signal=DEBUG_JTMS-SWDIO
+SPI3.FifoThreshold=SPI_FIFO_THRESHOLD_04DATA
+GIC.IPCC_TX0_IRQn=true\:false\:High level
+SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,BaudRatePrescaler,VirtualNSS,CLKPhase,MasterInterDataIdleness,MasterReceiverAutoSusp,FifoThreshold,MasterKeepIOState
+PC14-OSC32_IN.GPIO_Label=OSC RTC
+RCC.MCUDIVCLKFreq_Value=200000000
+DDR_DQ12.Mode=DDR3
+DDR_CLKN.GPIOParameters=GPIO_Label
+VP_TAMP_VS_TAMP_Activate.Mode=TAMP_Enabled
+RCC.MPUCLKFreq_VALUE=648000000
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
+DDR_DQ9.GPIOParameters=GPIO_Label
+PC2.GPIO_Label=AUDIO
+PE3.Mode=mmc_4_bits_Wide_bus
+NVIC.TIM7_IRQn=true\:5\:0\:true\:false\:false\:false\:true\:false
+RCC.Tim2OutputFreq_Value=200000000
+PB3.GPIO_Label=EMMC
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+GIC.I2C1_EV_IRQn=true\:false\:High level
+DDR_DQS0N.GPIO_Label=DDR Memory
+PE8.GPIOParameters=GPIO_Label
+DDR_ATO.Signal=DDR_ATO
+PF8.GPIO_Speed_Medium_Default=GPIO_SPEED_FREQ_VERY_HIGH
+I2S2.Instance=SPI$Index
+PB9.GPIO_Label=TOUCH_SDA
+JTDI.Mode=JTAG_5_pins
+PC10.GPIO_Label=SDCARD
+ProjectManager.NoMain=false
+SPI1.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate
+DDR_DQ2.Mode=DDR3
+USART6.IPParameters=VirtualMode-Half_duplex(single_wire_mode),Mode,FIFOMode
+DDR_A2.Mode=DDR3
+DDR_DQ8.GPIO_Label=DDR Memory
+PC4.Signal=ADCx_INP4
+ADC1.DiscontinuousConvMode=DISABLE
+DDR.addrmap_bank_b1=7
+PD5.Signal=SDMMC3_D2
+VP_HSEM_VS_HSEM.Signal=HSEM_VS_HSEM
+DDR.addrmap_bank_b2=7
+DDR.addrmap_bank_b0=7
+DDR_A10.Mode=DDR3
+GIC.PMUIRQ1_IRQn=true\:false\:High level
+FDCAN1.IPParameters=AutoRetransmission,ProtocolException,StdFiltersNbr,ExtFiltersNbr,RxFifo0ElmtsNbr,RxFifo0ElmtSize,RxFifo1ElmtsNbr,RxFifo1ElmtSize,RxBuffersNbr,RxBufferSize,TxEventsNbr,TxBuffersNbr,TxFifoQueueElmtsNbr,TxElmtSize,FrameFormat,TransmitPause,Mode
+DDR_RASN.Mode=DDR3
+DDR_DQ13.Signal=DDR_DQ13
+VP_DDR_DDR3_16_4Gb.Signal=DDR_DDR3_16_4Gb
+DDR_DQ15.Signal=DDR_DQ15
+RCC.USART24CLockSelection=RCC_UART24CLKSOURCE_PCLK1
+TIM5.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
+TIM2.Pulse-PWM\ Generation1\ CH1=SERVO_MID_PULSE
+DDR_DQ3.GPIO_Label=DDR Memory
+NVIC.USART6_IRQn=true\:5\:0\:true\:false\:false\:true\:true\:false
+PE9.GPIOParameters=GPIO_Label
+DDR.DRAMTMG4=0x07040607
+DDR.DRAMTMG2=0x0607080F
+RCC.DSITXEscFreq_Value=15000000
+RCC.SPI6Freq_Value=66000000
+DDR.DRAMTMG1=0x000A041B
+PC8.GPIO_Label=SDCARD
+PC12.GPIOParameters=GPIO_PuPd,GPIO_Speed_High_Default,GPIO_Label
+DDR.DRAMTMG0=0x121B1214
+PF7.Mode=Single Bank 1
+TIM6.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE
+DDR.tREFI=3.9
+SH.S_TIM2_CH2.0=TIM2_CH2,PWM Generation2 CH2
+DDR_VREF.Mode=DDR3
+DDR_A9.Mode=DDR3
+RCC.SPI45Freq_Value=100000000
+PE15.GPIO_Label=MOTOR_NFAULT
+PD12.GPIOParameters=GPIO_Label
+GIC.I2C1_ER_IRQn=true\:false\:High level
+RCC.VCO4OutputFreq_Value=500000000
+ProjectManager.TargetToolchain=SW4STM32
+PE7.GPIOParameters=GPIO_Label
+DDR_DQS0P.GPIOParameters=GPIO_Label
+FREERTOS.configTIMER_TASK_STACK_DEPTH=512
+VP_TIM7_VS_OPM.Signal=TIM7_VS_OPM
+PB2.GPIOParameters=GPIO_PuPd,GPIO_Label
+DDR_DQS0N.GPIOParameters=GPIO_Label
+PD13.Mode=I2C
+PE4.Locked=true
+PE11.Signal=GPIO_Input
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+RCC.SDMMC12CLockSelection=RCC_SDMMC12CLKSOURCE_PLL4
+PB1.Locked=true
+RCC.I2C46Freq_Value=64000000
+PG9.GPIO_Label=IOMUX_B
+PG14.Signal=USART6_TX
+DDR.twtr=6
+DDR.t_faw=8
+DDR.addrmap_row_b13=6
+DDR.addrmap_row_b12=6
+DDR.addrmap_row_b11=6
+JTDI.GPIOParameters=GPIO_Label
+DDR_DQ9.Mode=DDR3
+DDR_DQ3.Signal=DDR_DQ3
+RCC.VCOInput1Freq_Value=8000000
+RCC.APB2Freq_Value=100000000
+SPI3.CalculateBaudRate=3.125 MBits/s
+FDCAN1.RxFifo1ElmtsNbr=16
+TIM7.IPParameters=Prescaler,TIM_MasterOutputTrigger,AutoReloadPreload,Period
+DDR_A13.Signal=DDR_A13
+PD4.GPIO_Label=WIFI
+PC13.GPIOParameters=GPIO_Label
+PF10.Signal=QUADSPI_CLK
+DDR.SCHED=0x00000C01
+DDR.txs=512
+SPI3.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
+DDR.txp=10
+VP_ETZPC_VS_ETZPC.Mode=ETZPC_Activate
+PH1-OSC_OUT.Signal=RCC_OSC_OUT
+DDR.addrmap_row_b15=15
+DDR.addrmap_row_b14=6
+FDCAN1.TxEventsNbr=32
+PD14.GPIO_Label=IOMUX_A
+PA4.GPIOParameters=GPIO_PuPd,GPIO_Label
+VP_DDR_DDR_16_bits.Mode=16bits
+RCC.LPTIM23CLockSelection=RCC_LPTIM23CLKSOURCE_PCLK3
+SPI3.MasterInterDataIdleness=SPI_MASTER_INTERDATA_IDLENESS_13CYCLE
+PE6.Signal=SDMMC2_D0
+PB15.GPIOParameters=GPIO_Label
+PE11.Locked=true
+Mcu.Name=STM32MP157CADx
+VP_IPCC_VS_IPCC.Mode=IPCC_Activate
+PD0.Mode=SD_4_bits_Wide_bus
+PA13.GPIO_Label=LED_RED
+PA2.Signal=S_TIM2_CH3
+RCC.DFSDFAFreq_Value=50000000
+VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
+PD14.Signal=GPIO_Output
+DDR_DQ8.Signal=DDR_DQ8
+PB3.Signal=SDMMC2_D2
+DDR_DQ0.GPIO_Label=DDR Memory
+DDR_WEN.Signal=DDR_WEN
+PA7.GPIO_Label=LED_BLUE
+PA12.Mode=FDCANFD
+DDR_A5.Signal=DDR_A5
+PG12.Locked=true
+PC5.GPIO_Label=DISP_LPTE
+RCC.MCUCLKSource=RCC_MCUSSOURCE_PLL3
+DDR_CLKP.GPIOParameters=GPIO_Label
+PB7.Mode=mmc_4_bits_Wide_bus
+PA14.Signal=GPIO_Output
+VP_CRYP1_VS_CRYP.Signal=CRYP1_VS_CRYP
+PF6.GPIOParameters=GPIO_Label,GPIO_Speed_Medium_Default
+PG12.GPIO_Label=IOMUX_EN
+ADC1.NbrOfConversionFlag=1
+RCC.DSIPixelFreq_Value=50000000
+RCC.DIVQ1Freq_Value=324000000
+PB8.Signal=S_TIM4_CH3
+PE3.GPIO_Label=EMMC
+USB_DP1.Mode=Enable
+VP_GPU_VS_GPU.Signal=GPU_VS_GPU
+PC9.Signal=SDMMC1_D1
+DDR_DQM0.GPIOParameters=GPIO_Label
+DDR_DTO1.Signal=DDR_DTO1
+RCC.VCOInput2Freq_Value=8000000
+RCC.APB1Freq_Value=100000000
+DDR.t_xs_dll_x32=16
+GIC.UART4_IRQn=true\:false\:High level
+ADC1.ClockPrescaler=ADC_CLOCK_ASYNC_DIV4
+PB11.Locked=true
+DDR_A6.GPIO_Label=DDR Memory
+ProjectManager.DeviceId=STM32MP157CADx
+PE0.Mode=Full_Duplex_Master
+USB_DM1.GPIO_Label=USB Host
+GIC.CRYP1_IRQn=true\:false\:High level
+ProjectManager.LibraryCopy=1
+SH.S_TIM3_CH4.0=TIM3_CH4,Input_Capture4_from_TI4
+PB1.GPIOParameters=GPIO_Label
+PA7.Signal=GPIO_Output
+FDCAN1.TxElmtSize=FDCAN_DATA_BYTES_64
diff --git a/txt2-M4-rt-core/cubemx/txt/txt2.xml b/txt2-M4-rt-core/cubemx/txt/txt2.xml
new file mode 100644
index 0000000..283aa47
--- /dev/null
+++ b/txt2-M4-rt-core/cubemx/txt/txt2.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<targetDefinitions xmlns="http://openstm32.org/stm32TargetDefinitions" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://openstm32.org/stm32TargetDefinitions stm32TargetDefinitions.xsd">
+ <board id="txt2">
+ <name>txt2</name>
+ <mcuId>STM32MP157CADx</mcuId> <!-- mcu-->
+ <dbgIF>JTAG</dbgIF>
+ <dbgDEV>ST-LinkV2-1</dbgDEV>
+ </board>
+</targetDefinitions>
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/CM4/Inc/stm32mp1xx_hal_conf.h b/txt2-M4-rt-core/cubemx/txt2-rev0/CM4/Inc/stm32mp1xx_hal_conf.h
index e08864f..7ea36c6 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/CM4/Inc/stm32mp1xx_hal_conf.h
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/CM4/Inc/stm32mp1xx_hal_conf.h
@@ -73,8 +73,8 @@
/*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_MDMA_MODULE_ENABLED
+/* #define HAL_DMA_MODULE_ENABLED */
+/* #define HAL_MDMA_MODULE_ENABLED */
#define HAL_RCC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index ce5a460..dfbdde7 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -1636,17 +1636,21 @@
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
* @{
*/
+#ifdef HAL_DMA_MODULE_ENABLED
#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#endif
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#ifdef HAL_DMA_MODULE_ENABLED
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
index 26f6be4..ed437d0 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
@@ -365,7 +365,9 @@ typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
+#ifdef HAL_DMA_MODULE_ENABLED
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+#endif
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
@@ -1783,10 +1785,12 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+#ifdef HAL_DMA_MODULE_ENABLED
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAError(DMA_HandleTypeDef *hdma);
void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);
+#endif
/**
* @}
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
index 4163ec8..11d8982 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
@@ -185,11 +185,11 @@ typedef struct __SPI_HandleTypeDef
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
-
+#ifdef HAL_DMA_MODULE_ENABLED
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
+#endif
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
index d6be3c2..7f5c0ff 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
@@ -334,9 +334,12 @@ typedef struct
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+#ifdef HAL_DMA_MODULE_ENABLED
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
+#endif
HAL_LockTypeDef Lock; /*!< Locking object */
+
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -2185,13 +2188,14 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
+#ifdef HAL_DMA_MODULE_ENABLED
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+#endif
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void TIM_ResetCallback(TIM_HandleTypeDef *htim);
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
index 6d03d2d..37e7505 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
@@ -299,9 +299,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+
+#ifdef HAL_DMA_MODULE_ENABLED
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+#endif
+
/**
* @}
*/
@@ -319,9 +323,12 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+#ifdef HAL_DMA_MODULE_ENABLED
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+#endif
+
/**
* @}
*/
@@ -338,9 +345,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+#ifdef HAL_DMA_MODULE_ENABLED
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+#endif
+
/**
* @}
*/
@@ -370,8 +381,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
+#ifdef HAL_DMA_MODULE_ENABLED
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
+#endif
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@@ -420,8 +433,10 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
+#ifdef HAL_DMA_MODULE_ENABLED
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
/**
* @}
*/
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
index 407b603..b8f8e82 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
@@ -219,11 +219,11 @@ typedef struct __UART_HandleTypeDef
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
-
+#ifdef HAL_DMA_MODULE_ENABLED
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
-
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
MDMA_HandleTypeDef *hmdmatx; /*!< UART Tx MDMA Handle parameters */
@@ -1532,11 +1532,14 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+#ifdef HAL_DMA_MODULE_ENABLED
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+#endif
+
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
index f00f4b5..05cfcd4 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
@@ -1984,6 +1984,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
* @note Interruptions enabled in this function:
@@ -2203,6 +2204,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
/**
* @brief Get ADC regular group conversion result.
@@ -3532,6 +3534,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA transfer complete callback.
* @param hdma pointer to DMA handle.
@@ -3651,6 +3654,7 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma)
HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
+#endif
/**
* @brief Configure boost mode of selected ADC.
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
index a335dde..c3dd12d 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
@@ -950,6 +950,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
}
#if defined(ADC_MULTIMODE_SUPPORT)
+
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
* @note Multimode must have been previously configured using
@@ -1186,6 +1188,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
/**
* @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
@@ -1463,6 +1466,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable ADC DMA transfer, disable
@@ -1546,8 +1550,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
#if defined(ADC_MULTIMODE_SUPPORT)
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
* @note Multimode is kept enabled after this function. Multimode DMA bits
@@ -1677,6 +1683,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/**
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
index 5424cb2..c58823d 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
@@ -156,6 +156,7 @@
/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -166,6 +167,8 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+#endif
+
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
@@ -1936,6 +1939,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin
}
#endif /* USE_HSPI_RELOAD_TRANSFER */
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
* @param hspi : pointer to a SPI_HandleTypeDef structure that contains
@@ -2417,6 +2421,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
__HAL_UNLOCK(hspi);
return errorcode;
}
+#endif
/**
* @brief Abort ongoing transfer (blocking mode).
@@ -2463,6 +2468,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the SPI DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
{
@@ -2500,6 +2506,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
}
}
}
+#endif
/* Proceed with abort procedure */
SPI_AbortTransfer(hspi);
@@ -2569,6 +2576,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Reset Callbacks */
hspi->hdmarx->XferAbortCallback = NULL;
hspi->hdmatx->XferAbortCallback = NULL;
@@ -2619,7 +2627,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
}
-
+ #endif
/* If no running DMA transfer, finish cleanup and call callbacks */
if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
{
@@ -2652,6 +2660,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
return errorcode;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Pause the DMA Transfer.
* This API is not supported, it is maintained for backward compatibility.
@@ -2667,6 +2676,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
return HAL_ERROR;
}
+
/**
* @brief Resume the DMA Transfer.
* This API is not supported, it is maintained for backward compatibility.
@@ -2696,6 +2706,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
return HAL_ERROR;
}
+#endif
/**
* @brief Handle SPI interrupt request.
@@ -2762,9 +2773,13 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
/* DMA Normal Mode */
+ #if defined(HAL_DMA_MODULE_ENABLED)
if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || // IT based transfer is done
((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode
((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) // DMA is used in normal mode
+ #else
+ if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ #endif
{
/* For the IT based receive extra polling maybe required for last packet */
if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
@@ -2899,7 +2914,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
/* Disable the SPI DMA requests */
CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
-
+ #if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the SPI DMA Rx channel */
if (hspi->hdmarx != NULL)
{
@@ -2922,6 +2937,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
}
}
+ #endif
}
else
{
@@ -3126,6 +3142,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
* @{
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA SPI transmit process complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -3382,6 +3399,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
HAL_SPI_AbortCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
+#endif
/**
* @brief Manage the receive 8-bit in Interrupt context.
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
index 02f7599..7e5ed3b 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
@@ -219,10 +219,12 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter);
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+#if defined(HAL_DMA_MODULE_ENABLED)
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
@@ -476,6 +478,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Base generation in DMA mode.
* @param htim TIM Base handle
@@ -561,6 +564,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -922,6 +926,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
* @param htim TIM Output Compare handle
@@ -1138,6 +1143,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -1501,6 +1507,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
* @param htim TIM PWM handle
@@ -1716,6 +1723,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -2048,6 +2056,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Input Capture measurement in DMA mode.
* @param htim TIM Input Capture handle
@@ -2252,6 +2261,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Return function status */
return HAL_OK;
}
+#endif
+
/**
* @}
*/
@@ -2961,6 +2972,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
* @param htim TIM Encoder Interface handle
@@ -3153,6 +3165,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -3854,6 +3867,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
* @param htim TIM handle
@@ -4412,6 +4426,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
* @retval HAL status
*/
+#endif
+
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
{
/* Check the parameters */
@@ -5682,7 +5698,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief TIM DMA error callback
* @param hdma pointer to DMA handle.
@@ -5936,6 +5952,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
HAL_TIM_TriggerHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+#endif
/**
* @brief Time Base configuration
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
index 1bfc0f6..6446870 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
@@ -393,7 +393,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
* @param htim TIM Hall Sensor Interface handle
@@ -442,6 +442,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
{
return HAL_ERROR;
}
+
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
@@ -482,6 +483,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
return HAL_OK;
}
+#endif
+
/**
* @}
*/
@@ -699,7 +702,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Return function status */
return HAL_OK;
}
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
@@ -881,6 +884,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -1108,6 +1112,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
@@ -1288,6 +1293,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -1567,7 +1573,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
return HAL_OK;
}
-
+#ifdef HAL_DMA_MODULE_ENABLED
/**
* @brief Configure the TIM commutation event sequence with DMA.
* @note This function is mandatory to use the commutation event in order to
@@ -1631,7 +1637,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3
return HAL_OK;
}
-
+#endif
/**
* @brief Configures the TIM in master mode.
* @param htim TIM handle.
@@ -2293,6 +2299,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
* @{
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief TIM DMA Commutation callback.
* @param hdma pointer to DMA handle.
@@ -2312,6 +2319,7 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+
/**
* @brief TIM DMA Commutation half complete callback.
* @param hdma pointer to DMA handle.
@@ -2330,7 +2338,7 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
HAL_TIMEx_CommutHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
+#endif
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
diff --git a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
index 3288f31..d3cbd71 100644
--- a/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
+++ b/txt2-M4-rt-core/cubemx/txt2-rev0/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
@@ -195,6 +195,7 @@
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+#if defined(HAL_DMA_MODULE_ENABLED)
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -205,6 +206,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
static void UART_MDMATransmitCplt(MDMA_HandleTypeDef *hmdma);
static void UART_MDMAReceiveCplt(MDMA_HandleTypeDef *hmdma);
@@ -1354,7 +1356,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
return HAL_BUSY;
}
}
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
@@ -1726,7 +1728,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
return HAL_OK;
}
-
+#endif
/**
* @brief Abort ongoing transfers (blocking mode).
* @param huart UART handle.
@@ -1744,12 +1746,13 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
/* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
-
+
+
/* Disable the UART DMA Tx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
+ #if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
{
@@ -1768,6 +1771,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
}
}
}
+ #endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hmdmatx != NULL)
@@ -1794,7 +1798,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
{
@@ -1813,6 +1817,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
}
}
}
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hmdmarx != NULL)
@@ -1882,7 +1887,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
{
@@ -1901,6 +1906,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
}
}
}
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use blocking MDMA Abort API (no callback) */
if (huart->hmdmatx != NULL)
@@ -1960,7 +1966,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+ #if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
{
@@ -1979,6 +1985,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
}
}
}
+ #endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use blocking MDMA Abort API (no callback) */
if (huart->hmdmarx != NULL)
@@ -2041,6 +2048,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
+ #if defined(HAL_DMA_MODULE_ENABLED)
if (huart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
@@ -2068,6 +2076,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
huart->hdmarx->XferAbortCallback = NULL;
}
}
+ #endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* MDMA Tx Handle is valid */
if (huart->hmdmatx != NULL)
@@ -2104,7 +2113,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
{
@@ -2121,6 +2130,8 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
abortcplt = 0U;
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use non blocking MDMA Abort API (callback) */
if (huart->hmdmatx != NULL)
@@ -2146,6 +2157,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
{
@@ -2163,6 +2175,9 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
abortcplt = 0U;
}
}
+
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use non blocking MDMA Abort API (callback) */
if (huart->hmdmarx != NULL)
@@ -2251,9 +2266,12 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if (huart->hdmatx != NULL)
+ else if (huart->hdmatx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
@@ -2266,6 +2284,8 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
huart->hdmatx->XferAbortCallback(huart->hdmatx);
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use non blocking MDMA Abort API (callback) */
else if (huart->hmdmatx != NULL)
@@ -2358,8 +2378,12 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if (huart->hdmarx != NULL)
+ else if (huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
@@ -2372,6 +2396,9 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
huart->hdmarx->XferAbortCallback(huart->hdmarx);
}
}
+#endif
+
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use non blocking MDMA Abort API (callback) */
else if (huart->hmdmarx != NULL)
@@ -2552,9 +2579,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL)
+ else if (huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
@@ -2567,6 +2597,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
huart->hdmarx->XferAbortCallback(huart->hdmarx);
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel */
else if (huart->hmdmarx != NULL)
@@ -3505,7 +3537,7 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
huart->RxISR = NULL;
}
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA UART transmit process complete callback.
* @param hdma DMA handle.
@@ -3841,6 +3873,8 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
HAL_UART_AbortReceiveCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/**
diff --git a/txt2-M4-rt-core/cubemx/txt2/CM4/Inc/stm32mp1xx_hal_conf.h b/txt2-M4-rt-core/cubemx/txt2/CM4/Inc/stm32mp1xx_hal_conf.h
index e08864f..7ea36c6 100644
--- a/txt2-M4-rt-core/cubemx/txt2/CM4/Inc/stm32mp1xx_hal_conf.h
+++ b/txt2-M4-rt-core/cubemx/txt2/CM4/Inc/stm32mp1xx_hal_conf.h
@@ -73,8 +73,8 @@
/*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_MDMA_MODULE_ENABLED
+/* #define HAL_DMA_MODULE_ENABLED */
+/* #define HAL_MDMA_MODULE_ENABLED */
#define HAL_RCC_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index ce5a460..dfbdde7 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -1636,17 +1636,21 @@
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
* @{
*/
+#ifdef HAL_DMA_MODULE_ENABLED
#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
+#endif
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
+#ifdef HAL_DMA_MODULE_ENABLED
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
+#endif
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
index 26f6be4..54a9c76 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h
@@ -365,7 +365,9 @@ typedef struct
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
+#ifdef HAL_DMA_MODULE_ENABLED
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
+#endif
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
@@ -1783,9 +1785,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+#if defined(HAL_DMA_MODULE_ENABLED)
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAError(DMA_HandleTypeDef *hdma);
+#endif
void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);
/**
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
index 4163ec8..11d8982 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_spi.h
@@ -185,11 +185,11 @@ typedef struct __SPI_HandleTypeDef
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
-
+#ifdef HAL_DMA_MODULE_ENABLED
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
+#endif
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
index d6be3c2..3bd6d92 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim.h
@@ -334,8 +334,10 @@ typedef struct
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
+#endif
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
@@ -2185,12 +2187,13 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
+#ifdef HAL_DMA_MODULE_ENABLED
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
index 6d03d2d..e0d9e6b 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_tim_ex.h
@@ -370,8 +370,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
+#ifdef HAL_DMA_MODULE_ENABLED
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
+#endif
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@@ -420,8 +422,10 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
/**
* @}
*/
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
index 407b603..9a6e822 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_uart.h
@@ -220,9 +220,11 @@ typedef struct __UART_HandleTypeDef
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
MDMA_HandleTypeDef *hmdmatx; /*!< UART Tx MDMA Handle parameters */
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
index f00f4b5..afc9859 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
@@ -1984,6 +1984,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
* @note Interruptions enabled in this function:
@@ -2068,7 +2069,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
/* ADC start (in case of SW start): */
@@ -2203,6 +2203,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
/**
* @brief Get ADC regular group conversion result.
@@ -3532,6 +3533,7 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
return HAL_OK;
}
+#ifdef HAL_DMA_MODULE_ENABLED
/**
* @brief DMA transfer complete callback.
* @param hdma pointer to DMA handle.
@@ -3651,6 +3653,7 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma)
HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
+#endif
/**
* @brief Configure boost mode of selected ADC.
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
index a335dde..98e6970 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
@@ -950,6 +950,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
}
#if defined(ADC_MULTIMODE_SUPPORT)
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
* @note Multimode must have been previously configured using
@@ -1017,7 +1018,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
@@ -1026,7 +1027,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
-
+#endif
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
@@ -1186,6 +1187,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
/**
* @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
@@ -1463,6 +1465,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable ADC DMA transfer, disable
@@ -1546,8 +1549,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
#if defined(ADC_MULTIMODE_SUPPORT)
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
* @note Multimode is kept enabled after this function. Multimode DMA bits
@@ -1677,6 +1682,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
+#endif
#endif /* ADC_MULTIMODE_SUPPORT */
/**
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
index 5424cb2..bd68e95 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_spi.c
@@ -156,6 +156,7 @@
/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -166,6 +167,8 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+#endif
+
static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
@@ -1936,6 +1939,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin
}
#endif /* USE_HSPI_RELOAD_TRANSFER */
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
* @param hspi : pointer to a SPI_HandleTypeDef structure that contains
@@ -1987,7 +1991,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
{
SPI_1LINE_TX(hspi);
}
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Packing mode management is enabled by the DMA settings */
if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
@@ -2023,6 +2027,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Adjustment done */
}
+
/* Set the SPI TxDMA Half transfer complete callback */
hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
@@ -2035,6 +2040,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Set the DMA AbortCpltCallback */
hspi->hdmatx->XferAbortCallback = NULL;
+
/* Clear TXDMAEN bit*/
CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
@@ -2060,6 +2066,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
+ #endif
/* Enable the SPI Error Interrupt Bit */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF));
@@ -2078,6 +2085,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
return errorcode;
}
+
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
* @param hspi : pointer to a SPI_HandleTypeDef structure that contains
@@ -2417,6 +2425,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
__HAL_UNLOCK(hspi);
return errorcode;
}
+#endif
/**
* @brief Abort ongoing transfer (blocking mode).
@@ -2462,7 +2471,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
}
while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
-
+ #if defined(HAL_DMA_MODULE_ENABLED)
/* Disable the SPI DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
{
@@ -2500,6 +2509,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
}
}
}
+ #endif
/* Proceed with abort procedure */
SPI_AbortTransfer(hspi);
@@ -2568,7 +2578,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
-
+ #if defined(HAL_DMA_MODULE_ENABLED)
/* Reset Callbacks */
hspi->hdmarx->XferAbortCallback = NULL;
hspi->hdmatx->XferAbortCallback = NULL;
@@ -2619,6 +2629,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
}
}
}
+ #endif
/* If no running DMA transfer, finish cleanup and call callbacks */
if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL))
@@ -2652,6 +2663,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
return errorcode;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Pause the DMA Transfer.
* This API is not supported, it is maintained for backward compatibility.
@@ -2696,6 +2708,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
return HAL_ERROR;
}
+#endif
/**
* @brief Handle SPI interrupt request.
@@ -2762,9 +2775,13 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
/* DMA Normal Mode */
- if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || // IT based transfer is done
- ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode
- ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) // DMA is used in normal mode
+ #if defined(HAL_DMA_MODULE_ENABLED)
+ if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || // IT based transfer is done
+ ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode
+ ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) // DMA is used in normal mode
+ #else
+ if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+ #endif
{
/* For the IT based receive extra polling maybe required for last packet */
if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
@@ -2900,6 +2917,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
/* Disable the SPI DMA requests */
CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
+ #if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the SPI DMA Rx channel */
if (hspi->hdmarx != NULL)
{
@@ -2911,6 +2929,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
}
}
+
/* Abort the SPI DMA Tx channel */
if (hspi->hdmatx != NULL)
{
@@ -2922,6 +2941,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
}
}
+ #endif
+
}
else
{
@@ -3126,6 +3147,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
* @{
*/
+#ifdef HAL_DMA_MODULE_ENABLED
/**
* @brief DMA SPI transmit process complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -3383,6 +3405,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
+#endif
+
/**
* @brief Manage the receive 8-bit in Interrupt context.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
index 02f7599..b4f3ac6 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim.c
@@ -219,10 +219,12 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter);
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
+#ifdef HAL_DMA_MODULE_ENABLED
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+#endif
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
@@ -476,6 +478,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Base generation in DMA mode.
* @param htim TIM Base handle
@@ -561,7 +564,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
-
+#endif
/**
* @}
*/
@@ -922,6 +925,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
* @param htim TIM Output Compare handle
@@ -1138,6 +1142,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -1501,6 +1506,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
* @param htim TIM PWM handle
@@ -1716,6 +1722,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -2048,6 +2055,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Input Capture measurement in DMA mode.
* @param htim TIM Input Capture handle
@@ -2252,6 +2260,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Return function status */
return HAL_OK;
}
+#endif
+
/**
* @}
*/
@@ -2961,6 +2971,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
* @param htim TIM Encoder Interface handle
@@ -3153,6 +3164,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -3854,6 +3866,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
* @param htim TIM handle
@@ -4124,7 +4137,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
/* Return function status */
return status;
}
+#endif
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
* @param htim TIM handle
@@ -4390,6 +4405,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
/* Return function status */
return status;
}
+#endif
/**
* @brief Generate a software event
@@ -5683,6 +5699,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
* @{
*/
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief TIM DMA error callback
* @param hdma pointer to DMA handle.
@@ -5936,6 +5953,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
HAL_TIM_TriggerHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
+#endif
/**
* @brief Time Base configuration
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
index 1bfc0f6..357c0ed 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c
@@ -394,6 +394,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
* @param htim TIM Hall Sensor Interface handle
@@ -481,6 +482,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -700,6 +702,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
@@ -881,6 +884,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -1108,6 +1112,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
@@ -1288,6 +1293,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Return function status */
return HAL_OK;
}
+#endif
/**
* @}
@@ -1568,6 +1574,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
return HAL_OK;
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Configure the TIM commutation event sequence with DMA.
* @note This function is mandatory to use the commutation event in order to
@@ -1631,6 +1638,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3
return HAL_OK;
}
+#endif
/**
* @brief Configures the TIM in master mode.
@@ -2293,6 +2301,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
* @{
*/
+#ifdef HAL_DMA_MODULE_ENABLED
/**
* @brief TIM DMA Commutation callback.
* @param hdma pointer to DMA handle.
@@ -2330,7 +2339,7 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
HAL_TIMEx_CommutHalfCpltCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
+#endif
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
diff --git a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
index 3288f31..2e5cd35 100644
--- a/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
+++ b/txt2-M4-rt-core/cubemx/txt2/Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_uart.c
@@ -193,8 +193,10 @@
/** @addtogroup UART_Private_Functions
* @{
*/
+
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+#ifdef HAL_DMA_MODULE_ENABLED
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -205,6 +207,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
static void UART_MDMATransmitCplt(MDMA_HandleTypeDef *hmdma);
static void UART_MDMAReceiveCplt(MDMA_HandleTypeDef *hmdma);
@@ -1355,6 +1358,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
@@ -1726,6 +1730,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
return HAL_OK;
}
+#endif
/**
* @brief Abort ongoing transfers (blocking mode).
@@ -1745,11 +1750,12 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
/* Disable the UART DMA Tx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
{
@@ -1768,6 +1774,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
}
}
}
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hmdmatx != NULL)
@@ -1794,7 +1801,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
{
@@ -1813,6 +1820,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
}
}
}
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hmdmarx != NULL)
@@ -1882,7 +1890,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmatx != NULL)
{
@@ -1901,6 +1909,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
}
}
}
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use blocking MDMA Abort API (no callback) */
if (huart->hmdmatx != NULL)
@@ -1960,7 +1969,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
if (huart->hdmarx != NULL)
{
@@ -1979,6 +1988,8 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
}
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use blocking MDMA Abort API (no callback) */
if (huart->hmdmarx != NULL)
@@ -2041,6 +2052,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
+#if defined(HAL_DMA_MODULE_ENABLED)
if (huart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
@@ -2068,6 +2080,8 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
huart->hdmarx->XferAbortCallback = NULL;
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* MDMA Tx Handle is valid */
if (huart->hmdmatx != NULL)
@@ -2105,6 +2119,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
/* Disable DMA Tx at UART level */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
{
@@ -2121,6 +2136,8 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
abortcplt = 0U;
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use non blocking MDMA Abort API (callback) */
if (huart->hmdmatx != NULL)
@@ -2145,7 +2162,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
{
@@ -2163,6 +2180,8 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
abortcplt = 0U;
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use non blocking MDMA Abort API (callback) */
if (huart->hmdmarx != NULL)
@@ -2251,7 +2270,10 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmatx != NULL)
{
@@ -2266,6 +2288,8 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
huart->hdmatx->XferAbortCallback(huart->hdmatx);
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Tx channel : use non blocking MDMA Abort API (callback) */
else if (huart->hmdmatx != NULL)
@@ -2353,11 +2377,16 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
if (huart->hdmarx != NULL)
{
@@ -2372,6 +2401,8 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
huart->hdmarx->XferAbortCallback(huart->hdmarx);
}
}
+#endif
+
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel : use non blocking MDMA Abort API (callback) */
else if (huart->hmdmarx != NULL)
@@ -2552,9 +2583,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
+ if (1 == 2) {
+ // dummy
+ }
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort the UART DMA Rx channel */
- if (huart->hdmarx != NULL)
+ else if (huart->hdmarx != NULL)
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
@@ -2567,6 +2601,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
huart->hdmarx->XferAbortCallback(huart->hdmarx);
}
}
+#endif
#ifdef HAL_MDMA_MODULE_ENABLED
/* Abort the UART MDMA Rx channel */
else if (huart->hmdmarx != NULL)
@@ -3505,7 +3540,7 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
huart->RxISR = NULL;
}
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA UART transmit process complete callback.
* @param hdma DMA handle.
@@ -3841,7 +3876,9 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
HAL_UART_AbortReceiveCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
-#ifdef HAL_MDMA_MODULE_ENABLED
+#endif
+
+#if defined(HAL_MDMA_MODULE_ENABLED)
/**
* @brief MDMA UART transmit process complete callback.
diff --git a/txt2-M4-rt-core/ft/ft.hpp b/txt2-M4-rt-core/ft/ft.hpp
index c8e31ad..9d5501d 100644
--- a/txt2-M4-rt-core/ft/ft.hpp
+++ b/txt2-M4-rt-core/ft/ft.hpp
@@ -521,6 +521,12 @@ public:
*/
std::string getSlaveName(int number) { return ftop_get_txt_name(adaptee, number); }
+ /**
+ @brief Get master linux firmware
+ @return Slave name
+ */
+ std::string getMasterLinuxFirmware() { return ftop_get_txt_masterlinuxfirmware(adaptee); }
+
/**
@brief Get slave serial number
@param [in] number slave number
diff --git a/txt2-M4-rt-core/ft/ftop.h b/txt2-M4-rt-core/ft/ftop.h
index cd37c87..d67da1e 100644
--- a/txt2-M4-rt-core/ft/ftop.h
+++ b/txt2-M4-rt-core/ft/ftop.h
@@ -102,6 +102,20 @@ void ftop_set_pwm(void *device, int value);
*/
unsigned int ftop_get_pwm(void *device);
+/**
+ @brief Set servo limits
+ @param [in] device device
+ @param [in] u16Min (300-3000) min value
+ @param [in] u16Max (300-3000) max value
+ */
+void ftop_set_servo_limits(void *device, int num, uint16_t u16Min, uint16_t u16Max);
+
+/**
+ @brief Set servo limits
+ @param [in] device TXT2 device
+ */
+void ftop_init_servo_limits(void *device);
+
/* Motor specific procedures */
/**
diff --git a/txt2-M4-rt-core/ft/ftslave.h b/txt2-M4-rt-core/ft/ftslave.h
index a0f8ff3..31ca206 100644
--- a/txt2-M4-rt-core/ft/ftslave.h
+++ b/txt2-M4-rt-core/ft/ftslave.h
@@ -46,6 +46,13 @@ int ftop_get_version(fttxt2 *device);
*/
int ftop_get_firmware(fttxt2 *device);
+/**
+ @brief Get TXT2 master Linux firmware version
+ @param [in] device TXT2 controller
+ @return Device master Linux firmware version
+ */
+const char* ftop_get_masterlinuxfirmware(void *device);
+
/**
@brief Setup TXT2 mode
@param [in] device TXT2 controller
@@ -85,6 +92,13 @@ uint32_t ftop_get_txt_uid(fttxt2 *device, unsigned int number);
*/
const char *ftop_get_txt_name(fttxt2 *device, unsigned int number);
+/**
+ @brief Get TXT2 master linux firmware
+ @param [in] device master TXT2 controller
+ @return slave name
+ */
+const char *ftop_get_txt_masterlinuxfirmware(void *device);
+
/**
@brief Get TXT2 slave serial number
@param [in] device master TXT2 controller
diff --git a/txt2-M4-rt-core/ftinc/ftcmdline.h b/txt2-M4-rt-core/ftinc/ftcmdline.h
new file mode 100644
index 0000000..c9c2335
--- /dev/null
+++ b/txt2-M4-rt-core/ftinc/ftcmdline.h
@@ -0,0 +1,72 @@
+
+/*
+ * Copyright (c) 2023 Accso. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**
+ * @file inc/ftctrl.h
+ * @brief FT Control utility
+ */
+
+
+// command line inspired by https://github.com/schreinerman/ioCommandLine
+
+#ifndef __FTCMDLINE_H__
+#define __FTCMDLINE_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <string.h>
+#include <stdio.h>
+#include <stdint.h>
+
+#define CMDLINE_MAXBUFFER 512
+#define CMDLINE_MAXCMDARGS 5
+
+typedef void (*pfn_ftctrl_cmdline_callback_t)(char* args[], uint8_t argv);
+
+typedef int (*pfn_ftctrl_cmdline_putchar)(char c);
+
+struct stc_ftctrl_cmdline_item;
+
+typedef struct stc_ftctrl_cmdline_item
+{
+ pfn_ftctrl_cmdline_callback_t pfnCallback;
+ char* pcCommand;
+ char* pcHelpText;
+ struct stc_ftctrl_cmdline_item* nextListItm;
+} stc_ftctrl_cmdline_item_t;
+
+void FtCmdLine_Init(void);
+void FtCmdLine_AddCommands(stc_ftctrl_cmdline_item_t apfnCommands[], uint8_t u8CommandCount);
+void FtCmdLine_Execute(char *pcString);
+void FtCmdLine_ExecuteCommand(char* pcCommand,char* pcArgumentString);
+void FtCmdLine_ExecuteCommandArgs(char* pcCommand,char* args[],uint8_t argv);
+void FtCmdLine_Update(void);
+#if CMDLINE_MAXBUFFER > 0
+void FtCmdLine_AddChar(char cChar);
+void FtCmdLine_AddString(char* pcChar);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FTCMDLINE_H__
\ No newline at end of file
diff --git a/txt2-M4-rt-core/ftinc/ftext.h b/txt2-M4-rt-core/ftinc/ftext.h
index f7835f0..53f9b67 100644
--- a/txt2-M4-rt-core/ftinc/ftext.h
+++ b/txt2-M4-rt-core/ftinc/ftext.h
@@ -99,7 +99,15 @@ struct TXT2_ext_info_command {
uint8_t pad1; /*!< padding */
uint16_t cid; /*!< CAN ID */
uint32_t version; /*!< Slave version */
- uint32_t firmware; /*!< Slave firmware */
+ union
+ {
+ uint32_t firmware; /*!< Slave firmware */
+ struct
+ {
+ uint32_t rtCoreFirmware:16;
+ uint32_t txtFirmware:16; /* format: decimal xyyzz */
+ } firmware_f;
+ };
char device_name[FT_NAME_SIZE]; /*!< Slave TXT2 device name */
char sn[FT_NAME_SIZE]; /*!< Slave serial number */
};
diff --git a/txt2-M4-rt-core/ftinc/ftimpltypes.h b/txt2-M4-rt-core/ftinc/ftimpltypes.h
index 4652bd0..9d62c2a 100644
--- a/txt2-M4-rt-core/ftinc/ftimpltypes.h
+++ b/txt2-M4-rt-core/ftinc/ftimpltypes.h
@@ -82,6 +82,8 @@ enum ftop_commands {
ftop_op_nresponse, /*!< New values response */
ftop_op_nping, /*!< New ping op value */
ftop_op_motor_coast, /*!< Set motor coast mode */
+ ftop_op_set_servo_limits, /*!< Setservo limits */
+ ftop_op_set_pwm_us /*!< set pwm in us, S1-S3 */
};
/** Command packet header */
@@ -142,6 +144,27 @@ struct ftop_set_pwm {
ft_pwm_type pwm; /*!< new PWM value 0-512 */
};
+/** PWM setup packet */
+struct ftop_set_pwm_us {
+ struct ftop_command_packet packet; /*!< common command header */
+ uint8_t devid; /*!< device id */
+ ft_pwm_type pwm; /*!< new PWM value 0-512 */
+};
+
+/** Servo calibration struct */
+struct ft_servo_calibration
+{
+ int8_t servonum;
+ uint16_t min;
+ uint16_t max;
+};
+
+/** Set servo calibration */
+struct ftop_set_servo_limits {
+ struct ftop_command_packet packet; /*!< common command header */
+ struct ft_servo_calibration servocalibration[FT_MAX_SERVO];
+};
+
/** Start motor packet */
struct ftop_start_motor {
struct ftop_command_packet packet; /*!< common command header */
diff --git a/txt2-M4-rt-core/ftinc/ftinc.i b/txt2-M4-rt-core/ftinc/ftinc.i
index d9540fa..ae21cd0 100644
--- a/txt2-M4-rt-core/ftinc/ftinc.i
+++ b/txt2-M4-rt-core/ftinc/ftinc.i
@@ -18,6 +18,9 @@
%module(docstring="This module is to control a new TXT4 controller") ft
%nothread;
+%include "../ftinc/ftimpltypes.h"
+%include "../ft/fttypes.h"
+
%pythonbegin %{
import threading
from math import sqrt, log
@@ -75,6 +78,7 @@ class ftTXTControllerInfo:
self.role = self.name
self.uid = txt.get_txt_uid(num)
self.sn = txt.get_txt_SN(num)
+ self.masterlinuxfirmware = txt.get_txt_masterlinuxfirmware()
def __str__(self):
return "(name=\"{}\", role=\"{}\", uid=0x{:08x})".format(self.name, self.role, self.uid)
@@ -157,6 +161,8 @@ typedef struct {
const int firmware;
%feature("autodoc", "Number of slave controllers connected to the TXT4 controller") nslaves;
const int nslaves;
+ %feature("autodoc", "TXT4 controller master Linux firmware version") masterlinuxfirmware;
+ const char masterlinuxfirmware[32];
%thread;
fttxt2(const char *host = "auto", int port = 65000) {
@@ -313,6 +319,11 @@ typedef struct {
return ftop_get_txt_name($self, num);
}
+ %feature("autodoc", "Get slave TXT2 controller Linux firmware version") get_txt_masterlinuxfirmware;
+ const char* get_txt_masterlinuxfirmware() {
+ ftop_get_txt_masterlinuxfirmware($self);
+ }
+
%feature("autodoc", "Get slave TXT2 controller uid") get_txt_uid;
unsigned int get_txt_uid(int num) {
return ftop_get_txt_uid($self, num);
@@ -388,6 +399,10 @@ unsigned int fttxt2_firmware_get(fttxt2 *txt2) {
return ftop_get_firmware(txt2);
}
+const char * fttxt2_masterlinuxfirmware_get(fttxt2 *txt2) {
+ return ftop_get_masterlinuxfirmware(txt2);
+}
+
unsigned int fttxt2_nslaves_get(fttxt2 *txt2) {
return ftop_get_slaves_number(txt2);
}
diff --git a/txt2-M4-rt-core/ftinc/ftlibtypes.h b/txt2-M4-rt-core/ftinc/ftlibtypes.h
index 58772e3..3fd4dff 100644
--- a/txt2-M4-rt-core/ftinc/ftlibtypes.h
+++ b/txt2-M4-rt-core/ftinc/ftlibtypes.h
@@ -198,7 +198,7 @@ typedef struct ftobject_txt2 {
ftvalues current_values; /*!< Current values copy */
ftobject_txt2_dynamic_settings dynamic_settings;
-
+ char txtMasterLinuxFirmware[32];
} ftobject_txt2;
#endif /* FTINC_FTLIBTYPES_H_ */
diff --git a/txt2-M4-rt-core/ftinc/ftshmem.h b/txt2-M4-rt-core/ftinc/ftshmem.h
index 1f32c5b..694d518 100644
--- a/txt2-M4-rt-core/ftinc/ftshmem.h
+++ b/txt2-M4-rt-core/ftinc/ftshmem.h
@@ -44,7 +44,16 @@
*/
struct ft_shm_common {
uint32_t version; /*!< version */
- uint32_t firmware; /*!< firmware */
+ union
+ {
+ uint32_t firmware; /*!< firmware */
+ struct
+ {
+ uint32_t rtCoreFirmware:16;
+ uint32_t txtFirmware:16; /* format: decimal xyyzz */
+ } firmware_f;
+ };
+
ftuid uid; /*!< Processor UID */
uint32_t mode; /*!< ft_txt_mode */
uint32_t nslave; /*!< slave number */
diff --git a/txt2-M4-rt-core/ftsrc/ftext.c b/txt2-M4-rt-core/ftsrc/ftext.c
index 01bbb02..5575426 100644
--- a/txt2-M4-rt-core/ftsrc/ftext.c
+++ b/txt2-M4-rt-core/ftsrc/ftext.c
@@ -484,6 +484,7 @@ void ftProcessRequestExtRequest(ftop_client *ftc,
StartSyncMotor(ftc, ftcmd, stxt);
break;
+ case ftop_op_set_pwm_us:
case ftop_op_set_pwm:
OS_LOCK(ftext_mutex);
diff --git a/txt2-M4-rt-core/ftsrc/ftserver.c b/txt2-M4-rt-core/ftsrc/ftserver.c
index 044f61b..14e2599 100644
--- a/txt2-M4-rt-core/ftsrc/ftserver.c
+++ b/txt2-M4-rt-core/ftsrc/ftserver.c
@@ -315,7 +315,7 @@ void ftInitServer()
/* Setup versions */
txt2_server.current.common.version = FT_M4_VERSION;
- txt2_server.current.common.firmware = FT_M4_FIRMWARE;
+ txt2_server.current.common.firmware_f.rtCoreFirmware = FT_M4_FIRMWARE;
sprintf(txt2_server.current.common.sn, "ft%8.8lX", txt2_server.uids[0]);
values_config = txt2_server.current.config;
@@ -964,7 +964,17 @@ void ftProcessRequest(ftop_client *ftc, unsigned char *buffer)
OS_UNLOCK(out_mutex);
}
break;
-
+ case ftop_op_set_pwm_us:
+ {
+ struct ftop_set_pwm *c = (void*) buffer;
+ uint16_t npwm = c->pwm;
+ if ((c->devid >= ftdev_s1) && (c->devid <= ftdev_s3)) {
+ npwm = npwm & 0x7FFF;
+ npwm = npwm >= 3000 ? 3000 : npwm;
+ HWServo_SetDutyUs(c->devid - ftdev_s1, npwm);
+ }
+ }
+ break;
case ftop_op_set_pwm:
{
struct ftop_set_pwm *c = (void*) buffer;
@@ -995,6 +1005,21 @@ void ftProcessRequest(ftop_client *ftc, unsigned char *buffer)
}
break;
+ case ftop_op_set_servo_limits:
+ {
+ struct ftop_set_servo_limits *c = (void*) buffer;
+ for (int i = 0; i < FT_MAX_SERVO;i++)
+ {
+ if ((c->servocalibration[i].servonum > 0)
+ && (c->servocalibration[i].min > 0)
+ && (c->servocalibration[i].max > 0))
+ {
+ HWServo_SetLimits(c->servocalibration[i].servonum-1,c->servocalibration[i].min,c->servocalibration[i].max);
+ }
+ }
+ }
+ break;
+
case ftop_op_zero:
{
zops++;
diff --git a/txt2-M4-rt-core/ftutil/ftcmdline.c b/txt2-M4-rt-core/ftutil/ftcmdline.c
new file mode 100644
index 0000000..46e4c47
--- /dev/null
+++ b/txt2-M4-rt-core/ftutil/ftcmdline.c
@@ -0,0 +1,203 @@
+#include "ftcmdline.h"
+
+#if CMDLINE_MAXBUFFER > 0
+static uint8_t au8InternBuffer[CMDLINE_MAXBUFFER];
+static volatile uint16_t u16CurrentPos;
+#endif
+
+static stc_ftctrl_cmdline_item_t* pRoot = NULL;
+
+static void FtCmdLine_Help(char* args[], uint8_t argv);
+
+
+#define COMMAND_COUNT 1
+static stc_ftctrl_cmdline_item_t astcCommands[] = {{FtCmdLine_Help,"help","Print help"}};
+static void putString(char* pcString);
+
+
+static void FtCmdLine_Help(char* args[], uint8_t argv)
+{
+ stc_ftctrl_cmdline_item_t* pCurrent = pRoot;
+ uint8_t i;
+ putString("\r\n");
+ putString("\r\n");
+ putString("Available command line options:\r\n");
+ while(pCurrent != NULL)
+ {
+ if ((NULL == pCurrent->pcCommand) || (NULL == pCurrent->pfnCallback))
+ {
+ putString("\r\n");
+ putString(pCurrent->pcHelpText);
+ putString("\r\n");
+ }
+ else
+ {
+ putString(" ");
+ putString(pCurrent->pcCommand);
+ for(i = strlen(pCurrent->pcCommand);i < 20;i++)
+ {
+ putString(" ");
+ }
+ putString(pCurrent->pcHelpText);
+ putString("\r\n");
+ }
+ pCurrent = pCurrent->nextListItm;
+ }
+ putString("\r\n");
+ putString("\r\n");
+}
+
+static void putString(char* pcString)
+{
+ printf("%s",pcString);
+}
+
+void FtCmdLine_Init(void)
+{
+ memset(au8InternBuffer,0,CMDLINE_MAXBUFFER);
+ FtCmdLine_AddCommands(astcCommands,COMMAND_COUNT);
+}
+
+void FtCmdLine_AddCommands(stc_ftctrl_cmdline_item_t apfnCommands[], uint8_t u8CommandCount)
+{
+ uint8_t i;
+ stc_ftctrl_cmdline_item_t* pLastItem = pRoot;
+ if (pRoot != NULL)
+ {
+ while(pLastItem->nextListItm != NULL)
+ {
+ pLastItem = pLastItem->nextListItm;
+ }
+ }
+ for(i = 0;i <u8CommandCount;i++)
+ {
+ if (pRoot == NULL)
+ {
+ pRoot = &apfnCommands[i];
+ pLastItem = pRoot;
+ apfnCommands[i].nextListItm = NULL;
+ }
+ else
+ {
+ pLastItem->nextListItm = &apfnCommands[i];
+ pLastItem = pLastItem->nextListItm;
+ }
+ }
+}
+
+void FtCmdLine_Execute(char *pcString)
+{
+ char* pcTmp = pcString;
+ while(*pcTmp != '\0')
+ {
+ if (*pcTmp == ' ')
+ {
+ *pcTmp = '\0';
+ pcTmp++;
+ FtCmdLine_ExecuteCommand(pcString,pcTmp);
+ return;
+ }
+ pcTmp++;
+ }
+ FtCmdLine_ExecuteCommand(pcString,NULL);
+}
+
+void FtCmdLine_ExecuteCommand(char* pcCommand,char* pcArgumentString)
+{
+ char* args[CMDLINE_MAXCMDARGS];
+ volatile uint8_t argv = 0;
+ char* pcTmp = pcArgumentString;
+ if (pcArgumentString != NULL)
+ {
+ while(*pcTmp != '\0')
+ {
+ if (*pcTmp != ' ')
+ {
+ args[argv] = pcTmp;
+ argv++;
+ while(*pcTmp != '\0')
+ {
+ if (*pcTmp == ' ')
+ {
+ *pcTmp = '\0';
+ pcTmp++;
+ break;
+ }
+ pcTmp++;
+ }
+ }
+ else
+ {
+ pcTmp++;
+ }
+ }
+ }
+ FtCmdLine_ExecuteCommandArgs(pcCommand,args,argv);
+}
+
+void FtCmdLine_ExecuteCommandArgs(char* pcCommand,char* args[],uint8_t argv)
+{
+ uint8_t i;
+ stc_ftctrl_cmdline_item_t* pCurrent = pRoot;
+ while(pCurrent != NULL)
+ {
+ if (strcmp(pcCommand,pCurrent->pcCommand) == 0)
+ {
+ if (pCurrent->pfnCallback != NULL)
+ {
+ pCurrent->pfnCallback(args,argv);
+ return;
+ }
+ }
+ pCurrent = pCurrent->nextListItm;
+ }
+ putString("Command not found: ");
+ putString(pcCommand);
+ putString("\r\n");
+
+}
+
+void FtCmdLine_Update(void)
+{
+ static uint16_t u16LastCheck = 0;
+ if (u16LastCheck != u16CurrentPos)
+ {
+ for(;u16LastCheck <= u16CurrentPos;u16LastCheck++)
+ {
+ if ((au8InternBuffer[u16LastCheck] == '\r') || (au8InternBuffer[u16LastCheck] == '\n') ||(u16LastCheck == CMDLINE_MAXBUFFER))
+ {
+ au8InternBuffer[u16LastCheck] = '\0';
+ FtCmdLine_Execute((char*)&au8InternBuffer[0]);
+ memcpy(&au8InternBuffer[0],&au8InternBuffer[u16LastCheck],(CMDLINE_MAXBUFFER - u16LastCheck));
+ u16LastCheck = 0;
+ u16CurrentPos = 0;
+ }
+ if (au8InternBuffer[u16LastCheck] == 0) break;
+ }
+ }
+}
+
+#if CMDLINE_MAXBUFFER > 0
+void FtCmdLine_AddChar(char cChar)
+{
+ if ((cChar == '\b') && (u16CurrentPos > 0))
+ {
+ u16CurrentPos--;
+ }
+
+ if (u16CurrentPos < (CMDLINE_MAXBUFFER - 1))
+ {
+ au8InternBuffer[u16CurrentPos] = cChar;
+ au8InternBuffer[u16CurrentPos+1] = '\0';
+ u16CurrentPos++;
+ }
+}
+void FtCmdLine_AddString(char* pcChar)
+{
+ while(*pcChar != '\0')
+ {
+ FtCmdLine_AddChar(*pcChar);
+ pcChar++;
+ }
+}
+#endif
\ No newline at end of file
diff --git a/txt2-M4-rt-core/ftutil/ftctrl.cpp b/txt2-M4-rt-core/ftutil/ftctrl.cpp
new file mode 100644
index 0000000..6699957
--- /dev/null
+++ b/txt2-M4-rt-core/ftutil/ftctrl.cpp
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2023 Accso. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/**
+ * @file ftutil/ftctrl.cpp
+ * @brief FT Control utility
+ */
+
+
+#include "ftcmdline.h"
+#include <iostream>
+#include <string>
+#include <stdio.h>
+#include <unistd.h>
+
+#ifdef __cplusplus
+ extern "C" {
+ #include "ftlock.h"
+ }
+ #include "ft.hpp"
+ #include "ftop.h"
+#else
+ #include "ftlock.h"
+ #include "ft.h"
+#endif
+
+#ifdef __cplusplus
+ using namespace ft;
+#endif
+
+
+#define SERVO_MIN 300UL
+#define SERVO_MAX 2700UL
+
+#ifdef __cplusplus
+TXT txt2;
+#else
+void *txt2;
+#endif
+
+static void cmdServoUs(char* args[], uint8_t argc);
+static void cmdServo9Bit(char* args[], uint8_t argc);
+
+#define COMMANDS_SERVO_COUNT (sizeof(astcCommandsServo) / sizeof(astcCommandsServo[0]))
+static stc_ftctrl_cmdline_item_t astcCommandsServo[] = {
+ {cmdServoUs,"servo_us","<num> <position in us>"},
+ {cmdServo9Bit,"servo_9bit","<num> <position 0-512"}
+ };
+
+
+static void cmdServoUs(char* args[], uint8_t argc)
+{
+ int servoNum = 1;
+ int servoPos=1485;
+ if (argc < 2)
+ {
+ printf("ERROR\n");
+ return;
+ }
+
+ servoNum = atoi(args[1]);
+ servoPos = atoi(args[2]);
+
+ if ((servoNum < 1) || (servoNum > 3))
+ {
+ printf("ERROR\n");
+ return;
+ }
+
+ if ((servoPos < SERVO_MIN) || (servoPos > SERVO_MAX))
+ {
+ printf("ERROR\n");
+ return;
+ }
+
+ if (ftlock_open() < 0)
+ {
+ printf("ERROR\n");
+ return;
+ }
+
+ Servo s { txt2, servoNum };
+
+ txt2.update_config();
+ s.setPwmUs(servoPos);
+
+ printf("OK\n");
+ return;
+}
+
+static void cmdServo9Bit(char* args[], uint8_t argc)
+{
+int servoNum = 1;
+ int servoPos=1485;
+ if (argc < 2)
+ {
+ printf("ERROR\n");
+ return;
+ }
+
+ servoNum = atoi(args[1]);
+ servoPos = atoi(args[2]);
+
+ if ((servoNum < 1) || (servoNum > 3))
+ {
+ printf("ERROR\n");
+ return;
+ }
+
+ if ((servoPos < SERVO_MIN) || (servoPos > SERVO_MAX))
+ {
+ printf("ERROR\n");
+ return;
+ }
+
+ if (ftlock_open() < 0)
+ {
+ printf("ERROR\n");
+ return;
+ }
+ Servo s { txt2, servoNum };
+
+ txt2.update_config();
+ s.setPwm(servoPos);
+
+ ftlock_unlock(); // can be skipped in this case
+ ftlock_close(); // can be skipped in this case
+ printf("OK\n");
+ return;
+}
+
+/**
+ * @brief Standard main procedure
+ * @param [in] argc number of arguments
+ * @param [in] argv arguments
+ * @return Error code
+ */
+int main(int argc, char **argv)
+{
+ FtCmdLine_Init();
+ FtCmdLine_AddCommands(astcCommandsServo,COMMANDS_SERVO_COUNT);
+ #ifndef __cplusplus
+ txt2 = ftop_alloc_txt("auto", 65000);
+ if (ltxt == NULL) {
+ fprintf(stderr,"Can't conect %s\n", argv[1]);
+ return 1;
+ }
+ #endif
+
+ if (argc > 2)
+ {
+ FtCmdLine_ExecuteCommandArgs(argv[1],&argv[1],argc-1);
+ } else if (argc > 1)
+ {
+ FtCmdLine_ExecuteCommandArgs(argv[1],&argv[1],0);
+ } else
+ {
+ FtCmdLine_ExecuteCommandArgs("help",NULL,0);
+ }
+
+ ftlock_unlock(); // can be skipped in this case
+ ftlock_close(); // can be skipped in this case
+}
\ No newline at end of file
diff --git a/txt2-M4-rt-core/ftutil/txt_servo_setpos.cpp b/txt2-M4-rt-core/ftutil/txt_servo_setpos.cpp
new file mode 100644
index 0000000..3c9931b
--- /dev/null
+++ b/txt2-M4-rt-core/ftutil/txt_servo_setpos.cpp
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2023 Accso. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <iostream>
+#include <string>
+#include <stdio.h>
+#include <unistd.h>
+
+extern "C" {
+#include "ftlock.h"
+}
+#include "ft.hpp"
+#include "ftop.h"
+
+using namespace ft;
+
+#define SERVO_MIN 300UL
+#define SERVO_MAX 2700UL
+
+int main(int argc, char **argv)
+{
+ int servoNum = 1;
+ int servoPos=1485;
+ if (argc < 2)
+ {
+ printf("ERROR\n");
+ return 1;
+ }
+
+ servoNum = atoi(argv[1]);
+ servoPos = atoi(argv[2]);
+
+ if ((servoNum < 1) || (servoNum > 3))
+ {
+ printf("ERROR\n");
+ return 1;
+ }
+
+ if ((servoPos < SERVO_MIN) || (servoPos > SERVO_MAX))
+ {
+ printf("ERROR\n");
+ return 1;
+ }
+
+ if (ftlock_open() < 0)
+ {
+ printf("ERROR\n");
+ return 1;
+ }
+ TXT txt2;
+ Servo s { txt2, servoNum };
+
+ txt2.update_config();
+ s.setPwmUs(servoPos);
+
+ ftlock_unlock(); // can be skipped in this case
+ ftlock_close(); // can be skipped in this case
+ printf("OK\n");
+ return 0;
+}
+
diff --git a/txt2-M4-rt-core/inc/HWServo.h b/txt2-M4-rt-core/inc/HWServo.h
index a7d88ba..feef9f8 100644
--- a/txt2-M4-rt-core/inc/HWServo.h
+++ b/txt2-M4-rt-core/inc/HWServo.h
@@ -53,6 +53,14 @@ void HWServo_SetDuty(unsigned int n, uint16_t duty);
*/
void HWServo_SetDutyUs(unsigned int n, uint16_t duty_us);
+/**
+ * @brief Servo set limits procedure
+ * @param n servo number 0-2
+ * @param minVal new min value in us
+ * @param maxVal new max value in us
+ */
+void HWServo_SetLimits(unsigned int n,uint16_t minVal,uint16_t maxVal);
+
#endif /* INC_HWSERVO_H_ */
/** @} */
diff --git a/txt2-M4-rt-core/inc/mcommon.h b/txt2-M4-rt-core/inc/mcommon.h
index ec7c16d..0fc947e 100644
--- a/txt2-M4-rt-core/inc/mcommon.h
+++ b/txt2-M4-rt-core/inc/mcommon.h
@@ -39,8 +39,8 @@
#define I1I8TimeResolution 200 /*!< I1-I8 clibration time resolution in ns */
#define I1I8Delay 2500 /*!< Initial value for I1-I8 period ns */
#define SERVO_PERIOD 20000 /*!< total servo period 20 ms */
-#define SERVO_MIN_PULSE 600 /*!< minimal servo pulse */
-#define SERVO_MAX_PULSE 2400 /*!< maxsimum servo pulse */
+#define SERVO_MIN_PULSE 610 /*!< minimal servo pulse */
+#define SERVO_MAX_PULSE 2360 /*!< maximum servo pulse */
#define SERVO_MID_PULSE ((SERVO_MIN_PULSE + SERVO_MAX_PULSE)/2) /*!< medium servo pulse */
#if TXT2_BOARD_REVISION
diff --git a/txt2-M4-rt-core/pyexamples/tdiscovery.py b/txt2-M4-rt-core/pyexamples/tdiscovery.py
index 7af08fd..01c5fde 100644
--- a/txt2-M4-rt-core/pyexamples/tdiscovery.py
+++ b/txt2-M4-rt-core/pyexamples/tdiscovery.py
@@ -11,18 +11,20 @@ txt2=ft.fttxt2()
ftlock.notify('R')
l=txt2.getControllerInfoList()
+
i=0
for ci in l:
- print("Controller name :", ci.name)
- print("Controller serial number :", ci.sn)
+ print("Controller name :", ci.name)
+ print("Controller serial number :", ci.sn)
if (i):
ts=txt2.getController(ci)
- print("Controller version :", ts.version)
- print("Controller firmware :", ts.firmware)
+ print("Controller version :", ts.version)
+ print("Controller firmware :", ts.firmware)
else:
- print("Controller version :", txt2.version)
- print("Controller firmware :", txt2.firmware)
+ print("Controller version :", txt2.version)
+ print("Controller firmware :", txt2.firmware)
+ print("Controller Linux firmware :", txt2.masterlinuxfirmware)
i=i+1
diff --git a/txt2-M4-rt-core/src/HWServo.c b/txt2-M4-rt-core/src/HWServo.c
index 9eecd72..33c1378 100644
--- a/txt2-M4-rt-core/src/HWServo.c
+++ b/txt2-M4-rt-core/src/HWServo.c
@@ -35,23 +35,35 @@ extern TIM_HandleTypeDef htim5; /*!< TIM5 HAL handle */
/*!< Initialization structure for servo motors PWM */
struct ft_servo_motors {
- TIM_HandleTypeDef* htim; /*!< pwm timer handle*/
- TIM_TypeDef* tim; /*!< pwm timer address*/
- uint32_t Channel; /*!< pwm channel*/
+ TIM_HandleTypeDef* htim; /*!< pwm timer handle */
+ TIM_TypeDef* tim; /*!< pwm timer address */
+ uint32_t Channel; /*!< pwm channel */
+};
+
+struct ft_servo_calibration {
+ uint32_t current; /*!< current value */
+ uint32_t min; /*!< min value */
+ uint32_t max; /*!< max value */
};
static const struct ft_servo_motors ftServoMotors[FT_MAX_SERVO] = {
#if TXT2_BOARD_REVISION == 0
- { &htim4, TIM4, TIM_CHANNEL_3 },
- { &htim5, TIM5, TIM_CHANNEL_2 },
- { &htim2, TIM2, TIM_CHANNEL_3 }
+ { &htim4, TIM4, TIM_CHANNEL_3},
+ { &htim5, TIM5, TIM_CHANNEL_2},
+ { &htim2, TIM2, TIM_CHANNEL_3}
#else
- { &htim2, TIM2, TIM_CHANNEL_3 },
- { &htim2, TIM2, TIM_CHANNEL_2 },
- { &htim2, TIM2, TIM_CHANNEL_1 },
+ { &htim2, TIM2, TIM_CHANNEL_3},
+ { &htim2, TIM2, TIM_CHANNEL_2},
+ { &htim2, TIM2, TIM_CHANNEL_1},
#endif /* TXT2_BOARD_REVISION */
};
+static struct ft_servo_calibration ftServoCalib[FT_MAX_SERVO] = {
+ { SERVO_MIN_PULSE + (SERVO_MAX_PULSE - SERVO_MIN_PULSE) / 2,SERVO_MIN_PULSE,SERVO_MAX_PULSE },
+ { SERVO_MIN_PULSE + (SERVO_MAX_PULSE - SERVO_MIN_PULSE) / 2,SERVO_MIN_PULSE,SERVO_MAX_PULSE },
+ { SERVO_MIN_PULSE + (SERVO_MAX_PULSE - SERVO_MIN_PULSE) / 2,SERVO_MIN_PULSE,SERVO_MAX_PULSE }
+};
+
/**
* @brief S1-S3 servo initialization procedure
*/
@@ -89,9 +101,9 @@ void HWServo_SetDuty(unsigned int n, uint16_t duty)
{
if (n >= FT_MAX_SERVO)
return;
-
+ ftServoCalib[n].current = ftServoCalib[n].min + (ftServoCalib[n].max - ftServoCalib[n].min) * duty / 512UL;
__HAL_TIM_SET_COMPARE(ftServoMotors[n].htim, ftServoMotors[n].Channel,
- SERVO_MIN_PULSE + (SERVO_MAX_PULSE - SERVO_MIN_PULSE) * duty / 512);
+ ftServoCalib[n].current);
}
/**
@@ -103,6 +115,30 @@ void HWServo_SetDutyUs(unsigned int n, uint16_t duty_us)
{
if (n >= FT_MAX_SERVO)
return;
+ ftServoCalib[n].current = duty_us;
+ __HAL_TIM_SET_COMPARE(ftServoMotors[n].htim, ftServoMotors[n].Channel,ftServoCalib[n].current);
+}
- __HAL_TIM_SET_COMPARE(ftServoMotors[n].htim, ftServoMotors[n].Channel,duty_us);
+/**
+ * @brief Servo set limits procedure
+ * @param n servo number 0-2
+ * @param minVal new min value in us
+ * @param maxVal new max value in us
+ */
+void HWServo_SetLimits(unsigned int n,uint16_t minVal,uint16_t maxVal)
+{
+ if (n >= FT_MAX_SERVO)
+ return;
+ ftServoCalib[n].min = minVal;
+ ftServoCalib[n].max = maxVal;
+ if (ftServoCalib[n].current > maxVal)
+ {
+ ftServoCalib[n].current = maxVal;
+ HWServo_SetDutyUs(n,ftServoCalib[n].current);
+ }
+ if (ftServoCalib[n].current < minVal)
+ {
+ ftServoCalib[n].current = minVal;
+ HWServo_SetDutyUs(n,ftServoCalib[n].current);
+ }
}
diff --git a/txt2-M4-rt-core/utils/install.sh b/txt2-M4-rt-core/utils/install.sh
new file mode 100644
index 0000000..86fc8df
--- /dev/null
+++ b/txt2-M4-rt-core/utils/install.sh
@@ -0,0 +1,36 @@
+#!/bin/bash
+B=$(dirname "$0")
+S=$(dirname "$0")
+D="/"
+bindir="usr/bin"
+datadir="usr/share"
+libdir="usr/lib"
+includedir="usr/include"
+base_libdir="lib"
+
+PYTHON_SITEPACKAGES_DIR="usr/lib/python3.5/site-packages/"
+install -d ${D}${bindir}
+install -m 0755 ${B}/ftconfig ${D}${bindir}/
+install -m 0755 ${B}/fttxtctrl ${D}${bindir}/
+install -m 0755 ${B}/ftcalib ${D}${bindir}/
+install -m 0755 ${B}/ftdaemon ${D}${bindir}/
+install -m 0755 ${B}/ftlock_test ${D}${bindir}/
+install -d ${D}${datadir}/txt2-utils/
+install -m 0755 ${B}/txt_servo_setpos ${D}${datadir}/txt2-utils/
+
+install -d ${D}${libdir}
+cp -drv ${B}/libTxtControlLib.so* ${D}${libdir}/
+cp -drv ${B}/libcftlock.so* ${D}${libdir}/
+
+install -d ${D}${PYTHON_SITEPACKAGES_DIR}
+install -m 0755 ${B}/_ft.so ${D}${PYTHON_SITEPACKAGES_DIR}/
+install -m 0755 ${B}/ft.py ${D}${PYTHON_SITEPACKAGES_DIR}/
+install -m 0755 ${B}/_ftlock.so ${D}${PYTHON_SITEPACKAGES_DIR}/
+install -m 0755 ${B}/ftlock.py ${D}${PYTHON_SITEPACKAGES_DIR}/
+
+install -d ${D}${includedir}
+cp -drv ${S}/includes/ft ${D}${includedir}/
+
+install -d ${D}${base_libdir}/firmware
+install -m 0755 ${B}/firmware/txt2-M4-rt-core-rev0.elf ${D}${base_libdir}/firmware/
+install -m 0755 ${B}/firmware/txt2-M4-rt-core-rev1.elf ${D}${base_libdir}/firmware/
\ No newline at end of file
--
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